TWI505437B - Electrostatic discharge protection circuit device - Google Patents

Description

Electrostatic discharge protection circuit device

The present invention relates to an electrostatic discharge protection circuit device, and more particularly to an electrostatic discharge protection circuit device that can adjust a crash speed.

Electrostatic discharge (ESD) is a phenomenon of electrostatic movement from a non-conductive surface, which causes damage to the semiconductor and other circuit components in the integrated circuit. For example, when a common body such as a human body walking on a carpet, a machine for packaging an integrated circuit, or an instrument for testing an integrated circuit contacts a wafer, it will discharge to the wafer, and the instantaneous power of the electrostatic discharge may cause The integrated circuit in the wafer is damaged or fails.

In order to prevent the integrated circuit from being damaged by the electrostatic discharge phenomenon, the design of the electrostatic discharge protection circuit device is added to the integrated circuit. In general, there are many design methods for ESD protection circuit devices. One common way is to use a two-stage N-type transistor connected in series to achieve electrostatic discharge protection. Two-stage N-type transistors are connected in series. The gate terminals are all biased at a fixed voltage. However, the holding voltage of the discharge path provided by such an architecture tends to be less than 10.5 volts. Therefore, when an internal circuit is operated, an electrical overstress (EOS) event tends to occur continuously due to a low holding voltage, thereby affecting the operation of the internal circuit.

Therefore, how to design and produce normal operation without affecting internal circuits The electrostatic discharge protection circuit device has become one of the most important topics in the industry.

The invention provides an electrostatic discharge protection circuit device, wherein a silicon controlled rectifier (SRC) can be triggered quickly.

The invention provides an electrostatic discharge protection circuit device capable of shortening the distance between the anode and the cathode without affecting the opening speed, thereby saving the layout area.

The present invention provides an ESD protection circuit device that can adjust the collapse speed of a transistor by controlling the distance between the gate and the doped region.

The invention provides an electrostatic discharge protection device comprising a substrate, a well region, a transistor, a third doping region, a fourth doping region, a fifth doping region and a sixth doping region. The substrate has a first conductivity type. The well region has a second conductivity type located in the substrate. The transistor includes a first doped region, a second doped region, and a gate. The first doped region is located in the substrate and extends into the well region. A second doped region is located in the substrate adjacent to the first doped region. The gate is on the substrate between the first doped region and the second doped region. The third doped region has a second conductivity type and is located in the substrate. The fourth doped region has a first conductivity type and is located in the substrate, wherein the third doped region is located between the second doped region and the fourth doped region. The fifth doped region has a first conductivity type and is located in the well region. The sixth doped region has a second conductivity type, located in the well region, wherein the fifth doped region is located between the first doped region and the sixth doped region. The fifth doped region and the sixth doped region are electrically connected to the pad, and the third doped region and the fourth doped region are electrically connected to a ground end.

The invention provides an electrostatic discharge protection device comprising a substrate, a well region, a transistor, a third doping region, a fourth doping region, a fifth doping region and a sixth doping region. The substrate has a first conductivity type. The well region has a second conductivity type located in the substrate. The transistor includes a first doped region, a second doped region, and a gate. The first doped region has a second conductivity type that is located in the substrate and extends into the well region. The second doped region has a first conductivity type, located in the substrate adjacent to the first doped region. The gate is on the substrate between the first doped region and the second doped region. The third doped region has a second conductivity type and is located in the substrate. The fourth doped region has a first conductivity type and is located in the substrate, wherein the third doped region is located between the second doped region and the fourth doped region. The fifth doped region has a first conductivity type and is located in the well region. The sixth doped region has a second conductivity type, located in the well region, wherein the fifth doped region is located between the first doped region and the sixth doped region. The fifth doped region and the sixth doped region are electrically connected to the pad, and the pad is electrically connected to the ground terminal and the gate via a circuit, and the third doped region and the fourth doped region are electrically connected. To the ground, and when an ESD voltage is applied to the pad, the ESD voltage is coupled to the gate.

Based on the above, the electrostatic discharge protection circuit device of the present invention can not only trigger the SRC faster, but also shorten the distance between the anode and the cathode without affecting the opening speed, thereby saving the layout area. Further, in the electrostatic discharge protection circuit device of the present invention, the collapse speed of the transistor can be adjusted by controlling the distance between the gate and the doping region.

The above described features and advantages of the present invention will be more apparent from the following description.

Please refer to FIG. 1A, the electrostatic discharge protection of the present invention. The circuit device includes a well region 11 disposed in the substrate 10, a plurality of first conductive type doped regions (14, 18, 20), a plurality of second conductive type doped regions (12, 16, 22), and a substrate disposed on the substrate Gate 24 on 10. In more detail, the electrostatic discharge protection circuit device of the present invention comprises a substrate 10, a well region 11, a transistor 30 (including a gate 24, a first doped region 12, a second doped region 14), and a third doped region. 16. A fourth doped region 18, a fifth doped region 20, and a sixth doped region 22.

Well zone 11 is located in substrate 10. Substrate 10 is, for example, a semiconductor substrate, such as a germanium substrate, or a semiconductor compound. In an embodiment, the substrate 10 has a first conductivity type; the well region 11 has a second conductivity type. In an embodiment, the first conductivity type is, for example, a P type; and the second conductivity type is, for example, an N type. The P-type dopant is, for example, boron. The N-type doping is, for example, phosphorus or arsenic.

In this embodiment, the indicated transistor 30 is a deformed transistor comprising a gate 24, a first doped region 12, and a second doped region 14. The first doped region 12 has a second conductivity type, located in the substrate 10 and extending into the well region 11. The second doped region 14 has a first conductivity type, located in the substrate 10 adjacent to the first doped region 12 and at a distance. The gate 24 is located on the substrate 10 between the first doped region 12 and the second doped region 14. The material of the gate 24 includes a conductor such as a stacked layer of doped polysilicon, metal germanide or both. A gate dielectric layer 26 is included between the gate 24 and the substrate 10. The gate dielectric layer 26 is, for example, hafnium oxide, tantalum nitride or a high-k dielectric layer having a dielectric constant of more than 4 or more.

The third doping region 16 and the fourth doping region 18 are located adjacent to the second doping region 14 is in the substrate 10 on one side. The third doping region 16 has a second conductivity type; the fourth doping region 18 has a first conductivity type. More specifically, the third doping region 16 is located between the second doping region 14 and the fourth doping region 18. In addition, the third doping region 16 and the fourth doping region 18 are electrically connected to the ground terminal GND. The third doping region 16 and the fourth doping region 18 are electrically connected to each other to the ground GND.

The fifth doping region 20 and the sixth doping region 22 are located in the well region 11 near one side of the first doping region 12. In more detail, the fifth doping region 20 is located between the first doping region 12 and the sixth doping region 22. The fifth doping region 20 has a first conductivity type; the sixth doping region 22 has a second conductivity type. The fifth doped region 20 and the sixth doped region 22 may be electrically connected to the pad 28 to each other.

In addition, the fifth doping region 20 is electrically connected to the pad 28 and serves as an anode of the SCR formed by the third doping region 16, the substrate 10, the well region 11 and the fifth doping region 20; The region 16 is electrically connected to the ground line and serves as a cathode for the SCR formed by the third doping region 16, the substrate 10, the well region 11, and the fifth doping region 20. At the same time, the sixth doping region 22 and the fourth doping region 18 can form a reverse diode to avoid leakage current.

Pad 28 acts as an input and receives an input signal (under normal operation). When an ESD event occurs, the ESD high voltage is applied to pad 28 and triggers the action of the SCR ESD protection circuit. In addition, the pad 28 can be electrically connected to the ground GND via an RC circuit composed of a capacitor C and a resistor R. The gate 24 is electrically connected to the capacitor C and the node A of the resistor R.

Simply put, when the above ESD protection circuit device is operated, when ESD is generated, since the high voltage of ESD is usually high frequency, it will be transparent. The capacitor C of the RC circuit is coupled to the gate 24, that is, the capacitor C assumes a state equivalent to a short circuit. This causes the breakdown voltage of the transistor 30 to drop rapidly, causing the ESD protection circuit to start and protecting the internal circuit. When in normal operation, the capacitance C of the RC circuit becomes an open circuit, and the potential on the gate 24 is substantially a ground voltage, so the transistor 30 acts like a reverse diode and does not collapse, that is, the ESD circuit does not start. Will not affect the operation of internal circuits.

Next, the operation principle of the ESD protection circuit will be described with reference to FIGS. 1B and 1C. FIG. 1B is a schematic diagram showing a current path when the ESD protection circuit operates, and FIGS. 1C and 1D are diagrams showing energy level changes of the transistor 30 before and after the ESD protection circuit is activated.

Referring to FIG. 1B, in one embodiment, the first conductivity type is a P type; and the second conductivity type is an N type. That is, the first doping region 12, the third doping region 16, and the sixth doping region 22 are N ⁺ doping regions, and the second doping region 14, the fourth doping region 18, and the fifth doping region 20 are It is a P ⁺ doped region. That is, the N ⁺ doped region and the P ⁺ doped region are alternately disposed in the substrate 10. The first doped region 12 of the transistor 30 is an N ⁺ doped region, the second doped region 14 is a P ⁺ doped region, and the middle portion (below the gate 24 ) is a portion of the substrate 10 and is P ⁻ (i) In the doped region, the Fermi level (hereinafter referred to as energy level) distribution map of this portion is shown in FIGS. 1C and 1D, wherein FIG. 1C is an energy level distribution of normal operation, and FIG. 1D is an energy level distribution when an ESD event occurs. .

When in normal operation, the energy level diagram of the portion of the transistor 30 is as shown in Fig. 1C, and the potential difference between P ^- (i) and P ⁺ is low (the energy level difference is small), and substantially no potential. In addition, the energy band between P ^- (i) and P ⁺ is wider at this time. Because of the energy bandwidth between the N region and the P region, the tunneling effect is not easily caused, and the current does not substantially tunnel the energy band between P ⁺ and P ^- (i), so the SCR element does not substantially start.

When an ESD event occurs in the pad 28, that is, an ESD high voltage is applied to the gate 24 of the transistor 30 via the RC circuit described above, at this time, the energy level change of the transistor 30 is as shown in FIG. 1D. The energy level of P ^- (i) will decrease, and the energy level of P ⁺ will rise, making the energy band between P ^- (i) and P ⁺ narrow, making the tunneling phenomenon easy, and the current can pass through. With the band, the SCR component will start and operate.

Referring to FIG. 1B, when an ESD event occurs in the pad 28, electrons and holes are generated in the substrate 10 below the gate 24. The electrons flow through the path formed by the N ⁺ -type first doping region 12, the N well region 11 and the N ⁺ sixth doping region 22; the holes flow through the P ⁺ -type second doping region 14, the P-type substrate 10 and a path formed by the P ⁺ -type fourth doping region 18 (first discharge path I), so that current can flow to the ground via the path I.

When the ESD voltage continues to rise, the paths of the N ⁺ -type third doping region 16, the P substrate 10, and the N-type well region 11 (NPN) are turned on, and the P substrate 10, the N-type well region 11, and the P ⁺ -type fifth doping region are turned on. The path of 20 (PNP) is then turned on, and a second discharge path (path II) is established.

In other words, when an ESD event occurs on the pad 28, the high voltage of the ESD is coupled to the gate 24 through the capacitance C of the RC circuit, causing the SCR circuit to be triggered so that current can flow to the ground via paths I, II. . More specifically, the trigger current first flows through path I, and once the SCR (path II) is turned on, the trigger current (path I) will not be present.

In the above embodiment, the gate 24 is adjacent to the second doped region 14 or overlapping. When the ESD protection circuit device is operated, the high voltage of the ESD is coupled to the gate 24 through the capacitor C of the RC circuit, and immediately forms the first doping region 12 and the second doping in the substrate 10 below the gate 24. The passage of the miscellaneous zone 14. However, in another embodiment, the length L of the gate 24 can be shortened to have a distance D from the second doped region 14, as described in Figure 2A.

FIG. 2A illustrates an ESD protection circuit device according to another embodiment of the invention.

Referring to FIG. 2A, in the present embodiment, the ESD protection circuit device also includes a well region 11 disposed in the substrate 10, a plurality of doping regions 12, 14, 16, 18, 20, 22 and disposed on the substrate 10. The gate is 24. In more detail, the electrostatic discharge protection circuit device of the embodiment also includes the well region 11, the transistor 30' (including the gate 24', the gate dielectric layer 26', the first doping region 12, and the second doping region. 14) a third doped region 16, a fourth doped region 18, a fifth doped region 20, and a sixth doped region 22, but the length of the gate 24 is shortened, and there is a gap between the second doped region 14 and the second doped region 14. Distance D. Furthermore, the ESD protection circuit arrangement may further comprise a lightly doped region 142 having the same conductivity as the second doped region 14, in the substrate 10 between the gate 24' and the second doped region 14. The distance D will vary depending on the breakdown voltage of the transistor, and is generally about a few nanometers.

Next, the operation principle of the ESD protection circuit of the second embodiment will be described with reference to Figs. 2B and 2C. 2B and 2C are schematic diagrams showing the depletion region below the gate 24 of the transistor 30 before and after the ESD protection circuit is activated.

Referring to FIG. 2B, first, the case where the gate 24 is normally operated, at this time, the breakdown voltage of the transistor 30 is relatively high. It is assumed that the gate 24 is floating or grounded at this time. In normal operation, the energy level diagram of the portion of the transistor 30 is also as shown in Fig. 1C, and the potential difference between P ^- (i) and P ⁺ is low (the energy level difference is small), and substantially no potential. In addition, the energy band between P ^- (i) and P ⁺ is wider at this time. Due to the potential energy bandwidth between the N region and the P region, the tunneling effect is not easily caused, so the current does not substantially penetrate the energy band between P ⁺ and P ^- (i), so the SCR element does not basically start to operate. .

When an ESD event occurs, that is, when a high voltage is applied to the gate 24, P ^- (i) below the gate 24 is reversed, thereby generating a virtual drain 32, a potential of the drain (N ⁺ ). Will bring the whole to the virtual bungee, the transistor 30 quickly collapses, making the ESD protection circuit work. It is worth mentioning that the distance between the gate 24 and the second doping region 14 can be used to adjust the collapse speed of the transistor 30. When the distance D between the gate 24 and the second doping region 14 is small, the speed at which the transistor 30 collapses is faster. When the distance D between the gate 24 and the second doping region 14 is larger, the transistor 30 collapses at a slower speed. So in this structure, the SCR will crash quickly when an ESD event occurs. In normal operation, the SCR crashes slowly, that is, it crashes according to the condition of the normal component.

The mechanism of the above embodiment includes Early breakdown and tunneling effects, through which the SCR can be triggered quickly within a few nanoseconds. In addition, the length of the gate 24 can be reduced to the depth of the nanometer so that the SCR can be activated within 1 nanosecond.

In the previous description of Figure 1, there is an RC circuit between pad 28, gate 24 and ground GND. In the above description, the simplest capacitor C and resistor R are used for illustration. The use of RC circuits typically uses protection between VDD and GND. This is because the VDD rise rate is slow, so the RC circuit can be used. However, if the input signal rises very quickly at the normal input, it is not easy to distinguish whether it is ESD, so the RC circuit is usually not used.

2D illustrates a circuit application of the electrostatic discharge protection circuit of the present invention.

The VDD control circuit 40 shown in Fig. 2D is an example. Under normal operation, VDD is provided, at which point node A becomes grounded and gate 24 is also grounded. When there is ESD, VDD will float. At this time, the potential of the node A becomes a high potential (H), and this high potential is applied to the gate 24, thereby turning on the SCR.

In summary, since the ESD protection circuit of the embodiment of the present invention is not triggered by the N-type MOS, there is no risk of the N-type MOS being damaged due to the opening of the parasitic NPN diode, so there is no need to use a large Drain contact to gate spacing (DCGS) to avoid junction burns out. The SRC of the ESD protection device of the embodiment of the invention can not only trigger faster, but also shorten the distance between the anode and the cathode without affecting the opening speed, thereby saving the layout area.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Base

11‧‧‧ Well Area

12‧‧‧First doped area

14‧‧‧Second doped area

16‧‧‧ Third doped area

18‧‧‧Four doped area

20‧‧‧ fifth doping area

22‧‧‧ sixth doping area

24, 24' ‧ ‧ gate

26, 26'‧‧‧ gate dielectric layer

28‧‧‧ solder pads

30‧‧‧Optoelectronics

32‧‧‧Virtual bungee

142‧‧‧lightly doped area

40‧‧‧ Circuitry

A‧‧‧ node

C‧‧‧ capacitor

D‧‧‧Distance

R‧‧‧resistance

L‧‧‧ length

FIG. 1A illustrates an ESD protection circuit device according to an embodiment of the invention.

FIG. 1B is a schematic diagram showing a current path when the ESD protection circuit operates, and FIGS. 1C and 1D are diagrams showing energy level changes of the ECD protection circuit before and after startup.

FIG. 2A illustrates an ESD protection circuit device according to another embodiment of the invention.

2B and 2C are schematic diagrams showing the depletion region of the ESD protection circuit below the gate of the transistor before and after startup.

2D illustrates a circuit application of the electrostatic discharge protection circuit of the present invention.

10‧‧‧Base

11‧‧‧ Well Area

12‧‧‧First doped area

14‧‧‧Second doped area

16‧‧‧ Third doped area

18‧‧‧Four doped area

20‧‧‧ fifth doping area

22‧‧‧ sixth doping area

24‧‧‧ gate

26‧‧‧gate dielectric layer

28‧‧‧ solder pads

30‧‧‧Optoelectronics

Claims (19)

An ESD protection circuit device comprising: a substrate having a first conductivity type; a well region having a second conductivity type located in the substrate; and a transistor comprising: a first doped region located in the substrate And extending into the well region; a second doped region is located in the substrate adjacent to the first doped region, wherein the first doped region is different from the second doped region; and a gate on the substrate between the first doped region and the second doped region; a third doped region having a second conductivity type in the substrate; and a fourth doped region having a first conductivity type, located in the substrate, wherein the third doping region is located between the second doping region and the fourth doping region; a fifth doping region having a first conductivity type, located in the well And a sixth doped region having a second conductivity type, located in the well region, wherein the fifth doped region is between the first doped region and the sixth doped region, wherein the first doped region The fifth doped region and the sixth doped region are electrically connected to a pad, and the third doped region and the fourth doped region are electrically connected Connected to a ground terminal. The ESD protection circuit device of claim 1, wherein the gate has a distance from the second doped region. The electrostatic discharge protection circuit as described in claim 2 The device, wherein the transistor further comprises a lightly doped region, the lightly doped region and the second doped region have the same conductivity type, and are located in the substrate between the gate and the second doped region . The electrostatic discharge protection circuit device of claim 1, wherein the gate is adjacent to or overlaps with the second doped region. The electrostatic discharge protection circuit device of claim 1, wherein the sixth doping region, the well region, the first doping region, the second doping region, the substrate, and the fourth doping The zones constitute a first discharge path. The electrostatic discharge protection circuit device of claim 1, wherein the fifth doping region, the well region, the substrate and the third doping region constitute a second discharge path. The electrostatic discharge protection circuit device of claim 1, wherein the first doped region has the second conductivity type. The electrostatic discharge protection circuit device of claim 1, wherein the second doped region has the first conductivity type. The electrostatic discharge protection circuit device according to claim 1, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The ESD protection circuit device of claim 1, wherein the ESD voltage is coupled to the gate when an ESD voltage is applied to the pad. An ESD protection circuit device comprising: a substrate having a first conductivity type; a well region having a second conductivity type located in the substrate, wherein the first conductivity type is different from the second conductivity type; a transistor comprising: a first doped region having a second conductivity type, located in the substrate and extending into the well region; a second doped region having a first conductivity type, located in the substrate, and The first doped region is adjacent to each other; and a gate is disposed on the substrate between the first doped region and the second doped region; a third doped region having a second conductivity type is located at the substrate a fourth doped region having a first conductivity type, located in the substrate, wherein the third doped region is between the second doped region and the fourth doped region; a fifth doping a region having a first conductivity type in the well region; and a sixth doping region having a second conductivity type in the well region, wherein the fifth doping region is located in the first doping region Between the sixth doped regions, wherein the fifth doped region and the sixth doped region are electrically connected to a pad, and the pad is electrically connected to the ground terminal and the gate via a circuit respectively. The third doped region and the fourth doped region are electrically connected to the ground end, and when an ESD voltage is applied to the pad, the ESD voltage is coupled to the gate . The electrostatic discharge protection circuit device according to claim 11, wherein the circuit is an RC circuit composed of a capacitor C and a resistor R, and the gate is electrically connected to a node connected to the capacitor C and the resistor R. The electrostatic discharge protection circuit device of claim 11, wherein the circuit comprises a control circuit. The electrostatic discharge protection circuit device of claim 11, wherein the gate has a distance from the second doped region. The electrostatic discharge protection circuit device of claim 14, wherein the transistor further comprises a lightly doped region having the first conductivity type between the gate and the second doped region. In the substrate. The ESD protection circuit device of claim 11, wherein the gate is adjacent to or overlaps the second doped region. The electrostatic discharge protection circuit device of claim 11, wherein the sixth doping region, the well region, the first doping region, the second doping region, the substrate, and the fourth doping The zones constitute a first discharge path. The electrostatic discharge protection circuit device of claim 11, wherein the fifth doping region, the well region, the substrate and the third doping region constitute a second discharge path. The electrostatic discharge protection circuit device according to claim 11, wherein the first conductivity type is a P type; and the second conductivity type is an N type.