JP2011118970A - Nonvolatile semiconductor memory - Google Patents

Abstract

An object of the present invention is to provide a nonvolatile semiconductor memory device that realizes reduction of current consumption and space saving of a circuit.
A plurality of memory cells formed by a series circuit including a memory element whose state is changed by application of a write voltage and a rectifying element that causes a current flowing from the first wiring to the second wiring through the memory element as a forward direction. A memory cell array having a first voltage, a second voltage lower than the first voltage, a third voltage lower than the second voltage, and a lower voltage than the third voltage; A power supply voltage for generating a fourth voltage whose potential difference from the voltage becomes a writing voltage, and a first voltage is applied to the selected first wiring and a second voltage is applied to the non-selected second wiring at the time of data writing, And a driver circuit that applies a third voltage to the unselected first wiring and a fourth voltage to the selected second wiring, wherein the second voltage is lower than the external power supply voltage.
[Selection] Figure 6

Description

  The present invention relates to a nonvolatile semiconductor memory device using a variable resistance element.

  In recent years, resistance change memory has attracted attention as a successor candidate of flash memory. Here, in the resistance change memory device, in addition to a resistance change memory (ReRAM: Resistance RAM) in a narrow sense that uses a transition metal oxide as a recording layer and memorizes its resistance value in a non-volatile manner, chalcogenide or the like is used as a recording layer to crystallize the resistance change memory device. A phase change RAM (PCRAM) that uses resistance value information of a state (conductor) and an amorphous state (insulator) is also included.

  It is known that the variable resistance element of ReRAM has two kinds of operation modes. One is to set a high resistance state and a low resistance state by switching the polarity of the applied voltage, which is called a bipolar type. The other is to control the voltage value and voltage application time without switching the polarity of the applied voltage, thereby enabling the setting of a high resistance state and a low resistance state, which is called a unipolar type (for example, Non-Patent Document 1).

  In order to realize a high-density memory cell array, a unipolar type is preferable. This is because, in the case of the unipolar type, a cell array can be configured by overlapping a variable resistance element and a rectifier element such as a diode at a cross point between a bit line and a word line without using a transistor. Furthermore, by arranging such cell arrays in a three-dimensional stack, a large capacity can be realized without increasing the cell array area (see, for example, Patent Document 1).

  In the case of a unipolar type ReRAM, data is written to the variable resistance memory by applying a program voltage of, for example, about 4 V (current value is about several tens of nA) to the variable resistance element for 10 ns to 1 μs. As a result, the variable resistance element changes from the high resistance state to the low resistance state. This state change is called “program” or “set”. Further, when an erasing voltage of about 3 V is applied to the variable resistance element in which data is set and a current of 1 μA to 10 μA is applied for several μs, the variable resistance element changes from the low resistance state to the high resistance state. This state change is called “erase” or “reset”.

  In these set operations and reset operations, necessary program voltages and erase voltages are applied to the variable resistance elements connected to the selected word lines and bit lines. On the other hand, a non-selected word line or bit line needs to be applied with a control voltage that is, for example, reverse biased so that the diode does not turn on. At this time, the reverse bias leakage current flowing through each diode is small, but the number of unselected word lines or bit lines is much larger than that of the selected word line or bit line. The current consumption due to the current becomes so large that it cannot be ignored. Further, the voltage applied to the non-selected word line or bit line uses the voltage obtained by boosting the external power supply voltage with a charge pump, similar to the program voltage or erase voltage applied to the selected word line or bit line. Yes. For this reason, if the current consumption due to reverse bias leakage is large, there is a problem that the load of the charge pump increases and the required pump area also increases.

Special table 2006-514392 Y. Hosoi et al, "High Speed Unipolar Switching Resistance RAM (RRAM) Technology" IEEE International Electron Devices Meeting 2006 Technical Digest p.793-796

  In view of the above, it is an object of the present invention to provide a nonvolatile semiconductor memory device that realizes reduction of current consumption and space saving of a circuit.

  A nonvolatile semiconductor memory device according to one embodiment of the present invention includes a plurality of first wirings and second wirings that intersect with each other, and between the first wirings and the second wirings at each intersection of the first wirings and the second wirings. And a series circuit including a memory element whose state is changed by application of a write voltage and a rectifier element that causes a current flowing from the first wiring to the second wiring through the memory element as a forward direction. A memory cell array having a plurality of memory cells, and a first voltage, a second voltage lower than the first voltage, a third voltage lower than the second voltage, and the third voltage by stepping up or down the external power supply voltage A power supply voltage that generates a fourth voltage whose potential difference from the first voltage is the write voltage, and among the plurality of memory cells during data write, Applying the first voltage to a selected first wiring connected to a selected memory cell selected for writing, applying the second voltage to a non-selected second wiring not connected to the selected memory cell, and A driver circuit that applies the third voltage to a non-selected first wiring not connected to a selected memory cell and applies the fourth voltage to a selected second wiring connected to the selected memory cell; The voltage is lower than the external power supply voltage.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device that realizes reduction of current consumption and space saving of a circuit.

1 is a block diagram of a nonvolatile memory according to an embodiment of the present invention. FIG. 4 is a perspective view of a part of the memory cell array of the nonvolatile memory according to the same embodiment. FIG. 3 is a cross-sectional view of one memory cell taken along line II ′ in FIG. 2 and viewed in the direction of the arrow. It is a typical sectional view showing an example of a variable resistance element in the embodiment. 3 is a diagram showing a bias state of the memory cell array in the same embodiment. FIG. 3 is a diagram showing a bias state of the memory cell array in the same embodiment. FIG. FIG. 3 is a system diagram of a power supply circuit of the nonvolatile memory according to the same embodiment. 3 is a diagram showing a bias state of the memory cell array in the same embodiment. FIG. 3 is a circuit diagram of a main row decoder of the nonvolatile memory according to the same embodiment. FIG. 3 is a circuit diagram of a row driver of the nonvolatile memory according to the same embodiment. FIG. FIG. 4 is a diagram showing a well structure of a row driver and its peripheral circuit of the nonvolatile memory according to the same embodiment. 3 is a circuit diagram of a write drive line driver of the nonvolatile memory according to the same embodiment. FIG. 2 is a circuit diagram of a column decoder of the nonvolatile memory according to the same embodiment. FIG. 2 is a circuit diagram of a column driver of the nonvolatile memory according to the same embodiment. FIG. FIG. 3 is a circuit diagram of a sense amplifier / write buffer of the nonvolatile memory according to the same embodiment. FIG. 3 is a circuit diagram of a selected bit line voltage generation circuit of the nonvolatile memory according to the same embodiment. 3 is a circuit diagram of a non-selected word line voltage generation circuit of the nonvolatile memory according to the same embodiment. FIG. 3 is a circuit diagram of a selected word line voltage generation circuit of the nonvolatile memory according to the same embodiment. FIG.

  Hereinafter, embodiments of a nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the drawings.

[overall structure]
FIG. 1 is a block diagram of a nonvolatile memory according to an embodiment of the present invention.

  The nonvolatile memory includes a memory cell array core unit 100 surrounded by a dotted line in FIG. 1 and a power supply circuit 200 that generates and supplies a voltage used for the memory cell array core unit 100.

  The memory cell array core unit 100 includes a memory cell array 110, a row control circuit, and a column control circuit. The memory cell array 110 includes a plurality of word lines WL that are a plurality of second wirings extending in the row direction, a plurality of bit lines BL that are a plurality of first wirings extending in the column direction intersecting the word lines WL, and the word lines WL and It consists of a plurality of memory cells MC provided at each intersection of the bit lines BL. The word lines WL are divided into a predetermined number of groups by the main word line. Similarly, the bit lines BL are also divided into a predetermined number of groups by the column selection lines.

  The memory cell array core unit 100 selects a predetermined memory cell in the memory cell array 110 based on an address signal (Address) and a control signal (Control) supplied from the outside, and performs each of the set / reset / read operations. A row control circuit and a column control circuit to be executed are provided.

  The row-related control circuit includes a main row decoder 120, a row driver 130, a write drive line (WDRV) driver 140, and a row-related peripheral circuit 150. The main row decoder 120 selects a predetermined main word line based on the address signal. The row driver 130 is provided for each main word line, and is necessary for a set operation or the like for a predetermined number of word lines corresponding to the main word line according to the selected / unselected state of the main word line. Supply voltage. The write drive line driver 140 prepares a voltage that the word line driver 130 supplies to the word line based on the address signal. The row-related peripheral circuit 150 includes other necessary row-related circuits.

  On the other hand, the column-related control circuit includes a column decoder 160, a column driver 170, a sense amplifier / write buffer 180, and a column-related peripheral circuit 190. The column decoder 160 selects a predetermined column selection line based on the address signal. The column driver 170 is provided for each column selection line, and performs data input / output with respect to a predetermined number of bit lines corresponding to the column selection line according to the selection / non-selection state of the column selection line. The sense amplifier / write buffer 180 outputs the data input via the data input / output signal (I / O) to the column driver 170 or the data appearing on the bit line received from the column driver 170 as the data input / output signal. Or send it to the outside. The column peripheral circuit 190 has other necessary column circuits.

[Memory cell array]
FIG. 2 is a perspective view of a part of the memory cell array 110, and FIG. 3 is a cross-sectional view of one memory cell taken along the line II 'in FIG.

  A plurality of second lines, word lines WL0-WL2, are arranged in parallel, and a plurality of first lines, bit lines BL0-BL2, are arranged in parallel. Memory cells MC are arranged so as to be sandwiched between both wirings. The first and second wirings are preferably made of a material that is resistant to heat and has a low resistance value. For example, W, WSi, NiSi, CoSi, or the like can be used.

  As shown in FIG. 3, the memory cell MC includes a series connection circuit of a variable resistance element VR and a non-ohmic element NO.

As the variable resistance element VR, the resistance value can be changed by applying voltage, through current, heat, chemical energy, etc., and electrodes EL1 and EL2 functioning as a barrier metal and an adhesive layer are arranged above and below. . As the electrode material, Pt, Au, Ag, TiAlN, SrRuO, Ru, RuN, Ir, Co, Ti, TiN, TaN, LaNiO, Al, PtIrO _x , PtRhO _x , Rh / TaAlN, or the like is used. It is also possible to insert a metal film that makes the orientation uniform. It is also possible to insert a buffer layer, a barrier metal layer, an adhesive layer, etc. separately.

  The variable resistance element VR has a resistance value changed by a phase transition between a crystalline state and an amorphous state, such as chalcogenide (PCRAM), and forms a bridging (conducting bridge) between electrodes by depositing metal cations. Or by changing the resistance value by ionizing the deposited metal and breaking the bridge (CBRAM), or by changing the resistance value by applying voltage or current (ReRAM) (trap in the charge trap existing at the electrode interface) And the like in which the resistance change occurs depending on the presence or absence of the generated charge, and the one in which the resistance change occurs depending on the presence or absence of the conduction path caused by oxygen deficiency or the like.

FIG. 4 is a diagram illustrating an example of the ReRAM. The variable resistance element VR shown in FIG. 4 has a recording layer 12 disposed between electrode layers 11 and 13. The recording layer 12 is composed of a composite compound having at least two kinds of cationic elements. At least one of the cation elements is a transition element having a d orbital incompletely filled with electrons, and the shortest distance between adjacent cation elements is 0.32 nm or less. Specifically, it is represented by the chemical formula AxMyXz (A and M are mutually different elements). For example, spinel structure (AM ₂ O ₄ ), ilmenite structure (AMO ₃ ), delafossite structure (AMO ₂ ), LiMoN ₂ structure ( AMN ₂ ), wolframite structure (AMO ₄ ), olivine structure (A ₂ MO ₄ ), hollandite structure (A _x MO ₂ ), ramsdellite structure (A _x MO ₂ ), perovskite structure (AMO ₃ ), etc. Consists of the materials it has.

  In the example of FIG. 4, A is Zn, M is Mn, and X is O. Small white circles in the recording layer 12 represent diffusion ions (Zn), large white circles represent anions (O), and small black circles represent transition element ions (Mn). The initial state of the recording layer 12 is a high resistance state, but when a fixed potential is applied to the electrode layer 11 and a negative voltage is applied to the electrode layer 13 side, some of the diffused ions in the recording layer 12 move to the electrode layer 13 side. As a result, the diffusion ions in the recording layer 12 decrease relative to the anions. The diffused ions that have moved to the electrode layer 13 side receive electrons from the electrode layer 13 and are deposited as metal, so that the metal layer 14 is formed. Inside the recording layer 12, anions become excessive, and as a result, the lower layer of transition element ions in the recording layer 12 is raised. As a result, the recording layer 12 has electron conductivity by carrier injection, and the setting operation is completed. For reproduction, it is sufficient to pass a minute current value that does not cause a change in resistance of the material constituting the recording layer 12. In order to reset the program state (low resistance state) to the initial state (high resistance state), for example, a large current is allowed to flow through the recording layer 12 for a sufficient period of time to promote the oxidation-reduction reaction of the recording layer 12. good. The reset operation can also be performed by applying an electric field in the direction opposite to that at the time of setting. Hereinafter, the voltage necessary for the set operation and the voltage necessary for the reset operation are referred to as “write voltage”.

  5 and 6 are diagrams showing a bias state of the memory cell array during the set / reset operation in the present embodiment. Here, a case where the memory cell MC ′ surrounded by a dotted line in FIG. 5 is set / reset will be described as an example.

  As shown in FIG. 5, a bit line BL ′ (hereinafter referred to as “selected bit line”) connected to the selected memory cell MC ′ and a word line WL (hereinafter referred to as “non-selected”) not connected to the selected memory cell MC ′. Word line ”), bit line BL not connected to the selected memory cell MC ′ (hereinafter referred to as“ non-selected bit line ”), and word line WL ′ (hereinafter referred to as“ non-selected bit line ”). The selected bit line voltage VWR as the first voltage, the unselected word line voltage VUX as the second voltage, the unselected bit line voltage VUB as the third voltage, and the fourth voltage, respectively. The selected word line voltage VSSROW is applied.

  Here, the selected bit line voltage VWR is higher than the selected word line voltage VSSROW by a write voltage (for example, 4.0 V). As a result, the selected memory cell MC ′ is set / reset because the write voltage is applied in the forward direction of the diode Di. The unselected word line voltage VUX is higher than the unselected bit line voltage VUB. As a result, the voltage “VUX−VUB” is applied to the memory cell MC (hereinafter referred to as “non-selected memory cell”) connected to the non-selected word line WL and the non-selected bit line BL in the reverse direction of the diode Di. Therefore, no set / reset occurs. The unselected word line voltage VUX is lower than the selected bit line voltage VWR by a voltage equal to or lower than VF (for example, 0.8 V) of the diode Di of the memory cell MC. Similarly, the unselected bit line BL is higher than the selected word line voltage VSSROW by a voltage equal to or lower than VF of the diode Di of the memory cell MC. Thus, the memory cells MC connected to the unselected word lines WL and the selected bit lines BL ′ or the memory cells MC connected to the selected word lines WL ′ and the unselected bit lines BL (hereinafter referred to as “half-selected memory cells”). Is not biased in excess of VF in the forward direction of the diode Di, and therefore no set / reset occurs. The selected word line voltage VSSROW is a voltage obtained by stepping down the ground voltage VSS and becomes a negative voltage (for example, −0.8 V).

  Next, current consumption in the bias state shown in FIGS. 5 and 6 will be described. As can be seen from FIG. 5, most of the plurality of memory cells MC are non-selected memory cells. Accordingly, it can be said that most of the consumption current occupying the entire nonvolatile memory is the off-leakage current in the reverse direction generated by the non-selected memory cells.

  Here, if the write voltage is 4.0 V and the VF of the diode Di is 0.8 V, the selected bit line voltage VWR is 4.0 V based on the ground voltage VSS (0 V) that is the selected word line voltage in the conventional case. The unselected word line voltage VUX is 3.2V, and the unselected bit line voltage VUB is 0.8V.

  In this case, considering that the general external voltage VCC is 2.7 V to 3.3 V, it is necessary to boost the external voltage VCC in order to obtain the selected bit line voltage VWR. In consideration of the influence of the voltage drop and the like, in order to surely obtain the unselected word line voltage VUX, the selected bit line voltage VWR generated by the charge pump is stepped down by the regulator to reduce the unselected word line voltage VUX. Must be generated. That is, it is necessary to consider the pump efficiency of the charge pump for the off-leak current of the unselected memory cell MC that receives the supply of the unselected word line voltage VUX. That is, when the pump efficiency is 50%, the current consumption caused by the off-leakage current of the non-selected memory cell MC is doubled, that is, the current consumption of the entire nonvolatile memory is increased by about twice. Furthermore, since the number of memory cells that can be accessed simultaneously is limited due to an increase in current consumption, a decrease in data throughput also becomes a problem. Further, the circuit area increases as the charge pump load increases.

  Therefore, in the present embodiment, the unselected bit line voltage VUB is maintained while maintaining the bias relationship among the conventional selected bit line voltage VWR, unselected word line voltage VUX, unselected bit line voltage VUB, and selected word line voltage VSSROW. Is shifted in the negative direction as a whole so that becomes less than or equal to the external power supply voltage VCC.

  In this case, as shown in FIG. 7, the unselected word line voltage VUX can be directly converted from the external power supply voltage VCC by a regulator. That is, since it is not necessary to drive the off-leak current of the non-selected memory cell MC that occupies most of the consumption current by the charge pump, the load current of the charge pump can be suppressed.

  In the case of this embodiment, the selected word line voltage VSSROW needs to be stepped down from the ground voltage VSS by a charge pump, which is not conventional, so it may be necessary to consider when calculating the consumption current. . However, the load of the unselected word line voltage VUX when the unselected word line voltage VUX is generated by the charge pump is on the order of mA, whereas the selected word line voltage when the selected word line voltage VSSROW is generated by the charge pump. Since the VSSROW load is on the order of μA, it can be considered that the influence on the current consumption is extremely small.

  Furthermore, since the load current of the charge pump is reduced, the charge pump can be reduced in size, and the circuit area can be reduced accordingly.

  Here, the current consumption of the memory cell array shown in FIG. 8 will be considered as a more specific memory cell array. The memory cell array shown in FIG. 8 is divided into unit memory cell arrays (hereinafter referred to as “MAT”) every 36.2 M bits, and word lines WL and bit lines BL are shared between adjacent MATs. That is, the word lines WL are alternately shared between the left and right adjacent MATs in the figure, and the bit lines BL are alternately shared between the upper and lower adjacent MATs in the figure. FIG. 8 also shows a bias state when two memory cells MC ′ and MC ″ in MAT <4> are selected. The bit line BL and the word line WL that are not shared with MAT <4> are in a floating state (F).

  In the case of a memory cell array having such a structure, the current consumption can be expressed as “off-leak current of diode in reverse bias state of selected MAT × number of selected MAT × shared coefficient of adjacent MAT”.

  When one MAT <4> is selected, MAT <5> sharing the selected word line WL ′ connected to the selected memory cells MC ′ and MC ″, connected to the selected memory cells MC ′ and MC ″. For MAT <1> and MAT <7> that share selected bit lines BL ′ and BL ″, there are unselected memory cells MC corresponding to 1/2 of 36.2 Mbits. Further, unselected memory cells MC corresponding to 1/4 of 36.2 Mbits exist for MAT <2> and MAT <8> sharing the bit line BL with MAT <5>. Therefore, by selecting the two memory cells MC ′ and MC ″ of MAT <4>, there are approximately 36.2 Mbit × 3 non-selected memory cells.

  Therefore, assuming that the off-leakage current generated in one diode Di in the reverse bias state is 10 pA, an off-leakage current of about 1.1 mA is generated.

  In this case, when the unselected word line voltage VUX is boosted by the charge pump as in the prior art, it is necessary to consider the pump efficiency of this charge pump to 1.1 mA. For example, when the pump efficiency is 50%, it becomes about 2.2 mA. On the other hand, in the case of this embodiment, since it is not necessary to consider the pump efficiency, it can be halved to about 1.1 mA.

  Hereinafter, a row control circuit, a column control circuit, and a power supply circuit that realize the bias relationship as shown in FIGS. 5 and 6 will be described. An example in which the memory cell array 110 includes memory cells MC of 2K bits (= 2048 bits) in the word line direction and 512 bits in the bit line direction will be described.

[Row control circuit]
First, the main row decoder 120 will be described.

  FIG. 9 is a circuit diagram of the main row decoder 120. The main row decoder 120 is a predecoder and receives a row address and selects one of 256 pairs of main word lines MWLx and MWLbx (x = <255: 0>). The main row decoder 120 includes the circuit shown in FIG. 9 for each of the 256 pairs of main word lines MWLx and MWLbx. As shown in FIG. 9, one main row decoder 120 receives an NAND gate G121 that receives an address signal (Address), a level shifter L / S that shifts the output of the NAND gate G121, and an output of the level shifter L / S. The inverter IV121 is an input, and the inverter IV122 is an output of the inverter IV121. Here, the outputs of the inverters IV121 and IV122 are the main word lines MWLx and MWLbx, respectively.

  The main row decoder 120 selects a predetermined x based on an address signal (Address), supplies voltages VSSROW (“H”) and VWR (“L”) to the selected main word lines MWLx and MWLbx, Voltages VWR and VSSROW are supplied to unselected main word lines MWLx and MWLbx, respectively.

  Next, the row driver 130 will be described.

  FIG. 10 is a circuit diagram of the row driver 130. One of the 256 pairs of main word lines MWLx and MWLbx (x = <255: 0>) is input to the row driver 130. Eight row drivers 130 are provided for one main row decoder 120. As shown in FIG. 10, the row driver 130 is provided between the write drive lines WDRV <7: 0> and the word lines WLx <7: 0>, and is controlled by the main transistors MWLbx and MWLx, respectively. , QN131, and a transistor QP132 provided between the power supply line of the unselected word line voltage VUX and the word line WLx <7: 0> and controlled by the main word line MWLx.

  The row driver 130 selects either the write drive line WDRV <7: 0> or the power supply line of the unselected word line voltage VUX and the word line WLx <7 according to the selected / unselected state of the main word line MWLx. : 0> is connected. As a result, either the selected word line voltage VSSROW or the unselected word line voltage VUX is supplied to the word lines WLx <7: 0>.

  The row driver 130 is formed in common on a P-type substrate having the same first conductivity type as other peripheral circuits, but the selected word line voltage VSSROW (for example, −0.8 V) that becomes a negative voltage. In order to obtain the above, the triple well structure shown in FIG. 11 is provided. Specifically, there is a P-type substrate having a ground voltage VSS as a well voltage, and an N-type well of the second conductivity type having a non-selected word line voltage VUX as a well voltage on the P-type substrate. A P-type well having a selected word line voltage VSSROW as a well voltage is sequentially formed on the well, and an NMOS transistor is formed on the P-type well.

  Next, the write drive line driver 140 will be described.

  FIG. 12 is a circuit diagram of the write drive line driver 140. The write drive line driver 140 is a predecoder. The write drive line circuit 140 includes a NAND gate G141 that receives an address signal (Address), a level shifter L / S that shifts the output of the NAND gate G141, and an inverter IV141 that receives the output of the level shifter L / S. Composed. The inverter IV141 is provided between the unselected word line voltage VUX and the selected word line voltage VSSROW, and its output is connected to the write drive line WDRV.

  The write drive line circuit 140 supplies the selected word line voltage VSSROW to the write drive line WDRV <127: 0> corresponding to the input address signal, and unselected words to the other write drive lines WDRV <127: 0>. Supply line voltage VUX. The voltage of the write drive line WDRV is supplied to the word line WLx via the row driver 130.

  The main row decoder 120, the row driver 130, and the write drive line driver 140 having the above configuration supply the selected word line voltage VSSROW only to the word line WLx selected by the address signal, and the other word lines WL are not selected. The word line voltage VUX is supplied.

[Column control circuit]
First, the column decoder 160 will be described.

  FIG. 13 is a circuit diagram of the column decoder 160. The column decoder 160 receives a column address and selects one of 128 pairs of column selection lines CSLy and CSLby (y = <127: 0>). Note that the column decoder 160 has a circuit as shown in FIG. 13 for each of 128 pairs of column selection lines CSLy and CSLby. As shown in FIG. 13, one column decoder 160 receives a NAND gate G161 that receives an address signal (Address), a level shifter L / S that level-shifts the output of the NAND gate G161, and outputs the output of the level shifter L / S. The inverter IV161 is an input and the inverter IV162 is an output of the inverter IV161. Here, the outputs of the inverters IV161 and IV162 are column selection lines CSLy and CSLby, respectively.

  The column selection line 160 selects a predetermined y based on an address signal (Address), and supplies voltages VWR (“H”) and VSS (“L”) to the selected column selection lines CSLy and CLLby, Voltages VSS and VWR are supplied to unselected column selection lines CSLy and CSLby, respectively.

  Next, the column driver 170 will be described.

  FIG. 14 is a circuit diagram of the column driver 170. Any one of 128 pairs of column selection lines CSLy and CSLby (y = <127: 0>) is input to the column driver 170. Eight column drivers 170 are provided for one column decoder 160. As shown in FIG. 14, the column driver 170 is provided between the local data lines LDQ <7: 0> and the bit lines BLy <7: 0>, and is controlled by the column selection lines CSLy and CSLby, respectively. , QN171 and a transistor QN172 provided between the power supply line of the unselected bit line voltage VUB and the bit line BLy <7: 0> and controlled by the column selection line CSLby.

  The column driver 170 connects the power line of the local data line LDQ <7: 0> / unselected bit line voltage VUB and the bit line BLy according to the selection / non-selection state of the column selection line CSCy. Here, the voltage of the local data line LDQ <7: 0> is a voltage VSS corresponding to the selected bit line voltage VWR or the unselected bit line voltage VUB supplied from the sense amplifier / write buffer 180. As a result, either the selected bit line voltage VWR or the unselected bit line voltage VUB is supplied to the bit lines BLy <7: 0>.

  Next, the sense amplifier / write buffer 180 will be described.

  FIG. 15 is a circuit diagram of the sense amplifier / write buffer 180. The sense amplifier / write buffer 180 is roughly composed of a sense amplifier 181 and a write buffer 182.

  The sense amplifier 181 detects and amplifies the data of the memory cell MC appearing on the local data line LDQ <7: 0> to be transmitted to the outside via the latch circuit LAT and the data input / output line I / O <7: 0>. Circuit. The sense amplifier 182 is activated by a read enable signal 181 (not shown). The sense amplifier 181 can be of various types such as a single end type or a differential type using a reference cell.

  The write buffer 182 includes a level shifter L / S for level-shifting data input via the data input / output lines I / O <7: 0> and the latch circuit LAT <7: 0>, and the level shifter L / S The inverter IV181 has an output as an input and a local data line LDQ <7: 0> as an output. The inverter IV181 is activated by the write enable signals WE and WEb. When the data is “1” in accordance with the write data input via the data input / output lines I / O <7: 0> and the latch circuit LAT, the write buffer 182 uses the local data line LDQ <7. : 0> is supplied with the ground voltage VSS, and when the data is “0”, the write voltage VWR is supplied to the local data line LDQ <7: 0>. The write buffer 182 is activated by the write enable signal WE.

  The column decoder 160, the column driver 170, and the sense amplifier / write buffer 180 having the above configuration supply the selected bit line voltage VWR only to one bit line BLy selected by the address signal during the set operation, and other bits. The unselected bit line voltage VUB is supplied to the line BLy.

[Power supply circuit]
The power supply circuit 200 boosts the external power supply voltage VCC, selects a selected word line voltage generation circuit 210 that generates a selected bit line voltage VWR, adjusts the external power supply voltage VCC, and generates an unselected word line voltage VUX. The voltage generation circuit 220 includes a selection word line voltage generation circuit 240 that steps down the ground voltage VSS and generates a selection word line voltage VSSROW.

  First, the write voltage generation circuit 210 will be described.

  FIG. 16 is a circuit diagram of the selected bit line voltage generation circuit (charge pump) 210. The selected bit line voltage generation circuit 210 includes three transistors QN211 to QN213 connected in series between an input (external power supply voltage VCC) and an output terminal (selected bit line voltage VWR). These three transistors QN211 to QN213 are in diode connection with the input side serving as an anode and the output side serving as a cathode. The selected bit line voltage generation circuit 210 includes capacitors C211 and C212, one end of which is connected to the drain side of the transistors QN211, QN212, and QN213 and the other end connected in common, and a limiter circuit (Limiter).

  The selected bit line voltage generation circuit 210 accumulates the charge supplied from the external power supply voltage VCC in the capacitor C211, and further accumulates the charge and the charge supplied from the external power supply voltage VCC in the capacitor C241 in a superimposed manner. . By discharging the charge accumulated in the capacitor C212, a selected bit line voltage VWR higher than the external power supply voltage VCC can be obtained. The output of the selected bit line voltage generation circuit 210 is limited by the limiter circuit so as not to exceed the selected bit line voltage VWR.

  Next, the unselected word line voltage generation circuit 220 will be described.

  FIG. 17 is a circuit diagram of the unselected word line voltage generation circuit 220. The unselected word line voltage generation circuit 220 includes a PMOS transistor QP221, a variable resistor R221, and a fixed resistor R222 connected in series between the external power supply voltage VCC and the ground line. In addition, an operational amplifier OP221 is provided in which a voltage at a connection point between the resistors R221 and R222 is input to the non-inverting input terminal, and a predetermined reference voltage VREF for generating the unselected word line voltage VUX is input to the inverting input terminal. The output of the operational amplifier OP221 is input to the gate of the transistor QP221. The non-selected word line voltage generation circuit 220 forms a constant voltage circuit as described above, and the non-selected word line voltage VUX is generated at the connection point of the transistor QP221 and the resistor 221 in this circuit.

  Next, the selected word line voltage generation circuit 240 will be described.

  FIG. 18 is a circuit diagram of the selected word line voltage generation circuit (charge pump) 240. The selected word line voltage generation circuit 240 includes three transistors QN241 to QN243 connected in series between an input (ground voltage VSS) and an output (selected word line voltage VSSROW). Each of these three transistors QN241 to QN243 has a diode connection in which the input side is a cathode and the output side is an anode. The selected word line voltage generation circuit 240 includes capacitors C241 and C242 having one end connected to the source side of the transistors QN241, QN242 and QN243 and the other end connected in common, and a limiter circuit (Limiter). .

  The selected word line voltage generation circuit 240 accumulates the charge supplied from the selected word line voltage VSSROW in the capacitor C242, and further accumulates the charge and the charge supplied from the ground voltage VSSROW in the capacitor C241 in a superimposed manner. . By discharging the charge accumulated in the capacitor C241 to the ground voltage VSS side, the selected word line voltage VSSROW which is a negative voltage can be obtained.

  As described above, according to the present embodiment, since a charge pump is not used to generate a non-selected word line voltage, an increase in current consumption due to the effect of pump efficiency can be suppressed. Further, since the load of the charge pump can be reduced, the charge pump can be formed small, and the chip area can be reduced.

  DESCRIPTION OF SYMBOLS 11, 13 ... Electrode layer, 12 ... Recording layer, 14 ... Metal layer, 100 ... Memory cell array core part, 110 ... Memory cell array, 120 ... Main row decoder, 130 ... Row driver 140 ... Write drive line driver 150 ... Row system peripheral circuit 160 ... Column decoder 170 ... Column driver 180 ... Sense amplifier / write buffer 181 ... Sense amplifier, 182... Write buffer, 190... Column system peripheral circuit, 200... Power supply circuit, 210... Selected bit line voltage generation circuit, 220. ... Selected word line voltage generation circuit.

Claims (5)

A plurality of first wirings and second wirings that intersect each other, and a memory that is connected between the first wirings and the second wirings at each intersection of the first wirings and the second wirings, and whose state is changed by application of a write voltage A memory cell array having a plurality of memory cells formed by a series circuit including an element and a rectifying element that causes a current flowing from the first wiring to the second wiring through the memory element as a forward direction;
Boosting or stepping down the external power supply voltage, the first voltage, the second voltage lower than the first voltage, the third voltage lower than the second voltage, and lower than the third voltage, A power supply voltage for generating a fourth voltage at which the potential difference of
At the time of data writing, the first voltage is applied to the selected first wiring connected to the selected memory cell selected for data writing among the plurality of memory cells, and the non-selected not connected to the selected memory cell The second voltage is applied to the second wiring, the third voltage is applied to the non-selected first wiring not connected to the selected memory cell, and the fourth voltage is applied to the selected second wiring connected to the selected memory cell. A driver circuit for applying
The nonvolatile semiconductor memory device, wherein the second voltage is lower than the external power supply voltage. The nonvolatile semiconductor memory device according to claim 1, wherein the fourth voltage is a negative voltage. The nonvolatile semiconductor memory device according to claim 1, wherein the power supply circuit boosts the external power supply voltage to generate the first voltage. The nonvolatile semiconductor memory device according to claim 1, wherein the third voltage is a ground voltage. The driver circuit includes a triple well including a first conductivity type substrate, a second conductivity type well formed on the first conductivity type substrate, and a first conductivity type well formed on the second conductivity type well. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device has a structure.

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