JP2011118963A - Data transfer device and semiconductor test device - Google Patents

Abstract

An object of the present invention is to make the arrangement of data in a data storage unit that stores data to be transferred coincide with that of a device to be transferred and a data holding unit in the device, and to increase the data transfer speed.
A data transfer device (1) for connecting a plurality of transfer target devices (2) having a plurality of registers (R) and serially transferring data to each transfer target device (2). A RAM 13 that arranges and stores data to be stored in order, a master address storage unit 16 that stores and arranges addresses for reading data from the RAM 13 in the order of the register R in the order of the transfer target device 2, and a master address An address counter 15 that performs address designation for the storage unit 16 by incrementing, and a plurality of transfer units 14 that transfer data read from the RAM 13 to the transfer target device 2 are provided.
[Selection] Figure 1

Description

  The present invention relates to a data transfer apparatus for transferring data between apparatuses and a semiconductor test apparatus including the data transfer apparatus.

  As a method of transferring data between apparatuses, parallel transfer and serial transfer are mainly used. In parallel transfer, a large number of data can be transferred at the same time. However, serial transfer has been used in recent years because the data to be transferred must be synchronized.

  FIG. 7 shows an example of a conventional data transfer apparatus that performs serial transfer between apparatuses. As shown in this figure, N (N is a natural number) transferred devices 102-1 to 102-N (collectively transferred devices 102) are connected to the data transfer device 101. Data is serially transferred to the transfer target device 102. The data transfer apparatus 101 and each transferred apparatus 102 are connected by serial transfer paths 103-1 to 103-N (collectively, serial transfer paths 103) for serially transferring data. A control device 104 that controls the operation of the data transfer apparatus 101 is connected to the data transfer apparatus 101.

  The transfer target device 102 is a transfer destination of data from the data transfer device 101. Each transferred device 102 is provided with M (M is a natural number) registers R1 to RM (collectively, register R), and data transferred to the transferred device 102 is stored in each register R. . Each transferred device 102 and the register R in the transferred device 102 are numbered. That is, the transfer target devices 102 are numbered in order from 102-1 to 102-N, and as shown in FIG. 8B, the registers R in the transfer target device 102 are sequentially from R1 to RM. Numbered.

  The data transfer apparatus 101 includes a controller 111, an address counter 112, a RAM 113, N transfer units 114-1 to 114 -N (collectively transfer unit 114), and an enable signal generating unit 115. The control device 104 includes a trigger generator 121 and a selection signal generator 122, and is schematically configured.

  The controller 111 controls the operation of the address counter 112 and starts the operation of the address counter 112 at the timing of the trigger signal output from the control device 104. The address counter 112 designates the address of data read from the RAM 113. For this reason, the address counter 112 stores the start address of the RAM 113 as an initial value, and sequentially designates the designated address from the start address.

  The RAM 113 stores data to be transferred to each transfer target device 102, and reads and outputs the address data output from the address counter 112. Since the data to be transferred becomes M registers R for the N devices to be transferred 102, the number thereof is N × M. Here, N × M pieces of data are stored in order of address from the top address of the RAM 113.

  At this time, the data stored in the RAM 113 is arranged in the order of the registers R in the order of the transfer target device 102. FIG. 8A shows an arrangement of data stored in the RAM 113, and N × M pieces of data (Data) are arranged in order from the head address. Each data is divided into N data groups, which are arranged in order from the first data group to the Nth data group. Each data group is composed of M pieces of data, and each data is also arranged in numerical order. Each data has two identifiers “X” and “Y”, and is DataX−Y (1 ≦ X ≦ N, 1 ≦ Y ≦ M: X and Y are natural numbers). “X” of DataX-Y indicates a data group, and “Y” indicates data constituting the data group.

  As shown in FIG. 8B, the data group corresponds to the transfer target device 102, and each data constituting the data group corresponds to the register R. That is, “X” indicates the order of the transfer target device 102, and “Y” indicates the order of the register R in the transfer target device 102. As a result, the arrangement order of the transferred device 102 and the arrangement order of the registers R constituting the transferred device 102 are matched with the arrangement order of the data group stored in the RAM 113 and the arrangement order of the data constituting the data group. be able to. That is, the images in the order of arrangement can be made the same.

  Each of the N transfer units 114 is connected to the serial transfer path 103 and outputs data to the serial transfer path 103. Data is input from the RAM 113 to each transfer unit 114, and this data is parallel data. For this reason, the transfer unit 114 converts parallel data into serial data and outputs the data to the serial transfer path 103.

  The enable signal generation unit 115 in FIG. 7 has two functions, the first is a function for specifying the transfer unit 114 to be operated, and the second is a function for preventing data that does not need to be transferred from being transferred. It is. First, a function for specifying the transfer unit 114 will be described. The address designated by the RAM 113 is input from the address counter 112 to the enable signal generation unit 115, and which transfer unit 114 performs the transfer operation based on this address. The enable signal generator 115 outputs an enable signal only to the specified transfer unit 114, and the transfer unit 114 performs a transfer operation based on the enable signal.

  In addition to the address, the enable signal generator 115 receives a selection signal from the selection signal generator 122. The selection signal is a signal indicating whether or not to transfer each data stored in the RAM 13. When the address input from the address counter 112 is compared with the selection signal, if the selection signal corresponding to the address indicates that transfer is to be performed, an enable signal is output, and if it indicates that no transfer is performed Outputs an enable signal. This avoids transferring unnecessary data.

  The operation in the above configuration will be described. The trigger generation unit 121 of the control device 104 outputs a trigger signal to the controller 111, and the controller 111 causes the address counter 112 to output the address of the RAM 113 based on the trigger signal. Since the initial value of the address counter 112 is the top address of the RAM 113, the data read out first is Data1-1.

  The address is also input to the enable signal generation unit 115, and the transfer unit 114 to be operated is specified based on the address. In the case of the head address, it becomes the transfer unit 114-1. Therefore, Data 1-1 read from the RAM 113 is output from the transfer unit 114-1 to the serial transfer path 103-1, and data is serially transferred to the transfer target device 102-1. Then, Data1-1 is stored in the register R of the transferred device 102-1.

  The address counter 112 outputs an address incremented from the head address. Data is sequentially read from the RAM 113 and the data input by the transfer unit 114 is sequentially transferred to the transfer target device 102. Then, when the last DataN-M transfer is completed, the transfer of all data (M × N data) stored in the RAM 113 is completed. As a technique for performing serial transfer in this way, for example, there is a technique disclosed in Patent Document 1.

JP 2001-43697 A

  As shown in FIGS. 8A and 8B, the arrangement of data stored in the RAM 113 matches the arrangement order of the transfer target device 102 and the register R. As a result, it is possible to quickly and clearly grasp which data stored in the RAM 113 corresponds to the register R of the transfer target device 102. Therefore, when data is stored in the RAM 113, when the stored data is changed, when the data is referred to, the target data can be specified very easily.

  As shown in FIG. 8A, each piece of data constituting one data group of the RAM 113 is stored at successive addresses, and the address from which data is read is designated by increment, so that one piece of data M pieces of data in the group are read continuously. That is, data to be transferred to M registers R in one transferred device 102 is continuously read.

  Therefore, M pieces of data are continuously input to one transfer unit 114, and the transfer unit 114 outputs M pieces of data to the serial transfer path 103 continuously to perform data transfer. For this reason, the data transferred to one serial transfer path 103 is concentrated, and the next data cannot be transferred until the transfer of one data is completed. As a result, the next data cannot be read from the RAM 113, and the next data must be waited.

  That is, despite having N serial transfer paths 103, only one of the N serial transfer paths 103 is in a transfer operation state, and the transfer efficiency is extremely low. Become. Therefore, the reading speed of the RAM 113 is very low depending on the transfer speed of the serial transfer path 103. For this reason, the overall transfer rate is significantly reduced.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to make the data arrangement of the data storage unit for storing the data to be transferred coincide with the device to be transferred and the data holding unit in the device, and to increase the data transfer speed. .

  In order to solve the above problems, a data transfer device according to claim 1 of the present invention connects a plurality of transfer target devices having a plurality of data holding units for holding transferred data, and transmits data to each transfer target device A data transfer device for serial transfer, wherein the data is stored in the order of the data holding unit in order of the transfer target device, and an address for reading the data from the data storage unit Read out from the data storage unit, a master address storage unit that stores data in the order of the transferred devices in order of the data holding unit, an address counter that performs address designation for the master address storage unit by increment A plurality of transfer units for transferring the transferred data to the transfer target device.

  According to this data transfer device, since the arrangement of data stored in the data storage unit matches the order of the transfer target device and the data holding unit, data handling becomes extremely easy. Since the data read from the data storage unit is sequentially output to each transfer unit, data transfer from each transfer unit can be performed in parallel, and the data transfer speed can be increased.

  A data transfer device according to a second aspect of the present invention is the data transfer device according to the first aspect, wherein the data transfer device is provided between the master address storage unit and the data storage unit, and the master address storage unit stores the data. The apparatus further comprises a selection address storage unit for sequentially arranging and storing addresses excluding addresses not transferred to the transfer target device from existing addresses.

  According to this data transfer device, since data excluding data not to be transferred is stored in the selected address storage unit, only the data that needs to be transferred is read and transferred to the device to be transferred. . For this reason, the data transfer rate can be further increased.

  A data transfer device according to a third aspect of the present invention is the data transfer device according to the second aspect, wherein the addresses stored in the master address storage unit are read in order from the top and stored in the selected address storage unit. In some cases, the information processing apparatus further includes a selection address control unit that performs control for prohibiting a storage operation to the selection address storage unit when an address that is not transferred is read.

  According to this data transfer device, the address of the data storage unit read in order from the head address of the master address storage unit is unnecessary for the selected address storage unit by prohibiting the storage operation when the data address is not transferred. It is possible to store addresses excluding the addresses of various data.

  A data transfer device according to a fourth aspect of the present invention is the data transfer device according to the third aspect, wherein an operation of transferring data from the transfer unit to the transfer target device and the master address storage unit to the selected address storage unit It is characterized in that it overlaps with the operation of storing the address.

  According to this data transfer apparatus, since the operation for storing data in the selected address storage unit is overlapped with the data transfer operation, the transfer time as a whole can be further shortened.

  The data transfer device according to claim 5 of the present invention is the data transfer device according to claim 1, wherein data is transferred from the transfer unit to the transfer target device, and an address is stored in the master address storage unit. And are overlapped with each other.

  According to this data transfer apparatus, since the operation for storing data in the master address storage unit overlaps the data transfer operation, the transfer time as a whole can be further shortened.

  A semiconductor test apparatus according to a sixth aspect of the present invention includes the data transfer apparatus according to any one of the first to fifth aspects.

  The data transfer apparatus described above can be used in a semiconductor test apparatus. For example, in a memory tester for testing a memory, the test is performed by connecting the memory tester to a plurality of pins provided in the memory and transferring data to each pin. The data transfer device described above can be applied to such a memory tester.

  According to the present invention, the data stored in the data storage unit is matched with the arrangement order of the device to be transferred and the data holding unit, so that the handling of the data becomes extremely simple. Since data read from the data storage unit is sequentially output to each transfer unit, data transfer is performed in parallel from each transfer unit, so that the data transfer rate can be increased. become.

It is a block diagram which shows schematic structure of the data transfer apparatus of embodiment. It is a figure which shows the structure of the to-be-transferred apparatus and register | resistor of FIG. It is a figure which shows the arrangement | sequence of a master address memory | storage part, a selection address memory | storage part, and RAM. It is a time chart which shows the 1st comparative example. It is a time chart which shows the 2nd comparative example. It is a time chart which shows the 3rd comparative example. It is a block diagram which shows schematic structure of the conventional data transfer apparatus. It is a figure for demonstrating the relationship between the arrangement | sequence of the data memorize | stored in RAM of FIG. 7, a to-be-transferred apparatus, and a register.

  Embodiments of the present invention will be described below with reference to the drawings. The data transfer apparatus described below will be described as an example applied to a semiconductor test apparatus, particularly a semiconductor test apparatus that functions as a memory tester for testing a memory. Of course, the data transfer apparatus of the present invention can also be applied to a semiconductor test apparatus for testing a device under test such as an IC or LSI other than a memory. Further, the present invention can be applied to any device other than a semiconductor test device as long as it is a device that serially transfers data between devices.

  In FIG. 1, a data transfer apparatus 1 of the present invention is connected to N (N is a natural number) transferred apparatuses 2-1 to 2-N. Since the data transfer device 1 and each transferred device 2 are connected by a serial transfer path 3, and the serial transfer path 3 is provided for each transferred device 2, the number of serial transfer paths 3 is N. Become a book. The serial transfer path 3 is a signal cable or the like for connecting apparatuses, and is a path for serially transferring data. The data transfer device 1 is connected to the control device 4, and the data transfer device 1 operates under the control of the control device 4.

  The data transfer device 1 is a device for transferring data, and the transferred device 2 is a device to which data is transferred. When applied to a memory tester, the data transfer device 1 can function as a pin electronics card, and the transferred device 2 can function as a DCL (driver comparator load). The DCL is a circuit including a driver for applying a signal to be input to the memory, a comparator for determining a signal output from the memory, and a load connected to the memory. The DCL includes a pin of the memory to be tested. Connected.

  A signal input to the memory by the DCL and data for generating a signal necessary for the determination are necessary, and this data is transferred from the data transfer device functioning as a pin electronics card. The transferred device 2 functioning as a DCL holds the transferred data and inputs a signal to the memory.

  Therefore, the transferred device 2 includes a data holding unit (register) that holds the transferred data. Here, it is assumed that the transferred device 2 includes M (M is a natural number) registers R1 to RM (collectively, registers R). In the following description, the number of registers R provided in each transfer target device 2 is described as being the same M, but the number of registers R may be different depending on the transfer target device 2.

  In FIG. 1, the devices to be transferred 2-1 to 2-N are shown as “# 1” to “#N”. Each transferred device 2 is arranged in numerical order from 2-1 to 2-N. As shown in FIG. 2, the registers R provided in each transferred apparatus 2 are also arranged in numerical order, and are arranged in order from the first register R1 to the Mth register RM. The data stored in each register R can be output to the outside (memory or the like) in order from the top register R1.

  The configuration of the data transfer device 1 will be described. The data transfer apparatus 1 includes a controller 11, an enable signal generator 12, a RAM 13, N transfer units 14-1 to 14-N (collectively transfer unit 14), an address counter 15, a master address storage unit 16, and a selected address store. A part 17, a selection address control part 18, and a selector 19 are schematically configured. The control device 4 that controls the data transfer device 1 includes a trigger generation unit 21 and a selection signal generation unit 22 and is schematically configured.

  The controller 11 controls the enable signal generator 12, the address counter 15 and the selector 19. The controller 11 is connected to the trigger generator 21 of the control device 4 and starts control based on a trigger signal generated by the trigger generator 21. The enable signal generation unit 12 generates and outputs an enable signal to the transfer unit 114 that performs the transfer operation based on the address output from the selected address storage unit 17.

  The RAM 13 is a data storage unit that stores data to be transferred to the transfer target device 2. Each data is stored in the RAM 13 in the array of FIG. 3C (the same array as FIG. 8). That is, each piece of data is stored in an array in which the registers R are arranged in order for each transfer device 2. Specifically, N data groups (from the first data group to the Nth data group) are arranged in numerical order, and M data (Data) are arranged in numerical order in each data group. Yes.

  Each data group corresponds to the transfer target device 2, and data constituting one data group corresponds to each register R. As shown in FIG. 3C, each data is given two identifiers. Of DataX-Y (1 ≦ X ≦ N, 1 ≦ Y ≦ M: X and Y are natural numbers), “X” represents a data group (transferred device 2), and “Y” represents data constituting the data group ( Register R). As described above, N × M pieces of data are arranged in order from the top address of the RAM 13.

  The transfer unit 14 is connected to the serial transfer path 3 and outputs the input data to the serial transfer path 3. As a result, data is serially transferred from the serial transfer path 3 to the transfer target device 2. Data handled in the data transfer device 1 is parallel data, and the parallel data is converted into serial data and output to the serial transfer path 3. If the transfer unit 14 is inputting serial data, the data is output as it is without being converted. Of the N transfer units 14, only the transfer unit 114 that has received the enable signal from the enable signal generation unit 12 outputs data to the serial transfer path 3.

  The address counter 15 is an address designating unit for designating the addresses of the master address storage unit 16 and the selected address storage unit 17. The address counter 15 stores the initial addresses of the master address storage unit 16 and the selected address storage unit 17 as initial values, and increments the designated address from the initial address. Here, it is assumed that the top addresses of the two storage units are zero (address 0).

  The address counter 15 starts address output and increment under the control of the controller 11. When the last data in the master address storage unit 16 and the selected address storage unit 17 is read, the address designated by the address counter 15 is returned to the initial value by the controller 11 (reset is performed).

  The master address storage unit 16 stores the address (memory address) of the RAM 13 as data. FIG. 3A shows an array of memory addresses (Add) stored in the master address storage unit 16, and AddX-Y shows an address where DataX-Y is stored.

  The order of the memory addresses stored in the master address storage unit 16 is arranged in the order of X for every Y order. That is, the array starts with Add1-1 and increments Y each time X is incremented from the first to the Mth. As described above, since X indicates the transferred device 2 and Y indicates the register R, the order of the memory addresses stored in the master address storage unit 16 is determined according to the order of the register R. It is an array arranged in order.

  Note that the order of the data (Data) stored in the RAM 13 is arranged in the order of Y for every X order, and starts from Data1-1 and increments Y from the first to the Nth. In this array, X is incremented every time.

  The selected address storage unit 17 will be described. The selection address storage unit 17 extracts and stores only the memory address of the data to be transferred from the memory addresses stored in the master address storage unit 16. In other words, the memory address of the data that is not transferred is excluded from the data stored in the master address storage unit 16 and stored.

  The selection address control unit 18 functions as a decoder / counter, performs operation control when the selection address storage unit 17 stores a memory address as a decoder function, and generates an address of the selection address storage unit 17 as a counter function. For this purpose, the selection address control unit 18 operates based on the address output from the address counter 15 and the selection signal output from the selection signal generation unit 22 of the control device 4.

  Here, the selection signal will be described. The selection signal is output from the selection signal generation unit 22 and is information indicating whether or not to transfer data corresponding to each memory address stored in the master address storage unit 16. The selection signal generator 22 stores the arrangement order of the memory addresses stored in the master address storage unit 16 shown in FIG. 3A, and has information on whether or not to transfer each memory address. is doing.

  For example, the selection signal can be binary data of M × N bits. From Add1-1 stored in the head address of the master address storage unit 16 to AddN-M in order from the first bit to the N × M bit of the selection signal, and transfer when the bit value is “1” It is possible to indicate that transfer is not performed when “0”.

  Whether or not to perform the transfer operation can be arbitrarily set according to various situations. For example, when the data transfer device 1 is applied to a memory tester, there are cases where there are unused pins among the pins of the memory. In this case, data transfer is not performed from the transfer target device 2 connected to the pin. In addition, the device to be transferred 2 may not be used regardless of the memory pin. In any case, data transfer may not be necessary for the transfer target device 2 or the register R. In this case, data is not read from the RAM 13.

  The selection address control unit 18 inputs the above selection signal. As described above, an address is input from the address counter 15 to the selected address control unit 18. This address is sequentially incremented from the leading address (zero) of the master address storage unit 16. The selection signal is information indicating whether or not the transfer is performed in the arrangement order of the memory addresses stored in the master address storage unit 16. Based on the selection signal and the input address, whether or not the data of the address is transferred. You can determine whether or not. For example, when an M × N bit signal is used as described above, it is possible to recognize whether or not to perform transfer by referring to the bit corresponding to the input address.

  Thereby, the selected address control unit 18 can determine whether or not to perform transfer for each input address. If it is determined that transfer is to be performed, a write control signal is output to the selected address storage unit 17. This write control signal is a signal for permitting the storage operation of the selected address storage unit 17. On the other hand, when the write control signal is not output, the storage operation is prohibited.

  The selected address control unit 18 also functions as a counter function. The selection address control unit 18 counts a value, and increments the value when a write control signal is output from the selection address control unit 18. Then, the initial address (zero) of the selected address control unit 18 is stored as an initial value, and the address of the selected address storage unit 17 is thereby generated. The generated address is output to the selected address storage unit 17.

  The selector 19 is controlled by the controller 11 and selects one of the address output from the address counter 15 and the address output from the selected address control unit 18 and outputs the selected address to the selected address storage unit 17. The selection signal also functions as a trigger for starting the operation of the controller 11. When the operation of the controller 11 is started based on the trigger signal generated by the trigger generation unit 21, the address of the address counter 15 is selected, and the selection signal When the operation of the controller 11 starts based on the above, the address of the selected address control unit 18 is selected.

  The above is the schematic configuration. Next, the operation will be described. The following operations are divided into two operations, a data storage operation and a data transfer operation. First, the data storage operation will be described. During the data storage operation, the master address storage unit 16 is set to a read mode (a mode for reading data), and the selection address storage unit 17 is set to a write mode (a mode for storing data). In the data transfer operation, the selected address storage unit 17 is set to the read mode.

  The data storage operation is started with the selection signal generated by the selection signal generator 22 as a trigger. The generated selection signal is input to the controller 11, and the controller 11 controls the selector 19 so as to select the address output by the selection address control unit 18.

  Then, the controller 11 starts the operation of the address counter 15. Initially, the head address (zero) of the master address storage unit 16 is output from the address counter 15, and sequentially incremented addresses are output. The output address is input to the master address storage unit 16 and the selected address control unit 18.

  The address input to the master address storage unit 16 specifies the address of the master address storage unit 16. In the data storage operation, since the master address storage unit 16 is in the read mode, the memory address Add1-1 stored in the head address is sequentially read up to AddN-M. The read memory addresses are sequentially output to the selected address storage unit 17.

  The address output from the address counter 15 is also input to the selected address control unit 18. Based on the address from the address counter 15 and the selection signal, the selection address control unit 18 determines whether or not to transfer the data at the memory address stored in the master address storage unit 16 (decoder function). . When it is determined that transfer is to be performed, a write control signal is output to the selected address storage unit 17. The write control signal is input to the selected address storage unit 17, and the selected address storage unit 17 stores the memory address output from the master address storage unit 16 only when this write control signal is input.

  The selected address control unit 18 counts the value, and outputs the counted value to the selector 19 (counter function). This value is incremented by the number of times the write control signal has been output starting from the head address (zero) of the selected address storage unit 17. The write control signal is a signal for controlling the memory address output from the master address storage unit 16 to be stored in the selected address storage unit 17. The number of times this write control signal is output is effectively stored in the selected address storage unit 17. This is the number of memory addresses.

  Thus, the selection address control unit 18 counts the number of memory addresses that are effectively stored in order from the top address (zero) of the selection address storage unit 17. Therefore, the counted value designates the address of the selected address storage unit 17. That is, an address is specified when memory addresses to be effectively stored in order from the top address are arranged.

  The selection address control unit 18 outputs the counted value as the address of the selection address control unit 18. Since the selector 19 selects the address output from the selected address control unit 18, the address is input to the selected address control unit 18.

  Accordingly, the memory address sequentially output from the master address storage unit 16 is input to the selected address storage unit 17 as data, the address output from the selection address control unit 18 designates the address, and the storage operation is performed by the write control signal. Prohibition or permission is controlled.

  Even if the memory address is input from the master address storage unit 16, the memory address is not stored unless the write control signal is input, and the memory address is stored only when the write control signal is input. Only the memory addresses are stored. Since the selection address control unit 18 designates the addresses to be effectively stored in order from the top address, only the memory addresses of data that need to be transferred are stored in order from the top address.

  FIG. 3B shows an example of a memory address stored in the selected address storage unit 17. In this example, data is not transferred to the transfer target device 2 other than the transfer target devices 2-1, 2-3, and 2-5, and the data groups 2-1, 2-3, and 2-5 are configured. Only the data to be stored is stored. That is, only data of X, 1, 3, and 5 is stored in AddX-Y. In other words, data other than these are excluded and stored.

  Therefore, the amount of data stored in the selected address storage unit 17 can be greatly reduced. As a result, the capacity required for the selected address storage unit 17 can be reduced, and the amount of data (memory addresses) to be stored is small, so that data can be read at high speed.

  When the address counter 15 performs the above operation from the top address (zero) of the master address storage unit 16 to M × N memory addresses, the data storage operation ends. When the data storage operation is completed, the controller 11 returns the address counter 15 to the initial value (zero).

  After the above data storage operation is completed, the data transfer operation is performed. The data transfer operation is actually an operation of transferring data to the transfer target device 2. When this data transfer operation is performed, the selected address storage unit 17 is set to the read mode. Note that since the master address storage unit 16 does not affect the data transfer operation, any mode may be set.

  The data transfer operation is started when the controller 11 inputs a trigger signal output from the trigger generator 21. The controller 11 increments the address output from the address counter 15 from the initial value (the head address of the selected address storage unit 17). At the same time, the controller 11 starts the operation based on the trigger signal, and therefore controls the selector 19 to select the address output from the address counter 15.

  In the above-described data storage operation, the address counter 15 designates the address of the master address storage unit 16, but in the data transfer operation, the address of the selected address storage unit 17 is designated. Since the selector 19 selects the address output from the address counter 15, this address is input to the selected address storage unit 17.

  The address input to the selected address storage unit 17 is sequentially incremented from the top address. Accordingly, memory addresses as shown in FIG. 3B are sequentially read from the head address. In the data transfer operation, since the selected address storage unit 17 is in the read mode, it is not affected by the write control signal.

  The memory address sequentially read from the selected address storage unit 17 designates the address of data read from the RAM 13. Then, the transfer target devices 2 are arranged in order (the order of “X” in AddX-Y) in the order of the registers R (the order of “Y” in AddX-Y), and transfer is performed. This excludes memory addresses of data that are not to be executed.

  In the example of FIG. 3B, they are arranged in the order of Add 1-1, 3-1, 5-1,... 1 to 5 are arranged in numerical order, and “X” is the first (transferred device 2-1), third (transferred device 2-3), and fifth (transferred) that perform transfer. Only the device 2-5) is stored.

  The enable signal generation unit 12 inputs memory addresses output from the selected address storage unit 17 in order from the head address, and outputs an enable signal based on the memory address. Since the input memory address is AddX-Y, the transfer unit 14 that performs the operation can be specified by referring to “X”. Then, an enable signal is output only to the transfer unit 14 that operates.

  Therefore, the memory address first output from the selected address storage unit 17 is Add1-1, and this memory address reads Data1-1 which is the first data in the first data group of the RAM13. Then, the read Data 1-1 is output to each transfer unit 14. On the other hand, the enable signal generator 12 outputs an enable signal only to the transfer unit 14-1 based on Add1-1.

  Therefore, only the transfer unit 14-1 performs the data transfer operation. The transfer unit 14-1 converts the input Data 1-1 from parallel data to serial data, and outputs it to the serial transfer path 3-1. As a result, Data 1-1 is serially transferred through the serial transfer path 3-1. The transferred Data 1-1 is stored in the first register R1 of the transferred device 2-1.

  Next, the memory address read from the selected address storage unit 17 is Add3-1. Add3-1 designates the first data Data3-1 of the third data group of the RAM 13. Then, the enable signal generator 12 outputs an enable signal only to the transfer unit 14-3 based on Add3-1. Therefore, the transfer unit 14-3 performs data conversion of Data3-1 and outputs Data3-3 to the serial transfer path 3-3.

  Next, the memory address read from the selected address storage unit 17 is Add5-1, whereby the first data Data5-1 of the fifth data group of the RAM 13 is read, and the enable signal generation unit 12 is transferred to the transfer unit 14. Since the enable signal is output only to −5, only the transfer unit 14-5 performs the data transfer operation.

  Accordingly, data sequentially read from the RAM 13 is input to different transfer units 14 to perform a data transfer operation. That is, data can be sequentially output to different transfer units 14, and the transfer units 14 to which data is input can be operated in parallel. In the above case, data can be sequentially output to the transfer units 14-1, 14-3, and 14-5, and the transfer units 14 can be operated in parallel. Thereby, since the some transfer part 14 operate | moves in parallel, the transfer efficiency of data can improve and the transfer rate as a whole can be sped up.

  Here, although the operation of the present invention is divided into the data storage operation and the data transfer operation, the data storage operation may be omitted. The data storage operation is an operation that excludes the memory address of data that is not transferred, and the transfer units 14 can be operated in parallel without performing this operation. Alternatively, when all the data stored in the RAM 13 is transferred, it is not necessary to exclude it in the first place.

  In the case of transferring all data, since the memory addresses in which the transfer target devices 2 are arranged in order of the registers R are read out for all the registers R and transfer target devices 2, Data 1-1, 2-1. 3-1,..., Data output to different transfer units 14 are read from the RAM 13. Thereby, since each transfer part 14 can be operated in parallel, high-speed data transfer can be achieved. In this case, the selection address storage unit 17, the selection address control unit 18, and the selector 19 are not necessary, and the master address storage unit 16 and the RAM 13 are directly connected.

  Next, a comparative example will be described with reference to FIGS. 4, 5, and 6. FIG. 4 shows a time chart of the first comparative example, and data is read in order from the head address of the RAM 13 as in the case described in the background art. FIG. 5 shows a time chart of the second comparative example, in which data is read sequentially from the head address of the RAM 13 as in the background art, but each transfer unit 14 is provided with a FIFO (First In First Out). Yes. FIG. 6 shows a time chart of the third comparative example, illustrating the operation of the present invention. However, the case where all data is transferred is shown (data not transferred is not excluded).

  4 to 6, “# 1” to “#N” indicate the devices to be transferred 2-1 to 2-N, and t1 is the time from reading data from the RAM 13 to input to the transfer unit 14. T2 indicates a time until data is transferred from the transfer unit 14 to the transfer target device 2.

  The processing speed inside the data transfer apparatus 1 is high. This is because the data transfer device 1 constitutes one circuit board, and signal transmission is performed at high speed inside the board. On the other hand, the transfer speed of the serial transfer path 3 is very low compared to the internal processing speed of the data transfer apparatus 1. This is because a signal cable or the like is used for the serial transfer path 3. Therefore, the time t1 is very short with respect to t2.

  As shown in FIG. 4, in the first comparative example, data is sequentially read from the head address of the RAM 13, and data (Data1-1) to be stored in the M registers R constituting one transfer target device 2 is shown. 1-2,..., 1-M) are continuously read out, so that M pieces of data are continuously output to one transfer unit 14. For this reason, the transfer operation of the next transfer unit 14-2 is started after M data transfers from the transfer unit 14-1 to the transfer target device 2-1.

  For this reason, the transfer unit 14-1 completes the transfer of M pieces of data when the time t2 × M has elapsed. Since the N transfer units 14 require the same time, all data transfer is completed after t2 × M × N has elapsed. Since time t1 is required from the time when the first Data 1-1 is read from the RAM 13 to the time when it is input to the transfer unit 14-1, the time required until all data transfer is completed after the trigger signal is input. Becomes t1 + t2 × M × N.

  Next, a second comparative example will be described. In this comparative example, each transfer unit 14 is provided with a FIFO. Accordingly, data can be sequentially read out from the RAM 13 and output regardless of the transfer operation of the transfer unit 14. That is, by providing the FIFO in each transfer unit 14, the operation of the RAM 13 and the operation of the transfer unit 14 can be made independent. For this reason, it is necessary to provide the FIFO with the number of stages capable of storing at least “M−1” data.

  Therefore, by providing the FIFO, data can be output to the next transfer unit 14 when M data is output to one transfer unit 14. As shown in FIG. 5, when M pieces of data are output to the FIFO of the transfer unit 14-1, data is output to the next transfer unit 14-2. Since t1 is much shorter than t2, when data is output to the transfer unit 14-2, the transfer unit 14-1 still performs the data transfer operation. Thereby, the transfer units 14-1 and 14-2 can be operated in parallel. Similarly, the transfer units 14-3 and later can be operated in parallel.

  As described above, the transfer unit 14-2 starts the transfer operation by outputting M data (Data 1-1 to Data 1 -M) continuously read from the head address of the RAM 13 to the transfer unit 14-1. When the time t1 × M has elapsed. Therefore, the transfer unit 14-N starts the transfer operation after elapse of t1 × M × (N−1). The transfer operation is completed when transfer of M data is completed after the transfer unit 14-N starts the transfer operation, and therefore it takes time t2 × M.

  Therefore, the time required from the input of the trigger signal to the completion of the transfer operation of all the data is t1 + t1 × M × (N−1) + t2 × M in consideration of the data 1-1 reading time t1. Compared with the first comparative example, since the time multiplied by t2 is only M, the second comparative example can complete the transfer operation faster than the first comparative example.

  However, since it takes t1 × M × (N−1) time until the transfer unit 14-N starts the transfer, and t1 is a short time but is multiplied by M and N−1. It will take some time. This time is a wasteful waiting time (overhead), which causes a reduction in the transfer rate.

  FIG. 6 shows a third comparative example. The third comparative example is an operation according to the present invention, in which data is not read from the start address of the RAM 13 in order but from the RAM 13 in the order of the memory addresses arranged in order from the start address of the master address storage unit 16. Is read out. Since the master address storage unit 16 stores the memory addresses in the order of the transfer target device 2 in the order of the registers R, the data read from the RAM 13 is sequentially input to the different transfer units 14. .

  Therefore, Data 1-1 first read from the RAM 13 is input to the transfer unit 14-1, and Data 2-1, Data 2-1,..., Data N-1 are transferred to the transfer units 14-2, 14-3,.・ It is input in order to 14-N. Accordingly, the time required from the input of Data 1-1 to the transfer unit 14-1 to the input of Data 2-1 to the transfer unit 14-2 is until one data is read from the RAM 13 and input to the transfer unit 14. It becomes time t1. For this reason, the time required until DataN-1 is input to the transfer unit 14-N is t1 × (N−1).

  Therefore, the time from when the trigger signal is input until the transfer unit 14-1 starts the transfer operation is t1 + t1 × (N−1) = t1 × N. Since the time required to transfer M pieces of data is t2 × M, the time required to complete the transfer of all data after inputting the trigger signal is t1 × N + t2 × M.

  That is, in the case of the third comparative example (that is, the present invention), the standby time can be reduced to 1 / M as compared with the second comparative example. As a result, the useless waiting time can be greatly shortened, so that the overall transfer time can be increased.

  In the example of FIG. 6, the case where all data is transferred has been described. However, unnecessary data transfer can be excluded by using the selection address storage unit 17. For example, when data transfer is unnecessary for half of the N transferred devices 2, the waiting time “t1 × N” is also halved. Further, as shown in FIG. 3B, when only three data transfers of the devices to be transferred 2-1, 2-3, and 2-5 are performed, the standby time is “t1 × 3”.

  In recent memory testers and the like, since various data are set for one transferred device 2, a large number of registers R are provided inside the transferred device 2. For this reason, the number M of the registers R becomes a large value. When the value of M is large, the waiting time can be greatly shortened.

  Further, when the transfer time of the serial transfer path 3 is increased and the time t2 is shortened and the difference between t1 and t2 is reduced, the standby time portion has a great influence on the entire transfer time. In this case, the transfer rate can be dramatically improved.

  Here, when t1 is remarkably shorter than t2, and t1 × M <t2, it is desirable to provide a FIFO in each transfer unit. Under this condition, data is input to the transfer unit 14-N by the time the transferred device 2-1 finishes transferring the first data 1-1, and even if the data 1-2 is read from the RAM 13, the transfer is performed. The unit 14-1 cannot be input. Therefore, it is necessary to wait for the RAM 13 to be read.

  Therefore, by providing a FIFO, data can be sequentially read from the RAM 13 regardless of t1 or t2. In this case, it is not necessary to provide so many FIFO stages.

  Therefore, in the present invention, by storing data in the RAM 13 in the same order as the arrangement order of the transfer target device 2 and the register R, it is very easy to generate, change, and refer to the data. In this case, the transfer unit 14 is operated in parallel to increase the transfer speed as a whole.

  In this regard, if the address of the data read from the RAM 13 can be freely changed, the master address storage unit 16 and the selection address storage unit 17 become unnecessary. For example, if a means such as a CPU that can generate and access an arbitrary address is used, the master address storage unit 16 becomes unnecessary. However, in this case, it is necessary to provide a means such as a CPU in the data transfer apparatus 1, which makes the control complicated and increases the complexity and size of the circuit.

  In the present invention, all address designations are performed by increment. That is, the address is specified by the address counter 15 having a simple function of incrementing the value by one. Thereby, it is not necessary to use means such as a CPU.

  As shown in FIG. 3C, when each data group has M data, that is, each transferred device 2 has M registers R, By changing the address of the data to be read from the RAM 13 by M, the data can be read in the order of the transfer target device 2 for each order of the registers R.

  In this case, data is read one by one from the first data group to the Nth data group, but after reading up to the Nth data group, the next data in the first data group is read again. You must control the address. If the number of registers R differs depending on the device to be transferred 2, data cannot be read simply by changing the address by M.

  In any case, address control for reading data from the RAM 13 becomes complicated. In the present invention, the master address storage unit 16 and the selection address storage unit 17 are provided, and the control is performed simply by incrementing the address of the data to be read. Therefore, the control becomes simple and the circuit scale is simple and small. Become.

  In the present invention, only the memory address of the data to be transferred is stored in the selected address storage unit 17 by the data storage operation. However, when the arrangement of data to be stored in the selected address storage unit 17 is obtained in advance. May be stored in the selected address storage unit 17 in an array excluding memory addresses of unnecessary data in advance without using the master address storage unit 16.

  Further, the selected address storage unit 17 can be configured so that data can be rewritten from the outside. That is, the memory address stored in the master address storage unit 16 is copied to the selection address storage unit 17 as it is, and the memory address of the data that is not transferred can be deleted by rewriting the selection address storage unit 17 from the outside. it can. Thereby, a memory address to be stored in the selected address storage unit 17 can also be configured. Of course, the same effect can be obtained by rewriting the master address storage unit 16 without providing the selection address storage unit 17.

  In this case, there is no data at the address of the selected address storage unit 17 (or master address storage unit 16) corresponding to the deleted memory address. Therefore, when the memory address is deleted, the subsequent addresses are decremented.

  In addition, by making the master address storage unit 16 and the selection address storage unit 17 rewritable from the outside, the order of data stored in the register R in the transfer target device 2 can be changed. For example, each register R of the transferred device 2 stores relay control setting information. When there is a request to change the order of the relay control, the order of the memory addresses stored in the selected address storage unit 17 is changed. By rewriting, the data transfer order can be changed.

  Further, the above-described data storage operation and data transfer operation can be overlapped. In the data transfer operation, data is read from the RAM 13 and input to the transfer unit 14 (first data transfer operation), and data is output from the transfer unit 14 to the serial transfer path 3 and transferred to the transfer target device 2. (Second data transfer operation). Among these, the first data transfer operation ends at an earlier stage than the second data transfer operation. This is because the time required for the first data transfer operation is t1 × N, and the time required for the second data transfer operation is t2 × M.

  When the second data transfer operation is performed, the RAM 13 is already open. For this reason, the second data transfer operation and the data storage operation can be overlapped. As a result, the overall transfer time can be further shortened. The master address storage unit 16 must store memory addresses in a predetermined arrangement in advance, but this storage operation is also overlapped with the second data transfer operation, thereby reducing the overall transfer time. Can be realized.

  In addition, the data transfer device 1 does not always operate at a constant speed, but the operation speed changes between a low speed and a high speed. For this reason, when the operation speed is low, a data storage operation or a memory address storage operation for the master address storage unit 16 may be performed.

1 Data Transfer Device 2 Transferred Device 3 Serial Transfer Path 4 Control Device 11 Controller 12 Enable Signal Generating Unit 13 RAM 14 Transfer Unit 15 Address Counter 16 Master Address Storage Unit 17 Selected Address Storage Unit 18 Select Address Control Unit 19 Selector 21 Trigger Generation Part 22 Selection signal generator

Claims (6)

A data transfer device for connecting a plurality of transfer target devices having a plurality of data holding units for holding transferred data and serially transferring data to each transfer target device,
A data storage unit for storing the data arranged in the order of the data holding unit for each order of the transferred devices;
A master address storage unit for storing addresses for reading the data from the data storage unit in the order of the transfer target device in order of the data holding unit;
An address counter for performing address designation for the master address storage unit by increment;
A plurality of transfer units that transfer the data read from the data storage unit to the transferred device;
A data transfer device comprising: A selection that is arranged between the master address storage unit and the data storage unit, and arranges and stores in order addresses from which addresses that are not transferred to the device to be transferred are excluded from addresses stored in the master address storage unit The data transfer device according to claim 1, further comprising an address storage unit. When the addresses stored in the master address storage unit are read in order from the beginning and stored in the selected address storage unit, a control for prohibiting the storage operation for the selected address storage unit is performed when the address not transferred is read. The data transfer apparatus according to claim 2, further comprising a selection address control unit for performing the selection. 4. The data transfer device according to claim 3, wherein an operation of transferring data from the transfer unit to the transfer target device and an operation of storing an address from the master address storage unit to the selected address storage unit are overlapped. . The data transfer device according to claim 1, wherein an operation of transferring data from the transfer unit to the transfer target device and an operation of storing an address in the master address storage unit are overlapped.   A semiconductor test apparatus comprising the data transfer apparatus according to claim 1.

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