JP2010501915A - Memory module command structure and memory system - Google Patents

Abstract

  A system including a memory system and a memory controller is connected to the host system. The memory system has at least one memory device that stores data. The controller translates the request from the host system into one or more separable commands that can be interpreted by at least one memory device. Each command has a modular structure that includes an address identifier for one of the at least one memory device and a command identifier representing an operation performed by one of the at least one memory device. The at least one memory device and the controller are configured in series connection for communication so that only one memory device communicates with the controller that inputs to the memory system. The memory system can include a plurality of memory devices connected to a common bus.

Description

Cross-reference to related applicationsThis application includes US Provisional Patent Application No. 60 / 839,329 filed on August 22, 2006, US Provisional Patent Application No. 60 / 902,003 filed on February 16, 2007, and It claims the benefit of priority of US Provisional Patent Application No. 60 / 892,705, filed March 2, 2007.

  The present invention relates generally to semiconductor memory devices, and more particularly to a system having a plurality of interconnected semiconductor memory devices and a command structure for the memory devices.

  Semiconductor memory devices are commonly found in many industrial and consumer electronic products. In addition to the smaller size requirements, the demand for higher memory capacity has increased and there is a need for a memory with a density that is difficult to achieve. As a result, multiple memory devices are often connected to one another to meet significant memory requirements. Such multi-device memory systems can be packaged together in a single package (ie, a multi-chip system) or multiple memory device packages grouped together on a printed circuit board.

  When multiple semiconductor memory devices are interconnected to function as a single system, the controller is responsible for individual memory that responds to requests for data storage, data access, and data manipulation within the system. Manage the flow of data between the device and the external interface. The command structure is used by the controller to provide those requests to individual memory devices that contain data. The command structure may depend on the configuration of interconnected memory devices and can affect system performance. For example, if individual memory devices communicate with the controller via a common bus, only one of the individual memory devices can be asserted at any given time. If individual memory devices are interconnected in series in a chain configuration and only one memory device is connected to the controller, commands for memory devices located at the back of the chain are commands that the front memory device cannot interrupt Can cause significant delays. In the configuration of memory devices connected in series, processing of commands in one device stops transmission of all commands in subsequent memory devices, so any other processing in the system is paused.

US Provisional Patent Application No. 60 / 839,329 US Provisional Patent Application No. 60 / 902,003 US Provisional Patent Application No. 60 / 892,705 US Provisional Patent Application No. 60 / 787,710 US Provisional Patent Application No. 60 / 802,645 US Provisional Patent Application No. 60 / 868,773

  According to one aspect of the present invention, a device identifier including an address for one of a plurality of memory devices and a bank address for one of a plurality of memory banks in one of the plurality of memory devices, and a plurality of memory devices A module command structure is provided that includes a command identifier that includes an operation code that represents an operation performed by one of the two.

  According to another aspect of the invention, a module command set comprising a plurality of separable commands representing a request from a processor for accessing one of a plurality of memory devices, wherein a plurality of separate commands Each is implemented by one of the plurality of memory devices and a device identifier including an address for one of the plurality of memory devices and a bank address for one of the plurality of memory banks in one of the plurality of memory devices. And a module command set including a command identifier including an operation code representing an operation to be performed.

  According to another aspect of the present invention, a memory system including at least one memory device for storing data, a processor for managing a request for access to the memory system, and a request from the processor for at least one memory device A controller that translates into one or more separable commands that are interpretable by each command, each command being executed by one of at least one memory device and an address identifier for one of the at least one memory device And a controller having a module structure including a command identifier representing an operation to be performed, wherein at least one memory device and the controller are configured in series for communication.

  According to another aspect of the present invention, a controller for a system having a plurality of memory devices for storing data, the processor configured in series for communication with the plurality of memory devices and accessing the plurality of memory devices A conversion device for converting a request from a processor and a request from a processor into a plurality of separable commands that can be interpreted by a plurality of memory devices, each command comprising a plurality of memories A conversion device having a module structure including an address identifier for one of the devices and a command identifier representing an operation executed by one of the plurality of memory devices, and a plurality of memory devices issuing a plurality of separable commands A controller is provided including a second connection for serial communication with one.

  According to another aspect of the present invention, a method for requesting access to at least one memory device, determining an address including an address for the at least one memory device, combined with at least one memory device Identifying a plurality of operations that satisfy a request for access to a device and providing a plurality of separable commands to at least one memory device, each of the commands including a device identifier that includes an address, and a plurality of commands And a command identifier comprising one of the operations, wherein the command identifier is interpretable by a memory device.

  According to one embodiment of the present invention, a command structure is provided that includes a plurality of separable commands that represent a request for access to one of a plurality of memory devices. Each of the plurality of separate commands includes a device identifier including an address for one of the plurality of memory devices and a bank address for one of the plurality of memory banks in one of the plurality of memory devices, and the plurality of memory devices And a command identifier including an operation code representing an operation executed by one of the above.

  According to another embodiment of the present invention, a device identifier comprising an address for one of a plurality of memory devices, a bank address for one of a plurality of memory banks in one of the plurality of memory devices, and a plurality of A module command structure is provided that includes a command identifier that includes an operation code representing an operation performed by one of the memory devices.

  According to another embodiment of the invention, a memory system including at least one memory device for storing data, a processor managing requests for access to the memory system, and requests from the processor to at least one memory A controller that translates into one or more separable commands that are interpretable by the device, each command executed by an address identifier for one of the at least one memory device and one of the at least one memory device And a controller having a module structure including a command identifier representing an operation to be performed, wherein at least one memory device and the controller are connected in series for communication.

  For example, the at least one memory device includes at least one memory bank. The address identifier may include a device address for one of the at least one memory device and a bank address for one of the at least one memory bank. For example, the memory device is a flash device such as a NAND flash memory device.

  If the memory system includes multiple memory devices, the devices can be connected in series or on a common bus.

  According to another embodiment of the present invention, there is provided a controller for a system having a plurality of memory devices for storing data, the controller configured in series interconnection for communication with the plurality of memory devices. The The controller is a first connection for receiving a request for access to a plurality of memory devices, and a conversion device that converts the request into a plurality of separable commands that can be interpreted by the plurality of memory devices, A conversion device having a module structure in which each command includes an address identifier for one of the plurality of memory devices and a command identifier representing an operation executed by one of the plurality of memory devices; and a plurality of separable commands And a second connection for communication with one of the plurality of memory devices to issue.

  According to another embodiment of the invention, determining an address including a memory device address, identifying a plurality of operations that satisfy a request for access to the memory, and a plurality of separable commands for the memory A method is provided that includes providing each command including a device identifier having a memory device address and a command identifier having one of a plurality of operations.

  Preferably, this method is used to translate a request for access to a memory device into a plurality of separable commands that can be interpreted by the memory device. This method can be used to translate a request for access to a memory device into a plurality of separable commands that can be interpreted by the memory device.

  Other aspects and features of the present invention will become apparent to those skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying drawings.

  Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying figures.

1 is a block diagram illustrating a host system and a system having a memory system and a memory controller to which embodiments of the present invention can be applied. 1 is a block diagram showing a memory system having a plurality of memory devices and one controller connected to the memory system via a common bus, to which an embodiment of the present invention can be applied. 1 is a block diagram illustrating a memory system having a plurality of memory devices interconnected in series and a controller connected to the memory devices, to which embodiments of the present invention can be applied. 1 is a block diagram illustrating a general configuration example of a flash memory device to which an embodiment of the present invention can be applied. It is a figure which shows the example of the module command structure for using with NAND flash memory which can apply embodiment of this invention. It is a figure which shows the example of the module command structure for using with NAND flash memory which can apply embodiment of this invention. It is a figure which shows the example of the module command structure for using with NAND flash memory which can apply embodiment of this invention. It is a block diagram which shows the structure of the flash controller which can apply embodiment of this invention. FIG. 6B is a block diagram showing an example of functional components of the flash command engine shown in FIG. 6A. FIG. 5 is a flowchart illustrating a process that is processed by a page read command from a controller using a module command structure. FIG. 10 illustrates the timing of a page read operation with a set waiting period from a flash memory device using a module command structure. FIG. 10 illustrates the timing of a page read operation with a status request from a flash memory device using a module command structure. FIG. 5 is a flowchart illustrating a process that is processed by a page program command from a controller that uses a module command structure. FIG. 6 illustrates the timing of a page program operation with a single data input from a flash memory device using a module command structure. FIG. 6 illustrates the timing of a page program operation with two data inputs from a flash memory device using a module command structure. FIG. 6 is a flowchart illustrating a process that is processed by a block erase command from a controller using a module command structure. FIG. 5 illustrates the timing of a block erase operation with a single block address to erase from a flash memory device using a module command structure. FIG. 6 illustrates the timing of a block erase operation with two block addresses to be erased from a flash memory device using a module command structure. FIG. 6 is a flowchart illustrating a process handled by a parallel page read command from a controller for two memory banks in the same flash memory device using a module command structure. FIG. 6 illustrates timing from a flash memory for a parallel page read operation for two memory banks in the same flash memory device using a module command structure. FIG. 5 is a flow chart illustrating a process that is processed by parallel page program commands from controllers for two memory banks in the same flash memory device using a module command structure. FIG. 6 illustrates timing from a flash memory for concurrent page program operations for two memory banks in the same flash memory device using a module command structure. FIG. 5 is a flowchart illustrating a process handled by a parallel block erase command from a controller for two memory banks in the same flash memory device using a module command structure. FIG. 10 illustrates timing from a flash memory for a parallel block erase operation for two memory banks in the same flash memory device using a module command structure. FIG. 6 is a flow chart illustrating a process handled by interleaved page read and page program commands from controllers for two memory banks in the same flash memory device using a module command structure. FIG. 5 illustrates timing from a flash memory device for interleaved page read and page program operations for two memory banks in the same flash memory device using a module command structure. FIG. 6 is a flow chart illustrating a process handled by paused and resumed page read and page program commands from a controller for two memory banks in the same flash memory device using a module command structure. FIG. 7 illustrates timing from a flash memory device for paused and resumed page read and page program operations for two memory banks in the same flash memory device using a module command structure. FIG. 7 illustrates an example of interleaved and parallel page read, block erase, page program, and page pair erase commands / operations for a plurality of flash memory devices each having a plurality of memory banks. FIG. 6 illustrates an example of interleaved and parallel page read commands / operations for a plurality of flash memory devices each having a plurality of memory banks. FIG. 7 illustrates an example of interleaved and concurrently suspended and resumed page read, block erase, and page program commands / operations for a plurality of flash memory devices each having a plurality of memory banks.

  In the following detailed description of example embodiments, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific example embodiments. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and other embodiments can be used without departing from the scope of the invention, as well as logical, mechanical, It is understood that electrical and other changes can be made. The following detailed description is, therefore, not to be taken in a limiting sense.

  Semiconductor memory devices are often interconnected to form large capacity memory systems. FIG. 1 shows a system to which an embodiment of the present invention can be applied. Referring to FIG. 1, a host system 102 having a processor 103 therein is connected to a system that includes a memory system 106 and a controller 104 that controls the memory system. The memory system 106 includes at least one memory device (eg, two flash memory devices 107-0 and 107-1). The controller 104 receives a request from the host system 102 and converts the request into a command that can be interpreted by the memory system 106. The controller 104 also translates logical addresses for the memory system 106 used by the host system 102 into physical addresses for the memory system 106. The controller 104 causes data stored in the memory system 106 to be distributed between the memory devices 107-0 and 107-1. An error correction code (ECC) is also generated by the controller 104 to check for errors in the execution of the command.

  FIG. 2 shows an example of a system configuration to which the embodiment of the present invention can be applied. Referring to FIG. 2, the controller 112 communicates via a common bus 114 with a memory system that includes a plurality of memory devices (eg, four flash memory devices 108-0 to 108-3). The controller 112 uses the common bus 114 to transfer data to and from the memory devices 108-0 to 108-3. By asserting the chip enable signal, only the specified flash memory device is asserted at once with this configuration.

  FIG. 3 shows another example of a system configuration to which the embodiment of the present invention can be applied. The memory system includes memory devices connected in series. Referring to FIG. 3, a memory system including a controller 116 and a plurality of memory devices (eg, four flash memory devices 109-0 to 109-3) are interconnected in a loop configuration. Since the memory devices 109-0 to 109-3 are interconnected in series, only one device receives data and messages that reach the memory system via the controller 116. Each of the memory devices 109-0 to 109-3 is coupled to up to two other memory devices (i.e., previous and next devices). Thus, data and messages arriving at the memory system pass through all other memory devices to the last device 109-3 in series connection.

  The flash memory device may be any type of flash memory such as NAND type, NOR type, and AND type flash memory. The memory device may be a random access memory.

  NAND flash memory devices are generally interconnected to provide low cost and high density memory. FIG. 4 shows functional components of the NAND flash device 400. In NAND flash device 400, commands, addresses, and data are multiplexed via common I / O pins on the device chip. The NAND flash device 400 includes a memory bank 402 having a cell arrangement structure having a plurality (n) of erasable blocks. Each erasable block is subdivided into multiple (m) programmable pages. Each page consists of (j + k) bytes. The page is further divided into j bytes of data storage where the data is stored and a separate k bytes typically used for error management functions. Each page usually consists of 2,112 bytes, of which 2,048 bytes are used for data storage and 64 bytes are used for error management functions. The memory bank 402 is accessed page by page. Although FIG. 4 shows a single memory bank 402, the NAND flash device 400 can have more than one memory bank 402. Each such memory bank 402 may be capable of performing concurrent page read, page program, page erase, and block erase operations.

  Commands to access the memory bank 402 are received in a command register 414 and control logic 416 from a controller (eg, controller 116 shown in FIG. 3). The received command enters the command register 414 and remains there until executed. Control logic 416 converts the command into a form that is executable on memory bank 402. Commands generally enter the NAND flash device 400 by asserting different pins on the chip's external package, where different pins can be used to represent different commands. For example, the commands can include chip enable, read enable, write enable, and write protection. Read and write commands are executed on a page basis, while erase commands are executed on a block basis.

  When a command is received at command register 414 and control logic 416, the address for the page in memory bank 402 to which the command is associated is received at output driver 412. That address is provided to address buffer and latch 418, and then to control and predecoder 406, sense amplifier (S / A) and data register 404, and row decoder 408 for accessing the page indicated by the address. The The data register 404 receives a complete page, which is provided to an I / O (input / output) buffer and latch 410 and then provided to an output driver 412 for output from the NAND flash device 400.

  For example, a read command is received at command register 414 and control logic 416 and an associated address is received at address buffer and latch 418. Address buffer and latch 418 determines the page where the address is located and provides row address (s) corresponding to that page to row decoder 408. The corresponding line is activated. The data register and the S / A 404 read the page and transfer the data of the page to the data register 404. When the entire page of data is transferred to the data register, the data is read sequentially from the device via the I / O buffer and latch 410 and the output driver 412.

  Program commands are also processed on a page basis. Program commands are received at command register 414 and control logic 416, associated addresses are received at address buffer 418, and input data is received at output driver 412. Input data is transferred to the data register 404 via the I / O buffer and latch 410. When all input data enters data register 404, the page storing the input data is programmed with the input data.

  Erase commands are processed on a block basis. The erase command is received by command register 414 and control logic 416 and the block address is received by address buffer 418.

  A normal NAND flash memory command uses two command cycles to complete the command load. Table 1 shows an example of a NAND flash memory command set.

  Many of the commands issued to the NAND flash memory in two command cycles are considered as one procedure and therefore cannot be interrupted, interrupted, suspended, or resumed. When NAND flash memory is receiving these two command cycles, it cannot accept any additional commands other than a reset command and a status read command. In a flash memory device having multiple memory banks, this command structure limits the use of banks because one bank is processing commands while the other is inactive. This leads to a reduction in I / O utilization when the command being executed has long internal core operations (eg, 20 μs page read, 200 μs page program, and 1.5 ms block erase). In a system having multiple flash memories interconnected in series, this command structure is used because the flash memory device that is processing the command cannot transfer another command to the subsequent flash memory device until the processing is complete. The overall processing speed may be reduced.

  An example of a command structure applicable to a system according to an embodiment of the present invention includes a command field having byte (s). For example, the command field has a first byte for device address and bank address and a second byte for operation code.

  FIG. 5A shows an example of a module command structure used in the NAND flash memory. In this particular example, the module command structure is byte based. Referring to FIG. 5A, the module command structure 500 includes a first byte 502 and a second byte 508 (bytes 1 and 2), each byte having a plurality of bits. In this particular example, the first byte 502 and the second byte 508 of the command structure include an 8-bit address and an 8-bit operation code, respectively. The first byte 502 has a 6-bit address 504 for the destination memory device. The 6-bit address 504 is used to distinguish memory devices in a system that includes multiple memory devices. The first byte 502 also includes a 2-bit address 506 for the memory bank of the memory device for use in a memory device having a plurality of memory banks. The second byte 508 of the command structure includes an 8-bit operation code 510 indicating a command to be executed by the memory device. Table 2 shows examples of operation codes.

  There are many variations on the command structure. In another example of a 2-byte command structure, the first byte has an 8-bit device address (DA), and the second byte has a 4-bit OP code and a 4-bit bank address (BA).

  FIG. 5B shows another example of the module command structure used in the NAND flash memory. Referring to FIG. 5B, the command structure 520 includes a plurality of bytes. In the illustrated example, the command structure 520 has a 2-byte module command structure (bytes 1 and 2) with a 3-byte row address 522 (bytes 3-5). The partial structure of the 2-byte module command in FIG. 5B is the same as the 2-byte module command structure shown in FIG. 5A. The first byte 502 has a 6-bit address 504 for the destination memory device and a 2-bit address 506 for the memory bank. The second byte 508 has an 8-bit operation code 510. The 3-byte row address 522 provides a 24-bit address 524 to the row (s) in the memory bank indicated by the first byte 502. This 24-bit (ie, 3 byte) row address 524 is used for commands where a row address is required to specify the location of the row on which the command is executed.

  FIG. 5C shows another example of the module command structure used in the NAND flash memory. Referring to FIG. 5C, the command structure 540 includes a plurality of bytes. In the illustrated example, the command structure 540 has a 2-byte module command structure (bytes 1 and 2) with a 2-byte column address 542 (bytes 3-4). The partial structure of the 2-byte module command in FIG. 5C is that the 2-byte module command of FIG. 5B has the first byte 502 having a 6-bit address 504 for the destination memory device and a 2-bit address 506 for the memory bank. Is the same. The second byte 508 has an 8-bit operation code 510. The 2-byte address 542 provides a 16-bit address 544 for the column (s) in the memory bank indicated by the first byte 502. This 16-bit (ie, 2 byte) column address 544 is used for commands where a column address is required to specify the column location where the command is to be executed.

  The command structures 500, 520, and 540 depend on the command being sent to the memory device. As shown in Table 2, some commands require an additional address (ie, row address or column address) supplied with the command. Thus, the command structures 500, 520, and 540 depend on the operation code in the second byte 508.

  Referring to FIGS. 1 and 5A-5C, the controller 104 translates the request from the host system 102 into one of command structures 500, 520, and 540 that can be interpreted by the flash memory device. Based on the operation code 510, the controller 104 determines whether a row address, a column address, or no address is supplied to the memory device. The controller 104 forms commands used by the memory devices 107-0, 107-1 to perform the operations.

  Each of the command structures 500, 520, and 540 includes both a memory device address 504 and a bank address 506. Thus, command processing can be interrupted and suspended by different memory devices. In addition, since the first byte 502 contains all the address information, each memory device will have the command indicated by the second byte 508 directed to those memory devices or passed to the next memory device. Can be determined very quickly.

  The module command structures 500, 520, and 540 can be used with any NAND flash memory device, but in the example below, the module command structures 500, 520, and 540 that use HLNAND ™ (HyperLink NAND) flash devices as examples Various command processing is described. The HLNAND ™ flash device is described in detail in US Provisional Patent Application No. 60 / 839,329 filed Aug. 22, 2006.

  An exemplary input sequence of module commands 500, 520, and 540 depending on the specific command in the operation code for the HLNAND ™ flash device is shown in Table 3. All commands, addresses, and data are shifted into and out of the device starting with the most significant bit (MSB). In the HLNAND ™ flash device, the serial data input (SDn) is sampled on the positive or negative clock edge while the serial data input enable (SDE) is “high”. In the specific example shown in Table 3, each command is a 1-byte target address (first byte) and table represented by “TDA” according to the command structures 500, 520, and 540 shown in FIGS. 5A to 5C. Contains the 1-byte operation code (second byte) shown in. When SDE goes logic high, the 1-byte address is shifted inward, followed by the 1-byte operation code. An exception to this operation is a device address write where the first byte entering the device is a page read command. Depending on the command, either the 3-byte row address represented by “R” in Table 3 or the 2-byte column address represented by “C” in Table 3 (3rd to 5th bytes) follows. . If data is provided to the flash device, the data is entered into the device after any row address or column address (as required) and is represented by “D” in Table 3.

  Examples of operation of the HLNAND ™ flash device using the module command structures 500, 520, and 540 for various operations are described below. The following example includes a timing diagram illustrating the processing of a memory device (eg, the memory device shown in FIGS. 1-3). The timing diagram signals are shown for an HLNAND ™ flash device as an example. The chip enable (CE #) signal indicates that the memory device is enabled when this signal is “low”. The serial data input (SDn) signal indicates a command, an address, and input data. The serial data output (SQn) signal indicates transmission of output data during a read operation. The serial data input enable (SDE) signal controls the data input so that the command address and input data (SDn) are latched into the device when this signal is "high". The serial data output enable (SQE) signal enables the output (SQn) when this signal is "high".

  If a device address is assigned to all serially connected devices (eg, the configuration shown in FIG. 3) at the start of system operation, the first byte of the command does not require a device address write. Sequential device address allocation is disclosed in US Provisional Patent Application No. 60 / 787,710 filed March 28, 2006 and US Provisional Patent Application No. 60 / 802,645 filed May 23, 2006.

  FIG. 6A shows an example of a flash controller to which the embodiment of the present invention can be applied. The flash controller corresponds to the controllers 104, 112, and 116 shown in FIGS.

  Referring to FIG. 6A, the flash controller 310 includes a central processing unit (CPU) 312 and a memory 314 having a random access memory (RAM) 316 and a read only memory (ROM) 318. The flash controller 310 also includes a flash command engine 322, an error correction code (ECC) manager 324, and a flash device interface 326. Further, the flash controller 310 includes a host interface controller 332 and a host interface 334. The CPU 312, the memory 314, the flash command engine 322, and the host interface controller 332 are connected via a common bus 330. Host interface 334 is for connecting to external devices via bus, connection link, interface, etc. (e.g. ATA (Advanced Technology Attachment), PATA (Parallel ATA), SATA (Serial ATA), USB (Universal Serial Bus)) It is. The host interface 334 is controlled by the host interface controller 332. The CPU 312 operates according to instructions stored in the ROM 318, and the processed data is stored in the RAM 316. The flash command engine 322 interprets the command, and the flash controller 310 controls the operation of the flash device via the flash device interface 326. The ECC manager 324 generates an ECC, and ECC verification is performed. In case of an error, an error message is generated. The flash controller 310 can be configured as a system on chip, system in package, or multiple chips.

  FIG. 6B shows an example of functional components of the flash command engine 322 of FIG. 6A when issuing a command to the flash device. Referring to FIGS. 1, 6A, and 6B, the flash command engine 322 interprets the request from the host system 102 into a plurality of separable commands that can be interpreted by the flash memory device. In this way, the flash controller 310 converts the request for access to the flash memory device into at least one command that uses the module command structure shown in FIGS. 5A to 5C. The flash controller 310 includes a connection to the bus 330 connected to the host interface controller 332. This connection allows communication with the host system 102 for the purpose of receiving a request from the processor 103 of the host system 102 to access the flash memory device. The flash controller 310 also includes a flash device interface 326 that communicates with the flash memory device. The flash device interface 326 operates as another connection for issuing commands to the flash memory device of the memory system.

  The flash command engine 322 includes a command structure mechanism 558, a bank interleave mechanism 560, a device interleave mechanism 562, an address identification mechanism 564, a command identification mechanism 566, a row address identification mechanism 568, and a column address identification mechanism 570. Command structure mechanism 558 handles the module command structure used in the memory device (eg, the module command structure shown in FIGS. 5A-5C). The address identification mechanism 564 and the command identification mechanism 566 analyze the request from the host system 102 and extract the memory device address and / or the bank address and the command from the request, respectively. The command identification mechanism 566 determines a plurality of commands used to execute the request. Each command is separable and combined to satisfy the request from the host system 102. The command identification mechanism 566 collects information including the address from the address identification mechanism 564 and forms a command. If any command that forms the request is associated with a row address or column address, the command identification mechanism 566 forms part of the command using the row address identification mechanism 568 or the column address identification mechanism 570, respectively. Get the row or column address.

  The bank interleave mechanism 560 and the device interleave mechanism 562 order the commands sent to the memory banks or memory devices via the device interface 326, respectively. The module command structure is configured so that each memory bank can be processed simultaneously by a flash memory device having a plurality of memory banks. Similarly, the module command structure is configured such that processing is performed simultaneously in serially connected memory devices. The bank interleaving mechanism 560 interleaves commands for different memory banks in the same memory device (see FIGS. 16 to 21 for examples of parallel operations in a plurality of memory banks). The device interleave mechanism 562 interleaves commands for different memory devices in the same memory system (see FIGS. 22-28).

  The EEC manager 324 generates an error correction code (ECC) to verify that a command was successful and executed completely.

  FIG. 6B shows the functional components of the flash command engine 322 and can be implemented in many configurations that would be recognized by one skilled in the art.

  The module command can include a page read command. In the command structure, the first cycle of the page read command is input, and then the column address of the start column address in the target page address and the row address of the target page address are input. A second cycle of page read commands is entered, after which the device is busy for a period of time (eg, 20 μs) until the internal page read operation is complete. After such a waiting period, a burst data read operation is performed to retrieve data from the device buffer. The device cannot perform another operation from the start of this operation until the burst data reading is completed.

Fig. 7 shows the flow of the page read command. The controller for the system generates a page read command at step 602 that includes a destination flash device address, a memory bank address, a page read operation code, and a 3-byte row address for the row (s) that define the page to be read. The page read command passes through the flash devices forming the system until the destination flash device address matches the flash device that receives the page read command. A page read command including the row address (es) is received at the destination flash device. The page read command is provided to the destination flash command register and the address latch cycle begins to input a 3-byte row address. At the end of the address latch cycle, a page read operation is initiated on the flash device and the data in the selected page is read and data is transferred in less than time t _R (transfer time from memory bank to data register, eg 20 μs). Transferred to a register.

The controller waits for t _R to collect data from the page or generates a device status query and sends it to the flash device to receive notification when the page is accessed. If the controller generates a device status command, the command is sent to the flash device at step 604. The flash device will respond to this request with a continuous busy indication until the page is accessed and the flash device indicates that the memory bank is ready and no longer busy. The controller continuously checks at step 606 to determine whether the memory bank is ready.

When the memory bank becomes ready or the controller waits for t _R , a burst data read command with a device address and column address is issued at step 608. If the controller does not send a device status query and does not wait for t _R , steps 604 and 606 are not executed. When the device receives a burst data read, the SQE signal is then enabled and the page data in the data register is read in step 610 starting from the column address provided in the command. This reading continues until SQE goes low via SQn.

  An error correction code (ECC) is generated by the controller at step 612 and verified at step 614. If the ECC is not verifiable, an error message is issued at step 616. If the ECC is verified, the page read operation is successful and the operation is completed at step 618. For example, the flash device controller generates ECC parity bits for 2048 bytes of input data per page. Thus, 2048 bytes of data with ECC parity bits are programmed (usually 1 byte of ECC for every 512 bytes and 4 bytes of ECC for every 2048 bytes per page). ECC parity bits are programmed with a 64-byte spare field in the page. During a page read, the flash device controller reads 2048 bytes of data along with ECC parity information. The flash device controller verifies 2048 bytes of data along with 4 bytes of ECC information. Therefore, the ECC process is executed by the flash device controller, and the flash memory device stores only ECC parity information.

FIG. 8 shows a timing diagram of a page read operation as seen from the flash device, in which the controller waits until the period of t _R to expire in order to obtain the requested data. If a burst data read command is issued and SQE is enabled during the bank busy period t _R , all output data is invalid.

  FIG. 9 shows a timing diagram of a page reading operation accompanied by a device status from the controller as seen from the flash device.

  Module commands can include page program commands. In the command structure, the first cycle of the page program command is input, and then the column address of the start column address and the row address of the target page address in the target page address are input. The input data is then loaded, followed by the second cycle of page program commands. Until the internal page program operation is complete, the device will be busy for a period of time (eg, 200 μs) after the second cycle. These steps are all considered as one procedure when the page program operation is completed and are not interruptible.

  FIG. 10 shows the flow of the page program command from the flash device controller. The controller for the system generates a burst data load start command in step 902 that includes the destination flash device address, memory bank address, burst data load start operation code, and the 2-byte column address of the column (s) to be programmed. . The burst data load start command passes through the flash devices forming the system until the destination flash device address matches the flash device that receives the burst data load start command. The burst data load start command is provided to the command register of the destination flash unit together with the 2-byte column address at step 904 and then with the input data at step 906. The burst data load start command resets all data registers in the destination flash device. If the burst data load start operation has not entered all the data into the flash device, a subsequent burst data load command can be used to place all the data in the device.

The flash device controller again generates a page program command specifying the destination device address and memory bank address, and the page program operation code and row address (s) specifying the line to be written by the page program operation, at step 908. The page program command is generated by the controller after time t _DDE after data is loaded into the flash device by a burst data load start command. This loads the loaded data into the selected page position.

  The controller uses the device status command issued at step 910 to monitor the status of the page program operation. The flash device will respond to this request with a continuous busy indication until a page is accessed, indicating that the flash device's memory bank is ready and no longer busy. The controller continuously checks in step 912 to determine whether the memory bank is ready. When the memory bank becomes ready, the controller checks whether the page program operation was successful. If unsuccessful, an error is output at step 916, otherwise the page program operation is completed at step 918.

  FIG. 11 shows a timing diagram of the page program operation seen from the flash device, where the start of burst data loading is sufficient to load all the data into the device. FIG. 12 shows a timing diagram of a page program operation that requires a burst data load operation after a burst data load start operation to load all data into the device.

  The module command can include a block erase command. In the command structure, the first cycle of the block erase command is input, and then the row address of the target block address is input. The second cycle of the block erase command is entered after the device has been busy for 1.5 ms to complete the internal block erase operation.

  FIG. 13 shows the flow of block erase operation from the controller. The flash device controller for the system generates a block erase address input command including a device address, a memory bank address, and an operation code in step 1202, and generates a 3-byte row address in step 1204. If more than one block is erased at a time in step 1206, an additional block erase address input command is generated by the controller to specify these additional blocks. When all blocks have been specified, the controller generates a block erase command at step 1208 to initiate a flash device that performs a block erase operation on the selected block. The block erase command generated by the controller includes a device address, a memory bank address, and an operation code.

  The controller issues a status command at step 1210 that is used to determine when the memory bank is available and the block erase operation is complete. In step 1212, the controller continuously checks for device status until a memory bank is available. When the block erase operation is complete, the controller checks in step 1214 if the operation was successful. If the operation was not successful, an error is issued at step 1216, otherwise the block erase operation is completed at step 1218.

  FIG. 14 shows a timing diagram of a block erase operation in which only a single block is erased as seen from the flash device. FIG. 15 shows a timing diagram of a block erase operation in which a plurality of blocks are erased.

  The module command structure shown in FIGS. 5A-5C provides a memory bank address that is supplied in the first byte along with the device address. This memory bank address is used to designate a memory bank as a destination of a command in an environment where the flash memory device has two or more memory banks. A command having a module command structure specifies a memory bank address with the command, so a flash device having a configuration in which each memory bank operates independently executes operations in two or more memory banks of the flash device at a time. Can be made. The HLNAND ™ flash device is an example of such a flash memory.

  The pin configuration of multiple HLNAND ™ flash devices cascaded at the top level may be the same as one of the single devices. In a serial interconnect configuration, each device introduces an additional half clock cycle wait time, for example, on the cascading path. Thus, the number of cascaded devices determines the total clock latency of operation in a series interconnect configuration. In multiple device configurations with multiple interconnected memory banks, the controller can effectively schedule many different procedures accessing time-consuming core operations by command interleaving.

  FIGS. 16 to 21 illustrate parallel operations being performed on two memory banks in a single flash memory device.

FIG. 16 shows the flow of a parallel page read operation from two memory banks in the same flash memory device. A page read command is provided to memory bank 0 in step 1502. Memory bank 0 then proceeds to process the request by accessing the requested page. While memory bank 0 is processing the page read command, a second page read command is provided to memory bank 1 at step 1504. Memory bank 1 then proceeds to process the request by accessing the requested page while memory bank 0 is processing its own request in parallel. The time t _R1 after the page read request is given to memory bank 0 has elapsed in step 1506, and then the burst data read command steps to access the data obtained from the page read command issued in step 1502. 1508 is given to memory bank 0. The time t _R2 after the page read request is given to memory bank 1 has elapsed in step 1510, and then the burst data read command steps to access the data obtained from the page read command issued in step 1504. At 1512, it is given to memory bank 1.

  FIG. 17 shows the timing of the parallel page reading operation shown in FIG.

  FIG. 18 shows the flow of concurrent page program operations in two memory banks of the same flash memory device. At step 1702, a burst data load start command is provided to memory bank 0 along with the data programmed into memory bank 0. At step 1704, a burst data load start command is provided to memory bank 1 along with data to be programmed into memory bank 1. In step 1706, a page program command is provided to memory bank 0, and in step 1708, a page program command is provided to memory bank 1. A status read command is provided to memory bank 0 at step 1710 and to memory bank 1 at step 1712 to monitor the progress of completion of the page program operation for each memory bank. When the status returns a pass for each memory bank, the page program operation is complete and other operations can be performed on the memory bank.

  FIG. 18 shows a burst data load start command given to each memory bank before the page program command is provided to each bank. Both the burst data load start command and the page program command can be applied to memory bank 0 before any command is applied to memory bank 1. FIG. 19 shows the timing of the concurrent page program operation in which the burst data load start command and the page program command are given to the memory bank 0 before any command is given to the memory bank 1.

  FIG. 20 shows the flow of a parallel block erase operation in two memory banks of the same flash memory device. In step 1902, a block erase address input command is given to the memory bank 0 together with the address of the block to be erased. At step 1904, a block erase address input command is applied to the memory bank 1 together with the address of the block to be erased. Upon receiving that the block indicated by the block erase address input command received at step 1902 is erased, the block erase command is provided to the memory bank 0 at step 1906. Upon receiving that the block indicated by the block erase address input command received at step 1904 is erased, the block erase command is given to the memory bank 1 at step 1908. A status read command is provided to memory bank 0 at step 1910 and to memory bank 1 at step 1912 to monitor the progress of the block erase operation. When the status returns a pass for each memory bank, the block erase operation is complete and other operations can be performed on the memory bank.

  FIG. 20 shows a block erase address input command given to each memory bank before the block erase command is provided to each bank. Both the block erase address input command and the block erase command can be applied to the memory bank 0 before any command is applied to the memory bank 1. FIG. 21 shows the timing of the parallel block erase operation in which the block erase address input command and the block erase command are given to the memory bank 0 before any command is given to the memory bank 1.

  Operations performed in parallel by the memory bank need not be the same operation. 22-25 show different operations performed in parallel by two memory banks of the same flash memory device.

FIG. 22 shows the flow of parallel page read operations and page program operations in two memory banks of the same flash memory device. A page read command is provided to memory bank 0 in step 2102. While memory bank 0 is accessing the page indicated by the page read command, a burst data load start command is provided to memory bank 1 in step 2104 along with the data programmed into memory bank 1. A page program command is provided to memory bank 1 at step 2106 to begin programming data into memory bank 1. To access the data retrieved by the page read operation after the time t _R has elapsed in step 2108 after the page read command was given in step 2102 so that memory bank 0 can retrieve the requested data , A burst data read command is provided to memory bank 0 in step 2110. A status read command is provided to memory bank 1 at step 2112 to monitor the progress of page program operations. When the status returns pass for memory bank 1, the page program operation is complete and other operations can be performed in memory bank 1.

  FIG. 23 shows the timing of the parallel page reading operation and page program operation of FIG.

FIG. 24 shows the flow of pause and resume operations performed in two memory banks of the same flash memory device where a page read operation is performed in memory bank 0 and a page program operation is performed in memory bank 1. . Burst data load start is provided to memory bank 1 at step 2302 along with data programmed into memory bank 1. Before all data is loaded into memory bank 1 with the burst data load start operation, this operation is suspended when a page read command is applied to memory bank 0 at step 2306. After a page read command is completely received at memory bank 0 and while memory bank 0 is accessing the requested page, an operation at memory bank 1 uses a burst data load operation with the remaining data. And resumed at step 2308. When data is provided to memory bank 1, a page program command is provided to memory bank 1 at step 2310, where it begins programming the data. After a page read command is provided to memory bank 0 in step 2306, time t _R is passed in step 2312. When t _R elapses, a burst data read command is provided to memory bank 0 in step 2314 to start extracting the requested data from memory bank 0. The burst data read command is suspended at step 2316 when a status read command is provided to memory bank 1 at step 2318 to monitor the status of the memory bank. The burst data read command is resumed at step 2320 when a status read command is received. When the page program operation is complete, memory bank 1 returns a pass to the status read command and other operations can be performed in memory bank 1.

  FIG. 25 shows the timing of the page reading operation and the page program operation that are paused and resumed in FIG.

  FIG. 26 to FIG. 28 show the interleaving of operations between a plurality of devices. FIG. 26 shows a page read operation in both memory bank 0 and memory bank 1 of flash device 0 and flash device 1, a block erase operation in memory bank 0 of flash device 2, memory bank 1 and flash device of flash device 2. 3 shows a page program operation in the memory bank 0 and a page pair erase operation in the memory bank 1 of the flash device 3. FIG. 27 shows a page read operation in memory banks 0 and 1 of flash devices 0, 1, 2, and 3. FIG. 28 shows the page program operation in the memory bank 0 of the flash device 0 and the subsequent page read operation, the page read operation and the subsequent block erase operation in the memory bank 1 of the flash device 0, and the flash devices 1 and 3. Block erase operation in memory bank 0 and memory bank 1 of flash devices 2 and 3, page program operation in memory bank 1 of flash device 1, and page read operation followed by page in memory bank 0 of flash device 2 Indicates program operation.

  In the above embodiment, the memory device is described as a flash memory device. It will be apparent to those skilled in the art that the memory device may be a random access memory device, such as, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a magnetoresistive random access memory (MRAM). Further, the plurality of memory devices included in the memory system may be the same type of device or a device in which a plurality of types are mixed. A configuration of mixed types of devices connected in series is disclosed in US Provisional Patent Application No. 60 / 868,773, filed Dec. 6, 2006.

  In the above-described embodiments, the device elements and circuits are connected to each other as shown in the figure for simplicity. In practical applications, these devices, elements, circuits, etc. can be connected directly to each other or indirectly through other devices, elements, circuits, etc. Thus, in an actual configuration, the elements, circuits, and devices are coupled to each other directly or indirectly.

  The above-described embodiments of the present invention are intended to be examples only. Changes, modifications, and variations to the specific embodiments can be made by those skilled in the art without departing from the scope of the invention, which is defined only by the claims appended hereto.

102 Host system
103 processor
104 controller
106 Memory system
107-0 flash memory device
107-1 Flash memory device
108-0 flash memory device
108-1 Flash memory device
108-2 Flash memory device
108-3 Flash memory device
109-0 flash memory device
109-1 Flash memory device
109-2 Flash memory device
109-3 Flash memory device
112 controller
114 Common bus
116 controller
310 flash controller
312 CPU
314 memory
316 RAM
318 ROM
322 Flash command engine
324 ECC Manager
326 Flash device interface
330 Common bus
332 Host interface controller
334 Host interface
400 NAND flash device
402 memory bank
404 S / A and data registers
406 Control and Predecoder
408 line decoder
410 I / O buffers and latches
412 Output driver
414 Command register
416 control logic
418 Address buffer and latch
500 module command structure
502 1st byte
504 Memory device address
506 Bank address
508 2nd byte
510 Operation code
520 Command structure
522 line address
524 line address
540 Command structure
542 column address
544 column address
558 Command structure mechanism
560 Bank Interleave Organization
562 Device interleave mechanism
564 Address identification mechanism
566 Command identification mechanism
568 Line address identification mechanism
570 column address identification mechanism

Claims (35)

A command structure including a plurality of separable commands representing a request for access to one of a plurality of memory devices, each of the plurality of separate commands comprising:
A device identifier comprising an address for the one of the plurality of memory devices and a bank address for one of a plurality of memory banks in the one of the plurality of memory devices;
And a command identifier including an operation code representing an operation executed by the one of the plurality of memory devices.   The one memory device includes at least one memory bank, and the address identifier includes a device address for one of the at least one memory device and a bank address for one of the at least one memory bank. Item 1. Command structure.   3. The command structure according to claim 2, wherein the address identifier includes an identifier of m bytes, and m is an integer.   4. The command structure according to claim 3, wherein the device address includes an n-bit address, the bank address includes a p-bit address, and n and p are each integers.   The command structure according to claim 1, wherein the command identifier includes a command identifier of q bytes, and q is an integer.   The command structure according to claim 1, wherein the module structure further includes a row address designating a row in a memory bank of the at least one memory device to which the operation with the command identifier is applied.   The module structure further includes a row address when the type of operation has been determined, the row address in the memory bank of the at least one memory device to which the operation with the command identifier is applied. The command structure of claim 1, wherein the command structure specifies a line.   7. The command structure according to claim 6, wherein the row address includes an address of r bytes, and r is an integer.   2. The command structure of claim 1, wherein the module structure further includes a column address specifying a column in a memory bank of the at least one memory device to which the operation with the command identifier is applied.   The module structure further includes a column address when the type of operation has been determined, the column address in the memory bank of the at least one memory device to which the operation with the command identifier is applied. The command structure of claim 1, wherein the command structure specifies a column.   10. The command structure according to claim 9, wherein the column address includes an address of s bytes, and s is an integer.   The one memory device includes at least one memory bank, and the address identifier includes a device address for one of the at least one memory device and a bank address for one of the at least one memory bank. The module command structure according to claim 11.   13. The module command structure according to claim 12, wherein the command identifier includes an identifier of q bytes, and q is an integer.   13. The module command structure according to claim 12, wherein the module structure further includes a row address designating a row in a memory bank of the at least one memory device to which the operation with the command identifier is applied.   The module structure further includes a row address when the type of operation has been determined, the row address in the memory bank of the at least one memory device to which the operation with the command identifier is applied. The module command structure of claim 12, wherein the module command structure specifies a line.   16. The module command structure of claim 15, wherein the row address includes an r-byte address, and r is an integer.   13. The module command structure according to claim 12, wherein the module structure further includes a column address designating a column in a memory bank of the at least one memory device to which the operation with the command identifier is applied.   The module structure further includes a column address when the type of operation has been determined, the column address in the memory bank of the at least one memory device to which the operation with the command identifier is applied. The module command structure of claim 12, which specifies a column. The m-byte identifier includes a 1-byte identifier,
The n-bit address includes a 6-bit address;
5. The command structure according to claim 4, wherein the p-bit address includes a 2-bit address.   9. The command structure according to claim 8, wherein the r-byte row address includes a 3-byte address.   6. The command structure according to claim 5, wherein the q-byte command identifier includes a 1-byte operation code. A device identifier comprising an address for one of a plurality of memory devices and a bank address for one of a plurality of memory banks in the one of the plurality of memory devices;
A module command structure including a command identifier including an operation code representing an operation executed by the one of the plurality of memory devices. A memory system including at least one memory device for storing data;
A processor that manages requests for access to the memory system;
A controller that translates the request from the processor into one or more separable commands that are interpretable by the at least one memory device, wherein each command is directed to one of the at least one memory device. A system having a module structure including an address identifier and a command identifier representing an operation performed by the one of the at least one memory device, wherein the at least one memory device and the controller communicate with each other System connected in series for.   The at least one memory device includes at least one memory bank, and the address identifier includes a device address for one of the at least one memory device and a bank address for one of the at least one memory bank. 24. The system of claim 23.   25. The system of claim 24, wherein the controller generates one or more separable commands on different memory devices and interleaves the issuance of these one or more separable commands to different memory devices.   The at least one memory device includes at least two memory banks, and the controller generates one or more separable commands for each of the at least two memory banks, one or more of these 26. The system of claim 25, wherein the issuance of separable commands is interleaved, so that the at least two memory banks process the issued separable command or commands in parallel.   24. The system of claim 23, wherein the memory devices in the memory system are connected to a common bus.   24. The system of claim 23, wherein the memory devices in the memory system are connected in series.   24. The system of claim 23, wherein the memory device comprises a NAND flash memory device. A controller for a system having a plurality of memory devices for storing data, comprising a serial interconnection for communication with the plurality of memory devices,
A first connection for receiving a request for access to the plurality of memory devices;
A translation device that translates the request into a plurality of separable commands that are interpretable by the plurality of memory devices, each command having an address identifier for one of the plurality of memory devices, and the plurality of memories A conversion device having a modular structure including a command identifier representing an operation performed by one of the devices;
And a second connection for communication with one of the plurality of memory devices that issues the plurality of separable commands. Determining an address including a memory device address;
Identifying a plurality of operations that satisfy a request for access to memory;
Providing a plurality of separable commands for the memory, each of the commands including a device identifier having a memory device address and a command identifier having one of the plurality of operations. ,Method. A method of translating a request for access to a memory device into a plurality of separable commands that can be interpreted by the memory device,
The step of determining includes determining an address for the memory device and an address for a memory bank of the memory device;
The identifying step includes identifying a plurality of operations that are combined to satisfy the request;
The providing step includes providing the plurality of separable commands, each command including a device identifier including the memory device address and the memory bank address, and one of the plurality of operations. 32. The method of claim 31, comprising: an identifier, wherein the command identifier is interpretable by the memory device, and the plurality of separable commands are issued to the memory device. Said providing step comprises:
generating an apparatus identifier of m bytes, where m is an integer;
generating n-bit memory device addresses and p-bit memory bank addresses, where n and p are each integers;
generating a q-byte command identifier, wherein q is an integer,
32. The method of claim 31, further comprising interleaving the issuance of each of the plurality of separable commands having different device identifiers. The memory device comprises at least two memory banks, wherein the at least two memory banks are controlled in parallel;
The step of determining includes determining an address for the memory device and an address for each of the at least two memory banks;
The step of identifying includes identifying a plurality of operations that are combined to satisfy a request for access to each of the at least two memory banks;
The providing step includes generating the plurality of separable commands for each of the at least two memory banks, wherein each of the plurality of separable commands is issued to the memory device. 32. The method of claim 31. A method for interleaving requests for access to a plurality of memory devices, comprising:
The step of determining includes an address for each of the plurality of memory devices;
Said identifying step includes identifying a plurality of operations that are combined to satisfy each request;
The providing step is a step of generating a plurality of separable commands for each request related to each of the plurality of memory devices, wherein each command includes a device identifier having the memory device address and the plurality of operations. 32. A command identifier having one of the following: the command identifier is interpretable by the memory device, and each of the plurality of separable commands is issued to the memory device. the method of.

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