JP2011113877A - Photoelectric hybrid substrate, and semiconductor device - Google Patents

Abstract

An opto-electric hybrid board that can be easily manufactured at a reduced manufacturing cost and can perform high-speed optical communication is provided.
In the opto-electric hybrid board according to the present invention, a first semiconductor circuit and a first light emitting element are provided on the first semiconductor substrate, the first semiconductor circuit is electrically connected to the first light emitting element, and The first light-emitting element includes a first electrode, a second electrode having translucency, and a carrier part sandwiched between the first electrode and the second electrode, and the carrier The body portion is light-transmitting and has a light emitter inside, and the first light-emitting element optically outputs a signal that is processed by the first semiconductor circuit.
[Selection] Figure 1

Description

  The present invention relates to an opto-electric hybrid board and a semiconductor device.

  In recent years, with the development of information communication technology and information processing technology, the electrical wiring that connects the electronic circuits in devices such as computers and large-capacity switches has become denser, and this is a factor that hinders the large scale and high performance of the system It has become. In addition, the remarkable development of LSI in recent years has led to higher density of input / output terminals of LSI and higher density of electric wiring inside LSI, and has become a bottleneck for improving performance. In order to solve such a problem, an optical interconnection technique for connecting electronic circuits with light has been attracting attention.

  In general, an optical interconnection device includes a light emitting element such as a surface emitting semiconductor laser (VCSEL), a driver IC that drives the light emitting element, a light receiving element such as a photodiode, and a receiver that drives the light receiving element. A component such as an IC is two-dimensionally arranged on the submount substrate. For example, as described in Patent Document 1 and Patent Document 2, it is connected to an LSI circuit on which a CPU circuit or a memory circuit is mounted by a technique such as flip chip bonding or wire bonding.

  For example, as shown in FIG. 20, a general VCSEL light emitting device uses a compound semiconductor such as GaAs as a support substrate, and an n-type electrode 111, an n-type contact layer 102, an n-type DBR formed thereon. The structure includes a layer 103, an active layer 104, a p-type DBR layer 105, a p-type contact layer 108, a p-type electrode 110, and the like.

  Further, for example, in an optical interconnection device in which a VCSEL light emitting element is mounted by a flip chip bonding technique, the VCSEL light emitting element 120 and the submount substrate 125 are electrically connected by solder bumps 122 as shown in FIG. have.

JP 2009-21430 A JP 2007-59673 A

However, since the VCSEL light emitting device has a complicated structure, there is a drawback that the product cost is increased.
In addition, a conventional optical interconnection device in which a VCSEL light emitting element is mounted by a flip chip bonding method requires a certain connection area (for example, about several hundreds of um), and it is difficult to mount the light emitting elements at high density. . Furthermore, because of the bump connection, parasitic inductance and parasitic capacitance increase, which may make high-speed optical communication difficult. In addition, there is a possibility of being exposed to a high voltage such as static electricity when mounting the VCSEL light emitting element.
The present invention has been made in view of such circumstances, and provides an opto-electric hybrid board that can be easily manufactured at a reduced manufacturing cost and can perform high-speed optical communication.

  The present invention is a circuit in which a first semiconductor circuit and a first light emitting element are provided on a first semiconductor substrate, and the first semiconductor circuit is electrically connected to the first light emitting element and performs signal processing. The first light-emitting element includes a first electrode, a second electrode having translucency, and a carrier part sandwiched between the first electrode and the second electrode, and the carrier part has translucency. In addition, there is provided an opto-electric hybrid board characterized by having a light emitter inside, and the first light emitting element optically outputs a signal processed by the first semiconductor circuit.

According to the present invention, since the light emitting element having a simple structure is provided on the same semiconductor substrate as the semiconductor circuit, the step of mounting the light emitting element on the submount substrate by a technique such as flip chip bonding or wire bonding is omitted. Can do.
In addition, according to the present invention, since the light emitting element has a simple structure including the first electrode, the carrier portion having the light emitter inside, and the second electrode, the light emitting element can be easily provided on the semiconductor substrate. it can.
Therefore, the opto-electric hybrid board of the present invention can be easily manufactured at a reduced manufacturing cost.
Furthermore, according to the present invention, since the light emitting element can be provided adjacent to the semiconductor circuit, parasitic inductance and parasitic capacitance can be reduced. Thus, according to the present invention, high-speed optical communication can be performed stably.

(A) is a schematic plan view of the opto-electric hybrid board of one embodiment of the present invention, (b) is a schematic cross-sectional view thereof, and (c) is a schematic cross-sectional view of a first light emitting element included in the substrate. is there. It is a schematic plan view of the opto-electric hybrid board of one embodiment of the present invention. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention. It is a schematic sectional drawing of the opto-electric hybrid board of one embodiment of the present invention. (A) (b) is a schematic plan view of the opto-electric hybrid board of this embodiment. It is a schematic sectional drawing of the opto-electric hybrid board of one embodiment of the present invention. It is a schematic sectional drawing of the 1st light emitting element contained in the opto-electric hybrid board of one embodiment of the present invention. FIG. 8 is a band diagram in the vicinity of a pn junction included in the first electrode illustrated in FIG. 7. (A) is a schematic sectional drawing of the 1st light emitting element which is a 1st light emitting element contained in the opto-electric hybrid board of one embodiment of the present invention, and used a carbon nanotube etc. as a convex part. FIG. 2B is a schematic cross-sectional view of a first light emitting element that is a first light emitting element included in the opto-electric hybrid board according to the embodiment of the present invention and that has a conical convex portion formed thereon. (C) is a schematic sectional drawing of the 1st light emitting element contained in the photoelectric hybrid board | substrate of one Embodiment of this invention at the time of applying a voltage between a 1st electrode and a 2nd electrode. It is a schematic sectional drawing of the opto-electric hybrid board of one embodiment of the present invention. It is a schematic sectional drawing of the semiconductor device of one Embodiment of this invention. It is explanatory drawing of the manufacturing method of the opto-electric hybrid board of one Embodiment of this invention. It is explanatory drawing of the manufacturing method of the opto-electric hybrid board of one Embodiment of this invention. It is a schematic sectional drawing of the light emitting element created by EL experiment. It is the emission spectrum of the light emitting element created by EL experiment. It is an emission spectrum of the light emitting element produced on various temperature conditions. It is an emission spectrum of the light emitting element produced on various germanium ion implantation conditions. (A) is the XPS spectrum in each depth of the silicon oxide film contained in the light emitting element produced by EL experiment. (B) is a graph showing the relationship between the depth of the silicon oxide film included in the light emitting device produced in the EL experiment and the ratio of Ge, GeO, or GeO ₂ . The depth of the silicon oxide film in the light-emitting element manufactured in EL experiment is a graph showing the relationship between the ratio of GeO or GeO _2. It is a schematic sectional drawing of the conventional VCSEL light emitting element. It is a schematic sectional drawing of the optical interconnection apparatus carrying the conventional VCSEL light emitting element.

  In the opto-electric hybrid board according to the present invention, the first semiconductor circuit and the first light emitting element are provided on the first semiconductor substrate, the first semiconductor circuit is electrically connected to the first light emitting element, and the signal calculation is performed. The first light-emitting element includes a first electrode, a second electrode having translucency, and a carrier part sandwiched between the first electrode and the second electrode, and the carrier part includes: The first light-emitting element has a light-transmitting property and has a light-emitting body inside. The first light-emitting element optically outputs a signal processed by the first semiconductor circuit.

The opto-electric hybrid board refers to a board in which a semiconductor circuit and an optical element are mixed on one board.
A light-emitting element refers to an element that emits light when a current is applied or a voltage is applied.
The light receiving element is an element that generates an electromotive force by receiving light.

In the opto-electric hybrid board according to the present invention, it is preferable that the light emitter is a fine particle containing GeO and GeO ₂ .
According to such a configuration, the first light emitting element can emit light by applying a voltage to the first light emitting element.
In the opto-electric hybrid board according to the present invention, it is preferable that the light emitter contains 10% or more of GeO when the total of GeO and GeO ₂ contained in the light emitter is 100%.
According to such a configuration, the first light emitting element can emit light with higher luminance.

In the opto-electric hybrid board of the present invention, it is preferable that the first light emitting element exhibits electroluminescence having an emission wavelength peak in a range of 340 to 440 nm.
According to such a configuration, higher-speed optical communication can be performed.
In the opto-electric hybrid board according to the present invention, the light emitter is preferably a fine particle having a maximum particle size of 1 nm or more and 20 nm or less.
According to such a configuration, the first light emitting element can emit light with higher luminance.

In the opto-electric hybrid board of the present invention, it is preferable that the second electrode has a light transmittance of 60% or more and 99.99% or less with a wavelength of 300 nm to 500 nm.
According to such a configuration, light emitted from the light emitter can be extracted more efficiently.
In the opto-electric hybrid board according to the present invention, the first light emitting element is preferably provided adjacent to the first semiconductor circuit.
According to such a configuration, the parasitic inductance and the parasitic capacitance can be further reduced.

In the opto-electric hybrid board of the present invention, the first semiconductor substrate is preferably a silicon substrate, a germanium substrate, a silicon compound substrate, or a germanium compound substrate.
According to such a configuration, the opto-electric hybrid board can be formed more easily.
In the opto-electric hybrid board according to the present invention, the first electrode is preferably a part of the first semiconductor substrate and a part doped with an n-type impurity.
According to such a configuration, the first light emitting element can emit light with higher luminance.

In the opto-electric hybrid board according to the present invention, the first electrode has a p-type semiconductor portion and an n-type semiconductor portion, and the p-type semiconductor portion and the n-type semiconductor portion are pn on the surface in contact with the carrier portion. It is preferable to have the part to join.
According to such a configuration, the first light emitting element can efficiently emit light at a lower voltage.

In the opto-electric hybrid board according to the present invention, it is preferable that at least one of the p-type semiconductor portion and the n-type semiconductor portion has an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ or more.
According to such a configuration, the first light emitting element can efficiently emit light at a lower voltage.
In the opto-electric hybrid board according to the present invention, the first electrode has a plurality of convex portions on the surface in contact with the carrier portion, and an interval between the upper end of the convex portion and the second electrode is the convex portion of the first electrode. It is preferable that the distance between the other part and the second electrode is narrower.
According to such a configuration, the first light emitting element can emit light evenly.

In the opto-electric hybrid board according to the present invention, the interval between the portion of the first electrode other than the convex portion and the second electrode is 1.1 times or more the interval between the upper end of the convex portion and the second electrode. preferable.
According to such a configuration, the first light emitting element can emit light evenly.
In the opto-electric hybrid board according to the present invention, the distance between the upper end of the convex portion and the second electrode is preferably 5 nm or more and 100 nm or less.
According to such a configuration, the first light emitting element can emit light with a lower applied voltage.

In the opto-electric hybrid board according to the present invention, the convex portion is preferably made of a carbon nanotube, a conical metal, or silicon.
According to such a structure, the 1st light emitting element in which the 1st electrode has a convex part can be formed more easily.
In the opto-electric hybrid board according to the present invention, it is preferable that two adjacent convex portions have an interval of 10 nm or more and 3 μm or less.
According to such a configuration, the first light emitting element can emit light evenly.

In the opto-electric hybrid board according to the present invention, it is preferable that the convex portion has a conical shape in which the inclination becomes gentler as the distance from the apex increases.
According to such a configuration, the first light emitting element can emit light with a lower applied voltage.

In the opto-electric hybrid board according to the present invention, it is preferable that a fourth light emitting element is further provided on the first semiconductor substrate, the fourth light emitting element is electrically connected to the first semiconductor circuit, and the first semiconductor circuit is It is preferable to optically output the signal subjected to the arithmetic processing with light having a wavelength different from that of the first light emitting element.
According to such a configuration, the amount of information that the first semiconductor circuit can optically output can be further increased.
In the opto-electric hybrid board according to the present invention, it is preferable that a second semiconductor circuit and a second light receiving element are further provided on the first semiconductor substrate, the second semiconductor circuit is electrically connected to the second light receiving element, and The second light receiving element preferably inputs light output from the first light emitting element through an optical connection unit.
According to such a configuration, it is possible to transmit a signal that has been subjected to arithmetic processing by the first semiconductor circuit to the second semiconductor circuit.

In the opto-electric hybrid board of the present invention, it is preferable that the first semiconductor substrate is further provided with a second light emitting element and a first light receiving element, and the second light emitting element is electrically connected to the second semiconductor circuit, and The second semiconductor circuit performs optical processing on the signal that is processed, the first light receiving element is electrically connected to the first semiconductor circuit, and the light output from the second light emitting element is passed through the optical connection unit. It is preferable to input light.
According to such a configuration, the first semiconductor circuit and the second semiconductor circuit can perform bidirectional optical communication.

The present invention also includes the opto-electric hybrid board of the present invention and a second semiconductor substrate, wherein the second semiconductor substrate is provided with a third semiconductor circuit and a third light receiving element, It is a circuit that is electrically connected to the light receiving element and performs signal arithmetic processing. The third light receiving element also provides a semiconductor device that optically inputs the light output from the first light emitting element.
According to the semiconductor device of the present invention, it is possible to transmit a signal obtained by performing arithmetic processing by the first semiconductor circuit to the third semiconductor circuit formed on the second semiconductor substrate.

In the semiconductor device of the present invention, it is preferable that a first light receiving element is further provided on the first semiconductor substrate, a third light emitting element is preferably further provided on the second semiconductor substrate, and the third light emitting element is a third semiconductor. A signal electrically connected to the circuit and the third semiconductor circuit performing an arithmetic process; and a first light receiving element electrically connected to the first semiconductor circuit and a third light emitting element It is preferable to optically input the output light.
According to such a configuration, the first semiconductor circuit provided on the first semiconductor substrate and the third semiconductor substrate provided on the second semiconductor substrate can perform bidirectional optical communication.
In the semiconductor device of the present invention, it is preferable that the first light emitting element and the third light receiving element are arranged to face each other, and the third light emitting element and the first light receiving element are arranged to face each other.
According to such a configuration, the optical waveguide can be omitted and the first semiconductor circuit and the second semiconductor circuit can be optically communicated in both directions.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The configurations shown in the drawings and the following description are merely examples, and the scope of the present invention is not limited to those shown in the drawings and the following description.

Configuration FIG. 1 and FIG. 2 of the opto-electric hybrid board and the semiconductor device or the like schematic plan view of the opto-electric hybrid board according to an embodiment of the present invention. FIG. 3 is a schematic plan view of a semiconductor device according to an embodiment of the present invention.

In the opto-electric hybrid board 11 of this embodiment, the first semiconductor circuit 1 and the first light emitting element 3 are provided on the first semiconductor substrate 6, and the first semiconductor circuit 1 is electrically connected to the first light emitting element 3. The first light emitting element 3 is sandwiched between the first electrode 8, the second electrode 10 having translucency, the first electrode 8, and the second electrode 10. The carrier unit 9 is provided. The carrier unit 9 is translucent and has a light emitter 7 therein. The first light emitting element 3 is a signal obtained by performing arithmetic processing by the first semiconductor circuit 1. Is output as light.
Further, the opto-electric hybrid board 11 of the present embodiment further includes the first light receiving element 5, the second semiconductor circuit 31, the second light emitting element 33, the second light receiving element 35, the fourth light emitting element 43, and the optical connection portion 45. You may have.

The semiconductor device 60 of this embodiment includes the opto-electric hybrid board 11 of this embodiment and a second semiconductor substrate 56, and the second semiconductor substrate 56 is provided with a third semiconductor circuit 51 and a third light receiving element 55. The third semiconductor circuit 51 is a circuit that is electrically connected to the third light receiving element 55 and performs signal calculation processing. The third light receiving element 55 emits light output from the first light emitting element 3 as light. input.
Further, the second semiconductor substrate 56 may further include a third light emitting element 53.
Hereinafter, the opto-electric hybrid board 11 of this embodiment and the semiconductor device 60 of this embodiment will be described.

1. First Semiconductor Substrate The first semiconductor substrate 6 is not particularly limited as long as it is a semiconductor substrate on which the first light emitting element 3 and the first semiconductor circuit 1 can be provided. For example, a silicon substrate, a germanium substrate, or a silicon compound is used. A substrate or a substrate of a germanium compound. The first semiconductor substrate 6 may be an impurity semiconductor substrate to which an n-type impurity or a p-type impurity is added. The first semiconductor substrate 6 further may be those forming a silicon layer and a germanium layer on the SiO ₂ or the like substrate, an insulating layer such as SiO ₂ on such Si substrate, a silicon layer Ya thereon What formed the germanium layer may be used. For example, when the first semiconductor substrate 6 is an SOI (Silicon On Insulator) substrate, the first light emitting element 3 may be formed on a crystalline silicon substrate, or an insulator such as SiO ₂ using a CVD method or the like. Amorphous silicon may be formed on the layer, and the first light emitting element 3 may be formed thereon.
This is because conventional semiconductor circuits such as CMOS circuits are manufactured on a substrate made of a group IV element material.

2. First Semiconductor Circuit The first semiconductor circuit 1 is not particularly limited as long as it is a circuit that is provided on the first semiconductor substrate 6 and is electrically connected to the first light emitting element 3 and performs signal processing. For example, the first semiconductor circuit 1 is a semiconductor circuit composed of a plurality of transistors and the like. For example, it is a semiconductor integrated circuit. When the first light emitting element 3 is incorporated in a semiconductor integrated circuit, the first semiconductor circuit may be a part other than the first light emitting element 3 of the semiconductor integrated circuit.

  FIG. 4 is a schematic cross-sectional view of an opto-electric hybrid board according to an embodiment of the present invention. In this opto-electric hybrid board, an n-type transistor and a p-type transistor that form a CMOS circuit and a first light emitting element are formed on the same semiconductor substrate on a semiconductor substrate 6 to which an n-type impurity is added. More specifically, a p-type transistor 65 is formed on the n-type region included in the first semiconductor substrate 6, and an n-type transistor 66 is formed on the p-type well 24 formed in the first semiconductor substrate 6. . The p-type transistor 65 includes a gate insulating film 25, a gate electrode 21, a p-type source region 16 and a drain region 17. The n-type transistor 66 includes the gate insulating film 25, the gate electrode 21, the source region 16, and the drain region 17.

  These transistors are driven by the inversion carriers induced by the voltage applied to the gate electrode 21 being attracted to the drain voltage. Here, a MOS field effect transistor (MOSFET) in which only inversion carriers move is illustrated as a transistor, but a bipolar transistor in which electrons and holes move may be used.

  The channel concentration of the p-type transistor 65 can be obtained by forming an n-type well in the n-type region of the semiconductor substrate 6 to obtain a desired transistor threshold value. Further, a halo region or an extension region may be formed in the vicinity of the source / drain regions of the p-type and n-type transistors to suppress the short channel effect and reduce the resistance of the source / drain regions.

3. First Light-Emitting Element The first light-emitting element 3 is provided on the first semiconductor substrate 6, and has a light-emitting body 7 sandwiched between the first electrode 8, the second electrode 10, the first electrode 8, and the second electrode 10. It is an element provided with a carrier part 9. The first light emitting element 3 optically outputs a signal that has been subjected to arithmetic processing by the first semiconductor circuit 1. Further, the first light emitting element 3 can emit light by applying a voltage between the first electrode 8 and the second electrode 10.

  In addition, a plurality of first light emitting elements 3 are provided on the first semiconductor substrate 6, and one or more of them are formed by forming a phosphor-containing layer on the second electrode 10, thereby converting the light emission wavelength. It may be an element.

As shown in FIG. 1C, the first light emitting element 3 has a structure in which a carrier portion 9 containing a light emitter 7 is sandwiched between a first electrode 8 and a second electrode 10. Further, as shown in FIG. 4, a light emission window 63 may be opened on the upper part of the first light emitting element, and light emission can be taken out to the outside. For the light emitting window 63, it is desirable to select a material having a high transmittance for the wavelength of light emitted from the light emitter 7. Here, the light emitter 7 is desirably fine particles containing GeO and GeO ₂ .

  Since the first light emitting element 3 can be fabricated on the same substrate as the first semiconductor substrate 6 on which the transistor is fabricated, parasitic capacitance caused when using conventional techniques such as wire bonding and flip chip bonding And increase in parasitic inductance. In addition, since the first light emitting element 3 can be manufactured at the same time as the transistor, there is no fear of being exposed to static electricity or the like caused during wire bonding or flip chip bonding.

In FIG. 4, one n-type transistor 66, one p-type transistor 65, and one first light emitting element 3 are formed. However, a plurality of n-type transistors 66 and p-type transistors 65 are formed to form a CMOS circuit. It is also possible to arrange a plurality of first light emitting elements 3 to form a light emitting array and to electrically connect them. The electrical wiring can be formed most simply by connecting the source electrode 20, the gate electrode 21, the drain electrode 22 and the electrode 62, and an interlayer film is further formed on the source electrode 20 or the like depending on the application. And can be connected by an upper wiring layer. With these configurations, the calculation result of the first semiconductor circuit 1 can be optically output by the first light emitting element 3.
In addition, the fact that a light emitting element can be formed on a silicon substrate is an important point that led to the present invention.

  FIG. 5A and FIG. 5B are schematic plan views of the opto-electric hybrid board of this embodiment. One of the light emitting elements 57 described in FIGS. 5A and 5B is the first light emitting element 3. The other light emitting element 57 may be one in which a layer containing a phosphor is formed on the first light emitting element 3. As a result, it is possible to output light at a wavelength different from that of the first light emitting element 3 in which the phosphor-containing layer is not formed on the upper portion, and the amount of information that can be output can be increased. Still another light emitting element 57 may be a fourth light emitting element. As a result, light can be output at different wavelengths, and the amount of information that can be output can be further increased.

The first light emitting element 3 may be received adjacent to the first semiconductor circuit 1. For example, the first light emitting element 3 can be provided as shown in FIG. Accordingly, the first semiconductor circuit 1 and the first light emitting element 3 can be arranged in the opto-electric hybrid board 11 so that the parasitic capacitance and the parasitic inductance are reduced.
That is, in the prior art, since the IC chip and the light emitting element array constituting the electric arithmetic circuit are separately arranged, the bonding area restriction, the parasitic capacitance, and the parasitic inductance increase. In the opto-electric hybrid board 11 of the present embodiment, a semiconductor circuit including a CMOS circuit and a light emitting element can be manufactured on the same substrate, so that any arbitrary parasitic capacitance and parasitic inductance can be used. It becomes possible to arrange a light emitting element and a light receiving element at a place.

  In addition, the encoding circuit 58 may be provided between the first light emitting element 3 and the first semiconductor circuit. For example, an encoding circuit 58 can be provided as shown in FIG. As a result, the first light emitting element 3 can optically output the signal that the first semiconductor circuit 1 has performed the arithmetic processing. Note that the encoding circuit 58 may be included in the first semiconductor circuit 1.

4). 1st electrode The 1st electrode 8 is an electrode which comprises the 1st light emitting element 3, and if it is an electrode which can apply a voltage to the support body part 9, it will not specifically limit. For example, a metal film such as Al or Cu may be used, and a semiconductor such as a p-type semiconductor or an n-type semiconductor may be used. Moreover, as for the 1st electrode 8, when the semiconductor substrate 6 is the semiconductor substrate 6 to which the n-type impurity was added as illustrated in FIG. 4, the first electrode 8 and the semiconductor substrate 6 may be the same. This is because the step of forming the first electrode 8 can be omitted in this case.

  The first electrode 8 may be made of a semiconductor to which an n-type impurity is added. This is because the first light-emitting element 3 has a result that the n-type semiconductor has a higher emission intensity than the p-type semiconductor.

The first electrode 8 has a p-type semiconductor portion and an n-type semiconductor portion, and has a portion where the p-type semiconductor portion and the n-type semiconductor portion are pn-junction on the surface in contact with the carrier portion 9. May be. With this configuration, the first light emitting element 3 can efficiently emit light at a lower voltage than a light emitting element using FN tunneling. Hereinafter, the first light-emitting element 3 having this configuration will be described with reference to the drawings.
FIG. 6 is a schematic cross-sectional view of an opto-electric hybrid board according to an embodiment of the present invention, and FIG. 7 is a schematic cross-sectional view of a first light emitting element included in the opto-electric hybrid board according to an embodiment of the present invention. . The first electrode 8 illustrated in FIGS. 6 and 7 includes a p-type semiconductor portion 71 and an n-type semiconductor portion 72 (in the case of the opto-electric hybrid substrate illustrated in FIG. 6, the p-type well 24 is a p-type. Semiconductor portion 71, and part of n-type semiconductor substrate 6 is n-type semiconductor portion 72). FIG. 8 is a band diagram in the vicinity of the pn junction included in the first electrode 8 illustrated in FIG.

  As shown in FIG. 7, when a negative voltage is applied to the p-type semiconductor portion 71 included in the first electrode 8 and a GND voltage is applied to the n-type semiconductor portion 72 included in the first electrode 8, a reverse bias is generated, and the potential difference is When it is low, no current flows between the p-type semiconductor portion 71 and the n-type semiconductor portion 72. When a somewhat high negative voltage is applied to the p-type semiconductor portion 71, the energy band near the pn junction included in the first electrode 8 is as shown in FIG. In such a case, since the electric field applied to the pn junction is increased, a tunnel current is generated in which electrons in the valence band of the p-type semiconductor portion 71 flow in the conduction band of the n-type semiconductor portion 72. Electrons flowing from the valence band of the p-type semiconductor unit 71 to the conduction band of the n-type semiconductor unit 72 are generated by an electric field between the p-type semiconductor unit 71 and the n-type semiconductor unit 72 or a positive voltage with the p-type semiconductor unit 71. Accelerated by the electric field between the second electrodes 10 applied to, and collide with the lattice atoms to generate hot electron and hot hole pairs. It is considered that some of the hot electrons are accelerated by the electric field between the p-type semiconductor part 71 and the second electrode 10 or the n-type semiconductor part 72 and the second electrode 10 and supplied to the carrier part 9. It is considered that the hot electrons interact with the light emitter 7 inside the carrier portion 9 to excite the energy level of the light emitter 7 and cause the light emitter 7 to emit light.

  In order to cause the first light emitting element 3 to emit light, an electric field capable of generating a tunnel current is applied between the p-type semiconductor portion 71 and the n-type semiconductor portion 72 and the generated hot electrons are transferred to the carrier portion 9. It is necessary to apply an electric field that can be supplied between the p-type semiconductor portion 71 and the second electrode 10 or between the n-type semiconductor portion 72 and the second electrode 10. The electric field applied between the p-type semiconductor part 71 and the second electrode 10 or between the n-type semiconductor part 72 and the second electrode 10 is larger than the electric field that can supply electrons to the conduction band of the carrier part 9 by FN tunneling. It is a small electric field. As a result, the efficiency of electron injection into the carrier portion 9 using the pn junction is higher than when FN tunneling is used. The ratio of the electron injection efficiency to the carrier portion 9 of the first light emitting element 3 having the pn junction and the electron injection efficiency to the carrier portion 9 of the light emitting element using FN tunneling is about 7: 1 from the experimental results. And calculated. Therefore, the first light-emitting element 3 in which the first electrode 8 has a pn junction can efficiently cause the light-emitting element to emit light at a lower voltage than a light-emitting element using FN tunneling.

In addition, when the same voltage is applied to the first light-emitting element 3 in which the first electrode 8 has a pn junction and the light-emitting element using FN tunneling, the first light-emitting element 3 in which the first electrode 8 has a pn junction has a higher luminance. Becomes larger. Further, in the first light emitting element 3 in which the first electrode 8 has a pn junction, there is no problem that the electric field concentrates on one place of the carrier portion 9 and the entire element is destroyed.
Furthermore, in the electron injection method using FN tunneling, the location where hot electrons are generated and the acceleration location are the carrier 9, and therefore, when the voltage necessary for light emission is applied, the carrier 9 is greatly damaged. On the other hand, according to the electron injection method using the pn junction, the hot electron generation site is the pn junction and the acceleration site is the carrier portion 9 and is separated, so that a high electric field is applied. There is an advantage that damage to the carrier portion 9 is small.

In addition, in a light-emitting element using FN tunneling, strong light emission occurs at a portion where the electric field between the electrodes is the largest, and light emission is uneven at a portion where the electric field between the electrodes is small. Therefore, the film thickness variation of the carrier portion 9 directly affects the unevenness of light emission.
On the other hand, in the first light emitting element 3 having a pn junction, it is considered that the light emitter 7 emits light when hot electrons generated near the pn junction in the first electrode 8 collide with the light emitter 7. The energy of hot electrons generated by this method is determined by the electric field applied between the p-type semiconductor portion 71 and the second electrode 10 or between the n-type semiconductor portion 72 and the second electrode 10, and the film thickness variation of the carrier portion 9. Regardless of, the energy gained by hot electrons is determined. Accordingly, since the influence of the film thickness of the carrier portion 9 is small, it is possible to suppress the uneven light emission.

The pn junctions formed by the p-type semiconductor unit 71 and the n-type semiconductor unit 72 may be formed on the surface of the first electrode 8 in contact with the carrier 9 at regular intervals. Further, the pn junction formed by the p-type semiconductor portion 71 and the n-type semiconductor portion 72 may be formed uniformly on the surface of the first electrode 8 in contact with the carrier portion 9. As a result, the first light emitting element 3 can emit light evenly.
For example, the first electrode 8 may form a comb-type p-type silicon region on an n-type silicon substrate, or may form a p-type silicon region in a cross-beam type on an n-type silicon substrate. Further, the p-type silicon and the n-type silicon may be reversed. With such a configuration, the pn junction can be formed on the surface of the first electrode 8 in contact with the carrier portion 9 at a constant interval or uniformly.

The first electrode 8 has a plurality of convex portions on the surface in contact with the carrier portion 9, and the interval between the upper end of the convex portion and the second electrode 10 is a portion other than the convex portions of the first electrode 8. And may be narrower than the distance between the second electrode 10 and the second electrode 10. With such a configuration, the first light emitting element 3 can emit light evenly. This will be described below with reference to the drawings.
FIG. 9A is a schematic cross-sectional view of a first light-emitting element that is a first light-emitting element included in the opto-electric hybrid board according to the embodiment of the present invention and uses carbon nanotubes or the like as convex portions. FIG. 9B is a schematic cross-sectional view of a first light-emitting element that is a first light-emitting element included in the opto-electric hybrid board according to the embodiment of the present invention and that has a conical convex portion. FIG. 9C is a schematic cross-sectional view of the first light emitting element included in the opto-electric hybrid board according to the embodiment of the present invention when a voltage is applied between the first electrode and the second electrode.

  In the first light-emitting element 3 having a plurality of convex portions 75, the length D1 between the upper end of the convex portion 75 and the second electrode 10 is as shown in FIGS. 9A and 9B. This is shorter than the length D2 between the first electrode 8 and the second electrode 10 where no is formed. When a voltage is applied between the first electrode 8 and the second electrode 10 of the first light emitting element 3, the electric field applied to the carrier portion 9 between the upper end of the convex portion 75 and the second electrode 10 is The electric field applied to the carrier portion 9 between the first electrode 8 and the second electrode 10 in the portion where the convex portion 75 is not formed becomes larger. Further, due to the electric field concentration effect on the tip of the convex portion 75, the electrons at the upper end of the convex portion 75 are more easily supplied to the carrier 9 than the electrons of the first electrode 8 at the upper end of the portion where the convex portion 75 is not formed. . As a result, electrons selectively flow between the upper end of the convex portion 75 and the second electrode 10.

  Electrons supplied from the upper end of the convex portion 75 and flowing through the carrier portion 9 are accelerated by the electric field applied between the first electrode 8 and the second electrode 10. The first light emitting element 3 emits light by the accelerated electrons, but the mechanism is not clear. For example, it can be considered as follows. It is considered that the accelerated electrons interact with the light emitter 7 in the carrier portion 9 to excite the electrons of the light emitter 7 so that the light emitter 7 emits light. Alternatively, it is considered that the energy of the accelerated electrons is once converted into other energy such as electromagnetic waves, and then energy is given to the light emitter 7 so that the light emitter 7 emits light. Thus, it is considered that the electrons of the light emitter 7 are excited by directly or indirectly applying energy and the light emitter 7 emits light.

  Furthermore, in the 1st light emitting element 3 in which the 1st electrode 8 has the some convex part 75, since the convex part 75 can be uniformly distributed on the surface of the 1st electrode 8, it is uniform like FIG.9 (c). The light emitting body 7 included in the light emitting region 76 between the convex portions 75 distributed in the second electrode 10 can emit light. As a result, unevenness in light emission does not occur in the first light emitting element 3 in which the first electrode 8 has a plurality of convex portions 75. In this description, it has been described that electrons are supplied from the first electrode 8, but the same effect also occurs when electrons are supplied from the second electrode 10.

Further, by making the upper portion of the convex portion 75 have a pointed shape, electrons at the upper end of the convex portion 75 are more easily supplied to the carrier portion 9. As a result, the light emitter 7 between the upper end of the convex portion 75 and the second electrode 10 can easily emit light. In addition, the light emitting region 76 that emits light can be made more uniform by making the upper portion of the convex portion 75 have a pointed shape.
Further, the convex portion 75 may be uniformly formed on the surface of the first electrode 8 in contact with the carrier portion 9. Thereby, the first light emitting element can emit light evenly.

Next, the formation method of the convex part 75 which the 1st electrode 8 can have is demonstrated concretely.
The 1st electrode 8 which has the convex part 75 can be formed, for example using a conductive silicon substrate. Here, as an example, a forming method using etching, a forming method using laser annealing, and a method of forming carbon nanotubes will be described.

First, the formation method of the convex part 75 using an etching is demonstrated.
A dot-like etching mask is formed on the surface of the first electrode 8, and the surface of the first electrode 8 is etched. In the etching, it is removed from the first electrode 8 on which the mask is not formed, and is gradually removed from the outside of the first electrode 8 under the dot-like etching mask. When the etching is continued, the conical first electrode 8 having the first electrode 8 directly below the center of the dot-shaped etching mask as a vertex can be left without being etched. Then, the 1st electrode 8 which has the cone-shaped convex part 75 can be formed by removing a mask.

Next, a method for forming the convex portion 75 using laser annealing will be described.
For example, a silicon substrate is irradiated with a coherent linearly polarized laser beam while being moved in the horizontal direction, and this irradiation is sequentially performed in the vertical direction of the silicon substrate for annealing treatment. In this annealing process, a temperature distribution corresponding to the periodic light intensity distribution is generated in the silicon substrate. Therefore, a stripe shape having periodic modulation is formed on the surface of the silicon substrate. Further, this silicon substrate can be rotated by 90 degrees around the vertical axis of the irradiated surface, irradiated with a laser beam again, and similar annealing treatment can be performed. As a result, the first electrode 8 having the island-shaped convex portions 75 at the intersections of the stripes intersecting at 90 degrees can be formed. For example, when the above silicon substrate is annealed using a laser having a wavelength of 532 nm, the first electrode 8 having convex portions with an interval of about 500 to 550 nm and a height of 30 to 50 nm can be formed. .

Next, a method for forming the convex portion 75 using carbon nanotubes will be described.
A material (for example, iron group metal such as iron, nickel, cobalt, platinum, rhodium, etc.) having a catalytic action in the growth of carbon nanotubes is formed on the surface of the first electrode 8 by plating, and then methane, ethane, propane, Carbon nanotubes can be formed on the surface of the first electrode 8 by flowing a hydrocarbon-based gas such as ethylene or propylene and using the thermal CVD method or the plasma CVD method.

5. Carrier part The carrier part 9 constitutes the first light emitting element 3, is sandwiched between the first electrode 8 and the second electrode 10, has translucency, and has a light emitter 7 inside, so that it is particularly limited. Not. For example, the carrier part 9 is an insulator. For example, the carrier 9 is made of silicon oxide, silicon nitride, or silicon oxynitride. These are silicon-based insulators, and silicon is more easily bonded to oxygen than germanium. Therefore, when the light emitter is a fine particle containing GeO and GeO ₂ , germanium atoms can be prevented from being unnecessarily bonded to oxygen. it can. In addition, since silicon oxide, silicon nitride, or silicon oxynitride is relatively difficult to transmit oxygen, germanium atoms are not oxidized by permeation of outside air, so that light emission is stable and deterioration is small. Silicon oxide, silicon nitride, or silicon oxynitride is excellent in mass productivity because it can be formed by a normal silicon semiconductor process.

The thickness of the carrier 9 is, for example, 10 nm or more and 100 nm or less (for example, a range between any two of 10, 20, 30, 40, 50, 60, 70, 80, 90, and 100 nm).
Note that translucency in the present invention means that light emitted from the light-emitting element can be transmitted. As for the light transmittance of the carrier part 9, it is preferable that the transmittance | permeability of the light with a wavelength of 300-500 nm is 80% or more, for example. When the light emitter 7 is a fine particle containing GeO and GeO ₂ , the peak wavelength of the light emitted from the light emitter 7 is around 390 nm. Therefore, if the light transmittance at a wavelength of 300 to 500 nm is high, the light extraction efficiency is correspondingly increased. Because it becomes higher.

6). Light Emitter The light emitter 7 is not particularly limited as long as it is formed inside the carrier portion 9 and emits light when a voltage is applied between the first electrode 8 and the second electrode 10. Further, a plurality of the light emitters 7 may be formed on the carrier portion 9. For example, fine particles, metal atoms, metal ions, and fine particles of, for example, germanium, silicon, or tin. Further, the light emitter 7 can be a fine particle containing, for example, GeO and GeO ₂ . In this case, the light emitter 7 may contain germanium (metal). The number density of the light emitters 7 is not particularly limited, and is, for example, 1 × 10 ¹⁶ pieces / cm ³ to 1 × 10 ²¹ pieces / cm ³ .

  When the light emitter 7 is a fine particle, the light emitter 7 preferably has a maximum particle diameter of 1 nm or more and 20 nm or less. This is because the luminous efficiency is particularly high in this case. In the present invention, the “maximum particle size” is 100 nm of an arbitrary cross section of the carrier portion 9 (a cross section as shown in FIG. 1C or a cross section perpendicular to the paper surface). It means the particle size of the largest particle among the fine particles that can be observed when the corner range is observed by TEM. Further, in the present invention, “particle size” means the length of the longest line segment that can be projected on a TEM photograph and included in a planar image of a fine particle when viewed with a cross-sectional TEM photograph. The maximum particle size of the fine particles is, for example, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, or 20 nm. The maximum particle diameter of the fine particles may be within a range between any two numerical values exemplified here, or may be equal to or smaller than any one numerical value.

When light emitter 7 is a particulate containing GeO and GeO _2, the ratio of GeO to the entire germanium oxide (GeO ₂ + GeO), in spectrum around 3d peak of Ge XPS spectra, the area of the peak due to GeO ₂ S _GeO2 When obtains the area S _GeO the peak due to GeO, it can be determined by calculating the _{S GeO / (S GeO2 + S} GeO). As an X-ray source for XPS measurement, for example, monochromatic Al and Kα rays (1486.6 eV) can be used. The peaks due to GeO ₂ and the peaks due to GeO have overlapping _bases , but Gaussian fitting is performed to separate the peaks due to GeO ₂ and the peaks due to GeO into waveforms S _{GeO 2} and S _GeO . Can be sought. The peak energies of GeO ₂ and GeO are about 33.5 and 32 eV, respectively.

When the luminous body 7 is a fine particle containing GeO and GeO ₂ , GeO can be contained at 10% or more when the total of GeO and GeO ₂ contained in the luminous body 7 is 100%. If the proportion of GeO is too small, there is a possibility that no light is emitted or the light emission intensity is too small. Specifically, the proportion of GeO is, for example, 10, 20, 30, 40, 50, 60, 70, 80, 90, 95, 99, 100%. The ratio of GeO may be within a range between any two of the numerical values exemplified here.

Incidentally, in the spectrum around 2p peak of Ge XPS spectra, determined the area S _Ge of peaks due to germanium (Ge), the area S _Ge oxide of peak caused by germanium oxide _{(GeO + GeO 2), S} GeO / ( The oxidation rate of Ge can be obtained by calculating (S _Ge + S oxide _Ge ). Although the average value of this oxidation rate is not specifically limited, For example, 1, 5, 10, 15, 20, 25, 30, 34.9, 35, 40, 45, 50, 55, 60, 60.1, 65 , 70, 70.1, 75, 80, 85, 90, 95, 99, 100%. The average value of the oxidation rate may be within a range between any two of the numerical values exemplified here.

  In the first light-emitting element 3 included in the opto-electric hybrid board 11 of the present embodiment, the peak of electroluminescence (EL) wavelength when a voltage is applied between the first electrode 8 and the second electrode 10 is 340 to 400. It is within the range of 440 nm (more strictly speaking, 350 to 430 nm, 360 to 420 nm, 370 to 410 nm, 380 to 400 nm, or 385 to 395 nm). Or the peak of the wavelength of cathodoluminescence (CL) when irradiating the support 9 with an electron beam at 5 keV is 340 to 440 nm (more strictly, 350 to 430 nm, 360 to 420 nm, 370 to 410 nm, 380 ˜400 nm or 385 to 395 nm). The EL wavelength may be slightly different from the CL wavelength, but is approximately the same as the CL wavelength.

7). 2nd electrode The 2nd electrode 10 is an electrode which comprises the 1st light emitting element 3, and if it has translucency, it will not specifically limit. For example, the second electrode 10 can be an electrode having a light transmittance of 60% or more and 99.99% or less with a wavelength of 300 nm or more and 500 nm or less. The translucency may be possessed by the material constituting the second electrode 10 itself, or may be imparted by forming a gap or a hole in the second electrode 10. For example, the second electrode 10 is a metal oxide thin film such as ITO, a metal thin film such as Al, Ti, or Ta, or a semiconductor thin film such as Si, SiC, or GaN.

8). First Light Receiving Element The first light receiving element 5 may be provided on the first semiconductor substrate 6. The first light receiving element 5 is electrically connected to the first semiconductor circuit 1 and can receive light output from the second light emitting element 33 or the third light emitting element 53. Further, the first light receiving element 5 can receive light output from the second light emitting element 33 or the third light emitting element 53 through the optical connection portion 45.
By providing the first light receiving element 5, the first semiconductor circuit 1 can perform bidirectional high-speed optical communication with the second semiconductor circuit 31, the third semiconductor circuit 51, and the like.

  The first light receiving element 5 can be provided adjacent to the first light emitting element 3. Thus, bidirectional high-speed optical communication can be performed using one optical connection unit 45. A decoder circuit may be provided between the first light receiving element 5 and the first semiconductor circuit 1. As a result, the encoded signal received by the first light receiving element 5 can be decoded and transmitted to the first semiconductor circuit 1.

  FIG. 10 is a schematic cross-sectional view of an opto-electric hybrid board according to an embodiment of the present invention, in which a first semiconductor circuit 1, a first light emitting element 3, and a first light receiving element 5 are provided. As shown in FIG. 10, in addition to the p-type transistor 65, the n-type transistor 66 and the first light emitting element 3 constituting the CMOS circuit which is the first semiconductor circuit 1, the first light receiving element 5 is fabricated on the first semiconductor substrate 6. can do.

For example, as shown in FIGS. 1B and 10, the first light receiving element 5 has a region where the n-type region 12 and the p-type region 13 are pn-junctioned, and has a light-receiving window 68 on the upper portion thereof. It has a structure. When light incident from the light receiving window 68 through the optical connection portion 45 enters the pn junction, electrons and holes are generated in the silicon substrate, and a voltage is generated. Thereby, an optical signal can be converted into an electric signal.
When the first semiconductor substrate 6 is a p-type semiconductor or an n-type semiconductor, one of the p-type region 13 and the n-type region 12 can be omitted.

9. Fourth Light Emitting Element The fourth light emitting element 43 may be provided on the first semiconductor substrate 6. The fourth light emitting element 43 is electrically connected to the first semiconductor circuit 1, and even if the signal subjected to the arithmetic processing by the first semiconductor circuit 1 is output as light having a wavelength different from that of the first light emitting element 3. Good. As a result, different signals can be transmitted between the first light emitting element 3 and the fourth light emitting element 43, and the amount of information in optical communication can be increased.
The fourth light emitting element 43 may be provided adjacent to the first light emitting element 3 as shown in FIG. As a result, the light output by the first light emitting element 3 and the fourth light emitting element 43 can be transmitted using the same optical connection portion 45.

Further, the fourth light emitting element 43 may be included in the light emitting element 57 shown in FIG. The fourth light emitting element 43 may be plural, and may output light with different wavelengths of light. As a result, the amount of information in optical communication can be increased.
For example, the fourth light emitting element 43 may have a structure similar to that of the first light emitting element 3 but may be formed with a filter including a phosphor on the top, and the types of the first light emitting element 3 and the light emitting body 7 may be selected. It may be changed. Further, the first light emitting element 3 may have a different structure.

10. Second Semiconductor Circuit The second semiconductor circuit 31 may be formed on the first semiconductor substrate 6. In addition, the second semiconductor circuit 31 may be a circuit that is electrically connected to the second light emitting element 33 and the second light receiving element 35 and performs signal calculation processing. For example, the second semiconductor circuit 31 is a semiconductor circuit composed of a plurality of transistors and the like. For example, a CMOS circuit. The second semiconductor circuit 31 can perform optical communication with the first semiconductor circuit 1 by being electrically connected to the second light emitting element 33 and the second light receiving element 35.

11. Second Light Emitting Element The second light emitting element 33 may be formed on the first semiconductor substrate 6. In addition, the second light emitting element 33 may be electrically connected to the second semiconductor circuit 31 and optically output a signal that has been subjected to arithmetic processing by the second semiconductor circuit 31. Further, the light output from the second light emitting element 33 may be input to the first light receiving element 5 through the optical connection portion 45. As a result, the signal processed by the second semiconductor circuit 31 can be transmitted to the first semiconductor circuit.
The second light emitting element 33 may have the same structure as the first light emitting element 3 or the fourth light emitting element 43, or may have a different structure.
Further, the second light emitting element 33 may be provided adjacent to the second semiconductor circuit 31. As a result, parasitic inductance and parasitic capacitance can be reduced.

12 Second Light Receiving Element The second light receiving element 35 may be formed on the first semiconductor substrate 6. Further, the second light receiving element 35 may be electrically connected to the second semiconductor circuit 31, and the light output from the first light emitting element 3 may be optically input via the optical connection unit 45. As a result, the signal that the first semiconductor circuit 1 has performed arithmetic processing can be transmitted to the second semiconductor circuit 31.
The second light receiving element 35 may have the same structure as the first light receiving element 5, or may have a different structure.

13. Second Semiconductor Substrate The second semiconductor substrate 56 may be a semiconductor substrate that constitutes the semiconductor device 60 and can be provided with the third semiconductor circuit 51, the third light emitting element 53, and the third light receiving element 55. For example, the second semiconductor substrate 56 may be the same type as the first semiconductor substrate 6 or the opto-electric hybrid board 11 or may be a different type. The second semiconductor substrate 56 may be installed in the same device as the first semiconductor substrate 6 or may be installed in a different device.
The second semiconductor substrate 56 may be disposed to face the first semiconductor substrate 6, the third light receiving element 55 may be disposed to face the first light emitting element 3, and the third light emitting element 53 is disposed. May be arranged to face the first light receiving element 5.

  FIG. 11 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 11, the first semiconductor substrate 6 and the second semiconductor substrate 56 can be arranged. As a result, the first semiconductor circuit 1 and the third semiconductor circuit 51 can perform bidirectional optical communication. Further, the optical connection portion 45 can be omitted by arranging in this way. The first semiconductor substrate 6 and the second semiconductor substrate 56 can be bonded by using a conventional bonding technique. This makes it possible to manufacture a high-performance substrate that occupies a small area.

14 Third Semiconductor Circuit The third semiconductor circuit 51 may be formed on the second semiconductor substrate 56. In addition, the third semiconductor circuit 51 may be a circuit that is electrically connected to the third light emitting element 53 and the third light receiving element 55 and performs signal calculation processing. For example, the third semiconductor circuit 51 is a semiconductor circuit composed of a plurality of transistors and the like. For example, a CMOS circuit. The third semiconductor circuit 51 can perform optical communication with the first semiconductor circuit 1 by being electrically connected to the third light emitting element 53 and the third light receiving element 55.

15. Third Light Emitting Element The third light emitting element 53 may be formed on the second semiconductor substrate 56. In addition, the third light emitting element 53 may be electrically connected to the third semiconductor circuit 51 and optically output a signal that the third semiconductor circuit 51 has performed arithmetic processing. Further, the light output from the third light emitting element 53 may be input to the first light receiving element 5 through the optical connection portion 45. Thus, the signal processed by the third semiconductor circuit 51 can be transmitted to the first semiconductor circuit 1.
The third light emitting element 53 may have the same structure as the first light emitting element 3 and the fourth light emitting element 43, or may have a different structure.

16. Third Light Receiving Element The third light receiving element 55 may be formed on the second semiconductor substrate 56. Further, the third light receiving element 55 may be electrically connected to the third semiconductor circuit 51, and the light output from the first light emitting element 3 may be optically input through the optical connection unit 45. As a result, the signal that the first semiconductor circuit 1 has performed arithmetic processing can be transmitted to the third semiconductor circuit 51.
The third light receiving element 55 may have the same structure as the first light receiving element 5 or may have a different structure.

17. Optical connection portion The optical connection portion 45 is a portion that optically connects the light emitting element and the light receiving element. For example, an optical fiber or an optical waveguide.
For example, the optical waveguide can be provided on the first semiconductor substrate 6. For example, it can be provided in the upper layer of the interlayer film 64. Further, the optical fiber can be installed on the first semiconductor substrate 6 or the second semiconductor substrate 56.

Described opto-electric hybrid board manufacturing method of an embodiment of a method of manufacturing the present invention of the opto-electric hybrid board.
12 and 13 are explanatory diagrams of a method for manufacturing an opto-electric hybrid board according to an embodiment of the present invention. In this embodiment, since a silicon substrate is used as the first semiconductor substrate 6, the transistors included in the first semiconductor circuit 1 are formed first, and then the first light emitting element 3 is formed. This is because the activation annealing temperature of the source / drain region of the transistor is generally higher than the annealing temperature necessary for forming the light emitter 7 of the first light emitting element 3 including the light emitter 7 which is a fine particle containing GeO and GeO _2. It is. However, when a compound of silicon and germanium or a germanium substrate is used as the first semiconductor substrate 6, the two temperatures may be reversed because a high temperature is not required for the activation annealing of the source / drain regions. In this case, the transistor may be formed after the first light emitting element 3 is formed.

1. Formation of Transistor The transistor is formed in a state where the light emitting element region is covered with silicon oxide or silicon nitride. Since the manufacturing method of the Si MOSFET is well known, it will be briefly described here.
(1) trench 27 formation, (2) p-type well 24 formation, (3) gate insulating film 25 formation, (4) polysilicon film formation, (5) gate etching, (6) sidewall on n-type silicon substrate It is formed in the order of formation, (7) p-type, n-type source / drain implantation, (8) activation annealing, and (9) silicide formation. A cross-sectional view through the processes up to here is shown in FIG.

  Here, in the step (4) polysilicon film formation, the gate metal may be directly deposited by sputtering or the like as the gate metal. As described above, the channel concentration of the p-type transistor 65 can be obtained by forming an n-type well in the n-type region of the first semiconductor substrate 6 to obtain a desired transistor threshold value. Further, a halo region or an extension region may be formed in the vicinity of the source / drain regions of the p-type and n-type transistors to suppress the short channel effect and reduce the resistance of the source / drain regions.

2. Formation of First Light-Emitting Element After the transistor is formed, for example, an interlayer film 64 made of a silicon oxide film is deposited, and only the light-emitting element region is opened by etching. When the film thickness of the carrier portion 9 of the first light-emitting element 3 used in a process described later is sufficiently thick, or when the implantation energy at the time of ion implantation of the light-emitting body 7 is sufficiently low, the transistor and the first light-emitting element 3 The interlayer film 64 may be formed at the same time.
The first light emitting element 3 is formed on the n-type silicon substrate in the order of (1) the carrier 9, (2) the light emitter 7, and (3) the second electrode 10.

2-1. Formation of the carrier part The carrier part 9 is formed on the n-type silicon substrate which is the first electrode 8. For example, silicon oxide or silicon nitride can be deposited and formed by CVD or sputtering.

2-2. Formation of luminous body The luminous body 7 is formed inside the carrier portion 9. The method of forming the light emitter 7 inside the carrier portion 9 is not particularly limited. However, when the light emitter 7 is a fine particle containing GeO and GeO ₂ , germanium is ion-implanted into the carrier portion 9, and then A method of performing heat treatment is conceivable. Ions are aggregated by heat treatment after ion implantation, and a large number of fine particles are formed in the carrier 9 and Ge is oxidized to form GeO and GeO ₂ . The ion implantation of germanium can be performed, for example, under conditions of an implantation energy of 5 to 100 keV and an implantation amount of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ ions / cm ² .

The ratio of GeO to GeO ₂ can be adjusted as appropriate by changing the amount of germanium implanted, the heat treatment time, the heat treatment temperature, the heat treatment atmosphere, and the like. Specifically, the GeO ratio can be increased by adjusting the partial pressure and flow rate of oxygen in the heat treatment atmosphere. For example, when the atomic concentration of germanium in silicon oxide having a film thickness of 100 nm is 10% or less, in the heat treatment at 800 ° C. for 1 hour, an inert gas is supplied while evacuating (400 liters per minute) (50 per minute). In the case of milliliter), germanium partially binds to oxygen, but oxygen is insufficient, so that it is not completely oxidized and GeO can be generated. In an atmosphere of 1 atm in which oxygen of 20% volume is mixed with an inert gas, a large amount of GeO ₂ is formed due to excessive supply of oxygen, and GeO decreases. The atmosphere suitable for increasing the proportion of GeO depends on other parameters such as germanium implantation conditions, heat treatment time, and temperature, but in one example, the atomic concentration of germanium is relatively high and oxygen is added to the inert gas. The ratio of GeO can be increased by supplying the mixed gas while evacuating.

  Further, germanium is preferably ion-implanted so that the germanium concentration in the carrier portion 9 is 0.1 to 10.0 atomic%. This is because when the inert gas is supplied (50 milliliters per minute) while evacuating (400 liters per minute) in a heat treatment at 600 ° C. for 1 hour, the luminous efficiency is relatively high in this range. Specifically, the germanium concentration is, for example, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1.0, 2 0.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0 atomic%. This concentration may be within a range between any two of the numerical values exemplified herein. The germanium concentration can be measured, for example, by a high resolution RBS (Rutherford backscattering) method. In addition, it can be measured by various analysis methods such as SIMS (secondary ion mass spectrometry). The germanium concentration is measured in a range where the germanium concentration is 1/100 or more of the peak value. 400-900 degreeC is preferable and the temperature of heat processing has more preferable 500-800 degreeC. This is because the luminous efficiency is relatively high in this range.

2-3. Formation of the second electrode The second electrode 10 is formed on the carrier portion 9 on which the light emitter 7 is formed. For example, an ITO electrode can be formed by a coating method, sputtering, or the like.
A cross-sectional view through the processes up to here is shown in FIG.

2-4. Formation of wiring After the interlayer film 64 is formed on the entire surface of the substrate, the wiring holes of the gate and source / drain regions of the p-type transistor 65 and n-type transistor 66 and the wiring holes of the light emitting element are formed by etching, and the electrode material is sputtered. It deposits by the method etc. and forms a desired wiring by etching.
Through the wiring process, the opto-electric hybrid board of FIG. 4 can be manufactured.

  The light emitting window 63 for extracting light emitted from the first light emitting element 3 may be formed simultaneously with the etching of the wiring hole or may be formed separately. In addition, it is desirable to deposit a material that easily transmits the wavelength of light emitted from the light emitting element, for example, a silicon oxide film or a silicon nitride film after the opening.

Experiment for confirming characteristics of first light emitting element EL Experiment As a reference experiment for confirming the light emission wavelength characteristic and the light emission cause of the first light emitting element 3 by the following method, an element as shown in FIG. 14 was produced and an EL experiment was performed.
First, a silicon thermal oxide film was formed on the surface by thermally oxidizing the n-type and p-type silicon substrates in an oxygen atmosphere at 1050 ° C. for 100 minutes.
Next, Ge ions in the silicon thermal oxide film are 1.4 × 10 ¹⁶ ions / cm ² at 50 keV, 3.2 × 10 ¹⁵ ions / cm ² at 20 keV, and 2.2 × 10 ¹⁵ ions / cm ^{2 at} 10 keV. In this order, multiple injections were made in this order.

Next, nitrogen was introduced while pulling with a rotary pump, and heat treatment was performed at 800 ° C. for 1 hour. Ge is oxidized by aggregation and oxidation of Ge implanted during the heat treatment, and at least a part thereof is oxidized to GeO and GeO ₂ . Next, an ITO electrode was formed on the silicon thermal oxide film, an aluminum electrode was formed on the silicon substrate side, and a light emitting element used for EL experiments was obtained. When a voltage of about 30 V was applied between the ITO electrode and the aluminum electrode of these light emitting elements, blue light emission was confirmed in the light emitting element using the n-type silicon substrate, but the light emitting element using the p-type silicon substrate. In luminescence was not confirmed.

  Further, FIG. 15 shows an emission spectrum of the blue light emission. Referring to FIG. 15, it was found that the confirmed blue emission was light having a wavelength of 340 nm to 550 nm, and electroluminescence emission having a peak between 340 nm and 440 nm.

2. Relationship between GeO and GeO ₂ and light emission It was confirmed that GeO and GeO ₂ were involved in light emission of the light emitting device by the method described below.
First, two hypotheses were considered for the light emission mechanism. The first hypothesis is that the Ge nanoparticles emit light due to the quantum size effect. This light emission mechanism is the same as the light emission mechanism of normal nanoparticles, and the emission wavelength depends on the particle size. The second hypothesis is that GeO and GeO ₂ are involved in light emission. Since the energy level difference between the excited state and the ground state of GeO is 2.9 to 3.2 eV (387 to 427 nm), according to the second hypothesis, the emission wavelength is about 387 to 427 nm. It is thought that the wavelength does not depend on the particle size.

  In order to verify which of these hypotheses is correct, a light emitting device was manufactured under various temperature conditions and injection conditions different from each other, and the EL wavelength when a voltage was applied to the device by the above method was measured. For the measurement of the EL wavelength, “Spectrofluorophotometer RF-5300PC manufactured by Shimadzu Corporation” was used. The manufacturing method of the light emitting element is as described in “1. EL experiment” except that the heat treatment temperature and the Ge implantation amount are appropriately changed.

  The obtained results are shown in FIGS. The temperature in FIG. 16 shows the heat treatment temperature (time is 1 hour). “Atom%” in FIG. 17 indicates the Ge concentration in the silicon oxide film after Ge implantation. The Ge concentration in FIG. 16 is 5.0 atomic%, and the heat treatment temperature in FIG. 17 is 700 ° C. (time is 1 hour).

  Referring to FIGS. 16 and 17, it can be seen that the peak wavelength of EL is constant at about 390 nm even if the heat treatment temperature and Ge concentration are changed. When the heat treatment temperature or Ge concentration changes, the size of the formed nanoparticles also changes, so that the EL peak wavelength should be shifted if the light emission mechanism follows the first hypothesis. Therefore, the EL wavelength confirmed in FIGS. 16 and 17 cannot be explained by the first hypothesis. On the other hand, the wavelength of 390 nm is within the range of the emission wavelength (387 to 427 nm) predicted by the second hypothesis.

From the above, it can be seen that the EL wavelength from the light emitting element cannot be explained by the first hypothesis but can be explained by the second hypothesis. Therefore, it was confirmed that GeO and GeO ₂ were involved in light emission of the light emitting element.
By the way, referring to FIG. 16, it is understood that the heat treatment temperature is preferably 600 to 700 ° C. Referring to FIG. 17, it can be seen that the Ge concentration is preferably 3.0 atomic% or more, and more preferably 3.0 to 5.0 atomic%.

3. Ge, GeO, to produce a light-emitting device according to the method described in the depth direction distribution of the ratio of GeO ₂ "1.EL experiment", Ge in the silicon oxide film, GeO, the depth direction distribution of the ratio of GeO ₂ Examined. The light-emitting element manufactured here has a Ge concentration of 5.0 atomic% and a heat treatment temperature of 800 ° C. (time is 1 hour).
Since XPS can usually analyze the depth of several nm from the sample surface, by alternately performing etching with an argon ion beam and XPS measurement, the depth of Ge, GeO, GeO ₂ in the region up to a depth of 50 nm can be obtained. The change in the direction was examined. The energy of the argon ion beam was 4 keV, the beam current was 15 mA, and irradiation was performed for 300 seconds per time. FIG. 18A shows the XPS measurement results at that time in which the graphs are translated and arranged in the vertical direction for easy understanding. Also shows the state of the Ge atoms contained in each depth, the Ge (metal Ge), GeO, a graph showing a ratio of GeO ₂ FIG 18 (b).

According to this, in the region of a depth of 10 to 50 nm where the Ge implantation concentration is relatively high by the implantation method described in “1. EL experiment”, the proportion of unoxidized Ge is 30 to 70%. GeO ₂ is between 0-20% and approximately 10%. GeO in which Ge is not completely oxidized but partially oxidized is between 10% and 50%.
Ge at each depth, GeO, ratio of GeO _2, in XPS spectrum around 3d peak of Ge spectra, the area S _Ge of peaks due to Ge, the area S _GeO the peak due to GeO, GeO obtains the peak area S _GeO2 caused by _2, was determined by calculating at each depth _{(S Ge, S GeO, S} GeO2) / (S Ge + S GeO + S GeO2).

Further, the graph of FIG. 19 shows the ratio of GeO and GeO _{2 to} the entire germanium oxide (GeO ₂ + GeO) at each depth.
According to this, the proportion of germanium oxide that is completely oxidized to GeO ₂ is approximately the same except for the vicinity of the surface where germanium is easily oxidized due to the low concentration of germanium and the strong influence of the atmosphere. Between 20 and 60%, Ge is not completely oxidized but partially oxidized GeO is between approximately 40 and 80%. In the region of 10 to 40 nm in which the Ge implantation concentration is relatively high by the implantation method described in “1. EL experiment”, the proportion of germanium oxide that is completely oxidized to GeO ₂ is approximately 50%. Below, it is approximately 20-30%. GeO that is partially oxidized but not completely oxidized is approximately 50% or more and 70 to 80%. GeO at each depth, the ratio of GeO _2, in XPS spectrum around 3d peak of Ge spectra, determined the area S _GeO the peak due to GeO, and a peak area S _GeO2 due to GeO _2, (S _GeO, S _GeO2) was determined by calculating in / (S _GeO + S _GeO2) each depth. The XPS spectrum was measured using monochromatic Al and Kα rays (1486.6 eV) as an X-ray source.

1: 1st semiconductor circuit 3: 1st light emitting element 5: 1st light receiving element 6: 1st semiconductor substrate 7: Light emitter 8: 1st electrode 9: Carrier part 10: 2nd electrode 11: Opto-electric hybrid loading Substrate 12: n-type region 13: p-type region 16: source region 17: drain region 20: source electrode 21: gate electrode 22: drain electrode 24: p-type well 25: gate insulating film 27: trench isolation 31: first 2 semiconductor circuit 33: second light emitting element 35: second light receiving element 43: fourth light emitting element 45: optical connection portion 51: third semiconductor circuit 53: third light emitting element 55: third light receiving element 56: second semiconductor Substrate 57: Light emitting element 58: Coding circuit 60: Semiconductor device 62: Electrode 63: Light emitting window 64: Interlayer film 6 5: P-type transistor 66: N-type transistor 68: Light receiving window 71: P-type semiconductor part 7 2: n-type semiconductor portion 75: convex portion 76: light emitting region 78: silicon oxide 101: semiconductor substrate 102: n-type contact layer 103: n-type DBR layer 104: active layer 105: p-type DBR layer 108: p-type contact Layer 110: P electrode 111: N electrode 115: Insulating layer 118: Light emitting part 120: Light emitting element 122: Solder bump 123: Electrode pattern 125: Submount substrate

Claims (23)

A first semiconductor circuit and a first light emitting element are provided on the first semiconductor substrate;
The first semiconductor circuit is a circuit that is electrically connected to the first light emitting element and performs signal processing.
The first light emitting element includes a first electrode, a second electrode having translucency, and a carrier portion sandwiched between the first electrode and the second electrode,
The carrier part has translucency and has a light emitter inside,
An opto-electric hybrid board, wherein the first light emitting element optically outputs a signal obtained by performing arithmetic processing by the first semiconductor circuit. The substrate according to claim 1, wherein the light emitter is a fine particle containing GeO and GeO ₂ . The substrate according to claim 2, wherein the light emitter includes 10% or more of GeO when the total of GeO and GeO ₂ contained in the light emitter is 100%.   4. The substrate according to claim 2, wherein the first light emitting element exhibits electroluminescence having a light emission wavelength peak in a range of 340 to 440 nm.   The substrate according to claim 1, wherein the light emitter is a fine particle having a maximum particle diameter of 1 nm or more and 20 nm or less.   The substrate according to claim 1, wherein the second electrode has a light transmittance of 60% or more and 99.99% or less with a wavelength of 300 nm or more and 500 nm or less.   The substrate according to claim 1, wherein the first light emitting element is provided adjacent to the first semiconductor circuit.   The substrate according to claim 1, wherein the first semiconductor substrate is a silicon substrate, a germanium substrate, a silicon compound substrate, or a germanium compound substrate.   The substrate according to claim 1, wherein the first electrode is a part of the first semiconductor substrate and is a portion doped with an n-type impurity.   The first electrode has a p-type semiconductor portion and an n-type semiconductor portion, and has a portion where the p-type semiconductor portion and the n-type semiconductor portion are pn-junction with a surface in contact with the carrier portion. The substrate according to any one of 8. The substrate according to claim 10, wherein at least one of the p-type semiconductor part and the n-type semiconductor part has an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ or more. The first electrode has a plurality of convex portions on the surface in contact with the carrier portion,
The board | substrate as described in any one of Claims 1-9 whose space | interval of the upper end of the said convex part and 2nd electrode is narrower than the space | interval of parts other than the said convex part of a 1st electrode, and a 2nd electrode.   The board | substrate of Claim 12 whose space | interval of a part other than the said convex part of a 1st electrode and a 2nd electrode is 1.1 times or more of the space | interval of the upper end of the said convex part, and a 2nd electrode.   The board | substrate of Claim 12 or 13 whose space | interval of the upper end of the said convex part and 2nd electrode is 5 nm or more and 100 nm or less.   The said convex part is a board | substrate as described in any one of Claims 12-14 which consists of a carbon nanotube, a cone-shaped metal, or a silicon | silicone.   The board | substrate as described in any one of Claims 12-15 with which the said adjacent 2 convex part has a space | interval of 10 nm or more and 3 micrometers or less.   The substrate according to any one of claims 12 to 16, wherein the convex portion has a conical shape in which an inclination becomes looser as the distance from the apex increases. A fourth light emitting element is further provided on the first semiconductor substrate;
The fourth light emitting element is electrically connected to the first semiconductor circuit, and optically outputs a signal processed by the first semiconductor circuit with light having a wavelength different from that of the first light emitting element. The substrate according to any one of the above. A second semiconductor circuit and a second light receiving element are further provided on the first semiconductor substrate;
The second semiconductor circuit is a circuit that is electrically connected to the second light receiving element and performs signal processing.
The substrate according to any one of claims 1 to 18, wherein the second light receiving element optically inputs light output from the first light emitting element via an optical connection unit. A second light emitting element and a first light receiving element are further provided on the first semiconductor substrate;
The second light emitting element is electrically connected to the second semiconductor circuit, and optically outputs a signal that the second semiconductor circuit has performed arithmetic processing on,
The substrate according to claim 19, wherein the first light receiving element is electrically connected to the first semiconductor circuit and receives light output from the second light emitting element through the optical connection portion. An opto-electric hybrid board according to any one of claims 1 to 18 and a second semiconductor substrate,
A third semiconductor circuit and a third light receiving element are provided on the second semiconductor substrate;
The third semiconductor circuit is a circuit that is electrically connected to the third light receiving element and performs signal processing.
The third light receiving element is a semiconductor device that optically inputs light output from the first light emitting element. A first light receiving element is further provided on the first semiconductor substrate;
A third light emitting element is further provided on the second semiconductor substrate;
The third light emitting element is electrically connected to the third semiconductor circuit, and outputs a signal obtained by performing the arithmetic processing by the third semiconductor circuit,
The apparatus according to claim 21, wherein the first light receiving element is electrically connected to the first semiconductor circuit and receives light output from the third light emitting element. The first light emitting element and the third light receiving element are arranged to face each other,
The apparatus according to claim 22, wherein the third light emitting element and the first light receiving element are arranged to face each other.

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