JP2011101308A - Signal processor, signal transmission method, and data restoration method - Google Patents

Abstract

To provide a signal processing device capable of saving power by simple control.
A first signal generation unit that generates a first data signal synchronized with a first clock having a frequency f1 from first data, and a second clock having a frequency f2 = N * f1 from the second data. A second signal generation unit that generates a second data signal that is synchronized and that has a sum of amplitudes of ½ period of the first clock that is 0, and a first data signal that is generated by the first signal generation unit And a second data signal generated by the second signal generator, a signal adder that generates an added signal, a signal transmitter that transmits the added signal generated by the signal adder, a first A control circuit that operates the signal generation unit constantly, operates the second signal generation unit when transmitting the second data, and stops the operation of the second signal generation unit when the second data is not transmitted. A signal processing device is provided .
[Selection] Figure 10

Description

  The present invention relates to a signal processing device, a signal transmission method, and a data restoration method.

  In an information processing apparatus such as a mobile phone or a notebook personal computer (hereinafter referred to as a notebook PC), a movable member is used at a hinge portion that connects a main body portion operated by a user and a display portion on which information is displayed. There are many cases. However, since many signal lines and power lines are wired in the hinge portion, a device for maintaining the reliability of the wiring is required. First, it is conceivable to reduce the number of signal lines passing through the hinge portion. Therefore, data transmission processing is performed between the main body portion and the display portion not by the parallel transmission method but by the serial transmission method. When the serial transmission method is used in this way, the number of signal lines is reduced.

  In the case of a serial transmission method, data is encoded and then transmitted. In this case, for example, an NRZ (Non Return to Zero) code system, a Manchester code system, an AMI (Alternate Mark Inversion) code system, or the like is used as the encoding system. For example, Patent Document 1 below discloses a technique for transmitting data using an AMI code, which is a typical example of a bipolar code. In the same document, a technique is disclosed in which a data clock is expressed by an intermediate value of a signal level and transmitted, and the data clock is reproduced on the receiving side based on the signal level.

Japanese Patent Laid-Open No. 3-109984

  However, in an information processing apparatus such as a notebook PC, even if the serial transmission method using the above-described code is used, the number of signal lines wired to the hinge portion is still large. For example, in the case of a notebook PC, there is a wiring related to an LED backlight for illuminating the LCD in addition to a video signal transmitted to the display portion. When these signal lines are included, about several tens of signal lines are connected to the hinge portion. Will be wired. However, LCD is an abbreviation for Liquid Crystal Display. LED is an abbreviation for Light Emitting Diode.

  For the above reasons, an encoding method (hereinafter referred to as a new method) has been developed that does not include a DC component and that can easily extract a clock component from a received signal. Since the transmission signal generated based on this new system does not contain a DC component, it can be transmitted superimposed on a DC power source. Furthermore, by detecting the polarity inversion period from this transmission signal, it is possible to reproduce the clock without using a PLL on the receiving side. Therefore, a plurality of signal lines can be collected, the number of signal lines can be reduced, and power consumption and circuit scale can be reduced. However, PLL is an abbreviation for Phase Locked Loop.

  As another method for reducing power consumption, for example, a method of intermittently operating a circuit related to data transmission (hereinafter referred to as a transmission circuit) is known. This method is to intermittently operate the transmission circuit at a constant cycle when the amount of data to be transmitted is small. By operating the transmission circuit intermittently, the operation time of the transmission circuit can be kept low. As a result, the amount of power consumed for the operation of the transmission circuit can be reduced. However, the amount of power reduced by the intermittent operation depends on the cycle of the intermittent operation. In other words, the longer the intermittent operation cycle, the more the operation time of the transmission circuit is reduced, so that the power consumption is greatly reduced.

  However, the transmission circuit requires a certain time to start and stop. Therefore, if the period of intermittent operation is made too short, the operation time rate of the circuit cannot be reduced, and the effect of reducing power consumption is reduced. On the other hand, in order to prevent a delay in data transmission, it is necessary to limit the period of intermittent operation within a certain time. For example, in consideration of transmission of data with a short allowable delay time such as control data and sensor data, the cycle of the intermittent operation is limited to a short time. For these reasons, there is a limit to the power consumption that can be reduced by intermittent operation of the transmission circuit.

  Therefore, the present inventor noticed that the amount of data such as control data and sensor data is small, and with a relatively simple control method, while suppressing the influence of the transmission delay caused by the start / stop of the transmission circuit, the power consumption Devised a data transmission method and a transmission circuit operation control method capable of effectively reducing the above. An object of the present invention is to provide a data processing method, a transmission circuit operation control method, a signal processing apparatus capable of realizing the data transmission method and the transmission circuit operation control method, a signal transmission method, and data. It is to provide a restoration method.

  In order to solve the above-described problem, according to an aspect of the present invention, a first signal generation unit that generates a first data signal synchronized with a first clock having a frequency f1 from first data; A second value in which the value obtained by summing the amplitudes for the ½ period of the first clock is 0 is synchronized with the second clock having the frequency f2 = N * f1 (N is a natural number) from the data of 2. A second signal generation unit that generates the data signal, a first data signal generated by the first signal generation unit, and a second data signal generated by the second signal generation unit. A signal adding unit that generates an addition signal, a signal transmission unit that transmits the addition signal generated by the signal addition unit, and the first signal generation unit that is always operated to transmit the second data. Operating the second signal generator, and If it does not transmit the second data and a control circuit for stopping the operation of the second signal generation unit, the signal processing apparatus is provided.

  In addition, the signal processing apparatus includes a signal receiving unit that receives the addition signal transmitted by the signal transmission unit, and an amplitude value of the addition signal received by the signal reception unit for each cycle of the first clock. And a first signal restoration unit that restores the first data signal by subtracting the first data signal restored by the first signal restoration unit from the addition signal received by the signal reception unit A second signal restoring unit for restoring the second data signal; a first data restoring unit for restoring the first data from the first data signal restored by the first signal restoring unit; And a second data restoration unit that restores the second data from the second data signal restored by the signal restoration unit.

  The control circuit operates the first signal restoration unit and the first data restoration unit at all times, and operates the second signal restoration unit and the second data restoration unit when receiving the second data. In the case where the second data is not received, the operations of the second signal restoration unit and the second data restoration unit may be stopped.

  The control circuit inputs control data for controlling operations of the second signal restoration unit and the second data restoration unit to the first signal generation unit as the first data, and the control data is , Transmitted through the first signal generating unit, the signal adding unit, the signal generating unit, the signal receiving unit, the first signal restoring unit, the first data restoring unit, the second signal restoring unit, and the The second signal restoration unit and the second data restoration unit that are input to the second data restoration unit may be configured to start or stop the operation according to the control data.

  The first signal generation unit may be configured to encode the first data into a symbol string in which a DC component is suppressed, and to generate the first data signal based on the symbol string.

  The second signal generation unit includes a clock generation unit that generates the second clock, the second signal restoration unit includes a clock recovery unit that recovers the second clock, and the control circuit includes: The operation of the second signal generation unit and the second signal restoration unit may be configured to control at least the operations of the clock generation unit and the clock recovery unit.

  The signal processing apparatus further includes a display unit that displays image data, and an arithmetic processing unit that outputs the image data. The image data output by the arithmetic processing unit is the second data. As transmitted through the second signal generating unit, the signal adding unit, the signal transmitting unit, the signal receiving unit, the second signal restoring unit, and the second data restoring unit, and input to the display unit. It may be configured.

  In order to solve the above-described problem, according to another aspect of the present invention, a first signal generation step of generating a first data signal synchronized with a first clock having a frequency f1 from first data. From the second data, the value obtained by synchronizing the amplitudes with respect to the second clock having the frequency f2 = N * f1 (N is a natural number) and the ½ period of the first clock is 0. A second signal generation step for generating a second data signal, a first data signal generated in the first signal generation step, a second data signal generated in the second signal generation step, Are added to generate an addition signal, a transmission step for transmitting the addition signal generated in the addition step, and a process of the first signal generation step are always executed to transmit the second data In case A signal transmission method comprising: a control step of executing a process of the second signal generation step and controlling to stop the process of the second signal generation step when the second data is not transmitted. Is done.

  In order to solve the above-described problem, according to another aspect of the present invention, a first data signal generated from first data and synchronized with a first clock having a frequency f1, and second data A second value that is synchronized with a second clock having a frequency f2 = N * f1 (N is a natural number) and whose sum of amplitudes is ½ period of the first clock is 0. A first signal restoration unit that restores the first data signal by averaging the amplitude value of the addition signal obtained by adding the data signal for each period of the first clock; and A second signal restoration unit that subtracts the first data signal restored by the first signal restoration unit to restore the second data signal; and a first data signal restored by the first signal restoration unit. First data for restoring the first data from Comprising a base portion, and a second data restoring unit for restoring the second data from the second data signal restored by the second signal restoration unit, a signal processing apparatus is provided.

  In order to solve the above-described problem, according to another aspect of the present invention, a first data signal generated from first data and synchronized with a first clock having a frequency f1, and second data A second value that is synchronized with a second clock having a frequency f2 = N * f1 (N is a natural number) and whose sum of amplitudes is ½ period of the first clock is 0. A first signal restoring step for restoring the first data signal by averaging the amplitude value of the added signal obtained by adding the data signal for each period of the first clock; A second signal restoration step for restoring the second data signal by subtracting the first data signal restored in the first signal restoration step; and a first data signal restored in the first signal restoration step. Recover the first data from To include a first data recovery step, and a second data restoring step of restoring the second data from the second data signal restored by the second signal restoration step, the data decompression method is provided.

  As described above, according to the present invention, data transmission that can effectively reduce power consumption while suppressing the influence of transmission delay caused by starting and stopping of a transmission circuit by a relatively simple control method. The method and the operation control method of the transmission circuit can be realized.

It is explanatory drawing which shows the structural example of the portable terminal which employ | adopted the serial transmission system. It is explanatory drawing which shows the signal waveform of an AMI code | symbol. It is explanatory drawing which shows the function structural example of the portable terminal 10 which concerns on a new system. It is explanatory drawing which shows an example of the encoding method which concerns on a new system. It is explanatory drawing which shows an example of the frequency spectrum of the multilevel signal obtained using the encoding method which concerns on a new system. It is explanatory drawing which shows an example of the frequency spectrum of the transmission signal comprised by the narrowband signal arrange | positioned at a low region, and the wideband signal arrange | positioned at a high region. It is explanatory drawing which shows the relationship between the carrier wave of a wideband signal, a data clock, data, and a code | symbol. It is explanatory drawing which shows an example of the frequency spectrum of the transmission signal comprised by the narrowband signal arrange | positioned at a low region, and the wideband signal arrange | positioned at a high region. It is explanatory drawing which shows an example of the frequency spectrum of the transmission signal comprised by the narrowband signal arrange | positioned at a low region, and the wideband signal arrange | positioned at a high region. It is explanatory drawing which shows the structural example of the transmission side which can implement | achieve the signal transmission method which concerns on one Embodiment of this invention. It is explanatory drawing which shows the structural example of the transmission side which can implement | achieve the signal transmission method which concerns on the embodiment. It is explanatory drawing which shows the temporal relationship of the high-speed data transmitted with the signal transmission method which concerns on the embodiment, and low-speed data. It is explanatory drawing which shows the structure of the high-speed data based on the embodiment. It is explanatory drawing which shows an example of the binary code applicable to the signal transmission method which concerns on the same embodiment. It is explanatory drawing which shows an example of the ternary code | symbol applicable to the signal transmission method which concerns on the same embodiment. It is explanatory drawing which shows an example of the quinary code | symbol applicable to the signal transmission method which concerns on the same embodiment. It is explanatory drawing which shows the specific structural example of the transmission side which can implement | achieve the signal transmission method which concerns on the embodiment. It is explanatory drawing which shows the specific structural example of the receiving side which can implement | achieve the signal transmission method which concerns on the embodiment. It is explanatory drawing which shows in detail the structure which concerns on the reproduction | regeneration of a clock among the specific structural examples of the receiving side which can implement | achieve the signal transmission method which concerns on the embodiment. It is explanatory drawing which shows in detail the structure which concerns on the decoding of data among the specific structural examples of the receiving side which can implement | achieve the signal transmission method which concerns on the embodiment. It is explanatory drawing which shows the structural example of the production | generation circuit for producing | generating a partial response code | symbol. It is explanatory drawing which shows the signal waveform of the partial response code | cord | chord corresponding to the data 1. FIG. It is explanatory drawing which shows the signal waveform obtained by encoding 3 bit high-speed data into a partial response code. It is explanatory drawing which shows the generation method of the transmission signal which concerns on the same embodiment.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

[About the flow of explanation]
Here, the flow of explanation regarding the embodiment of the present invention described below will be briefly described. First, the device configuration of the mobile terminal 10 adopting the serial transmission method will be described with reference to FIG. Next, the signal waveform of the AMI code and its characteristics will be described with reference to FIG. Next, the functional configuration of the mobile terminal 10 according to the new method will be described with reference to FIG. Next, an encoding method according to the new scheme will be described with reference to FIG.

  Next, problems that occur when transmitting a signal having a frequency spectrum in which a narrowband signal is located in a low band and a wideband signal is located in a high band will be described with reference to FIGS. Next, a signal transmission method according to an embodiment of the present invention and configurations of a transmission side and a reception side capable of realizing this method will be described with reference to FIGS. Next, the relationship between the high speed data and the low speed data according to the present embodiment will be described with reference to FIGS. 12 and 13. Next, a configuration of codes applicable to high-speed data transmission will be described with reference to FIGS. 14A to 14C.

  Next, specific configurations of the transmission side and the reception side that can realize the signal transmission method according to the present embodiment will be described in detail with reference to FIGS. 15 and 16. Next, a clock recovery method used for decoding high-speed data and low-speed data, and a configuration of a clock recovery circuit capable of realizing this method will be described with reference to FIG. Next, a specific configuration of a decoding unit for decoding low-speed data will be described with reference to FIG. Next, a signal waveform of a high-speed data and a signal transmission method when a partial response code is applied will be described with reference to FIGS. 19A to 19C and FIG.

  Finally, the technical idea of the present embodiment will be summarized and the effects obtained from the technical idea will be briefly described.

(Description item)
1: Introduction 1-1: Serial transmission system 1-2: New system (multi-value transmission system) 2: Embodiment 2-1: Overview of signal transmission method / operation control method 2-2: Details of signal transmission method
2-2-1: Transmission side configuration
2-2-2: Configuration on the receiving side 3: Summary

<1: Introduction>
Hereinafter, a technique according to an embodiment of the present invention will be described in detail. Prior to this, a serial transmission scheme to which the technique of the present embodiment can be applied and the above-described new scheme will be described.

[1-1: Serial transmission method]
First, the device configuration of the mobile terminal 10 adopting the serial transmission method will be briefly described with reference to FIG. FIG. 1 is an explanatory diagram illustrating an example of a device configuration of a mobile terminal 10 adopting a serial transmission method.

  In FIG. 1, a mobile phone is schematically drawn as an example of the mobile terminal 10. However, the scope of application of the technology described below is not limited to mobile phones. For example, the present invention can be applied to an information processing apparatus such as a notebook PC and various portable electronic devices. In the following description, a case where image data is transmitted is described as an example, but the type of signal transmitted is not limited to this. For example, signals such as control data and audio data may be transmitted.

  As shown in FIG. 1, the mobile terminal 10 mainly includes an operation unit 12, a hinge unit 14, and a display unit 16. The operation unit 12 includes a baseband processor 22 (BBP), a parallel signal line 24, and a serializer 26. A serial signal line 28 is wired to the hinge portion 14. The display unit 16 mainly includes a deserializer 30, a parallel signal line 32, and a liquid crystal unit 34 (LCD). However, LCD is an abbreviation for Liquid Crystal Display.

  The liquid crystal unit 34 is provided in the display unit 16. The liquid crystal unit 34 is an example of a display unit that displays image data. Although an LCD is shown here as an example, the type of display means provided in the display unit 16 is not limited to this. For example, the display means provided in the display unit 16 may be an OELD (Organic Electro-Luminous Display), a PDP (Plasma Display Panel), or the like.

  Further, the hinge portion 14 is formed by a member (hereinafter referred to as a connection member) that connects the display portion 16 and the operation portion 12. This connecting member has, for example, a movable structure that allows the display unit 16 to rotate 180 degrees in the ZY plane, or enables the display unit 16 to rotate in the XZ plane. . Moreover, this connection member may have a movable structure that can arrange the display unit 16 in a free direction.

  The baseband processor 22 is an example of an arithmetic processing unit that provides communication control of the mobile terminal 10 and an application execution function. The baseband processor 22 outputs control data, image data, and the like in the form of parallel signals. For example, the parallel signal of the image data is transmitted to the display unit 16 and used for screen display in the liquid crystal unit 34. In order to transmit such a parallel signal as it is, a large number of signal lines are required. For example, the number of parallel signal lines used for screen display of a general mobile phone is about 50.

  Therefore, in the case of a general foldable mobile phone adopting a parallel transmission system, about 50 parallel signal lines are wired in the hinge portion. Therefore, the movable range of the hinge portion is often limited to one direction. If the mobile terminal 10 shown in FIG. 1 can be rotated 180 degrees in the ZY plane, twisting or pulling force is applied to about 50 parallel signal wires wired to the hinge portion. If the force is strong, the parallel signal line is disconnected. Therefore, in the case of a general foldable mobile phone that employs a parallel transmission method, the movable range of the hinge portion has been limited.

  However, in order to improve the design and the convenience of the user, there is a demand for a device that expands the movable range of the hinge part while avoiding the risk of disconnection. In response to such a request, a serial transmission type portable terminal 10 as shown in FIG. 1 was devised. When transmitting a signal from the operation unit 12 to the display unit 16, the portable terminal 10 converts the parallel signal into a serial signal and then transmits the signal. Therefore, the number of signal lines wired to the hinge portion 14 of the mobile terminal 10 is significantly smaller than that of a general mobile phone that employs a parallel transmission method. Hereinafter, the configuration of the mobile terminal 10 will be described in more detail.

  The portable terminal 10 transmits data such as image data through a serial signal line 28 wired to the hinge unit 14 based on a serial transmission method. Therefore, the operation unit 12 is provided with a serializer 26. The serializer 26 serializes the parallel signal output from the baseband processor 22. On the other hand, the display unit 16 is provided with a deserializer 30. The deserializer 30 parallelizes the serial signal transmitted through the serial signal line 28.

  The parallel signal output from the baseband processor 22 is input to the serializer 26 via the parallel signal line 24. When the parallel signal is input, the serializer 26 serializes the input parallel signal to generate a serial signal. The serial signal generated by the serializer 26 is input to the deserializer 30 through the serial signal line 28. When a serial signal is input, the deserializer 30 generates a parallel signal by parallelizing the input serial signal. The parallel signal generated by the deserializer 30 is input to the liquid crystal unit 34 through the parallel signal line 32.

  As described above, the serial signal line 28 is used for data signal transmission. However, the serial signal line 28 may be used for transmitting both the data signal and the clock. The number k of serial signal lines 28 is significantly smaller than the number n of parallel signal lines wired to a hinge portion of a general mobile phone (1 ≦ k << n). In addition, the number k of the serial signal lines 28 is reduced to about 1 when a method (for example, the above-described new method) in which a data signal and a clock are superimposed on a power supply line is used.

  As described above, when the serial transmission method is employed, the number of signal lines wired to the hinge portion 14 can be significantly reduced as compared with the case where the parallel transmission method used in a general mobile phone is employed. By reducing the number of signal lines wired to the hinge part 14, the movable range of the hinge part 14 can be increased while maintaining the reliability of the signal line. For example, if the number of signal lines is reduced to about one, the signal lines are less likely to be twisted or pulled due to the deformation of the hinge portion 14, and the risk of the signal lines being disconnected is greatly reduced.

  The apparatus configuration of the mobile terminal 10 has been briefly described above. The device configuration of the mobile terminal 10 adopting the serial transmission method is generally as described above. As described above, the number of signal lines wired to the hinge portion 14 can be reduced by adopting the serial transmission method. However, the number of signal lines depends on the characteristics of the signal flowing through the serial signal line 28 and the transmission method. For example, in the case of a transmission method in which a data signal that does not include a DC component is transmitted by being superimposed on a power supply line, the data line and the power supply line can be combined into about one or two.

  By the way, in many cases, the data signal flowing in the serial signal line 28 is encoded. That is, when transmitting data, the mobile terminal 10 encodes the data and converts it into encoded data, and transmits a data signal generated based on the encoded data through the serial signal line 28. In addition, the mobile terminal 10 detects the amplitude value of the data signal transmitted through the serial signal line 28 using a comparator, and restores the encoded data. Furthermore, the mobile terminal 10 restores the original data by decoding the encoded data.

  The decoding process of the encoded data uses the clock used when generating the encoded data. This clock is usually recovered from the data signal using a PLL. Recently, however, an encoding method (new method) has been devised that can recover a clock from a data signal without using a PLL. When this encoding method is used, it is not necessary to provide a PLL on the data signal receiving side (for example, the display unit 16), and power consumption can be reduced. Further, the circuit scale can be reduced by the amount that the PLL is not provided. In a small electronic device such as the portable terminal 10, power saving is strongly demanded, and it is desired to use a new encoding method.

[1-2: New method (multilevel transmission method)]
Here, a new encoding method will be briefly described with reference to FIGS. In the following, a specific description will be made regarding the new encoding method based on the AMI code, but the type of code applicable to the new encoding method is not limited to the AMI code. For example, partial response codes, Manchester codes, CMI codes, other bipolar codes, biphase codes, and the like are also included in the application target.

(Signal waveform of AMI code)
First, the AMI code will be briefly described. The signal waveform of the AMI code and the characteristics of the AMI code will be briefly described with reference to FIG. FIG. 2 is an explanatory diagram illustrating an example of a signal waveform of the AMI code. The AMI code is obtained by expressing data 0 as a potential 0 and data 1 as a potential A or -A (A is an arbitrary positive number). However, the potential A and the potential -A are alternately repeated. That is, when data 1 appears again after the data 1 is expressed by the potential A, the data 1 is expressed by the potential -A. Since data is expressed by repeating polarity inversion in this way, the AMI code is a code that hardly contains a DC component.

  As a code having the same characteristics as the AMI code, for example, a partial code represented by PR (1, -1), PR (1, 0, -1), PR (1, 0, ..., -1), etc. A response code is mentioned. A transmission code that expresses data using polarity inversion in this way is called a bipolar code. In addition, a dicode code, a biphase code, etc. can also be utilized for the encoding method of the new system mentioned later. However, in the following description, an encoding method based on an AMI code with a duty of 100% will be described.

  FIG. 2 schematically shows the AMI codes in the periods T1 to T14. In the figure, data 1 appears at timings T2, T4, T5, T10, T11, T12, and T14. When the potential is A at the timing T2, the potential is -A at the timing T4. At timing T5, the potential is A. As described above, the amplitude corresponding to the data 1 is alternately inverted between plus and minus. The characteristic in which plus and minus are alternately reversed is referred to as polarity reversal. On the other hand, all the data 0 is expressed by the potential 0.

  With such an expression, the AMI code becomes a code that hardly contains a DC component. However, as seen at timings T6,..., T9, depending on the combination of data, a section where the potential 0 continues appears. Thus, when the potential 0 continues, it becomes difficult to extract a clock component from the signal waveform without using a PLL. That is, it is necessary to provide a PLL on the receiving side. In view of such a problem, a method (a new encoding method) in which a clock is superimposed on an AMI code (or a code having equivalent characteristics) and transmitted is devised.

(Functional configuration of mobile terminal 10)
Hereinafter, the functional configuration of the mobile terminal 10 according to the new method will be described with reference to FIG. FIG. 3 is an explanatory diagram illustrating an example of a functional configuration of the mobile terminal 10 according to the new method. However, FIG. 3 is an explanatory diagram drawn centering on the functional configuration of the serializer 26 and the deserializer 30, and descriptions regarding other components are omitted.

(Serializer 26)
First, the serializer 26 will be described. As illustrated in FIG. 3, the serializer 26 includes a P / S conversion unit 102, an encoder 104, a driver 106, a PLL unit 108, and a timing control unit 110.

  As shown in FIG. 3, the parallel signal (P-DATA) and the parallel signal clock (P-CLK) are input to the serializer 26 from the baseband processor 22. The parallel signal input to the serializer 26 is converted into a serial signal by the P / S converter 102. The serial signal converted by the P / S conversion unit 102 is input to the encoder 104. The encoder 104 generates a transmission frame by adding a header or the like to the serial signal. Further, the encoder 104 encodes the generated transmission frame by a new encoding method described later to generate a transmission signal.

  Here, a method of generating an encoded signal in the encoder 104 will be described with reference to FIG. FIG. 4 is an explanatory diagram showing an example of an encoding method according to the new scheme. FIG. 4 describes an encoding method based on the AMI code. However, the types of codes that can be used in the new encoding method are not limited to this, and other codes having characteristics equivalent to those of the AMI code can be used in the same manner. For example, the new encoding method can be applied to bipolar codes, partial response codes, and the like.

  The code waveform in FIG. 4C is generated by a new encoding method. In this code waveform, data 1 is expressed by a plurality of potentials A1 (-1, -3, 1, 3), and data 0 is expressed by a plurality of potentials A2 (-2, 2) different from the potential A1. It is obtained. This code waveform is characterized in that the polarity is inverted every half cycle of the clock and that the same potential is not continuously obtained. For example, referring to a section where data 0 continues at timings T6,..., T9, the potentials are −2, 2, −2, 2. Therefore, even if the same data value appears continuously, it is possible to detect a clock component without using a PLL by detecting both rising and falling edges of the amplitude.

  Such a code waveform is obtained, for example, by a method of synchronously adding a clock as shown in FIG. 4B to a code waveform of an AMI code as shown in FIG. In order to implement this method, the encoder 104 includes an adder ADD. First, the encoder 104 encodes the input serial signal into an AMI code, and generates a code waveform of the AMI code as shown in FIG. Next, the encoder 104 inputs the generated code waveform of the AMI code to the adder ADD. Further, the encoder 104 generates a clock as shown in FIG. 4B and inputs it to the adder ADD.

  However, the clock has a frequency (Fb / 2) that is half the transmission rate Fb of the AMI code, as shown in FIG. Further, this clock has an amplitude that is N times (N> 1; N = 2 in the example of FIG. 4) as compared with the amplitude of the AMI code. In this way, by adding the AMI code and a clock having an amplitude larger than that of the AMI code, as shown in FIG. 4C, a code waveform in which the amplitude crosses zero every half cycle of the clock. Is obtained. At this time, the code waveform of the AMI code and the clock are synchronously added with the edges aligned. In this way, the encoder 104 generates a new code waveform (transmission signal).

  The code waveform of the new method has a plurality of amplitude levels for one data. For example, the code waveform of the new method illustrated in FIG. 4C can take six values of 3, 2, 1, -1, -2, and -3 as amplitude levels. Among them, 2 and -2 correspond to data 0, and 3, 1, -1, and -3 correspond to data 1. That is, the code of the new method is a multi-level code (six-level code in the example of FIG. 4). The frequency spectrum of the new code waveform has a shape as shown in FIG. As described above, since the code of the new method includes a clock component, a line spectrum also appears in the frequency spectrum at the position of the clock frequency Fb / 2.

  The encoding method by the encoder 104 and the characteristics of the code waveform generated by the encoder 104 have been described above. Here, in order to simplify the explanation, the method of synchronously adding an AMI code and a clock to generate a new code waveform has been described. However, data is converted into a new code waveform based on a predetermined coding rule. There is also a direct encoding method. For example, in the example of FIG. 4, based on a predetermined code rule, the data strings 0, 1, 0, 1, 1, 0,..., 1 to amplitude levels 2, −1, 2, −3, 3, −2, ..., -1 is determined, and a new type code waveform is generated based on the determination result.

  Refer to FIG. 3 again. The serial signal encoded by the encoder 104 as described above is input to the driver 106. The driver 106 transmits the input serial signal to the deserializer 30 by a differential transmission method using LVDS. On the other hand, the parallel signal clock input to the serializer 26 is input to the PLL unit 108.

  The PLL unit 108 generates a serial signal clock from the parallel signal clock, and inputs the serial signal clock to the P / S conversion unit 102 and the timing control unit 110. The timing control unit 110 controls the transmission timing of the serial signal by the encoder 104 based on the input serial signal clock. In this way, a serial signal is transmitted from the serializer 26 to the deserializer 30.

(Deserializer 30)
Next, the deserializer 30 will be described. As illustrated in FIG. 3, the deserializer 30 mainly includes a receiver 112, a decoder 114, an S / P converter 116, a timing controller 120, and a clock detector 118. Note that the clock detection unit 118 does not have a PLL.

  Now, a serial signal is transmitted from the serializer 26 to the deserializer 30 by a differential transmission method based on LVDS. This serial signal is received by the receiver 112. The serial signal received by the receiver 112 is input to the decoder 114 and the clock detection unit 118. The decoder 114 refers to the header of the input serial signal, detects the head portion of the data, and decodes the serial signal encoded by the encoder 104.

  Here, the decoding method by the decoder 114 will be described with reference to FIG. 4 again. As described above, the serial signal is encoded by the encoder 104 into a code waveform having six amplitude levels. Therefore, the decoder 114 performs threshold determination based on a plurality of threshold levels, and compares the amplitude levels. Then, the decoder 114 decodes the serial signal encoded by the encoder 104 by converting each amplitude level obtained by the threshold determination into original data.

  For example, by using the four threshold values (L1, L2, L3, L4) shown in FIG. 4C, the amplitude level A1 (-1, -3, 1, 3) corresponding to the data 1 and the data 0 are set. The corresponding amplitude level A2 (−2, 2) is determined. First, the decoder 114 compares the amplitude level of the input signal with the above four threshold levels to determine whether the amplitude level is A1 or A2. Next, the decoder 114 outputs the data 1 at the timing when the amplitude level is determined to be A1, and outputs the data 0 at the timing when the amplitude level is determined to be A2, so that the serial signal encoded by the encoder 104 is output. Decrypt.

  Refer to FIG. 3 again. The serial signal restored by the decoder 114 in this way is input to the S / P converter 116. The S / P converter 116 converts the input serial signal into a parallel signal (P-DATA). The parallel signal converted by the S / P conversion unit 116 is input to the liquid crystal unit 34. When the parallel signal is a video signal, the liquid crystal unit 34 displays a video based on the video signal.

  Now, a clock is required to execute the above decoding process. This clock is supplied by the clock detection unit 118. The clock detection unit 118 detects a clock component from the signal received by the receiver 112. Then, the clock detection unit 118 regenerates the original clock using the detected clock component. As described above, the code waveform of the new method is obtained by synchronously adding a clock to the AMI code. The polarity of this code waveform is inverted every half cycle of the clock. Therefore, the clock component is obtained by detecting the timing at which the amplitude level of the received signal crosses zero. That is, the clock detection unit 118 can reproduce the clock without using the PLL. Then, the power consumption and circuit scale of the deserializer 30 can be reduced by the amount that does not require the PLL.

  The clock detection unit 118 regenerates the original clock using the clock component detected from the received signal. The clock regenerated by the clock detection unit 118 is input to the decoder 114 and the timing control unit 120. The clock input to the decoder 114 is used for the decoding process in the decoder 114. In addition, the timing control unit 120 controls reception timing based on the clock input from the clock detection unit 118. The clock input to the timing control unit 120 is converted into a parallel signal clock (P-CLK) and output to the liquid crystal unit 34.

  Note that threshold determination processing performed by the decoder 114 and the clock detection unit 118 is executed using a comparator corresponding to each threshold. For example, the clock detection unit 118 extracts the clock component based on the output result of the comparator having the threshold value L0. The decoder 114 determines four threshold levels L1 (2.5), L2 (1.5), L3 (in order to determine six amplitude levels 3, 2, 1, -1, -2, -3. -1.5), a comparator having L4 (-2.5) is used. Then, the amplitude level is determined based on the output results of these comparators. Further, the original NRZ data is restored based on the determination result.

  In this way, by using a new code that does not include a DC component and can detect a clock component from the polarity inversion period, it is not necessary to use a PLL for clock detection executed by the deserializer 30. The power consumption of the mobile terminal 10 is greatly reduced. In the above example, the differential transmission method based on LVDS is exemplified, but it is also possible to superimpose and transmit the new method of the code waveform on the power signal supplied from the DC power supply. With such a configuration, the movable range of the hinge portion 14 can be further expanded.

(Consideration on power saving)
In recent years, in order to promote power saving of the mobile terminal 10, various methods including the encoding method according to the above-described new method have been studied. For example, when high-speed data transmission is required, a circuit related to data transmission (transmission circuit) is always operated, and when only low-speed data transmission is required, the operation of the transmission circuit is switched to intermittent operation. An operation control method has been proposed. For example, when a moving image is being reproduced, the image displayed on the liquid crystal unit 34 is frequently updated, and thus a large amount of data is continuously sent to the display unit 16. On the other hand, only a small amount of data is sent to the display unit 16 when updating clock information, displaying small display objects, or transmitting control information. Therefore, when data transmission is not performed or when the transmission speed is low, the operation of the transmission circuit is stopped or switched to the intermittent operation. During this time, the operation time rate of the transmission circuit is reduced, so that power consumption is suppressed.

  However, when stopping or intermittently operating the transmission circuit, it takes a certain amount of time to start and stop the transmission circuit. Therefore, if the intermittent cycle is too short, the operating time rate cannot be reduced and power consumption can be reduced. I can't. On the other hand, if the period of the intermittent operation is lengthened in order to reduce power consumption, a transmission delay occurs for that time. For example, in the case of control data or the like for which quick transmission is required, control processing may be hindered due to transmission delay. Therefore, the present inventor always operates a transmission circuit used for transmission of data (hereinafter referred to as low speed data) that requires a quick transmission although the amount of data is small, so that the data (a large amount of data and a high transmission speed are required) Hereinafter, a method of intermittently operating a transmission circuit used for high-speed data transmission was examined. In addition, a method of superimposing and transmitting a low-speed data signal and a high-speed data signal was studied.

  The low-speed data signal is obtained by modulating a low-frequency carrier wave according to the low-speed data value (or the encoded data value). On the other hand, a high-speed data signal is obtained by modulating a high-frequency carrier wave according to the value of high-speed data (or the value of encoded data). As shown in FIG. 6, the frequency spectrum obtained by superimposing both signals is such that a wideband signal corresponding to a high-speed data signal is arranged in the high band and a narrowband signal corresponding to the low-speed data signal is arranged in the low band. It becomes a shape. If the center frequencies of both signals are sufficiently separated, each signal can be easily separated from a superimposed signal obtained by superimposing both signals using a bandpass filter or the like. However, if the spread of the frequency spectrum of each signal is large, the interference between signals increases. As a result, it becomes difficult to correctly separate the signals, and the transmission error rate increases. In order to solve such a problem, the wideband signal may be sufficiently attenuated in the low band.

  The relationship among the carrier wave, data clock, data, and code (modulated wave) in the wideband signal illustrated in FIG. 6 is illustrated in FIG. The carrier wave has the center frequency of the broadband signal. The data clock indicates a data change point at the falling edge. Then, the product of the data and the carrier wave is a wideband signal (code (modulated wave)). As shown in FIG. 7, when the timings of the carrier wave and the data clock are shifted, an odd timing is generated in the wideband signal.

  When such an odd timing occurs, it becomes difficult to reproduce a clock having a correct timing when the clock is reproduced based on the waveform of the wideband signal. In order to solve this problem, as shown in FIG. 9, the value obtained by dividing the frequency of the carrier by the bandwidth of the broadband signal (the width of the main wave) may be an integer. However, as shown in FIG. 9, an unused band is generated between the wideband signal and the narrowband signal. As described above, when an unused band is generated, the transmission speed of the broadband signal is reduced.

  Further, as a method for sufficiently attenuating a wide band signal in a low band, as shown in FIG. 8, a method of cutting a low band component of a wide band signal with a filter can be considered. For example, a method is conceivable in which a low-band component of a baseband signal such as an AMI code that does not have a DC component is cut by a filter, and a narrowband signal is arranged at the cut position. However, when this method is applied, distortion occurs in the wideband signal due to the low-frequency component being cut by the filter. As a result, the transmission quality of the broadband signal is degraded.

<2: Embodiment>
In view of the above problems, the present inventor has proposed an encoding method in which a low-speed data signal (low-band narrowband signal) and a high-speed data signal (high-band wideband signal) can coexist without interference. And a transmission method was devised. When this method is applied, it is possible to switch operation / stop of the transmission circuit used for high-speed data with simple control. Therefore, power consumption can be reduced with simple control. Hereinafter, a signal transmission method and a transmission circuit operation control method according to an embodiment of the present invention will be described. Note that when expressed as a transmission circuit, the expression may be described with both the transmission circuit and the reception circuit in mind.

[2-1: Overview of signal transmission method and operation control method]
First, an outline of a signal transmission method / operation control method according to the present embodiment will be described with reference to FIGS. 10 to 14C. FIG. 10 is an explanatory diagram illustrating a configuration example on the transmission side capable of realizing the signal transmission method / operation control method according to the present embodiment. FIG. 11 is an explanatory diagram showing a configuration example on the receiving side capable of realizing the signal transmission method / operation control method according to the present embodiment. FIG. 12 is an explanatory diagram showing a temporal relationship between high-speed data and low-speed data during transmission when the signal transmission method according to the present embodiment is applied. FIGS. 13 and 14A to 14C are explanatory diagrams illustrating an example of a configuration and encoding method of high-speed data according to the present embodiment.

(Sender configuration)
First, the configuration on the transmission side will be described. As shown in FIG. 10, the configuration on the transmission side includes a low-speed data transmission unit 202, a high-speed data transmission unit 204, a control circuit 206, and an adder 208. The low-speed data transmission unit 202 is an example of a transmission circuit used for transmission of low-speed data. The high-speed data transmission unit 204 is an example of a transmission circuit used for high-speed data transmission. The control circuit 206 is a circuit that controls the operation of the low-speed data transmission unit 202 and the operation of the high-speed data transmission unit 204. The adder 208 is a circuit that adds the low-speed data signal output from the low-speed data transmission unit 202 and the high-speed data signal output from the high-speed data transmission unit 204.

  The low-speed transmission data having a small data amount is input to the low-speed data transmission unit 202. In addition, high-speed transmission data having a large amount of data is input to the high-speed data transmission unit 204. When the low-speed transmission data is input, the low-speed data transmission unit 202 encodes the low-speed transmission data to generate low-speed transmission encoded data, and outputs the low-speed data signal obtained based on the low-speed transmission encoded data. Output. When the high-speed transmission data is input, the high-speed data transmission unit 204 encodes the high-speed transmission data to generate high-speed transmission encoded data, and the high-speed data obtained based on the high-speed transmission encoded data Output a signal.

  The low speed data signal output from the low speed data transmission unit 202 is input to the adder 208. The high speed data signal output from the high speed data transmission unit 204 is input to the adder 208. When the low-speed data signal and the high-speed data signal are input, the adder 208 adds the low-speed data signal and the high-speed data signal and outputs an addition signal (transmission signal). The added signal output from the adder 208 is transmitted to the receiving side through a predetermined signal line. The low-speed transmission data is, for example, control data, sensor data, audio data, and the like. The high-speed transmission data is, for example, image data displayed on the liquid crystal unit 34. The predetermined signal line is, for example, the serial signal line 28.

  When high-speed transmission data is not input to the high-speed data transmission unit 204, the control circuit 206 stops the operation of the high-speed data transmission unit 204. At this time, the control circuit 206 also stops a clock generation circuit used for generating and transmitting a high-speed data signal. Conversely, when the high-speed transmission data is input to the high-speed data transmission unit 204, the control circuit 206 starts the operation of the high-speed data transmission unit 204, including the clock generation circuit.

  As a matter of course, the data clock of the high-speed data signal has a higher frequency than the data clock of the low-speed data signal. Further, the frequency of the carrier used for generating the high-speed data signal is higher than the frequency of the carrier used for generating the low-speed data signal. For this reason, the high-speed data transmission unit 204 is required to operate at high speed. As a result, the high-speed data transmission unit 204 consumes more power than the low-speed data transmission unit 202 during operation. That is, the power consumption of the high-speed data transmission unit 204 is larger than the power consumption of the low-speed data transmission unit 202.

  Therefore, by controlling the operation of the high-speed data transmission unit 204 by the control circuit 206, the power consumption on the transmission side can be effectively suppressed. On the other hand, the control circuit 206 always operates the low-speed data transmission unit 202. Since the low-speed data transmission unit 202 is always operating, the delay associated with the start / stop of operation of the low-speed data transmission unit 202 does not occur. For this reason, the low-speed transmission data is quickly transmitted from the low-speed data transmission unit 202. As a result, data with a short allowable delay time, such as control data and sensor data, is quickly transmitted to the receiving side, and it is possible to avoid the occurrence of problems associated with transmission delays.

(Receiver configuration)
Next, the configuration on the receiving side will be described. As shown in FIG. 11, the configuration on the receiving side includes a low-speed data receiving unit 212, a high-speed data receiving unit 214, and a control circuit 216. The low speed data receiving unit 212 is an example of a transmission circuit used for receiving low speed data. The high-speed data receiving unit 214 is an example of a transmission circuit used for receiving high-speed data. The control circuit 216 is a circuit that controls operations of the low-speed data receiving unit 212 and the high-speed data receiving unit 214. The low-speed data receiving unit 212 and the high-speed data receiving unit 214 receive the addition signal (reception signal) generated by the adder 208 on the transmission side.

  When the addition signal is input, the low-speed data receiving unit 212 separates the low-speed data signal from the addition signal. Then, the low-speed data receiving unit 212 restores the low-speed transmission data from the separated low-speed data signal, and outputs the restored low-speed transmission data as low-speed reception data. The low-speed data receiving unit 212 inputs a low-speed data signal separated from the addition signal to the high-speed data receiving unit 214. When the low-speed data signal and the addition signal are input, the high-speed data receiving unit 214 separates the high-speed data signal from the addition signal using the low-speed data signal. Then, the high-speed data receiving unit 214 restores the high-speed transmission data from the separated high-speed data signal, and outputs the restored high-speed transmission data as high-speed reception data.

  Further, when the high-speed transmission data is not transmitted, the control circuit 216 stops the operation of the high-speed data reception unit 214. At this time, the control circuit 216 also stops the clock generation circuit used for separating the high-speed data signal and restoring the high-speed transmission data. Conversely, when high-speed transmission data is transmitted, the control circuit 216 starts the operation of the high-speed data receiving unit 214 including the clock generation circuit. However, data indicating whether high-speed transmission data has been transmitted (hereinafter, operation control data) is transmitted in the form of low-speed transmission data. Therefore, the operation control data is received by the low-speed data receiving unit 212 and input to the control circuit 216. Then, the control circuit 216 controls the operation of the high-speed data receiving unit 214 according to the input operation control data.

  The control circuit 216 always operates the low speed data receiving unit 212. Since the low-speed data receiving unit 212 is always operating, a delay due to the start / stop of the operation of the low-speed data receiving unit 212 does not occur. Therefore, when the operation control data is transmitted, the low speed data receiving unit 212 can quickly receive the operation control data. Further, not only the operation control data but also the low-speed transmission data can be quickly received by the low-speed data receiving unit 212. As a result, it is possible to quickly receive data with a short allowable delay time, such as control data and sensor data, and it is possible to avoid the occurrence of problems associated with transmission delays.

(Encoding method)
Next, an encoding method according to the signal transmission method of the present embodiment will be described with reference to FIGS. 12, 13, and 14A to 14C. As described above, the signal transmission method according to the present embodiment is a method of adding and transmitting a low-speed data signal and a high-speed data signal. Therefore, as shown in FIG. 12, the signal transmission method according to the present embodiment has a timing at which both signals are simultaneously transmitted and received within the same time. Therefore, a device that avoids interference between the low-speed data signal and the high-speed data signal is required.

  In response to such a request, the present inventor has devised a method for transmitting a high-speed data signal in which the DC offset becomes 0 every half cycle of the low-speed data signal, as shown in FIG. The DC offset here is a total value of amplitude values in a certain period. For example, FIG. 14A shows a binary signal waveform in which the DC offset is zero. In the example of FIG. 14A, the amplitude values are {+1, -1, +1, -1, -1, +1, -1, +1}, and the sum of these amplitude values is zero. That is, the DC offset of this binary signal is 0 in the period illustrated in FIG. 14A. Similarly, FIG. 14B shows an example of a ternary signal with a DC offset of 0, and FIG. 14C shows an example of a quinary signal with a DC offset of 0.

  The addition signal obtained by adding the high-speed data signal whose DC offset becomes 0 every half cycle of the low-speed data signal and the low-speed data signal is separated into the low-speed data signal and the high-speed data signal using the following method. Is done. First, the amplitude value of the addition signal is averaged every half cycle of the low-speed data signal. For example, when the amplitude value of the low-speed data signal is 1 in a certain interval and the amplitude value of the high-speed data signal is {−1, 1, −1, 1} (DC offset = 0) in that interval, When the amplitude values {0, 2, 0, 2} are averaged, (0 + 2 + 0 + 2) / 4 = 1. That is, the amplitude value of the high-speed data signal becomes zero by averaging the amplitude value of the addition signal every half cycle of the low-speed data signal.

  Therefore, the low-speed data signal can be easily separated from the addition signal. When a low-speed data signal is obtained, a high-speed data signal can be obtained by subtracting the low-speed data signal from the addition signal. That is, the low-speed data signal and the high-speed data signal can be easily separated from the addition signal by the averaging process and the subtraction process. Note that a high-speed data signal having a DC offset of 0 every half cycle of the low-speed data signal is generated by the high-speed data transmission unit 204 described above. The averaging process is performed by the low-speed data receiving unit 212. The subtraction process is executed by the high-speed data receiving unit 214.

  By applying the above encoding method and signal transmission method, interference between the low-speed data signal and the high-speed data signal is avoided. Further, since low-speed transmission data such as control data can be transmitted and received quickly, problems associated with transmission delays are avoided. Furthermore, by controlling the operations of the high-speed data transmission unit 204 and the high-speed data reception unit 214, power consumption is effectively reduced. As described above, the signal transmission method / operation control method according to the present embodiment effectively reduces power consumption while avoiding interference between signals and avoiding transmission delay of low-speed transmission data. .

[2-2: Details of signal transmission method]
Hereinafter, the signal transmission method according to the present embodiment will be described more specifically. In the following description, description of components related to operation control is omitted.

(2-2-1: Configuration on the transmission side)
First, the configuration on the transmission side according to the present embodiment will be described in more detail with reference to FIG. FIG. 15 shows a configuration example on the transmission side according to the present embodiment in more detail.

  As shown in FIG. 15, the transmission side configuration includes PS conversion units 232 and 236, encoding units 234 and 238, and an adder 240. The PS conversion unit 232 is means for serializing high-speed transmission data input in the form of parallel data. The encoding unit 234 is means for encoding high-speed transmission data and generating a high-speed data signal. The PS converter 236 is a means for serializing low-speed transmission data input in the form of parallel data. Furthermore, the encoding unit 238 is means for encoding low-speed transmission data and generating a low-speed data signal. The adder 240 is a means for adding the high speed data signal and the low speed data signal.

  High-speed transmission data is input to the PS conversion unit 232 in the form of parallel data. For example, the image data output from the baseband processor 22 and input to the serializer 26 via the parallel signal line 24 is an example of high-speed transmission data. The PS conversion unit 232 receives a high-speed data word clock and a bit clock.

  The PS conversion unit 232 takes in the high-speed transmission data at the timing indicated by the word clock, and converts the parallel data into serial data. Then, the PS conversion unit 232 outputs the high-speed transmission data converted into serial data at the timing indicated by the bit clock. The high-speed transmission data output by the PS conversion unit 232 is input to the encoding unit 234. Note that how many bits are set for one word is appropriately set according to the embodiment.

  In addition to the high-speed transmission data input from the PS conversion unit 232, the encoding unit 234 receives a bit clock and a symbol clock for high-speed data. When the high-speed transmission data is input, the encoding unit 234 captures the high-speed transmission data at the timing indicated by the bit clock, and encodes the captured high-speed transmission data. At this time, the encoding unit 234 encodes the high-speed transmission data, and generates encoded data in which the DC offset becomes 0 every half cycle (1/2 symbol clock (low speed)) of the low-speed data signal. Furthermore, the encoding unit 234 generates a high-speed data signal based on the generated encoded data and outputs it at a timing indicated by the symbol clock. The high-speed data signal generated by the encoding unit 234 is input to the adder 240.

  On the other hand, the low-speed transmission data is input to the PS conversion unit 236 in the form of parallel data. For example, the display control data output from the baseband processor 22 and input to the serializer 26 via the parallel signal line 24 is an example of low-speed transmission data. The PS converter 236 receives a low-speed data word clock and a bit clock. When the low-speed transmission data is input, the PS conversion unit 236 serializes the low-speed transmission data using the word clock and the bit clock. The low-speed transmission data serialized by the PS conversion unit 236 is input to the encoding unit 238.

  In addition to the low-speed transmission data input from the PS conversion unit 236, the encoding unit 238 receives a bit clock and a symbol clock for low-speed data. When the low-speed transmission data is input, the encoding unit 238 takes in the low-speed transmission data at the timing indicated by the bit clock. Then, the encoding unit 238 encodes the captured low-speed transmission data to generate encoded data. Furthermore, the encoding unit 238 generates a low-speed data signal based on the generated encoded data, and outputs the low-speed data signal at the timing indicated by the symbol clock. However, the code used for encoding the low-speed transmission data is preferably a code that does not include a DC component.

  The low speed data signal output from the encoding unit 238 is input to the adder 240. When the high-speed data signal and the low-speed data signal are input, the adder 240 adds the high-speed data signal and the low-speed data signal to generate an addition signal, and outputs the generated addition signal toward the reception side. This addition signal is transmitted to the receiving side through the serial signal line 28, for example.

(2-2-2: Configuration on the receiving side)
Next, the configuration on the reception side according to the present embodiment will be described in more detail with reference to FIGS. 16 to 18 show more detailed configuration examples on the transmission side according to the present embodiment.

  As shown in FIG. 16, the configuration on the receiving side includes a clock recovery circuit 252, a decoding unit 254 (low speed), an SP conversion unit 256, a delay circuit 258, a subtractor 260, and a decoding unit 262 (high speed). And an SP conversion unit 264. The clock recovery circuit 252 is a means for recovering various clocks. The decoding unit 254 is means for separating the low-speed data signal from the addition signal and restoring the low-speed transmission data. The SP conversion unit 256 is means for parallelizing the low-speed transmission data restored by the decoding unit 254 (hereinafter referred to as low-speed data).

  The delay circuit 258 is a means for delaying the addition signal input to the subtractor 260 while the low-speed data signal is separated by the decoding unit 254. The subtracter 260 is means for subtracting the low-speed data signal from the addition signal. The decoding unit 262 is means for restoring high-speed transmission data from the high-speed data signal. The SP conversion unit 264 is means for parallelizing the high-speed transmission data restored by the decoding unit 262 (hereinafter, high-speed data).

  The addition signal (reception signal) transmitted from the transmission side is input to the clock recovery circuit 252, the decoding unit 254, and the delay circuit 258. When the addition signal is input, the clock recovery circuit 252 recovers the low-speed data word clock, the bit clock, and the symbol clock, and the high-speed data word clock, the bit clock, and the symbol clock from the addition signal.

  The word clock for low speed data reproduced by the clock reproduction circuit 252 is input to the SP conversion unit 256. The bit clock for low-speed data is input to the decoding unit 254 and the SP conversion unit 256. Further, the symbol clock for low-speed data is input to the decoding unit 254 and the delay circuit 258. Further, the high-speed data word clock reproduced by the clock reproduction circuit 252 is input to the SP conversion unit 264. Then, the bit clock for high-speed data is input to the decoding unit 262 and the SP conversion unit 264. Further, the symbol clock for high-speed data is input to the decoding unit 262. Here, the configuration of the clock recovery circuit 252 will be described in more detail with reference to FIG.

  FIG. 17 is an explanatory diagram showing a detailed configuration example of the clock recovery circuit 252. As shown in FIG. 17, the clock recovery circuit 252 includes a low-speed data symbol clock recovery unit 272, a low-speed data bit clock recovery unit 274, a low-speed data word clock recovery unit 276, and a high-speed data symbol clock recovery unit. 278, a high-speed data bit clock recovery unit 280, and a high-speed data word clock recovery unit 282.

  The addition signal input to the clock recovery circuit 252 is first input to the low-speed data symbol clock recovery unit 272. The low-speed data symbol clock recovery unit 272 recovers the low-speed data symbol clock from the added signal. The low-speed data symbol clock recovered by the low-speed data symbol clock recovery unit 272 is output toward the decoding unit 254. Further, the low-speed data symbol clock is input to the low-speed data bit clock recovery unit 274, the low-speed data word clock recovery unit 276, and the high-speed data symbol clock recovery unit 278.

  When the low-speed data symbol clock is input, the low-speed data bit clock recovery unit 274 recovers the low-speed data bit clock based on the low-speed data symbol clock. The low-speed data word clock recovery unit 276 regenerates the low-speed data word clock based on the low-speed data symbol clock. When the low-speed data symbol clock is input, the high-speed data symbol clock recovery unit 278 recovers the high-speed data symbol clock based on the low-speed data symbol clock.

  The high-speed data symbol clock recovered by the high-speed data symbol clock recovery unit 278 is input to the high-speed data bit clock recovery unit 280 and the high-speed data word clock recovery unit 282. When the high-speed data symbol clock is input, the high-speed data bit clock regeneration unit 280 regenerates the high-speed data bit clock based on the high-speed data symbol clock. The high-speed data word clock recovery unit 282 recovers the high-speed data word clock based on the high-speed data symbol clock.

  There is a predetermined relationship among the low-speed data symbol clock, the low-speed data bit clock, the low-speed data word clock, the high-speed data symbol clock, the high-speed data bit clock, and the high-speed data word clock. Therefore, the low-speed data bit clock, the low-speed data word clock, the high-speed data symbol clock, the high-speed data bit clock, and the high-speed data word clock are generated sequentially from the low-speed data symbol clock as described above. Note that the generation order and generation method of each clock are not limited to the above example, and can be appropriately changed according to the embodiment.

  Refer to FIG. 16 again. When the low-speed data symbol clock is input from the clock recovery circuit 252, the decoding unit 254 restores the low-speed data signal by averaging the amplitude value of the addition signal every half cycle (one symbol period) of the low-speed data symbol clock. To do. As described above, in the present embodiment, a method of encoding at the time of generating a high-speed data signal so that N symbols (N ≧ 2; N is a natural number) of the high-speed data signal is included in one symbol period of the low-speed data signal. Is used. Also, a code is used such that the sum of the amplitude values of the high-speed data signal is 0 in one symbol period of the low-speed data signal.

  Therefore, the component of the high-speed data signal can be made zero by averaging the amplitude value of the addition signal every half cycle of the low-speed data symbol clock. This averaging process is executed in the following three steps, for example.

(S1) A step of sampling the amplitude value of the addition signal at the timing indicated by the high-speed data symbol clock input from the clock recovery circuit 252.
(S2) A step of integrating the amplitude values sampled in step S1 over a half cycle (one symbol period) of the low-speed data symbol clock to calculate an integrated value.
(S3) A step of calculating an average value by dividing the integrated value calculated in step S3 by the number N of high-speed data symbols included in one symbol period of low-speed data.

  A signal having an average value of each symbol period obtained by these three steps as an amplitude value is a low-speed data signal. Moreover, the data string of these average values is low-speed data. That is, the low speed data is decoded by the above three steps. Here, a specific configuration of the decoding unit 254 will be described in more detail with reference to FIG. FIG. 18 is an explanatory diagram illustrating a specific configuration example of the decoding unit 254.

  As illustrated in FIG. 18, the decoding unit 254 includes, for example, an adder 292, a register 294, a decoding circuit 298, and a control circuit 296. An adder signal (reception signal) is input to the adder 292. A high-speed data symbol clock is input to the register 294 and the control circuit 296. Further, a low-speed data symbol clock is input to the control circuit 296 and the decoding circuit 298. The decoding circuit 298 receives a low-speed data bit clock.

  The register 294 holds the addition result by the adder 292. In addition to the addition signal, the adder 292 receives the signal output from the register 294. The adder 292 adds the addition signal and the signal output from the register 294. Therefore, the amplitude value of the addition signal can be integrated over one symbol period of low-speed data by appropriately controlling the timing at which the register 294 resets and holds.

  Control of the register 294 is performed by the control circuit 296. The control circuit 296 outputs a reset signal and a hold signal based on the timings indicated by the high-speed data symbol clock and the low-speed data symbol clock. The reset signal and hold signal output by the control circuit 296 are input to the register 294. The register 294 executes reset and hold operations according to the input reset signal and hold signal.

  The register 294 sets the register value to 0 at the head of one symbol of low-speed data in response to the input of the reset signal. The register 294 holds the output of the adder 292 in synchronization with the high-speed data symbol clock in response to the input of the hold signal. By such an operation, data from which the influence of the high speed data is removed is obtained at the end of each symbol of the low speed data. The output of the register 294 is input to the decoding circuit 298. The decoding circuit 298 restores the low-speed data using the output of the register 294, the low-speed data symbol clock, and the low-speed data bit clock.

  Refer to FIG. 16 again. When the low-speed data is restored as described above, the decoding unit 254 outputs the low-speed data at the timing indicated by the low-speed data bit clock input by the clock recovery circuit 252. The low speed data output by the decoding unit 254 is input to the SP conversion unit 256. Further, the low-speed data signal restored by the decoding unit 254 is input to the subtracter 260.

  When the low-speed data is input, the SP conversion unit 257 takes in the low-speed data at the timing indicated by the low-speed data bit clock input by the clock recovery circuit 252 and converts the low-speed data input in the form of serial data into parallel data. Convert to shape. Then, the SP conversion unit 257 outputs the low-speed data converted into the parallel data form at the timing indicated by the word clock of the low-speed data input by the clock recovery circuit 252. In this way, low speed data is received.

  On the other hand, when the addition signal is input, the delay circuit 258 adjusts the output timing of the addition signal, and outputs the addition signal at the timing indicated by the low-speed data symbol clock input by the clock recovery circuit 252. The addition signal output from the delay circuit 258 is input to the subtracter 260. Thus, by delaying the addition signal for a predetermined time and adjusting its output timing, the timing of the low-speed data signal input from the decoding unit 254 to the subtracter 260 and the timing of the addition signal are synchronized.

  When the low-speed data signal and the addition signal are input, the subtracter 260 subtracts the low-speed data signal from the addition signal to restore the high-speed data signal. Then, the high-speed data signal restored by the subtracter 260 is input to the decoding unit 262. The decoding unit 262 takes in the high-speed data signal at the timing indicated by the high-speed data symbol clock input by the clock recovery circuit 252 and restores the high-speed data from the high-speed data signal. Then, the decoding unit 262 outputs the restored high-speed data at the timing indicated by the high-speed data bit clock input from the clock recovery circuit 252.

  The high speed data output from the decoding unit 262 is input to the SP conversion unit 264. When high-speed data is input, the SP conversion unit 264 takes in the high-speed data at the timing indicated by the high-speed data bit clock input by the clock recovery circuit 252 and converts the high-speed data input in the form of serial data into parallel data. Convert to shape. Then, the SP conversion unit 264 outputs the high-speed data converted into the form of parallel data at the timing indicated by the high-speed data word clock input by the clock recovery circuit 252. In this way, high-speed data is received.

  The configuration of the transmission side and the reception side that can realize the signal transmission method according to the present embodiment has been described above in detail. By applying the above configuration, interference between the high-speed data signal and the low-speed data signal can be avoided.

(Specific example: Partial response code)
Here, the case where a partial response code is used for high-speed data is introduced. The partial response code is generated using the circuit (subtracter 302, delay circuit 304) shown in FIG. 19A. That is, the input data can be converted into a partial response code by delaying the input data by one clock and inverting the sign. For example, the waveform of the partial response code for the input data 1 is as shown in FIG. 19B. On the other hand, the partial response code for input data 0 is 0.

  For example, if four symbols of high-speed data are included in one symbol period of low-speed data, the relationship between the low-speed data signal and the high-speed data signal illustrated in FIG. 19C is obtained. The partial response code is a code that does not include a DC component. Therefore, as is clear from the example of FIG. 19C, the DC offset is 0 for four symbols of high-speed data. In the example of FIG. 19C, 3-bit high-speed data is transmitted in one symbol period of low-speed data. The fourth bit is set to 0 in order to reset the end of each symbol period of the low-speed data to the symbol value 0. With this configuration, the partial response code does not straddle adjacent symbol periods of low-speed data.

  In this way, when the partial response code is used, the sum of the symbol values of the high-speed data in one symbol period of the low-speed data becomes 0. Therefore, even if the high-speed data signal and the low-speed data signal are added, both The signals do not affect each other due to interference. When the partial response code is used, the low-speed data signal (L), the high-speed data signal (H), and the addition signal (C) have signal waveforms as shown in FIG.

  The specific configuration example in the case where the partial response code is applied to the encoding method for realizing the signal transmission method of the present embodiment has been described above. In addition to the partial response code, for example, a Manchester code, an AMI code, or any other code that can reduce the sum of symbol values to 0 during one symbol period is used as a code used to generate high-speed data. Can do. Moreover, as a code | symbol used for the production | generation of low speed data, the arbitrary codes | symbols which do not have a DC component are used, for example.

(Supplement)
Here, a supplementary explanation will be given for the high-speed data, the nature of the low-speed data, and the operation control method that have appeared in the above description. Examples of data exchanged between the operation unit 12 and the display unit 16 of the mobile terminal 10 include display data displayed on the liquid crystal unit 34, image data captured by a camera mounted on the display unit 16, and audio. Data, various sensor data, and control data for controlling the liquid crystal unit 34 and the camera. Display data and imaging data are high-speed data. On the other hand, voice data, data of various sensors, and control data are low speed data.

  Some sensor data and some control data have a short allowable delay time. Therefore, it is necessary to avoid the occurrence of a long delay time in the low-speed data transmission circuit (transmission circuit, reception circuit). It is also required to simplify the control of the transmission circuit for low-speed data and the transmission circuit for high-speed data. The operation control method according to the present embodiment employs a system that always operates a transmission circuit for low-speed data. Therefore, even if a low-speed data transmission opportunity with a short allowable delay time occurs, a transmission delay due to the start-up time of the transmission circuit does not occur. Further, since the start / stop of the transmission circuit for high-speed data is appropriately controlled according to the presence / absence of high-speed data, power consumption can be efficiently reduced by simple control.

  The signal transmission method according to the present embodiment has been described in detail above.

<3: Summary>
Finally, the technical contents according to the embodiment of the present invention will be briefly summarized. The technical contents described here can be applied to various information processing apparatuses such as PCs, mobile phones, portable game machines, portable information terminals, information appliances, car navigation systems, and the like.

  The functional configuration of the information processing apparatus can be expressed as follows, for example. The information processing apparatus includes the following first signal generation unit, second signal generation unit, signal addition unit, signal transmission unit, and control circuit. The first signal generation unit generates a first data signal synchronized with the first clock having the frequency f1 from the first data. Further, the second signal generation unit synchronizes with the second clock having the frequency f2 = N * f1 (N is a natural number) from the second data, and has an amplitude with respect to one cycle of the first clock. To generate a second data signal whose value is 0.

  The first data is transmitted in synchronization with a first clock having a frequency f1 lower than that of the second clock. For this reason, the transmission rate of the first data is smaller than that of the second data. Examples of the first data include control data, sensor data, audio data, and the like. In many cases, the amount of data such as control data, sensor data, and audio data is small. In addition, these data have a short allowable delay time.

  On the other hand, the second data is transmitted in synchronization with a second clock having a frequency f2 higher than that of the first clock. For this reason, the transmission rate of the second data is larger than that of the first data. Examples of the second data include image data displayed on the screen, image data taken by a camera function, and the like. In many cases, the amount of data such as image data is large. These data have a longer allowable delay time than data such as control data, sensor data, and audio data.

  The first and second data have the above characteristic differences. Of course, the first data may include image data or the like, and the second data may include audio data or the like. However, it is preferable to selectively use the type of data transmitted as the first data and the type of data transmitted as the second data according to the allowable delay time and the amount of data.

  In addition, the signal adding unit adds the first data signal generated by the first signal generating unit and the second data signal generated by the second signal generating unit to obtain an addition signal. Generate. And said signal transmission part transmits the addition signal produced | generated by the said signal addition part. Thus, the information processing apparatus according to the present embodiment adds the first data signal and the second data signal and transmits the sum.

  As described above, the first data signal is synchronized with the first clock having the frequency f1. The second data signal is synchronized with a second clock having a frequency f2 that is N times the frequency f1. For this reason, when the first data signal and the second data signal are added, the second data signal has a half-cycle of the first clock in which the amplitude value of the first data signal becomes a constant value. An added signal in which the amplitude variation is superimposed for N / 2 periods of the second clock is obtained.

  As described above, the second data signal is set so that the sum of the amplitudes for the ½ period of the first clock is zero. Therefore, when the amplitude value of the addition signal is averaged every half cycle of the first clock, the amplitude component of the second data signal becomes 0, and the component of the first data signal is obtained. That is, when the second data signal generation method as described above is applied, the first data signal can be easily separated from the addition signal. Further, the second data signal can be easily separated by subtracting the first data signal from the addition signal.

  As described above, when the technique of this embodiment is used, the first data signal and the second data signal can be transmitted simultaneously. Even if the input of the second data is stopped, the first data is correctly transmitted. That is, the independence of the first data signal and the second data signal is maintained. For this reason, even if the operation of the component related to the transmission of the second data signal is stopped, the transmission of the first data is not affected. In addition, the component for transmitting the first data signal in synchronization with the relatively low-speed first clock consumes relatively little power.

  Therefore, the control circuit operates the first signal generation unit at all times, operates the second signal generation unit when transmitting the second data, and does not transmit the second data. The operation of the second signal generator is stopped. In this way, the power consumption can be effectively reduced while suppressing the transmission delay by always operating the components related to the transmission of the first data signal and intermittently operating the components related to the transmission of the second data signal. Can be reduced. In accordance with the operation control of the second signal generation unit, the operation control of the clock generator for generating the second clock is also performed by the control circuit.

(Remarks)
The low-speed data transmission unit 202 and the encoding unit 238 are examples of the first signal generation unit. The high-speed data transmission unit 204 and the encoding unit 234 are examples of the second signal generation unit. The adder 208 is an example of a signal adder and a signal transmitter. The low speed data receiving unit 212 and the high speed data receiving unit 214 are examples of a signal receiving unit. The low-speed data receiving unit 212 and the decoding unit 254 are examples of the first signal restoring unit and the first data restoring unit. The high-speed data receiving unit 214, the delay circuit 258, the subtractor 260, and the decoding unit 262 are examples of the second signal restoring unit and the second data restoring unit. The clock recovery circuit 252 is an example of a clock recovery unit. The low-speed data transmission unit 202 includes a clock generation unit. The baseband processor 22 is an example of an arithmetic processing unit. The portable terminal 10 is an example of a signal processing device.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

DESCRIPTION OF SYMBOLS 10 Mobile terminal 12 Operation part 14 Hinge part 16 Display part 22 Baseband processor 24, 32 Parallel signal line 26 Serializer 28 Serial signal line 30 Deserializer 34 Liquid crystal part 102 P / S conversion part 104 Encoder 106 Driver 108 PLL part 110 Timing control part DESCRIPTION OF SYMBOLS 112 Receiver 114 Decoder 116 S / P converter 118 Clock detection part 120 Timing control part 202 Low speed data transmission part 204 High speed data transmission part 206 Control circuit 208 Adder 212 Low speed data reception part 214 High speed data reception part 216 Control circuits 232, 236 PS converter 234, 238 Encoder 240 Adder 252 Clock recovery circuit 254, 262 Decoder 256, 264 SP converter 258 Delay circuit 260 Subtractor 272 Symbol clock recovery unit for low speed data 274 Bit clock recovery unit for low speed data 276 Word clock recovery unit for low speed data 278 Symbol clock recovery unit for high speed data 280 Bit clock recovery unit for high speed data 282 Word clock recovery unit for high speed data 292 Adder 294 Register 296 Control circuit 298 Decoding circuit 302 Subtractor 304 Delay circuit

Claims (10)

A first signal generation unit that generates a first data signal synchronized with a first clock having a frequency f1 from the first data;
From the second data, a value obtained by synchronizing with a second clock having a frequency f2 = N * f1 (N is a natural number) and having a sum of amplitudes for ½ period of the first clock becomes zero. A second signal generator for generating two data signals;
A signal adder that adds the first data signal generated by the first signal generator and the second data signal generated by the second signal generator to generate an added signal;
A signal transmission unit for transmitting the addition signal generated by the signal addition unit;
The first signal generator is always operated, the second signal generator is operated when transmitting the second data, and the second signal generator is operated when not transmitting the second data. A control circuit for stopping
A signal processing apparatus comprising: A signal receiver for receiving the addition signal transmitted by the signal transmitter; and
A first signal restoration unit that restores the first data signal by averaging the amplitude values of the addition signals received by the signal reception unit for each cycle of the first clock;
A second signal restoration unit for restoring the second data signal by subtracting the first data signal restored by the first signal restoration unit from the addition signal received by the signal reception unit;
A first data restoration unit for restoring the first data from the first data signal restored by the first signal restoration unit;
A second data restoration unit for restoring the second data from the second data signal restored by the second signal restoration unit;
The signal processing apparatus according to claim 1, further comprising:   The control circuit always operates the first signal restoration unit and the first data restoration unit, and operates the second signal restoration unit and the second data restoration unit when receiving the second data, The signal processing apparatus according to claim 2, wherein when the second data is not received, the operations of the second signal restoration unit and the second data restoration unit are stopped. The control circuit inputs control data for controlling operations of the second signal restoration unit and the second data restoration unit to the first signal generation unit as the first data,
The control data is transmitted via the first signal generation unit, the signal addition unit, the signal generation unit, the signal reception unit, the first signal restoration unit, the first data restoration unit, and the second signal. Input to the restoration unit and the second data restoration unit;
The signal processing apparatus according to claim 3, wherein the second signal restoration unit and the second data restoration unit start or stop an operation according to the control data.   5. The signal processing according to claim 4, wherein the first signal generation unit encodes the first data into a symbol string in which a DC component is suppressed, and generates the first data signal based on the symbol string. apparatus. The second signal generation unit includes a clock generation unit that generates the second clock,
The second signal restoration unit includes a clock reproduction unit that reproduces the second clock,
The signal processing according to claim 5, wherein the control circuit controls at least operations of the clock generation unit and the clock recovery unit when controlling operations of the second signal generation unit and the second signal restoration unit. apparatus. A display for displaying image data;
An arithmetic processing unit for outputting the image data;
Further comprising
The image data output by the arithmetic processing unit includes the second data generation unit, the signal addition unit, the signal transmission unit, the signal reception unit, the second signal restoration unit, and the second data as the second data. The signal processing device according to claim 6, wherein the signal processing device is transmitted via a data restoration unit and input to the display unit. A first signal generation step of generating a first data signal synchronized with a first clock having a frequency f1 from the first data;
From the second data, a value obtained by synchronizing with a second clock having a frequency f2 = N * f1 (N is a natural number) and having a sum of amplitudes for ½ period of the first clock becomes zero. A second signal generating step for generating two data signals;
An addition step of adding the first data signal generated in the first signal generation step and the second data signal generated in the second signal generation step to generate an addition signal;
A transmission step of transmitting the addition signal generated in the addition step;
The process of the first signal generation step is always performed, the second signal generation step is performed when the second data is transmitted, and the second signal is transmitted when the second data is not transmitted. A control step for controlling to stop the processing of the generation step;
Including a signal transmission method. A second data generated from the first data and synchronized with the first clock having the frequency f1 and the second data and having the frequency f2 = N * f1 (N is a natural number) An amplitude value of an addition signal obtained by adding a second data signal that is 0 in synchronization with a clock and that has a sum of amplitudes over a half period of the first clock is 0. A first signal restoring unit that restores the first data signal on an average every one cycle of the clock;
A second signal restoration unit for subtracting the first data signal restored by the first signal restoration unit from the addition signal to restore the second data signal;
A first data restoration unit for restoring the first data from the first data signal restored by the first signal restoration unit;
A second data restoration unit for restoring the second data from the second data signal restored by the second signal restoration unit;
A signal processing apparatus comprising: A second data generated from the first data and synchronized with the first clock having the frequency f1 and the second data and having the frequency f2 = N * f1 (N is a natural number) An amplitude value of an addition signal obtained by adding a second data signal that is 0 in synchronization with a clock and that has a sum of amplitudes over a half period of the first clock is 0. A first signal restoring step of restoring the first data signal on an average for each period of the clock;
A second signal restoration step of subtracting the first data signal restored in the first signal restoration step from the added signal to restore the second data signal;
A first data restoration step for restoring the first data from the first data signal restored in the first signal restoration step;
A second data restoration step for restoring the second data from the second data signal restored in the second signal restoration step;
Including data restoration method.

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