JP2010268385A - Signal processing apparatus, timing synchronization circuit, signal processing method, and timing synchronization method - Google Patents

Abstract

A timing synchronization circuit for synchronizing a data signal and a clock without using a delay is provided.
A toggle circuit that toggles an input signal at a rise or fall timing, a clock and an output signal of the toggle circuit are input, and the output signal of the toggle circuit is synchronized with the rise or fall timing of the clock. A first synchronization circuit, an exclusive OR circuit that receives an output signal of the toggle circuit and an output signal of the first synchronization circuit, and outputs an exclusive OR of both the input output signals; and the clock; There is provided a timing synchronization circuit including a second synchronization circuit that receives the output signal of the exclusive OR circuit and synchronizes the output signal with the falling or rising timing of the clock.
[Selection] Figure 13

Description

  The present invention relates to a signal processing device, a timing synchronization circuit, a signal processing method, and a timing synchronization method.

  In an information processing apparatus such as a mobile phone or a notebook personal computer (hereinafter referred to as a notebook PC), a movable member is used at a hinge portion that connects a main body portion operated by a user and a display portion on which information is displayed. There are many cases. However, since many signal lines and power lines are wired in the hinge portion, a device for maintaining the reliability of the wiring is required. First, it is conceivable to reduce the number of signal lines passing through the hinge portion. Therefore, data transmission processing is performed between the main body portion and the display portion not by the parallel transmission method but by the serial transmission method. When the serial transmission method is used, the number of signal lines is reduced, and an effect of reducing electromagnetic interference (EMI) is also obtained.

  In the case of a serial transmission method, data is encoded and then transmitted. In this case, for example, an NRZ (Non Return to Zero) code system, a Manchester code system, an AMI (Alternate Mark Inversion) code system, or the like is used as the encoding system. For example, Patent Document 1 below discloses a technique for transmitting data using an AMI code, which is a typical example of a bipolar code. In the same document, a technique is disclosed in which a data clock is expressed by an intermediate value of a signal level and transmitted, and the data clock is reproduced on the receiving side based on the signal level.

Japanese Patent Laid-Open No. 3-109984

  However, in an information processing apparatus such as a notebook PC, even if the serial transmission method using the above-described code is used, the number of signal lines wired to the hinge portion is still large. For example, in the case of a notebook PC, there is a wiring related to an LED backlight for illuminating the LCD in addition to a video signal transmitted to the display portion. When these signal lines are included, about several tens of signal lines are connected to the hinge portion. Will be wired. However, LCD is an abbreviation for Liquid Crystal Display. LED is an abbreviation for Light Emitting Diode.

  In view of these problems, an encoding method (hereinafter referred to as a new method) has been developed that does not include a DC component and that can easily extract a clock component from a received signal. Since the transmission signal generated based on this new system does not contain a DC component, it can be transmitted superimposed on a DC power source. Furthermore, by detecting the polarity inversion period from this transmission signal, it is possible to reproduce the clock without using a PLL on the receiving side. Therefore, a plurality of signal lines can be collected, the number of signal lines can be reduced, and power consumption and circuit scale can be reduced. However, PLL is an abbreviation for Phase Locked Loop.

  The new transmission signal has a multi-level code waveform in which one bit value is expressed by a plurality of amplitude levels. Therefore, on the receiving side, it is necessary to detect each amplitude level using a plurality of comparators each having a different threshold level. Also, when extracting the clock component on the receiving side, a clock detection comparator is used to detect the timing at which the transmission signal crosses zero. These comparators perform threshold determination of amplitude levels at different threshold levels. The output of each comparator is obtained as a pulse signal expressed as a pulse that rises at the timing when the amplitude level of the transmission signal crosses each threshold level from bottom to top and falls at the timing when it crosses from top to bottom. .

  If it is an ideal transmission path, the output of each comparator obtained from the transmission signal of the above new method is a pulse whose edges are aligned with the pulse signal of the clock component (hereinafter referred to as detection clock) output from the comparator for clock detection. Signal (hereinafter, data signal). However, the pulse width of the data signal obtained from the transmission signal that has passed through a transmission line having a high-frequency cutoff characteristic, a filter circuit, or the like is narrower than the pulse width of the detection clock. In particular, when an amplitude level is to be detected from a transmission signal having a multilevel code waveform according to the above-described new method, the pulse width of the data signal output from the comparator having a threshold value having a large absolute value is equal to the pulse width of the detection clock. It will be very narrow compared to it.

  As a result, the edge of the pulse included in the detection clock and the edge of the pulse included in the data signal are greatly separated, and an error occurs during data extraction. For example, a method of delaying either the detection clock or the data signal to align the pulse edges and extracting the data using the detection clock and the data signal having the aligned pulse edges can be considered. However, it is very difficult to accurately control the delay in the integrated circuit. Furthermore, since the delay timing is affected by subtle fluctuations in the transmission signal, it is difficult to align the edges of both pulses accurately.

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is more reliably from a transmission signal having a multi-level code waveform obtained by synchronously adding a clock and data. It is an object of the present invention to provide a new and improved signal processing apparatus, timing synchronization circuit, signal processing method, and timing synchronization method that make it possible to extract data.

  In order to solve the above problems, according to an aspect of the present invention, a multilevel signal having a signal waveform obtained by synchronously adding a transmission signal and a clock and having a polarity inverted every half cycle of the clock is obtained. A signal receiving unit that receives the signal, a timing at which the amplitude level of the multilevel signal received by the signal receiving unit crosses zero, and a clock recovery unit that regenerates the clock based on the detection result; and A data signal having a pulse that rises when the amplitude level of the multilevel signal received by the signal receiver crosses from the bottom to the top and falls when the threshold level set between the amplitude levels crosses from the bottom to the top A data signal generating unit for generating the data, and synchronizing data by synchronizing the data signal generated by the data signal generating unit and the clock recovered by the clock recovery unit Provided with a signal synchronization unit that generates a signal and a data extraction unit that extracts data from the synchronized data signal generated by the signal synchronization unit based on the clock recovered by the clock recovery unit Is done.

  In addition, the signal synchronization unit includes a toggle signal generation unit that generates a toggle signal that toggles at a timing when the pulse of the data signal rises or falls, and a toggle signal generated by the toggle signal generation unit. Exclusive of a toggle synchronization signal generation unit that generates a toggle synchronization signal in synchronization with a fall or rise timing, and a toggle signal generated by the toggle signal generation unit and a toggle synchronization signal generated by the toggle synchronization signal generation unit An exclusive OR circuit that outputs a logical sum, and a synchronous data signal generation unit that generates the synchronous data signal by synchronizing the output signal of the exclusive OR circuit with the falling or rising timing of the clock. .

  Further, the data extraction unit is configured to sample the amplitude level of the synchronous data signal at the falling or rising timing of the clock reproduced by the clock reproduction unit, and extract data based on the sampling result. May be.

  The data signal generation unit includes a plurality of comparators for generating a plurality of the data signals corresponding to the plurality of threshold levels, and the signal synchronization unit includes each of the data signal generation units. Provided in a comparator, and the data extraction unit is configured to extract data based on a synchronization data signal for each threshold level generated by the signal synchronization unit provided in each comparator. Good.

  Further, the signal synchronization unit may be provided in a comparator corresponding to the threshold level having a large absolute value among the plurality of comparators.

  In order to solve the above problem, according to another aspect of the present invention, a toggle circuit that toggles an input signal at a rising or falling timing, a clock, and an output signal of the toggle circuit are input, and the toggle circuit A first synchronization circuit that synchronizes the output signal of the circuit with the rising or falling timing of the clock, the output signal of the toggle circuit, and the output signal of the first synchronization circuit, and the exclusive of both of the input output signals An exclusive OR circuit that outputs a logical OR, a second synchronization circuit that receives the clock and an output signal of the exclusive OR circuit, and synchronizes the output signal with the falling or rising timing of the clock; A timing synchronization circuit is provided.

  The clock has a signal waveform obtained by synchronously adding the transmission signal and the clock, and is reproduced based on the timing at which the amplitude level of the multilevel signal whose polarity is inverted every half cycle of the clock is zero-crossed. And the input signal rises when the amplitude level of the multilevel signal exceeds the threshold level based on the threshold level set between the amplitude levels of the multilevel signal. The pulse signal falls at a lower timing, and the output signal of the second synchronization circuit may be configured to be used for extracting data of the data signal using the clock.

  In order to solve the above-described problem, according to another aspect of the present invention, there is provided a signal waveform obtained by synchronously adding a transmission signal and a clock, and the polarity is inverted every half cycle of the clock. A signal receiving step for receiving a value signal, a clock recovery step for detecting the timing at which the amplitude level of the multilevel signal received in the signal receiving step crosses zero, and regenerating the clock based on the detection result, The threshold level set between the amplitude levels of the value signals rises when the amplitude level of the multilevel signal received in the signal receiving step crosses from bottom to top, and falls at the timing of crossing from top to bottom. A data signal generation step for generating a data signal, and the data signal generated in the data signal generation step and the clock recovery step. A signal synchronizing step for generating a synchronized data signal by synchronizing with the clock regenerated at the clock, and extracting data from the synchronized data signal generated at the signal synchronizing step based on the clock regenerated at the clock regenerating step And a data extraction step.

  Further, the signal synchronization step includes a toggle signal generation step for generating a toggle signal that toggles at the timing when the pulse of the data signal rises or falls, and the toggle signal generated at the toggle signal generation step is changed to the rising edge of the clock. A toggle synchronization signal generation step that generates a toggle synchronization signal in synchronization with a fall or rise timing, and the toggle signal generated in the toggle signal generation step and the toggle synchronization signal generated in the toggle synchronization signal generation step An exclusive OR calculation step of calculating a logical sum; a synchronous data signal generation step of generating the synchronous data signal by synchronizing the calculation result of the exclusive OR calculation step with the falling or rising timing of the clock; including.

  In order to solve the above-described problem, according to another aspect of the present invention, a toggle step for toggling an input signal at a rising or falling timing, and a clock and an output of the toggle step are input, and the toggle step A first synchronization step that synchronizes the output with the rising or falling timing of the clock, and an exclusive OR that calculates the exclusive OR of the two outputs that are input with the output of the toggle step and the output of the first synchronization step as inputs. A timing synchronization method comprising: a logical OR calculation step; and a second synchronization step that receives the output of the clock and the exclusive OR calculation step as input and synchronizes the output with the falling or rising timing of the clock. Provided.

  As described above, according to the present invention, data can be extracted more reliably from a transmission signal having a multilevel code waveform obtained by synchronously adding a clock and data.

It is explanatory drawing which shows the structural example of the portable terminal which employ | adopted the parallel transmission system. It is explanatory drawing which shows the structural example of the portable terminal which employ | adopted the serial transmission system. It is explanatory drawing which shows the function structural example of the portable terminal which concerns on a new system. It is explanatory drawing which shows the signal waveform of an AMI code | symbol. It is explanatory drawing which shows an example of the multi-value code production | generation method and amplitude determination method of the new system based on an AMI code. It is explanatory drawing which showed typically the eye pattern observed on the receiving side about the multi-value signal (6 value signal) of the new system based on an AMI code | symbol. It is explanatory drawing which shows the signal waveform of Manchester code | symbol. It is explanatory drawing which shows an example of the multi-value code production | generation method and amplitude determination method of the new system based on Manchester code | symbol. It is explanatory drawing which showed typically the eye pattern observed in the receiving side about the multi-value signal (4 value signal) of the new system based on Manchester code | symbol. It is explanatory drawing for demonstrating the difference in the pulse width between the data signal and clock which are obtained by carrying out threshold value determination of a multilevel signal on the receiving side. It is explanatory drawing which shows the example of 1 structure of the timing synchronization circuit which concerns on one Embodiment of this invention. It is explanatory drawing which showed typically the pulse waveform of the data signal obtained by carrying out threshold value determination of a multi-value signal, and the pulse waveform of a clock on the receiving side. FIG. 10 is an explanatory diagram showing a flow of signal processing executed in the timing synchronization circuit with respect to the timing synchronization method according to the embodiment. 3 is an explanatory diagram illustrating a configuration example of a timing synchronization circuit according to the embodiment. FIG. It is explanatory drawing which showed typically the pulse waveform of the data signal obtained by carrying out threshold value determination of a multi-value signal, and the pulse waveform of a clock on the receiving side. FIG. 10 is an explanatory diagram showing a flow of signal processing executed in the timing synchronization circuit with respect to the timing synchronization method according to the embodiment.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

[About the flow of explanation]
Here, the flow of explanation regarding the embodiment of the present invention described below will be briefly described. First, with reference to FIG. 1, a device configuration of the mobile terminal 100 adopting the parallel transmission method will be briefly described. In this paper, I will point out the problems related to the parallel transmission system. Next, the device configuration of the mobile terminal 130 adopting the serial transmission method will be briefly described with reference to FIG.

  Next, the functional configuration of the mobile terminal 130 according to the above new method will be described with reference to FIG. Next, an encoding method according to the new scheme based on the AMI code will be described with reference to FIGS. Note that AMI is an abbreviation for Alternate Mark Inversion. A signal waveform of a multilevel signal generated by the encoding method based on the AMI code will be described with reference to FIG. Next, an encoding method according to the above new method based on Manchester code will be described with reference to FIGS. In addition, a signal waveform of a multilevel signal generated by the encoding method based on Manchester code will be described with reference to FIG.

  Next, with reference to FIG. 10, points to be noted when using a multilevel signal generated by the above-described new encoding method and technical matters to be addressed by the present embodiment will be described. Next, a configuration of the timing synchronization circuit according to the present embodiment devised to extract data from the multi-level code according to the above-described new method more reliably will be described with reference to FIG. Among these, the signal waveform input to the timing synchronization circuit and the flow of processing executed by the timing synchronization circuit will be described with reference to FIGS.

  Next, referring to FIG. 14 to FIG. 16, the configuration of the timing synchronization circuit according to the present embodiment devised to extract data from the multilevel code according to the above-described new method more reliably, the timing synchronization circuit A supplementary description will be given of the input signal waveform and the flow of processing executed by the timing synchronization circuit. Finally, the technical idea of the present embodiment will be summarized and the effects obtained from the technical idea will be briefly described.

(Description item)
1: Introduction 1-1: Device configuration of mobile terminal 100 adopting parallel transmission method 1-2: Device configuration of mobile terminal 130 adopting serial transmission method 1-3: Functional configuration of mobile terminal 130 according to new method
1-3-1: Encoding method according to AMI code-based multilevel code
1-3-2: Decoding method according to AMI code-based multilevel code
1-3-3: Encoding method according to Manchester code-based multilevel code
1-3-4: Decoding method according to Manchester code-based multilevel code 2: Embodiment 2-1: Configuration of timing synchronization circuit 180
2-1-1: Circuit configuration
2-1-2: Flow of Synchronization Processing 2-2: Configuration of Timing Synchronization Circuit 190
2-2-1: Circuit configuration
2-2-2: Flow of synchronous processing 3: Summary

<1: Introduction>
First, prior to a detailed description of a technique according to an embodiment of the present invention, problems to be solved by the embodiment will be briefly summarized.

[1-1: Device Configuration of Mobile Terminal 100 Employing Parallel Transmission Method]
First, with reference to FIG. 1, a device configuration of the mobile terminal 100 adopting the parallel transmission method will be briefly described. FIG. 1 is an explanatory diagram illustrating an example of a device configuration of a mobile terminal 100 adopting a parallel transmission method. In FIG. 1, a mobile phone is schematically drawn as an example of the mobile terminal 100. However, the scope of application of the technology described below is not limited to mobile phones. For example, the present invention can be applied to an information processing apparatus such as a notebook PC and various portable electronic devices.

  As shown in FIG. 1, a mobile terminal 100 mainly includes a display unit 102, a liquid crystal unit 104 (LCD), a connection unit 106, an operation unit 108, a baseband processor 110 (BBP), and a parallel signal line. 112. However, LCD is an abbreviation for Liquid Crystal Display. Note that the display unit 102 may be referred to as a display side, and the operation unit 108 may be referred to as a main body side. Here, for convenience of explanation, a case where a video signal is transmitted through the parallel signal line 112 is taken as an example. Of course, the type of signal transmitted via the parallel signal line 112 is not limited to this, and examples include a control signal and an audio signal.

  As shown in FIG. 1, the display unit 102 is provided with a liquid crystal unit 104. Then, the video signal transmitted via the parallel signal line 112 is input to the liquid crystal unit 104. The liquid crystal unit 104 displays a video based on the input video signal. The connection unit 106 is a member that connects the display unit 102 and the operation unit 108. The connection member forming the connection unit 106 has a structure that can rotate the display unit 102 180 degrees in the ZY plane, for example. Further, the connection member may be formed so that the display unit 102 can rotate in the XZ plane. In this case, the portable terminal 100 has a structure that can be folded. Note that the connecting member may have a structure that allows the display unit 102 to move in a free direction.

  The baseband processor 110 is an arithmetic processing unit that provides communication control of the portable terminal 100 and an application execution function. The parallel signal output from the baseband processor 110 is transmitted to the liquid crystal unit 104 of the display unit 102 through the parallel signal line 112. A large number of signal lines are wired in the parallel signal line 112. For example, in the case of a mobile phone, the number of signal lines n is about 50. The transmission speed of the video signal is about 130 Mbps when the resolution of the liquid crystal unit 104 is QVGA. The parallel signal line 112 is wired so as to pass through the connection unit 106.

  That is, a large number of signal lines forming the parallel signal line 112 are wired to the connection unit 106. As described above, when the movable range of the connecting portion 106 is expanded, the risk of damage to the parallel signal line 112 due to the movement increases. As a result, the reliability of the parallel signal line 112 is impaired. On the other hand, if the reliability of the parallel signal line 112 is to be maintained, the movable range of the connecting portion 106 is restricted. For these reasons, the serial transmission method is increasingly used in mobile phones and the like for the purpose of achieving both the freedom of the movable member forming the connection portion 106 and the reliability of the parallel signal line 112. Also, serialization of transmission lines is being promoted from the viewpoint of radiated electromagnetic noise (EMI).

[1-2: Device Configuration of Mobile Terminal 130 Employing Serial Transmission Method]
Therefore, with reference to FIG. 2, a device configuration of the mobile terminal 130 adopting the serial transmission method will be briefly described. FIG. 2 is an explanatory diagram showing an example of the device configuration of the mobile terminal 130 adopting the serial transmission method. In FIG. 2, a mobile phone is schematically drawn as an example of the mobile terminal 130. However, the scope of application of the technology described below is not limited to mobile phones. For example, the present invention can be applied to an information processing apparatus such as a notebook PC and various portable electronic devices. Further, constituent elements having substantially the same functions as those of the mobile terminal 100 of the parallel transmission system shown in FIG. 1 are assigned the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 2, the mobile terminal 130 mainly includes a display unit 102, a liquid crystal unit 104 (LCD), a connection unit 106, and an operation unit 108. Further, the mobile terminal 130 includes a baseband processor 110 (BBP), parallel signal lines 132 and 136, a serial signal line 134, a serializer 150, and a deserializer 170.

  Unlike the portable terminal 100 described above, the portable terminal 130 transmits a video signal by a serial transmission method through a serial signal line 134 wired to the connection unit 106. Therefore, the operation unit 108 is provided with a serializer 150 for serializing the parallel signal output from the baseband processor 110. On the other hand, the display unit 102 is provided with a deserializer 170 for parallelizing a serial signal transmitted through the serial signal line 134.

  The serializer 150 converts the parallel signal output from the baseband processor 110 and input via the parallel signal line 132 into a serial signal. The serial signal converted by the serializer 150 is input to the deserializer 170 through the serial signal line 134. When the serial signal is input, the deserializer 170 restores the input serial signal to the original parallel signal. Then, the deserializer 170 inputs a parallel signal to the liquid crystal unit 104 through the parallel signal line 136.

  For example, NRZ data is transmitted to the serial signal line 134 alone, or a data signal and a clock signal are transmitted together. The number k of serial signal lines 134 is significantly smaller than the number n of parallel signal lines 112 included in the mobile terminal 100 of FIG. 1 (1 ≦ k << n). For example, the number k of wirings can be reduced to about several. Therefore, the degree of freedom regarding the movable range of the connecting portion 106 to which the serial signal line 134 is wired is much greater than that of the connecting portion 106 to which the parallel signal line 112 is wired. Further, the serial signal line 134 has high reliability. For the serial signal flowing through the serial signal line 134, a differential signal such as LVDS is usually used. However, LVDS is an abbreviation for Low Voltage Differential Signal.

  The apparatus configuration of the mobile terminal 130 has been briefly described above. The overall device configuration of the mobile terminal 130 adopting the serial transmission method is generally as described above. However, how much the number of signal lines wired to the connection unit 106 can be reduced depends on the form of the signal flowing through the serial signal line 134. The serializer 150 and the deserializer 170 determine the form of this signal. Hereinafter, functional configurations of the serializer 150 and the deserializer 170 according to the above new method will be described.

[1-3: Functional Configuration of Mobile Terminal 130 According to New Method]
Here, the functional configuration of the mobile terminal 130 according to the new method will be described with reference to FIG. FIG. 3 is an explanatory diagram illustrating a functional configuration example of the mobile terminal 130 according to the new method. However, the technical feature of the new system is the data encoding method and the encoded data transmission method. Therefore, only the main functional configuration of the serializer 150 that forms the transmission unit of the mobile terminal 130 and the main functional configuration of the deserializer 170 that forms the reception unit of the mobile terminal 130 are shown in FIG. 3. Therefore, it should be noted that description of other general components is omitted.

  As illustrated in FIG. 3, the serializer 150 mainly includes an encoding unit 152, a driver 154, and a superimposing unit 156. The deserializer 170 mainly includes a separation unit 172, a receiver 174, a clock extraction unit 176, and a decoding unit 178. The serializer 150 and the deserializer 170 are electrically connected through the coaxial cable 160. The coaxial cable 160 is an example of the serial signal line 134.

  When transmission data and a transmission clock are transmitted from the baseband processor 110 to the serializer 150 through the parallel signal line 132, the transmission data and the transmission clock transmitted to the serializer 150 are input to the encoding unit 152. The encoding unit 152 generates a multi-level code from the transmission data using a new encoding method. The multi-level code referred to here is a code representing one bit value with a plurality of amplitude levels. For example, a ternary code in which a bit value 1 is expressed by four values of amplitude levels +3, +1, −1, and −3 and a bit value 0 is expressed by amplitude levels +2 and −2 is an example of the multilevel code.

  The multilevel code generated by the encoding unit 152 is configured such that the polarity (+/−) is inverted every half cycle of the transmission clock. Such a multi-level code can be generated by synchronously adding a transmission clock to a bipolar code or a dicode code such as an AMI code, a Manchester code, or a partial response code, as will be described later. However, in practice, synchronous addition is rarely performed in signal processing. In many cases, a multi-level code is generated directly from transmission data using a table that associates the amplitude level of the signal waveform obtained by synchronously adding the bipolar code and the transmission clock with the bit value of the transmission data. Is done. The multi-level code generated in this way is converted into an appropriate amplitude level by the driver 154 and input to the superimposing unit 156.

  Since the multilevel code generated by the encoding unit 152 is a waveform whose polarity is inverted every half cycle of the transmission clock, it hardly contains a direct current component. Therefore, even if the multi-level code is superimposed on the DC power and transmitted, the multi-level code can be easily separated on the receiving side. Further, by superimposing and transmitting the multi-level code on the DC power source, it is possible to reduce the number of wirings of the connection unit 106 to about one. For such a reason, the superimposing unit 156 is provided in the serializer 150 illustrated in FIG. 3, and the superimposing unit 156 superimposes a DC power source on the multilevel code. A multi-level code (hereinafter, a superimposed signal) on which the DC power is superimposed by the superimposing unit 156 is input to the separating unit 172 through the coaxial cable 160.

  The superimposed signal input to the separation unit 172 through the coaxial cable 160 is separated into a DC power source and a multilevel code by the separation unit 172. The multilevel code separated by the separation unit 172 is input to the clock extraction unit 176 and the decoding unit 178 via the receiver 174. First, in the clock extraction unit 176, a clock component is extracted from the input multilevel code, and the transmission clock is reproduced. As described above, the multilevel code according to the new system has a waveform whose polarity is inverted every half cycle of the transmission clock. Therefore, by detecting the timing at which the amplitude level of the multilevel code crosses zero, the transmission clock can be regenerated from the detection result without using a PLL.

  In this way, the clock extraction unit 176 detects the timing at which the amplitude level of the multilevel code crosses zero using a comparator or the like set to the threshold level 0, and regenerates the transmission clock. In the following description, the transmission clock regenerated by the clock extraction unit 176 is referred to as a detection clock. The detected clock reproduced by the clock extraction unit 176 is output to other components of the display unit 102 and also input to the decoding unit 178. When the multilevel code and the detection clock are input, the decoding unit 178 detects the timing when the amplitude level of the multilevel code exceeds and falls below a predetermined threshold level, and uses the detection result and the detection clock to detect the multilevel code and the detection clock. Each amplitude level of the value code is detected.

  Further, the decoding unit 178 decodes the transmission data based on the detected amplitude level of the multilevel code. The transmission data decoded by the decoding unit 178 is output to other components of the display unit 102 as reception data. As described above, the mobile terminal 130 according to the new method transmits transmission data using a multilevel code in which one bit value is expressed by a plurality of amplitude levels. As described above, this multilevel code has a waveform whose polarity is inverted every half cycle of the clock. Therefore, it is possible to reproduce the clock without using the PLL by extracting the clock component from the multilevel code on the receiving side. As a result, the circuit scale and power consumption can be reduced as much as it is not necessary to provide a PLL on the receiving side.

(1-3-1: Encoding method according to AMI code-based multilevel code)
Here, an encoding method for generating a new multi-level code based on the AMI code will be described with reference to FIGS. 4 and 5. The encoding method described here is realized by the function of the encoding unit 152 in the mobile terminal 130 described above. As described above, the new multilevel code has a signal waveform obtained by synchronously adding a clock to a bipolar code. Here, an AMI code with a duty of 100% is taken as an example of a bipolar code.

(Signal waveform of AMI code)
First, the waveform of the AMI code will be briefly described with reference to FIG. FIG. 4 is an explanatory diagram illustrating an example of a signal waveform of the AMI code. However, A in the figure is an arbitrary positive number.

  The AMI code is a code that expresses a bit value 0 as a potential 0 and a bit value 1 as a potential A or -A. However, the potential A and the potential -A are alternately repeated. That is, after the bit value 1 is expressed after the potential A is expressed by the potential A, the bit value 1 is expressed by the potential -A. FIG. 4 shows an AMI code when bit values 0, 1, 0, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 1 are input at timings T1,. The signal waveform obtained by encoding based on the law is shown.

In the example of FIG. 4, the bit value 1 appears at timings T2, T4, T5, T10, T11, T12, and T14. When the amplitude level of the AMI code is the potential A at the timing T2, the polarity of the amplitude level at the timing T4 is inverted to the potential -A. Similarly, at the timing T5 when the bit value 1 appears next, the amplitude level of the AMI code becomes the potential A. As described above, the AMI code has a polarity inversion characteristic in which the amplitude level corresponding to the bit value 1 is alternately inverted between plus and minus. Note that the amplitude level of the AMI code corresponding to the bit value 0 is all represented by the potential 0.

  As described above, since the AMI code has the polarity inversion characteristic, it has a feature that it does not include a DC component. However, the potential 0 corresponding to the bit value 0 may appear continuously. For example, in the example of FIG. 4, the potential 0 is continuous at timings T6,. If there is a period in which the potential 0 continues in this way, the amplitude level does not change during that period, so that the clock component cannot be extracted from the received waveform of the AMI code without using the PLL. In response to these problems, a method for transmitting data using the multilevel code according to the above-described new scheme has been devised.

(About encoding method)
Here, a method for generating a multi-level code based on an AMI code will be described with reference to FIG. FIG. 5 is an explanatory diagram showing a method for generating a multi-level code based on the AMI code. Although a method for generating a multi-level code by synchronously adding a clock to an AMI code will be described here, a multi-level code is generated from transmission data based on a coding rule that associates bit values 0 and 1 with each amplitude level of the multi-level code. The signal waveform of the value code may be directly generated. In this case, the coding rule is held by the coding unit 152 in the form of a table or the like.

  FIG. 5C shows an AMI code-based multilevel code generated by the new encoding method. In this multi-level code, a bit value 1 is expressed by a plurality of potentials -1, -3, 1, 3 and a bit value 0 is expressed by a plurality of potentials -2, 2 different from these. In addition, this multi-level code is configured such that the amplitude level of the multi-level code is inverted every half cycle of the clock and does not continuously become the same potential. For example, in the example of FIG. 5, there is a period in which the bit value 0 continues at timings T6,..., T9, but the potentials are −2, 2, −2, and 2, and are not continuously the same potential. By using such a multi-level code, it is possible to extract a clock component by detecting the timing at which the amplitude level crosses zero even if the same bit value appears continuously.

  The signal waveform of the multilevel code shown in FIG. 5C is obtained, for example, by synchronously adding the AMI code shown in FIG. 5A and the clock shown in FIG. The signal waveform (A) of the AMI code shown in FIG. 5 is the same signal waveform as the AMI code shown in FIG. The clock shown in FIG. 5B has a frequency Fb / 2 that is half that of the transmission rate of the AMI code when the transmission rate is Fb. The clock (B) has a larger vibration width than the AMI code (A). In the example of FIG. 5, the vibration width of the AMI code (A) is −1 to +1, while the vibration width of the clock (B) is set to −2 to +2. More generally, it is possible to set the amplitude level of the clock (B) to N times (N> 1) the AMI code.

  When the AMI code (A) and the clock (B) shown in FIG. 5 are synchronously added with the edges aligned, the multilevel code shown in FIG. 5C is generated. At this time, since the vibration width of the clock (B) is set to be larger than the vibration width of the AMI code (A), a multi-level code in which one bit value is expressed by a plurality of amplitude levels is generated. For example, when the amplitude level of the AMI code (A) is expressed as A1 and the amplitude level of the clock (B) is expressed as A2, the amplitude level A1 + A2 of the multilevel code (C) is 1 + 2 = 3, 0 + 2 = 2, − The six values are 1 + 2 = 1, 1-2 = −1, 0−2 = −2, and −1-2 = −3. It should also be noted that the amplitude level of the multilevel code (C) reverses in polarity every half cycle of the clock (B).

  As described above, the multilevel code (C) according to the new method is obtained by synchronously adding the AMI code (A) and the clock (B). However, it is also possible to directly generate the multilevel code (C) from the transmission data using a table or the like that directly associates the bit values 0 and 1 with the amplitude level of the multilevel code (C). When such a table or the like is used, for example, bit strings 0, 1, 0, 1, 1, 0,..., 1 are amplitude levels 2, -1, 2, -3, 3, 3, -2, ..., -1 directly. Regardless of which method is used, the bit value 0 of the transmission data is represented by the amplitude levels 2 and -2 of the multilevel code (C), and the bit value 1 is the amplitude level 3, 1, -1, and -3. It is expressed by

  The encoding method related to the new multi-level code (C) generated based on the AMI code (A) has been described above. Next, a method for decoding original data from the multilevel code (C) will be described.

(1-3-2: Decoding method according to AMI code-based multilevel code)
Here, a decoding method related to the AMI code-based multilevel code (C) will be described with reference to FIGS. 5 and 6. Hereinafter, a method of extracting a clock component from the multilevel code (C), a method of detecting each amplitude level from the multilevel code (C), and a method of decoding data from the detected amplitude level will be sequentially described. Note that the clock extraction processing described here is realized by the function of the clock extraction unit 176. The amplitude level detection process and the data extraction process are realized by the function of the decoding unit 178.

(About clock extraction method)
First, referring to FIG. As described above, in the multilevel code (C), the polarity of the amplitude level is inverted every half cycle of the clock. Therefore, the clock extraction unit 176 can extract the clock component by detecting the timing at which the amplitude level of the multilevel code (C) crosses zero using the comparator in which the threshold level TH1 (TH1 = 0) is set. it can. For example, when the multilevel code (C) is compared at the threshold level TH1, the amplitude level of the multilevel code (C) rises at the timing of zero crossing from the bottom to the top and has a pulse that falls at the timing of zero crossing from the top to the bottom. A detection clock is obtained (see FIG. 10). The detection clock obtained in this way is input to the decoding unit 178.

(Amplitude level detection method and data decoding method)
As shown in FIG. 5, the multilevel code (C) according to the new AMI code-based scheme has six amplitude levels 3, 2, 1, −1, −2, and −3. Therefore, in order to detect these amplitude levels, at least four threshold levels are required.

  For example, the threshold level TH3 (TH3 = 2.5) is set near the middle of the amplitude levels 3 and 2, and the threshold level TH2 (TH2 = 1.5) is set near the middle of the amplitude levels 2 and 1. Further, a threshold level TH4 (TH4 = −1.5) is set near the middle of the amplitude levels −1 and −2, and a threshold level TH5 (TH5 = −2.5) is set near the middle of the amplitude levels −2 and -3. Is set. A comparator corresponding to each threshold level is provided, and the timing at which the amplitude level of the multilevel signal (C) crosses each threshold level is detected.

  For example, when the multilevel code (C) is compared at the threshold level TH2, the timing at which the amplitude level of the multilevel code (C) rises from the bottom to the top and crosses from the top to the bottom with respect to the threshold level TH2. A data signal with a pulse falling at is obtained. When the multi-level code (C) is compared at the threshold level TH3, the timing at which the amplitude level of the multi-level code (C) rises from the bottom to the top and crosses from the top to the bottom with respect to the threshold level TH3. A data signal is obtained having a pulse falling at (see FIG. 10).

  Similarly, when the multilevel code (C) is compared at the threshold level TH4, the multilevel code (C) rises at the timing when the amplitude level of the multilevel code (C) crosses from the bottom to the top and crosses from the top to the bottom. A data signal having a pulse falling at the timing is obtained. Then, when the multilevel code (C) is compared at the threshold level TH5, the timing at which the amplitude level of the multilevel code (C) rises from the bottom to the top and crosses from the top to the bottom with respect to the threshold level TH5. A data signal with a pulse falling at is obtained.

  When the data signal is obtained for each threshold level, the decoding unit 178 determines the amplitude level of the multilevel code (C) from the combination of these data signals. For example, when the amplitude level of the data signal corresponding to the threshold level TH3 is 1 at a certain timing, it is determined that the amplitude level of the multilevel code (C) is 3. If the amplitude level of the data signal corresponding to the threshold level TH3 is 0 and the amplitude level of the data signal corresponding to the threshold level TH2 is 1 at a certain timing, it is determined that the amplitude level of the multilevel code (C) is 2. Is done. Furthermore, when the amplitude level of the data signal corresponding to the threshold level TH2 is 0 and the amplitude level of the detection clock is 1 at a certain timing, it is determined that the amplitude level of the multilevel code (C) is 1.

  Similarly, when the amplitude level of the data signal corresponding to the threshold level TH5 is 0 at a certain timing, it is determined that the amplitude level of the multilevel code (C) is −3. Further, when the amplitude level of the data signal corresponding to the threshold level TH5 is 1 and the amplitude level of the data signal corresponding to the threshold level TH4 is 0 at a certain timing, the amplitude level of the multilevel code (C) is −2. Determined. Furthermore, when the amplitude level of the data signal corresponding to the threshold level TH4 is 1 and the amplitude level of the detection clock is 0 at a certain timing, it is determined that the amplitude level of the multilevel code (C) is -1. The determination result of the amplitude level thus obtained is converted into a bit value by the decoding unit 178.

  As described above, the amplitude levels 3, 1, -1, and -3 of the multilevel code (C) correspond to the bit value 1, and the amplitude levels 2 and -2 correspond to the bit value 0. Therefore, in accordance with the determination result, the decoding unit 178 converts the amplitude levels 3, 1, -1, and -3 into the bit value 1, and converts the amplitude levels 2 and -2 into the bit value 0. As a result, transmission data is decoded from the multilevel code (C). The amplitude level detection method and the data decoding method according to the new AMI code-based method are as described above. However, it is assumed here that a multi-level code (C) as shown in FIG. 5C is received on the receiving side assuming an ideal transmission path. Under such assumption, the amplitude level is correctly determined on the receiving side by the above method, and the transmission data is correctly decoded based on the determination result.

  However, in reality, an eye pattern having a shape as shown in FIG. 6 is observed under the influence of a transmission line having a high-frequency cutoff characteristic, a filter circuit, or the like. The characteristic of the eye pattern illustrated in FIG. 6 is a waveform that tapers as the absolute value of the amplitude level increases. For example, it can be seen that the interval L3 at which the threshold level TH3 crosses the amplitude level is smaller than the interval L1 at the point where the amplitude level crosses zero. As shown in FIG. 10, this corresponds to the fact that the pulse width L3 of the data signal obtained by the comparison at the threshold level TH3 is narrower than the pulse width L1 of the detection clock. Although not clearly shown in the figure, the same can be said for the pulse widths L2, L4, and L5 of the data signals corresponding to the threshold levels TH2, TH4, and TH5.

  In the case of such a tapered waveform, the pulse width L3 of the data signal corresponding to the threshold level TH3 is smaller than the pulse width L2 of the data signal corresponding to the threshold level TH2. Similarly, the pulse width L5 of the data signal corresponding to the threshold level TH5 is smaller than the pulse width L4 of the data signal corresponding to the threshold level TH4. That is, the larger the absolute value of the threshold level, the greater the difference between the pulse width of the detection clock and the pulse width of the data signal. If this difference becomes larger than a predetermined value, the amplitude level cannot be correctly extracted from the data signal using either the rising timing or falling timing of the detection clock, resulting in an error in the decoding result of the bit value. End up.

  As described above, in the data transmission method according to the new method, it is assumed that the multilevel code (C) is used. However, the multilevel code (C) has a larger amplitude level vibration width than the binary code such as the AMI code (A). For this reason, when the transmission path is affected by high-frequency cut-off, the multi-level code is more likely to cause errors during decoding than the binary code because it includes an amplitude level having a larger absolute value. As a countermeasure against such a transmission error, a method of reducing the multi-level number of the multi-level code (C), or a method of delaying the detection clock or the data signal to align the pulse edges can be considered.

  However, even if the multi-level number of the multi-level code (C) can be reduced to about four levels, the possibility that an error will occur at the time of decoding is still higher than that of the binary code. Even if it is attempted to align the edge of the detection clock and the edge of the data signal using the delay, it is very difficult to accurately control the delay in the integrated circuit. Furthermore, since the delay timing is affected by subtle fluctuations in the transmission signal, it is difficult to align edges accurately. In view of these problems, the present inventors have devised a timing synchronization circuit for appropriately timing-synchronizing the data signal with the detection clock extracted from the multilevel code (C). By using this timing synchronization circuit, the reliability of data transmission according to the new method can be improved. The configuration and application examples of this timing synchronization circuit will be described later.

(1-3-3: Encoding method according to Manchester code-based multilevel code)
The coding method according to the new system is based on various bipolar codes and dicode codes such as the partial response code, Manchester code, and CMI (Coded Mark Inversion) code in addition to the above AMI code. It is also possible. Accordingly, an encoding method for generating a new multi-level code based on Manchester code will be described with reference to FIGS. The encoding method described here is realized by the function of the encoding unit 152 in the mobile terminal 130 described above.

(Signal waveform of Manchester code)
First, the waveform of the Manchester code will be briefly described with reference to FIG. FIG. 7 is an explanatory diagram illustrating an example of a signal waveform of the Manchester code. However, A in the figure is an arbitrary positive number. The Manchester code is a code that expresses the bit value 0 as a rising waveform from the potential -A to A, and expresses the bit value 1 as a falling waveform from the potential A to -A.

  As an example, FIG. 7 shows a signal waveform obtained by encoding according to the Manchester code rule when bit values 1, 0, 0, 1, 1, 1 are input at timings T1,. Has been. For example, the bit value 1 input at the timings T1, T4, T5, and T6 is represented by a waveform that falls from the potential A to -A. Further, the bit value 0 input at the timings T2 and T3 is expressed by a waveform that rises from the potential −A to A. As described above, the amplitude level of the Manchester code is expressed by a binary value of potential -A or A. On the other hand, the amplitude level of the AMI code described above is expressed by three values of potentials -A, 0, and A. Therefore, there are fewer types of amplitude levels that the Manchester code can take than the AMI code.

(About encoding method)
Next, a method for generating a multi-level code based on Manchester code will be described with reference to FIG. FIG. 8 is an explanatory diagram showing a multi-level code generation method based on Manchester code. Although a method for generating a multi-level code by synchronously adding a clock to a Manchester code will be described here, a multi-level code is generated from transmission data based on a coding rule that associates bit values 0 and 1 with each amplitude level of the multi-level code. The signal waveform of the value code may be directly generated. In this case, the coding rule is held by the coding unit 152 in the form of a table or the like.

  FIG. 8C shows a Manchester code-based multilevel code generated by the new encoding method. This multi-level code expresses a bit value 1 by a change from potential 3 to -3 and a bit value 0 by a change from potential 1 to -1. In addition, this multi-level code is configured such that the amplitude level of the multi-level code is inverted every half cycle of the clock and does not continuously become the same potential. By using such a multilevel code, it is possible to easily extract a clock component by detecting the timing at which the amplitude level crosses zero.

  The signal waveform of the multilevel code shown in FIG. 8C is obtained, for example, by synchronously adding the Manchester code shown in FIG. 8A and the clock shown in FIG. The signal waveform (A) of the Manchester code shown in FIG. 8 is the same signal waveform as that shown in FIG. Further, the clock shown in FIG. 8B has the same frequency Fb as the transmission rate Fb of Manchester code. The clock (B) has a larger vibration width than the Manchester code (A). In the example of FIG. 8, the vibration width of the Manchester code (A) is −1 to +1, while the vibration width of the clock (B) is set to −2 to +2. More generally, it is possible to set the amplitude level of the clock (B) to N times the Manchester code (N> 1).

  When the Manchester code (A) and the clock (B) shown in FIG. 8 are synchronously added with the edges aligned, the multilevel code shown in FIG. 8C is generated. At this time, since the vibration width of the clock (B) is set to be larger than the vibration width of the Manchester code (A), a multi-level code in which one bit value is expressed by a plurality of amplitude levels is generated. For example, if the amplitude level of the Manchester code (A) is expressed as A1, and the amplitude level of the clock (B) is expressed as A2, the amplitude level A1 + A2 of the multilevel code (C) is 1 + 2 = 3, -1 + 2 = 1, The four values are 1-2 = -1 and -1-2 = -3. It should also be noted that the amplitude level of the multilevel code (C) reverses in polarity every half cycle of the clock (B).

  As described above, the multilevel code (C) according to the new method is obtained by synchronously adding the Manchester code (A) and the clock (B). However, it is also possible to directly generate the multilevel code (C) from the transmission data using a table or the like that directly associates the bit values 0 and 1 with the amplitude level of the multilevel code (C). When such a table or the like is used, for example, the bit strings 1, 0, 0, 1, 1, 1 have the amplitude levels (3, -3), (1, -1), (1) of the multilevel code (C). , -1), (3, -3), (3, -3), (3, -3). However, (X, Y) means that amplitude levels X and Y appear successively. Whichever method is used, the bit value 0 of the transmission data is represented by the amplitude level (1, −1) of the multilevel code (C), and the bit value 1 is the amplitude level (3, −3). Expressed.

  The encoding method according to the new multilevel code (C) generated based on the Manchester code (A) has been described above. Next, a method for decoding original data from the multilevel code (C) will be described.

(1-3-4: Decoding method according to Manchester code based multi-level code)
Here, a decoding method related to the Manchester code-based multilevel code (C) will be described with reference to FIGS. 8 and 9. Hereinafter, a method of extracting a clock component from the multilevel code (C), a method of detecting each amplitude level from the multilevel code (C), and a method of decoding data from the detected amplitude level will be sequentially described. Note that the clock extraction processing described here is realized by the function of the clock extraction unit 176. The amplitude level detection process and the data extraction process are realized by the function of the decoding unit 178.

(About clock extraction method)
First, referring to FIG. As described above, in the multilevel code (C), the polarity of the amplitude level is inverted every half cycle of the clock. Therefore, the clock extraction unit 176 can extract the clock component by detecting the timing at which the amplitude level of the multilevel code (C) crosses zero using a comparator in which the threshold level TH1 (TH1 = 0) is set. . For example, when the multilevel code (C) is compared at the threshold level TH1, the amplitude level of the multilevel code (C) rises at the timing of zero crossing from the bottom to the top and has a pulse that falls at the timing of zero crossing from the top to the bottom. A detection clock is obtained. The detection clock obtained in this way is input to the decoding unit 178.

(Amplitude level detection method and data decoding method)
As shown in FIG. 8, the multilevel code (C) according to the new Manchester code-based scheme has four amplitude levels 3, 1, -1, and -3. In order to detect these amplitude levels, at least two threshold levels are required.

  For example, the threshold level TH2 ′ (TH2 ′ = 2) is set near the middle of the amplitude levels 3 and 1, and the threshold level TH3 ′ (TH3 ′ = − 2) is set near the middle of the amplitude levels -3 and -1. The A comparator corresponding to each threshold level is provided, and the timing at which the amplitude level of the multilevel signal (C) crosses each threshold level is detected. Thus, the Manchester code-based multilevel code (C) has a smaller number of multilevels than the AMI code-based multilevel code (C). Therefore, the number of types of threshold levels used for determining the amplitude level is small. Further, the Manchester code-based multilevel code (C) can have a wider interval between the amplitude levels than the AMI code-based multilevel code (C). Therefore, it is difficult for erroneous determination to occur during threshold determination.

  For example, when the multilevel code (C) is compared at the threshold level TH2 ′, the amplitude level of the multilevel code (C) rises from the bottom to the top and crosses from the top to the bottom with respect to the threshold level TH2 ′. A data signal having a pulse that falls at the timing to be obtained is obtained. Further, when the multilevel code (C) is compared at the threshold level TH3 ′, the multilevel code (C) rises with respect to the threshold level TH3 ′ at the timing when the amplitude level of the multilevel code (C) crosses from bottom to top and crosses from top to bottom. A data signal having a pulse that falls at the timing to be obtained is obtained.

  When the data signal is obtained for each threshold level, the decoding unit 178 determines the amplitude level of the multilevel code (C) from the combination of these data signals. For example, when the amplitude level of the data signal corresponding to the threshold level TH2 'is 1 at a certain timing, it is determined that the amplitude level of the multilevel code (C) is 3. If the amplitude level of the data signal corresponding to the threshold level TH2 'is 0 and the amplitude level of the detection clock is 1 at a certain timing, it is determined that the amplitude level of the multilevel code (C) is 1.

  Similarly, when the amplitude level of the data signal corresponding to the threshold level TH3 'is 0 at a certain timing, it is determined that the amplitude level of the multilevel code (C) is -3. If the amplitude level of the data signal corresponding to the threshold level TH3 'is 1 and the amplitude level of the detection clock is 0 at a certain timing, it is determined that the amplitude level of the multilevel code (C) is -1. The determination result of the amplitude level thus obtained is converted into a bit value by the decoding unit 178.

  As described above, the amplitude level (3, -3) of the multilevel code (C) corresponds to the bit value 1 and the amplitude level (1, -1) corresponds to the bit value 0. Therefore, in accordance with the determination result, the decoding unit 178 detects the amplitude level (3, -3) pattern, converts it to the bit value 1, and detects the amplitude level (1, -1) pattern. Convert to bit value 0. As a result, transmission data is decoded from the multilevel code (C). The amplitude level detection method and data decoding method according to the new Manchester code based method are as described above. However, it is assumed here that a multi-level code (C) as shown in FIG. 8C is received on the receiving side assuming an ideal transmission path. Under such assumption, the amplitude level is correctly determined on the receiving side by the above method, and the transmission data is correctly decoded based on the determination result.

  However, in reality, an eye pattern having a shape as shown in FIG. 9 is observed under the influence of a transmission line having a high-frequency cutoff characteristic, a filter circuit, or the like. The eye pattern illustrated in FIG. 9 has a waveform that tapers as the absolute value of the amplitude level increases. For example, paying attention to the threshold level TH2 ', it can be seen that the pulse width L2 of the data signal obtained by the comparison at the threshold level TH2' is smaller than the pulse width L1 of the detection clock.

  Although not clearly shown in the figure, the same can be said for the pulse width L3 of the data signal corresponding to the threshold level TH3 '. If the difference between the pulse widths L1 and L2 (or L3) becomes larger than a predetermined value, the amplitude level cannot be correctly extracted from the data signal using any of the rising timing and falling timing of the detection clock. An error occurs in the decoding result of the bit value. In this regard, the Manchester code-based multilevel code (C) is the same as the above-mentioned AMI code-based multilevel code (C). In order to solve such a problem, the present inventor has devised a timing synchronization circuit that synchronizes the pulse of the data signal and the pulse of the detection clock without using a delay. Hereinafter, the configuration of the timing synchronization circuit and application examples thereof will be described.

<2: Embodiment>
Hereinafter, an embodiment of the present invention will be described. The present embodiment relates to a timing synchronization method for synchronizing a detection clock and a data signal when data is decoded from a multilevel code according to a new method. In particular, the present embodiment provides a timing synchronization circuit that can more reliably synchronize the data signal and the detection clock even when the pulse width of the data signal detected from the multilevel code is narrower than the pulse width of the detection clock. 180 and 190 are proposed.

  Note that timing synchronization circuits 180 and 190, which will be described later, are provided in, for example, the decoding unit 178 included in the mobile terminal 130 described above. The timing synchronization circuit 180 receives a data signal output from a comparator having a positive threshold level. On the other hand, the timing synchronization circuit 190 receives a data signal output from a comparator having a negative threshold level.

[2-1: Configuration of Timing Synchronization Circuit 180]
First, the configuration of the timing synchronization circuit 180 according to the present embodiment will be described with reference to FIGS. FIG. 11 is an explanatory diagram showing a circuit configuration example of the timing synchronization circuit 180 according to the present embodiment. FIG. 12 is an explanatory diagram illustrating a method of extracting the detection clock (CLK) and the data signal (DATA) from the multilevel code using a positive threshold level. FIG. 13 is an explanatory diagram showing the input / output signals of each component constituting the timing synchronization circuit 180 and the contents of signal processing executed by each component.

(2-1-1: Circuit configuration)
First, referring to FIG. As shown in FIG. 11, the timing synchronization circuit 180 includes sequential circuits 182, 184, 188 and an exclusive OR circuit 186. As the sequential circuits 182, 184, and 188, for example, D flip-flop circuits are used.

  First, a data signal is input to the CLK terminal of the sequential circuit 182. As shown in FIG. 12, this data signal has a pulse that rises when the amplitude level of the received multilevel code crosses a predetermined threshold level from the bottom to the top and falls when the crossing from the top to the bottom. Further, as described above, the pulse width of the data signal is narrower than the pulse width of the detection clock. The purpose of providing the timing synchronization circuit 180 is to ensure that data can be reliably extracted from a data signal having a narrow pulse width in synchronization with the detection clock.

  As described above, the data signal is input to the CLK terminal of the sequential circuit 182. Further, the signal output from the Q terminal of the sequential circuit 182 is inverted in polarity and input to the D terminal of the sequential circuit 182. Therefore, when a data signal (see “DATA” in FIG. 13) is input to the CLK terminal of the sequential circuit 182, a toggle signal (“TOGGLE_DATA in FIG. 13) that toggles from the Q terminal of the sequential circuit 182 at the rising timing of the data signal. Is output). The toggle signal output from the Q terminal of the sequential circuit 182 is input to the D terminal of the sequential circuit 184 and the exclusive OR circuit 186.

  In addition, a detection clock whose polarity is inverted is input to the CLK terminal of the sequential circuit 184. As shown in FIG. 12, this detection clock has a pulse that rises when the amplitude level of the received multilevel code zero-crosses from bottom to top and falls when it crosses from top to bottom. Thus, the sequential circuit 184 receives the detection clock whose polarity is inverted to the CLK terminal and the toggle signal to the D terminal. Therefore, a toggle synchronization signal (see “TOGGLE_SYN” in FIG. 13) obtained by synchronizing the toggle signal with the falling timing of the detection clock is output from the Q terminal of the sequential circuit 184. The toggle synchronization signal output from the Q terminal of the sequential circuit 184 is input to the exclusive OR circuit 186.

  As described above, the exclusive OR circuit 186 receives the toggle signal output from the Q terminal of the sequential circuit 182 and the toggle synchronization signal output from the Q terminal of the sequential circuit 184. The exclusive OR circuit 186 calculates an exclusive OR between the toggle signal and the toggle synchronization signal, and outputs it as an intermediate output signal (see “MID_OUT” in FIG. 13). The intermediate output signal output from the exclusive OR circuit 186 is input to the D terminal of the sequential circuit 188. In addition, a detection clock whose polarity is inverted is input to the CLK terminal of the sequential circuit 188. Therefore, a synchronous data signal (see “DATA_SYN” in FIG. 13) obtained by synchronizing the intermediate output signal with the falling timing of the detection clock is output from the Q terminal of the sequential circuit 188.

  The circuit configuration of the timing synchronization circuit 180 according to the present embodiment and the operation of each component have been described above. By providing the timing synchronization circuit 180, a synchronization data signal as shown in FIG. 13 can be obtained. As is apparent from FIG. 13, the synchronous data signal is synchronized with the falling timing of the detection clock. Therefore, data can be reliably extracted from the synchronous data signal using the falling timing of the detection clock.

(2-1-2: Flow of synchronization processing)
Here, a flow of timing synchronization processing between the data signal and the detection clock in the timing synchronization circuit 180 will be briefly described with reference to FIG.

  As shown in FIG. 13, first, the detection clock (CLK) and the data signal (DATA) extracted from the multilevel signal are input to the timing synchronization circuit 180. Then, a toggle signal (TOGGLE_DATA) that toggles at the rising timing (T1, T2) of the input data signal is generated. Next, a toggle synchronization signal (TOGGLE_SYS) is generated by synchronizing the toggle signal with the falling timing (S1, S2) of the detection clock. Next, an exclusive OR is calculated between the toggle signal and the toggle synchronization signal, and an intermediate output signal (MID_OUT) is generated. Further, the synchronization data signal (DATA_SYN) is generated by synchronizing the intermediate output signal with the falling timing of the detection clock.

  The flow of timing synchronization processing in the timing synchronization circuit 180 has been described above. By such timing synchronization processing, a synchronous data signal synchronized with the falling timing of the detection clock is generated. Therefore, data can be reliably extracted from the synchronous data signal based on the falling timing of the detection clock.

[2-2: Configuration of Timing Synchronization Circuit 190]
Next, the configuration of the timing synchronization circuit 190 according to the present embodiment will be described with reference to FIGS. FIG. 14 is an explanatory diagram showing a circuit configuration example of the timing synchronization circuit 190 according to the present embodiment. FIG. 15 is an explanatory diagram illustrating a method of extracting the detection clock (CLK) and the data signal (DATA) from the multilevel code using a negative threshold level. FIG. 16 is an explanatory diagram showing the input / output signals of each component constituting the timing synchronization circuit 190 and the contents of signal processing executed by each component.

(2-2-1: Circuit configuration)
First, referring to FIG. As shown in FIG. 14, the timing synchronization circuit 190 includes sequential circuits 192, 194, 198 and an exclusive OR circuit 196. As the sequential circuits 192, 194, 198, for example, D flip-flop circuits are used.

  First, the inverted data signal is input to the CLK terminal of the sequential circuit 192. As shown in FIG. 15, the data signal has a pulse that rises when the amplitude level of the received multilevel code crosses a predetermined threshold level from the bottom to the top and falls when the amplitude level crosses from the top to the bottom. However, since the pulse is threshold-determined with a negative threshold level, it should be noted that the level is 0 (Low) in the data section and the level is 1 (High) in the non-data section. Further, as described above, the pulse width of the data signal is narrower than the pulse width of the detection clock. The purpose of providing the timing synchronization circuit 190 is to ensure that data can be reliably extracted from a data signal having a narrow pulse width in synchronization with the detection clock.

  As described above, the inverted data signal is input to the CLK terminal of the sequential circuit 192. Further, the signal output from the Q terminal of the sequential circuit 192 is inverted in polarity and input to the D terminal of the sequential circuit 192. Therefore, when a data signal whose polarity has been inverted (see “inverted data signal” in FIG. 16) is input to the CLK terminal of the sequential circuit 192, the toggle is performed at the rising timing of the inverted data signal from the Q terminal of the sequential circuit 192. A toggle signal (see “TOGGLE_DATA” in FIG. 16) is output. The toggle signal output from the Q terminal of the sequential circuit 192 is input to the D terminal of the sequential circuit 194 and the exclusive OR circuit 196.

  A detection clock is input to the CLK terminal of the sequential circuit 194. As shown in FIG. 15, this detection clock has a pulse that rises when the amplitude level of the received multilevel code zero-crosses from bottom to top and falls when it crosses from top to bottom. Thus, in the sequential circuit 194, the detection clock is input to the CLK terminal and the toggle signal is input to the D terminal. Therefore, a toggle synchronization signal (see “TOGGLE_SYN” in FIG. 16) obtained by synchronizing the toggle signal with the rising timing of the detection clock is output from the Q terminal of the sequential circuit 194. The toggle synchronization signal output from the Q terminal of the sequential circuit 194 is input to the exclusive OR circuit 196.

  As described above, the exclusive OR circuit 196 receives the toggle signal output from the Q terminal of the sequential circuit 192 and the toggle synchronization signal output from the Q terminal of the sequential circuit 194. In the exclusive OR circuit 196, an exclusive OR between the toggle signal and the toggle synchronization signal is calculated and output as an intermediate output signal (see “MID_OUT” in FIG. 16). The intermediate output signal output from the exclusive OR circuit 196 is input to the D terminal of the sequential circuit 198. A detection clock is input to the CLK terminal of the sequential circuit 198. Therefore, a synchronous data signal (see “DATA_SYN” in FIG. 16) obtained by synchronizing the intermediate output signal with the rising timing of the detection clock is output from the Q terminal of the sequential circuit 198.

  The circuit configuration of the timing synchronization circuit 190 according to the present embodiment and the operation of each component have been described above. By providing the timing synchronization circuit 190, a synchronization data signal as shown in FIG. 16 can be obtained. As is apparent from FIG. 16, the synchronous data signal is synchronized with the rising timing of the detection clock. Therefore, data can be reliably extracted from the synchronous data signal using the rising timing of the detection clock.

(2-2-2: Flow of synchronization processing)
Here, a flow of timing synchronization processing between the data signal and the detection clock in the timing synchronization circuit 190 will be briefly described with reference to FIG.

  As shown in FIG. 16, first, the detection clock (CLK) extracted from the multilevel signal and the data signal (inverted data signal) whose polarity has been inverted are input to the timing synchronization circuit 190. Then, a toggle signal (TOGGLE_DATA) that toggles at the rising timing (T1, T2) of the input inverted data signal is generated. Next, a toggle synchronization signal (TOGGLE_SYS) is generated by synchronizing the toggle signal with the rising timing (S1, S2) of the detection clock. Next, an exclusive OR is calculated between the toggle signal and the toggle synchronization signal, and an intermediate output signal (MID_OUT) is generated. Furthermore, a synchronous data signal (DATA_SYN) is generated by synchronizing the intermediate output signal with the rising timing of the detection clock.

  The flow of timing synchronization processing in the timing synchronization circuit 190 has been described above. By such timing synchronization processing, a synchronous data signal synchronized with the rising timing of the detection clock is generated. Therefore, data can be reliably extracted from the synchronous data signal based on the rising timing of the detection clock.

  The embodiment of the present invention has been described above. By applying the timing synchronization method according to the present embodiment, even when the pulse width of the data signal is narrower than the pulse width of the detection clock, the data of the data signal is reliably synchronized with the rising edge or falling edge of the detection clock. Can be extracted. As a result, even if the multi-level code according to the above-mentioned new method is used for data transmission, it is possible to reduce the probability that a transmission error will occur due to the influence of the high-frequency cutoff of the transmission line, etc. Quality is improved.

<3: Summary>
Finally, the functional configuration of the signal processing apparatus of the present embodiment and the operational effects obtained by the functional configuration will be briefly summarized. The signal processing device can be mounted on, for example, a mobile phone such as the mobile terminal 130, a mobile game machine, a notebook PC, a mobile information terminal, or the like. Moreover, like the above-mentioned portable terminal 130, it is suitably used for an electronic device that includes constituent elements of a transmission unit and a reception unit corresponding to the serializer 150 and the deserializer 170 and includes a configuration for transmitting data between them. It is done.

  The functional configuration of the information processing apparatus described above can be expressed as follows. The signal processing apparatus includes a signal receiving unit, a clock recovery unit, a pulse signal generation unit, a signal synchronization unit, and a data extraction unit as described below. In addition, said signal receiving part respond | corresponds to the isolation | separation part 172 and the receiver 174 in said portable terminal 130, for example. The clock recovery unit corresponds to, for example, the clock extraction unit 176 in the mobile terminal 130 described above. Further, the pulse signal generation unit, the signal synchronization unit, and the data extraction unit correspond to, for example, the decoding unit 178 in the mobile terminal 130 described above.

  The signal receiving unit receives a multi-value signal having a signal waveform obtained by synchronously adding a transmission signal and a clock and having a polarity inverted every half cycle of the clock. The clock recovery unit detects a timing at which the amplitude level of the multilevel signal received by the signal reception unit crosses zero, and regenerates the clock based on the detection result. Thus, by using a signal whose polarity is inverted every half cycle of the clock for data transmission, it is possible to regenerate the clock from the received signal without using a PLL. Further, since the signal waveform obtained by synchronously adding the data signal and the clock contains almost no direct current component, it can be transmitted by being superimposed on a DC power source or the like. As a result, the signal lines and power supply lines used for data transmission can be combined into a single line, and the number of wirings can be reduced.

  The data signal generation unit rises at a timing at which the amplitude level of the multilevel signal received by the signal receiving unit crosses from the bottom to the top, and the threshold level set between the amplitude levels of the multilevel signal. A data signal having a pulse that falls at the timing of crossing down is generated. The multilevel signal has a signal waveform in which one bit value is expressed by a plurality of amplitude levels. Therefore, on the receiving side, it is necessary to determine each amplitude level of the received multilevel signal and decode data of the data signal based on the determination result. Therefore, the data signal generation unit performs threshold determination based on a threshold level set in advance between amplitude levels. Further, as a result of the threshold determination, the data signal generation unit outputs a data signal in which a period exceeding the threshold level is expressed as a pulse high level and a period below the pulse level is expressed as a pulse low level. A data signal is output for each threshold level.

  The data signal for each threshold level generated by the data signal generation unit as described above is input to the signal synchronization unit. As described above, the pulse width of the data signal obtained from the multilevel signal affected by the high-frequency cutoff in the transmission line or the filter circuit is narrower than the pulse width of the clock. When the difference in pulse width is greater than or equal to a predetermined value, it is difficult to correctly extract data even if data is extracted from the data signal based on the rising or falling timing of the clock. Therefore, in the present embodiment, the signal synchronization unit is provided to synchronize the data signal generated by the data signal generation unit and the clock recovered by the clock recovery unit. At this time, a synchronous data signal is output from the signal synchronization unit and input to the data extraction unit. The data extracting unit extracts data from the synchronized data signal generated by the signal synchronizing unit based on the clock reproduced by the clock reproducing unit. Since the synchronous data signal is synchronized with the clock, the data extraction unit correctly extracts the data.

  However, ingenuity is required to synchronize the data signal and the clock. For example, a method of synchronizing by delaying a data signal or a clock is conceivable, but it is difficult to accurately control the delay in the integrated circuit. Therefore, the inventor of the present invention has devised the following timing synchronization method as the configuration of the signal synchronization unit. The signal synchronization unit according to this timing synchronization method mainly includes the following toggle signal generation unit, toggle synchronization signal generation unit, exclusive OR circuit, and synchronization data signal generation unit.

  The toggle signal generation unit generates a toggle signal that toggles at the timing when the pulse of the data signal rises or falls. Further, the toggle synchronization signal generation unit generates a toggle synchronization signal by synchronizing the toggle signal generated by the toggle signal generation unit with the falling or rising timing of the clock. Further, the exclusive OR circuit outputs an exclusive OR of the toggle signal generated by the toggle signal generation unit and the toggle synchronization signal generated by the toggle synchronization signal generation unit. The synchronous data signal generation unit generates the synchronous data signal by synchronizing the output signal of the exclusive OR circuit with the falling or rising timing of the clock.

  Such a function of the signal synchronization unit is realized by the following timing synchronization circuit. The timing synchronization circuit receives a toggle circuit that toggles an input signal at a rising or falling timing, a clock and an output signal of the toggle circuit, and outputs the output signal of the toggle circuit at a rising or falling timing of the clock. A first synchronization circuit to be synchronized, an exclusive OR circuit that receives an output signal of the toggle circuit and an output signal of the first synchronization circuit, and outputs an exclusive OR of both of the input output signals; A clock and an output signal of the exclusive OR circuit are input, and the output signal is configured by a second synchronization circuit that synchronizes the output signal with the falling or rising timing of the clock.

  The toggle circuit corresponds to the sequential circuits 182 and 192 of the timing synchronization circuits 180 and 190 described above. The first synchronization circuit corresponds to the sequential circuits 184 and 194 of the timing synchronization circuits 180 and 190 described above. The exclusive OR circuit corresponds to the exclusive OR circuits 186 and 196 of the timing synchronization circuits 180 and 190 described above. Further, the second synchronization circuit corresponds to the sequential circuits 188 and 198 of the timing synchronization circuits 180 and 190 described above.

  Further, the data extraction unit is configured to sample the amplitude level of the synchronous data signal at the falling or rising timing of the clock reproduced by the clock reproduction unit, and extract data based on the sampling result. May be. For a data signal generated using a positive threshold level as a criterion, a synchronous data signal synchronized with the clock fall timing is obtained. Therefore, the amplitude level of the synchronous data signal is determined based on the clock fall timing. It is sampled (see FIG. 13). On the other hand, for a data signal generated with a negative threshold level as a criterion, a synchronous data signal synchronized with the clock rising timing is obtained, so that the amplitude level of the synchronous data signal is based on the clock rising timing. It is sampled (see FIG. 16).

  The data signal generation unit will be specifically described. The data signal generation unit includes a plurality of comparators for generating a plurality of the data signals corresponding to the plurality of threshold levels. Further, the signal synchronization unit is provided in each comparator included in the data signal generation unit. The data extraction unit extracts data based on the synchronization data signal for each threshold level generated by the signal synchronization unit provided in each comparator. As described above, the signal synchronization unit is provided for each comparator corresponding to each threshold level, and outputs a synchronization data signal corresponding to each data signal. The configuration of the signal synchronization unit corresponding to the positive threshold level (for example, the timing synchronization circuit 180) is slightly different from the configuration of the signal synchronization unit corresponding to the negative threshold level (for example, the timing synchronization circuit 190). Please be careful.

  Further, the signal synchronization unit may be provided only in a comparator corresponding to the threshold level having a large absolute value among the plurality of comparators. As described above, the difference between the pulse width of the data signal and the pulse width of the clock increases as the absolute value of the threshold level increases. Therefore, an error is likely to occur in the determination value of the amplitude level having a large absolute value. On the other hand, in order to reduce power consumption and circuit scale as much as possible, it is advantageous to provide signal synchronization units only for some of the comparators instead of providing signal synchronization units for all the comparators. In such a case, for the reason described above, it is preferable to provide a signal synchronization unit preferentially for a comparator having a threshold value having a large absolute value.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  For example, in the above description, the multi-level code of the new system based on the AMI code and the Manchester code is taken as an example, but the multi-level code based on the partial response code having the same characteristics as the AMI code is also used. The technique of this embodiment can be applied. Moreover, it is expressed by PR (1, -1), PR (1, 0, -1), PR (1, 0, 0, -1), PR (1, 0, ..., 0, -1), etc. It can be applied to various partial response codes.

DESCRIPTION OF SYMBOLS 100,130 Mobile terminal 102 Display part 104 Liquid crystal part 106 Connection part 108 Operation part 110 Baseband processor 112,132,136 Parallel signal line 134 Serial signal line 150 Serializer 152 Encoding part 154 Driver 156 Superimposition part 160 Coaxial cable 170 Deserializer 172 Separator 174 Receiver 176 Clock extractor 178 Decoder 180, 190 Timing synchronization circuit 182, 184, 188, 192, 194, 198 Sequential circuit 186, 196 Exclusive OR circuit

Claims (8)

A signal receiving unit that has a signal waveform obtained by synchronously adding a transmission signal and a clock, and that receives a multilevel signal whose polarity is inverted every half cycle of the clock;
A clock recovery unit that detects a timing at which the amplitude level of the multilevel signal received by the signal reception unit crosses zero, and regenerates the clock based on the detection result;
The threshold level set between the amplitude levels of the multilevel signal rises at the timing when the amplitude level of the multilevel signal received by the signal receiver crosses from bottom to top, and falls at the timing of crossing from top to bottom. A data signal generator for generating a data signal having a pulse;
A signal synchronization unit that generates a synchronization data signal by synchronizing the data signal generated by the data signal generation unit and the clock recovered by the clock recovery unit;
A data extraction unit for extracting data from the synchronous data signal generated by the signal synchronization unit based on the clock reproduced by the clock reproduction unit;
With
The signal synchronizer is
A toggle signal generator for generating a toggle signal that toggles at a timing when the pulse of the data signal rises or falls;
A toggle synchronization signal generation unit that generates a toggle synchronization signal by synchronizing the toggle signal generated by the toggle signal generation unit with the falling or rising timing of the clock;
An exclusive OR circuit that outputs an exclusive OR of the toggle signal generated by the toggle signal generation unit and the toggle synchronization signal generated by the toggle synchronization signal generation unit;
A synchronous data signal generator for generating the synchronous data signal by synchronizing the output signal of the exclusive OR circuit with the falling or rising timing of the clock;
Including a signal processing apparatus.   2. The data extraction unit according to claim 1, wherein the data extraction unit samples the amplitude level of the synchronous data signal at the falling or rising timing of the clock reproduced by the clock reproduction unit, and extracts data based on the sampling result. Signal processing device. The data signal generation unit has a plurality of comparators for generating a plurality of the data signals corresponding to a plurality of the threshold levels,
The signal synchronization unit is provided in each comparator included in the data signal generation unit,
The signal processing apparatus according to claim 2, wherein the data extraction unit extracts data based on a synchronization data signal for each threshold level generated by the signal synchronization unit provided in each comparator.   The signal processing device according to claim 3, wherein the signal synchronization unit is provided in a comparator corresponding to the threshold level having a large absolute value among the plurality of comparators. A toggle circuit that toggles the input signal at the rising or falling timing;
A first synchronization circuit that receives a clock and an output signal of the toggle circuit, and synchronizes the output signal of the toggle circuit with the rising or falling timing of the clock;
An exclusive OR circuit that receives the output signal of the toggle circuit and the output signal of the first synchronization circuit, and outputs an exclusive OR of both of the input output signals;
A second synchronization circuit that receives the clock and an output signal of the exclusive OR circuit, and synchronizes the output signal with the falling or rising timing of the clock;
A timing synchronization circuit comprising: The clock has a signal waveform obtained by synchronously adding the transmission signal and the clock, and is reproduced based on the timing at which the amplitude level of the multilevel signal whose polarity is inverted every half cycle of the clock is zero-crossed. Clock
The input signal is determined based on a threshold level set between the amplitude levels of the multilevel signal as a threshold, and rises when the threshold level is exceeded and rises when the level is below the threshold level. A pulse signal that falls,
6. The timing synchronization circuit according to claim 5, wherein an output signal of the second synchronization circuit is used for extracting data of the data signal using the clock. A signal receiving step for receiving a multi-value signal having a signal waveform obtained by synchronously adding a transmission signal and a clock, and having a polarity inverted every half cycle of the clock;
Detecting a timing at which the amplitude level of the multilevel signal received in the signal reception step crosses zero, and regenerating the clock based on the detection result; and
The threshold level set between the amplitude levels of the multilevel signal rises when the amplitude level of the multilevel signal received in the signal receiving step crosses from bottom to top, and falls when the amplitude level crosses from top to bottom. A data signal generation step for generating a data signal having a pulse;
A signal synchronization step of generating a synchronous data signal by synchronizing the data signal generated in the data signal generation step and the clock recovered in the clock recovery step;
A data extraction step of extracting data from the synchronized data signal generated in the signal synchronization step based on the clock recovered in the clock recovery step;
Have
The signal synchronization step includes
A toggle signal generating step for generating a toggle signal that toggles at a timing when the pulse of the data signal rises or falls;
A toggle synchronization signal generation step for generating a toggle synchronization signal by synchronizing the toggle signal generated in the toggle signal generation step with the falling or rising timing of the clock;
An exclusive OR calculation step of calculating an exclusive OR of the toggle signal generated in the toggle signal generation step and the toggle synchronization signal generated in the toggle synchronization signal generation step;
A synchronous data signal generation step of generating the synchronous data signal by synchronizing the calculation result of the exclusive OR calculation step with the falling or rising timing of the clock;
Including a signal processing method. Toggle step to toggle input signal at rising or falling timing;
A first synchronization step that takes a clock and the output of the toggle step as inputs, and synchronizes the output of the toggle step with the rising or falling timing of the clock;
An exclusive OR calculation step of calculating an exclusive OR of both of the inputted outputs, with the output of the toggle step and the output of the first synchronization step as inputs.
A second synchronization step in which the output of the clock and the exclusive OR calculation step is input, and the output is synchronized with the falling or rising timing of the clock;
Including a timing synchronization method.

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