JP2011100871A - Wiring board, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board high in the degree of freedom of a wire layout, and capable of transmitting a signal in high quality. <P>SOLUTION: First and second wires 11, 12 crossing each other are formed on this wiring board. In this case, the first wire 11 is formed in a first layer in a crossing region AR1, and formed in the first layer, a second layer lower than the first layer, and a third layer between the first and second layers in peripheral regions AR2. The second wire 12 is formed in the second layer in the crossing region AR1, and formed in the first layer, the second layer and the third layer in the peripheral regions AR2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a wiring board and an electronic device using the wiring board.

Wiring is formed in various shapes and arrangements on a wiring board on which electronic components such as semiconductor elements are mounted. In a wiring board, different wirings are often arranged so as to cross each other.
As a method of crossing, for example, a method in which different wirings are formed in separate layers in the wiring board and crossed, or, in a different wiring formed in the same layer in the wiring board, one of the regions where the wiring crosses There is known a method of bypassing only the wiring of the above to another layer.

  There is also known a method of providing a cross-linking structure straddling one wiring and forming another wiring on the cross-linking structure so as to cross the one wiring.

JP-A-5-48306

Providing a part where wirings intersect in the wiring board is preferable in terms of increasing the degree of freedom of wiring layout.
On the other hand, the wiring board has a small wiring width and a long wiring length depending on the type of electronic components such as semiconductor elements mounted thereon, the layout of such electronic components, the layout of the external connection terminals of the wiring board, and the like. May be formed. In such a wiring having a small wiring width and a wiring having a long wiring length, the quality and strength of a signal transmitted through the wiring may be deteriorated.

  According to an aspect of the present invention, a first layer, a second layer, and a third layer between the first layer and the second layer are formed in the first region in the first layer, The second region around the first region intersects the first wiring formed in the first layer, the second layer, and the third layer, and intersects the first wiring in the first region. Then, there is provided a wiring board formed on the second layer, and including the second wiring formed on the first layer, the second layer, and the third layer in the second region.

  According to the disclosed wiring board, the degree of freedom of wiring layout can be increased, and further, deterioration of signals transmitted through the wiring can be suppressed.

It is a principal part perspective schematic diagram which shows an example of wiring. It is a principal part cross-sectional schematic diagram which shows an example of wiring. It is FIG. (1) which shows another structural example of wiring. FIG. 11 is a second diagram illustrating another configuration example of wiring; It is a principal part perspective schematic diagram which shows another example of wiring. It is a principal part cross-sectional schematic diagram which shows another example of wiring. It is a plane schematic diagram of an example of an electronic device. It is a principal part perspective schematic diagram of the wiring which concerns on 1st Example. FIG. 9 is a schematic cross-sectional view (No. 1) of relevant parts in FIG. 8. FIG. 9 is a schematic sectional view (No. 2) of relevant parts in FIG. 8. It is explanatory drawing of an example of a 1st groove | channel formation process. It is explanatory drawing of an example of a 1st embedding process. It is explanatory drawing of an example of a 2nd groove | channel formation process. It is explanatory drawing of an example of a 2nd embedding process. It is explanatory drawing of an example of the external connection terminal formation process. It is explanatory drawing of an example of the semiconductor element connection terminal formation process. It is a principal part cross-section schematic diagram of an example of an electronic device. It is a figure which shows an example of the relationship between the frequency of a wiring board, and the transmittance | permeability. It is a principal part perspective schematic diagram of the wiring which concerns on 2nd Example. FIG. 20 is a schematic cross-sectional view (No. 1) of relevant parts in FIG. 19. FIG. 20 is a schematic cross-sectional view (No. 2) of relevant parts in FIG. 19.

  FIG. 1 is a schematic perspective view of an essential part showing an example of wiring. 2A and 2B are schematic cross-sectional views of the main part showing an example of wiring, where FIG. 2A is a schematic cross-sectional view taken along the line X1-X1 in FIG. 1, and FIG.

  FIG. 1 schematically shows a region where the first and second wirings 11 and 12 intersect (intersection region AR1) and a part of the peripheral region (peripheral region AR2). In FIG. 1, the illustration of the insulating layers (the first, second and third insulating layers 21, 22, and 23 shown in FIG. 2) formed around the first and second wirings 11 and 12 is omitted. is doing.

  The first and second wirings 11 and 12 are wirings in the wiring board formed using, for example, a conductive material such as copper or aluminum. The first and second wirings 11 and 12 may be signal lines, both may be ground lines, or one may be a signal line and the other may be a ground line.

1 and 2 exemplify the case where the first and second wirings 11 and 12 are formed across the three layers of the first, second, and third layers L1, L2, and L3 that are stacked. is doing.
The first wiring 11 includes an upper layer portion 11a formed in the first insulating layer 21 of the first layer L1, a lower layer portion 11b formed in the second insulating layer 22 of the second layer L2, and the first layer L1. The conductor part 11c formed in the 3rd insulating layer 23 of the 3rd layer L3 provided between the 2nd layers L2 is included. The second wiring 12 includes an upper layer portion 12a formed in the first insulating layer 21 of the first layer L1, a lower layer portion 12b formed in the second insulating layer 22 of the second layer L2, and a third layer L3. The conductor part 12c formed in the 3rd insulating layer 23 is included.

Here, as shown in FIGS. 1 and 2A, the upper layer portion 11a of the first wiring 11 is continuously formed on the first layer L1 of both the intersection region AR1 and the peripheral region AR2. Yes.
As shown in FIGS. 1 and 2A, the lower layer portion 11b of the first wiring 11 is not formed in the second layer L2 of the intersection region AR1, but is formed in the second layer L2 of the peripheral region AR2. Yes. In the second layer L2 of the intersection area AR1, the lower layer portion 12b of the second wiring 12 that intersects the first wiring 11, and the lower layer portion 12b of the second wiring 12 and the lower layer portion 11b of the first wiring 11 are electrically connected. There is a second insulating layer 22 to be separated.

  As shown in FIGS. 1 and 2A, the conductor portion 11c of the first wiring 11 reaches both the upper layer portion 11a and the lower layer portion 11b, and connects the third layer of the peripheral region AR2 so as to connect them. L3 is formed. The third insulating layer 23 exists in the third layer L3 in the intersection area AR1.

  The upper layer portion 11a and the lower layer portion 11b of the first wiring 11 are formed on the first layer L1 and the second layer L2 so as to extend in parallel to each other. Moreover, the conductor part 11c of the 1st wiring 11 can be formed as a layered conductor layer extended in parallel with the upper layer part 11a and the lower layer part 11b, for example.

  On the other hand, as shown in FIG. 1 and FIG. 2B, the upper layer portion 12a of the second wiring 12 is not formed in the first layer L1 of the intersection region AR1, but is formed in the first layer L1 of the peripheral region AR2. Has been. In the first layer L1 of the intersecting area AR1, the upper layer portion 11a of the first wiring 11 intersecting the second wiring 12, and the upper layer portion 11a of the first wiring 11 and the upper layer portion 12a of the second wiring 12 are electrically connected. There is a first insulating layer 21 to be separated.

As shown in FIGS. 1 and 2B, the lower layer portion 12b of the second wiring 12 is formed continuously in the second layer L2 of both the intersection region AR1 and the peripheral region AR2.
As shown in FIGS. 1 and 2B, the conductor portion 12c of the second wiring 12 reaches both the upper layer portion 12a and the lower layer portion 12b, and connects the third layer of the peripheral region AR2 so as to connect them. L3 is formed. The third insulating layer 23 exists in the third layer L3 in the intersection area AR1.

  The upper layer portion 12a and the lower layer portion 12b of the second wiring 12 are formed on the first layer L1 and the second layer L2 so as to extend in parallel to each other. Moreover, the conductor part 12c of the 2nd wiring 12 can be formed as a layered conductor layer extended in parallel with the upper layer part 12a and the lower layer part 12b, for example.

  Thus, in the first wiring 11, only the upper layer portion 11a is formed in the intersection region AR1 among the upper layer portion 11a, the lower layer portion 11b, and the conductor portion 11c, and the upper layer portion 11a and the lower layer portion 11b are formed in the peripheral region AR2. And the conductor part 11c is formed. Then, the lower layer portion 12b of the second wiring 12 is formed so as to intersect the first wiring 11 in the second layer L2 of the intersection region AR1 where the lower layer portion 11b is not formed.

  Of the upper layer portion 12a, the lower layer portion 12b, and the conductor portion 12c, the second wiring 12 includes only the lower layer portion 12b in the intersection region AR1, and the upper layer portion 12a, the lower layer portion 12b, and the conductor portion in the peripheral region AR2. 12c is formed. The upper layer portion 11a of the first wiring 11 is formed so as to intersect the second wiring 12 in the first layer L1 of the intersection region AR1 where the upper layer portion 12a is not formed.

  Thus, in the intersection region AR1, the first and second wirings 11 and 12 are each one layer of the upper layer portion 11a and the lower layer portion 12b. In the peripheral area AR2, the first wiring 11 includes an upper layer part 11a and a lower layer part 11b connected by a conductor part 11c, and the second wiring 12 includes an upper layer part 12a and a lower layer part 12b connected by a conductor part 12c. . By configuring the intersecting first and second wirings 11 and 12 as described above, an effective wiring cross-sectional area can be increased.

Here, for comparison, another configuration example of the wiring will be described with reference to FIGS.
3A and 3B are diagrams showing another configuration example of wiring, in which FIG. 3A is a schematic perspective view, FIG. 3B is a schematic cross-sectional view taken along the line X3-X3 in FIG. It is a cross-sectional schematic diagram.

  In FIG. 3, the first wiring 111 is formed in the first insulating layer 21 of the first layer L1, and the second wiring 112 intersecting the first wiring 111 is the second insulating layer 22 of the second layer L2. The case where it forms in is illustrated. The first and second wirings 111 and 112 are electrically separated by the third insulating layer 23 of the third layer L3 provided between the first and second layers L1 and L2.

4A and 4B are diagrams showing still another configuration example of the wiring, in which FIG. 4A is a schematic perspective view, FIG. 4B is a schematic cross-sectional view taken along the line X4-X4 in FIG. It is a Y4-Y4 cross-sectional schematic diagram.
In the example shown in FIG. 4, the first wiring 121 is formed in the first insulating layer 21 of the first layer L1, which is the same as the example in FIG. In the example shown in FIG. 4, the second wiring 122 is formed in the first insulating layer 21 of the first layer L <b> 1 in the region where the second wiring 122 does not intersect with the first wiring 121. Then, in the region intersecting with the first wiring 121, the second wiring 122 is detoured to the second layer L 2 by the via 123 that penetrates the third insulating layer 23 of the third layer L 3, and enters the second insulating layer 22. Is formed.

  In the example shown in FIGS. 3 and 4, the first wirings 111 and 121 are formed in the first layer L1, and the second wirings 112 and 122 are formed in the first layer L1 or the second layer L2 or depending on the region. It is formed in the second layer L2.

  On the other hand, in the example shown in FIGS. 1 and 2, the first and second wirings 11 and 12 are arranged in the first, second and third layers L1 and L2 in the peripheral area AR2 around the intersection area AR1. , L3. Therefore, when the number of layers and the layer thickness are the same in the case of FIGS. 3 and 4 and the case of FIGS. 1 and 2, the first and second wirings 11 and 12 shown in FIGS. The wiring cross-sectional area will increase.

  As a result, the wiring resistance can be reduced. Further, when the first wiring 11 and / or the second wiring 12 is used as a signal line, the attenuation of the signal transmitted through the first wiring 11 and / or the second wiring 12 is effectively reduced by increasing the wiring cross-sectional area. Can be reduced.

  Accordingly, even when the wiring width of the first and second wirings 11 and 12 becomes fine or the wiring length becomes long and the layout is made so as to intersect them, the wiring resistance can be reduced. In addition, the attenuation of the signal can be reduced.

  1 and 2 exemplify the case where a layered conductor layer is used as the conductor portions 11c and 12c formed in the third layer L3 that connects the first and second wirings 11 and 12. In addition, the conductor portions 11c and 12c can be at least one via formed in the third layer L3 between the first and second wirings 11 and 12.

  FIG. 5 is a schematic perspective view of a main part showing another example of wiring. 6A and 6B are schematic cross-sectional views of the main part showing another example of the wiring. FIG. 6A is a schematic cross-sectional view taken along the line X5-X5 in FIG. 5, and FIG.

  For example, as shown in FIGS. 5 and 6, the first and second wirings 11 and 12 use a plurality of vias 11d and 12d formed in the third layer L3 at regular intervals as shown in FIGS. It can also be formed. The vias 11d and 12d pass through the third insulating layer 23 of the third layer L3 provided between the first and second layers L1 and L2, respectively, and the upper layer portion 11a and the lower layer portion 11b of the first wiring 11 and the second layer 11b. The upper layer portion 12a and the lower layer portion 12b of the wiring 12 are formed so as to be connected.

  The interval between adjacent vias 11d and the interval between adjacent vias 12d can be set based on the wiring length, wiring width, etc. of the first and second wirings 11, 12, respectively. For example, when the first and second wirings 11 and 12 are formed with a wiring length of 20 mm and a wiring width of 5 μm, the interval between the vias 11 d and the interval between the vias 12 d can be set in a range of 0.01 mm to 1 mm.

  For convenience, FIG. 5 illustrates the case where the vias 11d and 12d have a cross section in the plane direction of the third layer L3 that is rectangular in a plan view. Of course, the cross section in the direction has a circular shape in a plan view. The vias 11d and 12d can be formed to have an elliptical shape.

  In the above description, the case where both the first and second layers L1 and L2 are one layer is exemplified, but each of the first and second layers L1 and L2 includes a laminated structure including two or more layers. It is good. In that case, the upper layer portions 11a and 12a may be formed so as to penetrate the first layer L1 having a laminated structure, and the lower layer portions 11b and 12b may be formed so as to penetrate the second layer L2 having a laminated structure. .

  In the above description, the case where the third layer L3 between the first and second layers L1 and L2 is a single layer is exemplified. However, the third layer L3 may have a laminated structure including two or more layers. Good. In that case, the conductor portions 11c and 12c (including the vias 11d and 12d) are formed so as to penetrate the laminated structure and to be connected to the upper layer portion 11a and the lower layer portion 11b, and to the upper layer portion 12a and the lower layer portion 12b, respectively. do it. In this case, conductor layers and vias may be repeatedly arranged in the stacking direction on the third layer L3 having a stacked structure.

  Further, the first and second wirings 11 and 12 may be formed by combining the conductor portions 11c and 12c with the above-described conductor layers and vias. For example, for one of the first and second wirings 11 and 12, a conductor layer may be used for connection between the upper layer portion and the lower layer portion, and for the other, a via may be used for connection between the upper layer portion and the lower layer portion. Alternatively, for both or one of the first and second wirings 11 and 12, a conductor layer is used to connect a part of the upper layer part and the lower layer part, and a via is used to connect another part of the upper layer part and the lower layer part. It can also be used.

Hereinafter, an embodiment to which the above wiring is applied will be described.
First, the first embodiment will be described.
FIG. 7 is a schematic plan view of an example of an electronic device.

The electronic device 30 shown in FIG. 7 includes semiconductor elements 41 and 42 that are one type of electronic components, and a wiring board 50.
As the semiconductor elements 41 and 42, for example, an IC (Integrated Circuit) chip or a packaged IC chip is used. Here, the semiconductor elements 41 and 42 are flip-chip mounted at predetermined positions on the wiring board 50. In FIG. 7, illustration of connection portions between the semiconductor elements 41 and 42 and the wiring board 50 is omitted, but electrodes (terminals) are respectively provided in the semiconductor elements 41 and 42 and the wiring board 50 at corresponding positions in advance. The corresponding electrodes are electrically connected through bumps.

  The semiconductor elements 41 and 42 flip-chip mounted on the wiring board 50 are electrically connected by a plurality of wirings (inter-element wirings) 51 formed on the wiring board 50 and arranged at a relatively high density. Yes. Further, the wiring substrate 50 includes a plurality of external connection electrodes (terminals) 60 disposed at the end of the surface opposite to the mounting surface of the semiconductor elements 41 and 42, the semiconductor elements 41 and 42, A plurality of wirings (element-terminal wirings) 53 for electrically connecting the terminals 60 are formed.

  The wiring substrate 50 is made of, for example, ceramics (aluminum nitride, etc.), glass, organic resin (polyimide, etc.), solid oxide (silicon oxide, carbon-containing silicon oxide, nitrogen-containing silicon oxide, etc.), semiconductor (silicon, etc.), etc. Can be used.

  For example, using an insulating material such as ceramics, glass, organic resin, solid oxide, etc., electrical connection between different inter-element wirings 51, different element-terminal wirings 53, and between the inter-element wirings 51 and the element-terminal wirings 53. An insulating layer can be formed for the purpose of separation. Also, different inter-element wiring 51, different element-terminal wiring 53, inter-element wiring 51 and element-terminal are formed on a substrate such as a semiconductor, ceramics, glass or the like using an insulating material such as an organic resin or a solid oxide. It is also possible to form an insulating layer for electrically separating between the inter-wirings 53.

The inter-element wiring 51 and the element-terminal wiring 53 formed on the wiring substrate 50 can be formed using, for example, copper, aluminum, or a metal material containing copper or aluminum.
From the viewpoint of miniaturization and high density of the inter-element wiring 51 and the element-terminal wiring 53, a solid oxide is formed on the semiconductor substrate as an insulating layer, and the inter-element wiring 51 and the element are formed in the insulating layer. It is preferable to obtain the wiring substrate 50 by forming the inter-terminal wiring 53. A method for forming such a wiring board 50 will be described later.

  The element-terminal wiring 53 formed on the wiring board 50 has a relatively long wiring length depending on the planar size of the wiring board 50 and the semiconductor elements 41 and 42 mounted thereon, the layout of the semiconductor elements 41 and 42 and the terminals 60, and the like. May be formed. Further, when the plurality of element-terminal wirings 53 are laid out, for example, as shown in a region D1 shown in FIG.

FIG. 8 is a schematic perspective view of a main part of the wiring according to the first embodiment. 9 is a schematic cross-sectional view taken along X8-X8 in FIG. 8, and FIG. 10 is a schematic cross-sectional view taken along Y8-Y8 in FIG.
FIG. 8 shows, as an example, four element-terminal wirings 53 formed in the region D1 of FIG. These four element-terminal wirings 53 are herein referred to as a first wiring 531, a second wiring 532, a third wiring 533, and a fourth wiring 534.

  The first, second, third, and fourth wirings 531, 532, 533, and 534 may be either ground lines or signal lines, respectively. For example, when the first, second, third, and fourth wirings 531, 532, 533, and 534 are all ground lines or signal lines, the first and second wirings 531 and 532 are ground lines. There may be a case where the third and fourth wirings 533 and 534 are signal lines (coplanar wiring).

  In the example shown in FIG. 8, the first and third wirings 531 and 533 are extended in parallel, the second and fourth wirings 532 and 534 are extended in parallel, and the first and third wirings 531 and 533 are extended. And the second and fourth wirings 532 and 534 intersect each other.

  The first wiring 531 includes an upper layer portion 531a, a lower layer portion 531b, and a plurality of conductor portions 531c, as shown in FIGS. Here, a case where a via is formed as the conductor portion 531c is illustrated.

  The upper layer portion 531a is formed in the intersection region AR1 and the peripheral region AR2 in the first insulating layer 541 of the first layer L1. The lower layer portion 531b is formed in the peripheral region AR2 in the second insulating layer 542 of the second layer L2. Lower layers 532b and 534b of second and fourth wirings 532 and 534 that intersect with the first wiring 531 are formed in the second layer L2 of the intersecting area AR1. The conductor portion 531c is formed in the peripheral region AR2 in the third insulating layer 543 of the third layer L3, passes through the third insulating layer 543, and connects the upper layer portion 531a and the lower layer portion 531b.

Similarly, the third wiring 533 extending in parallel with the first wiring 531 includes an upper layer portion 533a, a lower layer portion 533b, and a plurality of conductor portions (vias) 533c, as shown in FIG.
The upper layer portion 533a is formed in the first layer L1 of the intersection area AR1 and the peripheral area AR2. The lower layer part 533b is formed in the second layer L2 of the peripheral area AR2. Lower layers 532b and 534b of the second and fourth wirings 532 and 534 that intersect with the third wiring 533 are formed in the second layer L2 of the intersection region AR1. The conductor portion 533c is formed in the third layer L3 of the peripheral area AR2, and connects the upper layer portion 533a and the lower layer portion 533b.

  The second wiring 532 intersecting with the first and third wirings 531 and 533 also includes an upper layer portion 532a, a lower layer portion 532b, and a plurality of conductor portions (vias) 532c, as shown in FIGS. Yes.

  The upper layer portion 532a is formed in the peripheral area AR2 in the first insulating layer 541 of the first layer L1. In the first layer L1 of the intersection region AR1, upper layer portions 531a and 533a that intersect with the second wiring 532 are formed. The lower layer portion 532b is formed in the intersection region AR1 and the peripheral region AR2 in the second insulating layer 542 of the second layer L2. The conductor portion 532c is formed in the peripheral region AR2 within the third insulating layer 543 of the third layer L3, passes through the third insulating layer 543, and connects the upper layer portion 532a and the lower layer portion 532b.

Similarly, the fourth wiring 534 extending in parallel with the second wiring 532 includes an upper layer portion 534a, a lower layer portion 534b, and a plurality of conductor portions (vias) 534c, as shown in FIG.
The upper layer portion 534a is formed in the first layer L1 of the peripheral area AR2. In the first layer L1 of the intersection area AR1, upper layer portions 531a and 533a that intersect with the fourth wiring 534 are formed. The lower layer part 534b is formed in the second layer L2 of the intersection area AR1 and the peripheral area AR2. The conductor portion 534c is formed in the third layer L3 of the peripheral area AR2, and connects the upper layer portion 534a and the lower layer portion 534b.

  As described above, the first and third wirings 531 and 533 arranged in parallel intersect the second and fourth wirings 532 and 534 (lower layer portions 532b and 534b) in the intersection area AR1, and in the intersection area AR1, Only the upper layer portions 531a and 533a are formed in the first layer L1. In the peripheral area AR2, the first and third wirings 531 and 533 are respectively provided in the first, second, and third layers L1, L2, and L3 in the upper layer portions 531a and 533a, the lower layer portions 531b and 533b, and the conductor portions 531c and 533c. Is formed.

  On the other hand, the second and fourth wirings 532 and 534 arranged in parallel intersect the first and third wirings 531 and 533 (upper layer portions 531a and 533a) in the intersection area AR1, and in the intersection area AR1, the second wiring Only the lower layer portions 532b and 534b are formed in the layer L2. In the peripheral area AR2, the second and fourth wirings 532 and 534 are respectively connected to the first, second, and third layers L1, L2, and L3 in the upper layer portions 532a and 534a, the lower layer portions 532b and 534b, and the conductor portions 532c and 534c. Is formed.

  The first, second, third and fourth wirings 531, 532, 533 and 534 are formed using the first, second and third layers L 1, L 2 and L 3 in the peripheral area AR 2. It is possible to secure a wiring cross-sectional area. As a result, the wiring resistance can be reduced. Furthermore, when all or some of the first, second, third, and fourth wirings 531, 532, 533, and 534 are used as signal lines, those used as signal lines are caused by wiring resistance. It is possible to effectively reduce the attenuation of the transmission signal.

Next, a method for forming the wiring board 50 including the first, second, third, and fourth wirings 531, 532, 533, and 534 as described above will be described.
Here, as an example, a method for forming the wiring substrate 50 in a form in which an insulating layer and wiring are formed on a silicon substrate will be described. Hereinafter, the formation process will be described in order.

11A and 11B are explanatory views of an example of the first groove forming step, in which FIG. 11A is a schematic plan view, FIG. 11B is a schematic cross-sectional view taken along the line X11-X11 in FIG. It is a Y11 cross-sectional schematic diagram.
In forming the wiring substrate 50, first, an insulating layer (base insulating layer) 56 is formed on the surface of the silicon substrate 55, and the second insulating layer 542 is further formed thereon. As the base insulating layer 56, for example, a 0.7 μm thick silicon oxide layer is formed. Further, as the second insulating layer 542, for example, a silicon oxide layer having a thickness of 1 μm is formed.

  After the formation of the base insulating layer 56 and the second insulating layer 542, the second insulating layer 542 is provided with the lower layer portions 531 b, 532 b, 532 b of the first, second, third and fourth wirings 531, 532, 533, 534 described above. A groove 542A for forming 533b and 534b is formed. That is, as shown in FIGS. 11A and 11C, a continuous groove 542A having a planar bent shape corresponding to the shape of the lower layer portions 532b and 534b of the second and fourth wirings 532 and 534 is formed. At the same time, as shown in FIGS. 11A and 11B, grooves 542A having a planar linear shape corresponding to the shape of the lower layer portions 531b and 533b of the first and third wirings 531 and 533 and spaced apart at the intersecting region. Form.

The groove 542A can be formed by, for example, dry etching on the second insulating layer 542.
12A and 12B are explanatory diagrams of an example of the first embedding process, in which FIG. 12A is a schematic plan view, FIG. 12B is a schematic cross-sectional view taken along the line X12-X12 in FIG. It is a cross-sectional schematic diagram.

  After the formation of the groove 542A, a wiring material is deposited on the entire surface, and unnecessary wiring material deposited on the upper surface of the second insulating layer 542 is removed by using a CMP (Chemical Mechanical Polishing) method, and a wiring is formed in the groove 542A. Embed material. For the wiring material at this time, for example, copper or a metal material mainly composed of copper is used. For the deposition of the wiring material, for example, a CVD (Chemical Vapor Deposition) method or a plating method can be used.

  By filling the groove 542A with such a wiring material, the first, second, third and fourth wirings 531 and 532 are formed in the second insulating layer 542 as shown in FIGS. , 533, 534, lower layer portions 531b, 532b, 533b, 534b are formed.

  By applying a so-called single damascene process as shown in FIGS. 11 and 12, lower layers 531 b, 532 b, 533 b, and 534 b are formed in the second insulating layer 542.

13A and 13B are explanatory views of an example of the second groove forming step, where FIG. 13A is a schematic plan view, FIG. 13B is a schematic cross-sectional view taken along the line X13-X13 in FIG. It is a Y13 cross-sectional schematic diagram.
After the formation of the lower layer portions 531b, 532b, 533b, and 534b, the above-described third insulating layer 543 is formed on the entire surface, and further, the above-described first insulating layer 541 is formed thereon. As the third insulating layer 543, for example, a silicon oxide layer having a thickness of 0.5 μm is formed. Further, as the first insulating layer 541, for example, a silicon oxide layer having a thickness of 1 μm is formed.

  After the formation of the third and first insulating layers 543 and 541, a so-called dual damascene process is applied to form grooves 543A and 541A having predetermined shapes in the third and first insulating layers 543 and 541, respectively.

  The third insulating layer 543 has via grooves 543A for forming the conductor portions 531c, 532c, 533c, and 534c of the first, second, third, and fourth wirings 531, 532, 533, and 534 described above. Form. The via grooves 543A formed in the third insulating layer 543 are formed on the lower layer portions 531b, 532b, 533b, and 534b formed earlier, as shown in FIGS. 13 (A) to (C). Form to reach.

  Further, the first insulating layer 541 is provided with a groove 541A for forming the upper layer portions 531a, 532a, 533a, 534a of the first, second, third and fourth wirings 531, 532, 533, 534 described above. To do. That is, as shown in FIGS. 13A and 13B, a continuous linear groove 541A corresponding to the shape of the upper layer portions 531a and 533a of the first and third wirings 531 and 533 is formed. At the same time, as shown in FIGS. 13A and 13C, a groove 541A having a plane-bending shape corresponding to the shape of the upper layer portions 532a and 534a of the second and fourth wirings 532 and 534 and spaced apart at the intersecting region. Form. The groove 541A formed in the first insulating layer 541 is formed in parallel to the previously formed lower layer portions 531b, 532b, 533b, and 534b and so as to communicate with the lower layer groove 543A.

14A and 14B are explanatory views of an example of the second embedding process, in which FIG. 14A is a schematic plan view, FIG. 14B is a schematic cross-sectional view taken along the line X14-X14 in FIG. It is a cross-sectional schematic diagram.
After the formation of the grooves 543A and 541A, a wiring material is deposited on the entire surface, and unnecessary wiring material deposited on the upper surface of the first insulating layer 541 is removed by CMP, and the wiring material is placed in the grooves 543A and 541A. Embed. As the wiring material, for example, copper or a metal material mainly composed of copper can be deposited using a CVD method.

  By filling the grooves 543A and 541A with the wiring material, as shown in FIGS. 14A to 14C, the first, second, third and fourth wirings 531 and 532 are formed in the third insulating layer 543. Conductor portions 531c, 532c, 533c, and 534c of 533 and 534 are formed. At the same time, upper layer portions 531a, 532a, 533a, and 534a of the first, second, third, and fourth wirings 531, 532, 533, and 534 are formed in the first insulating layer 541.

As a result, first, second, third and fourth wirings 531, 532, 533 and 534 are formed above the silicon substrate 55.
The first, second, third, and fourth wirings 531, 532, 533, and 534 can have a wiring width of 5 μm and a wiring length of 20 mm, for example. When the first and third wirings 531 and 533 are used as a ground line and a signal line, respectively, the space between the first and third wirings 531 and 533 can be set to 10 μm, for example. Similarly, when the second and fourth wirings 532 and 534 are used as a ground line and a signal line, respectively, the space between the second and fourth wirings 532 and 534 can be set to 10 μm, for example. Moreover, the conductor parts 531c, 532c, 533c, and 534c can be arrange | positioned at the space | interval of 0.01 mm-1 mm, for example.

  Here, the case where the conductor portions 531c, 532c, 533c, and 534c and the upper layer portions 531a, 532a, 533a, and 534a are collectively formed by a dual damascene process is illustrated. In addition, the conductor portions 531c, 532c, 533c, and 534c may be formed by a single damascene process, and then the upper layer portions 531a, 532a, 533a, and 534a may be formed by a single damascene process.

  The first, second, third, and fourth wirings 531, 532, 533, and 534 of the wiring board 50 can be formed by the above process. The terminal 60 for external connection provided at the end of the wiring board 50 can be formed.

  15A and 15B are explanatory views of an example of the external connection terminal forming process, where FIG. 15A is a schematic cross-sectional view of the main part after the wiring is formed, and FIG. 15B is a schematic cross-sectional view of the main part of the via groove forming process. ) Is a schematic cross-sectional view of the relevant part in the via formation step, and FIG.

For example, as shown in FIGS. 11 and 12, the external connection terminal 60 is formed from the state after the formation of the lower layer portions 531b, 532b, 533b, and 534b.
For convenience, FIG. 15 illustrates a portion corresponding to the region D2 of FIG. 7 in the lower layer portion 531b of the first wiring 531 among the lower layer portions 531b, 532b, 533b, and 534b. The flow of will be described. The flow of forming the terminal 60 is the same for the other lower layer portions 532b, 533b, and 534b.

When the terminal 60 is formed, a land 531ba is formed at the end of the lower layer portion 531b on the end side of the wiring board 50 as shown in FIG.
Then, as shown in FIG. 15B, via grooves 61a that penetrate the silicon substrate 55 and the base insulating layer 56 and reach the lands 531ba are formed from the silicon substrate 55 side. After the formation of the via groove 61a, the via groove 61a is filled with a conductive material such as copper by using, for example, a CVD method and a CMP method, and the via 61 is formed as shown in FIG.

  After the formation of the via 61, as shown in FIG. 15D, a pad 62 is formed on the via 61 using aluminum or the like, and a part of the pad 62 is left to be protected on the silicon substrate 55. A film 63 is formed. The exposed portion of the pad 62 from the protective film 63 is used as the external connection terminal 60 of the wiring board 50.

  In this manner, the terminal 60 electrically connected to the lower layer portions 531b, 532b, 533b, 534b is formed. After the formation of the terminal 60, the conductor portions 531c, 532c, 533c, and 534c and the upper layer portions 531a, 532a, 533a, and 534a may be formed as shown in FIGS.

  Here, the case where the terminal 60 is formed after the formation of the lower layer portions 531b, 532b, 533b, and 534b is illustrated, but the timing of forming the terminal 60 is not limited to this.

  For example, after forming the lower layer parts 531b, 532b, 533b, 534b, the conductor parts 531c, 532c, 533c, 534c and the upper layer parts 531a, 532a, 533a, 534a, the terminal 60 is formed according to the example of FIG. It is also possible to do. When the conductor portions 531c, 532c, 533c, and 534c are formed by a single damascene process, the terminals 60 can be formed after the formation according to the example of FIG. That is, if at least the formation of the lower layer portions 531b, 532b, 533b, and 534b is performed, the terminal 60 can be formed according to the example of FIG.

  Further, the terminal 60 can be formed after the formation of the lower layer portions 531b, 532b, 533b, and 534b as described above, and may be performed before the formation of the lower layer portions 531b, 532b, 533b, and 534b. Is possible.

  In that case, for example, after the formation of the base insulating layer 56 on the surface of the silicon substrate 55 shown in FIG. 11, the land 531ba of the lower layer portions 531b, 532b, 533b, 534b and the like are formed from the back surface side. A via groove 61a is formed, and a via 61 is formed there. Then, after the formation of the via 61, for example, the pad 62 and the protective film 63 are formed, and the second insulating layer 542, the lower layer portions 531b, 532b, 533b, and 534b are formed, and the upper layer side is formed. do it. Alternatively, after the formation of the via 61, the formation of the second insulating layer 542, the formation of the lower layer portions 531b, 532b, 533b, and 534b, and the formation of the upper layer side as necessary, the pad 62 and the protective film 63 are performed. May be formed.

  As described above, the terminal 60 is formed at one end of the first, second, third, and fourth wirings 531, 532, 533, and 534, that is, at the end of the wiring board 50. Further, at the other end of the first, second, third and fourth wirings 531, 532, 533 and 534, that is, at the end of the central portion side of the wiring substrate 50 (mounting region side of the semiconductor elements 41 and 42), Terminals for connecting the semiconductor elements 41 and 42 are formed.

  FIG. 16 is an explanatory diagram of an example of a semiconductor element connection terminal forming process, where (A) is a schematic cross-sectional view of a relevant part in a via forming process, (B) is a schematic cross-sectional view of a relevant part in a pad forming process, and (C). These are the principal part cross-sectional schematic diagrams of an under bump metal formation process.

  For example, after the formation of the first, second, third and fourth wirings 531, 532, 533, 534 and the formation of the external connection terminal 60 as shown in FIGS. From this state, the terminal 64 used for connecting the semiconductor elements 41 and 42 is formed.

  For convenience, FIG. 16 illustrates a portion of the first wiring 531 corresponding to the region D3 in FIG. 7 among the first, second, third, and fourth wirings 531, 532, 533, and 534. The flow of terminal formation will be described. The flow of terminal formation is the same for the other second, third, and fourth wirings 532, 533, and 534.

  When forming the terminal 64 used for the connection of the semiconductor elements 41 and 42, as shown in FIG. 16A, at the end of the upper layer portion 531a and the lower layer portion 531b of the first wiring 531 on the center side of the wiring substrate 50, A land 531ab and a land 531bb are formed in advance. A conductor 531c may be provided between the lands 531ab and 531bb.

  After the formation of the first wiring 531, a fourth insulating layer 544 is further formed on the first insulating layer 541. Then, a via groove reaching the land 531ab through the fourth insulating layer 544 is formed, and the via groove is filled with a conductive material such as copper by using, for example, a CVD method and a CMP method. The via 65 is formed as shown in FIG.

  After the formation of the via 65, as shown in FIG. 16B, a pad 66 is formed on the via 65 using aluminum or the like, and a protective film 67 is formed leaving a part of the pad 66. The exposed portion of the pad 66 from the protective film 67 is used as a terminal 64 for connecting the semiconductor elements 41 and 42.

  When the semiconductor elements 41 and 42 and the terminal 64 are connected using a solder material such as a solder bump, an under bump metal (UBM) 68 may be formed on the terminal 64. . However, the UBM 68 is not necessarily formed on the terminal 64.

  FIG. 16 shows the protective film 63 formed on the back side of the silicon substrate 55. The formation of the protective film 63 and the formation of the terminal 60 on the back side prior to that are shown in FIG. It is also possible to carry out after the formation of the terminal 64 on the front surface side.

The semiconductor elements 41 and 42 are flip-chip mounted on the wiring board 50 formed as described above, and the electronic device 30 is formed.
FIG. 17 is a schematic cross-sectional view of an essential part of an example of an electronic device. Note that FIG. 17 schematically illustrates a main part of a cross section along the first wiring 531 as an example.

  The semiconductor elements 41 and 42 are previously formed with electrodes (terminals) 43 and protective films 44 that are electrically connected to circuit elements (not shown) such as internal transistors, capacitors, and resistors. The terminals 43 of the semiconductor elements 41 and 42 and the terminals 64 on the surface side of the wiring board 50 formed as described above are formed in advance at positions corresponding to each other.

When mounting the semiconductor elements 41, 42, bumps 45 (here, solder balls as an example) are connected in advance above the terminals 64 (on the UBM 68) of the wiring board 50.
Note that gold bumps or copper bumps may be connected to the terminals 43 of the semiconductor elements 41 and 42 in advance. Further, a UBM (not shown) may be formed on the terminals 43 of the semiconductor elements 41 and 42, and the bumps 45 may be connected thereto.

  The semiconductor elements 41 and 42 are arranged on the wiring board 50 by aligning the terminals 43 and the terminals 64 of the wiring board 50. Thereafter, by performing a reflow process, the semiconductor elements 41 and 42 and the wiring board 50 are electrically connected through the bumps 45.

  Also, bumps 69 (in this example, solder balls) are connected to the terminals 60 provided at the end on the back side of the wiring board 50, and the wiring board 50 on which the semiconductor elements 41 and 42 are mounted is connected to this bump. 69 is externally connected.

  According to the wiring board 50 as described above, the wiring resistance can be reduced, and the attenuation of the transmission signal due to the wiring resistance can be effectively reduced. The electronic device 30 can be realized.

FIG. 18 is a diagram showing an example of the relationship between the frequency of the wiring board and the transmittance.
FIG. 18 shows an example of the result of simulating the relationship between frequency and transmittance for the first, second, third and fourth wirings 531, 532, 533 and 534 arranged so as to cross like the wiring board 50. (Example). In this simulation, the wiring width of the first, second, third and fourth wirings 531, 532, 533 and 534 is 5 μm, and the wiring length (first and third wirings 531 and 533) is 20 mm. The first and second wirings 531 and 532 are ground lines, the third and fourth wirings 533 and 534 are signal lines, and the distance between the ground lines and the signal lines is 10 μm. The transmittance is obtained based on waveform attenuation of a signal input from one end of the signal line and output from the other end of the signal line.

  For comparison, the first and third wirings 531 and 533 are configured only by the upper layer portions 531a and 533a of the first layer L1, and the second and fourth wirings 532 and 534 are formed by the lower layer portions 532b and 532b of the second layer L2. A simulation is also performed for a configuration composed only of 534b (comparative example). That is, according to the example of FIG. 3 described above, two wirings formed in parallel in the first layer L1 and two wirings formed in parallel in the second layer L2 are arranged so as to intersect each other. , Doing a simulation. Also in this comparative example, the relationship between the ground line and the signal line is the same as in the above embodiment, and the wiring width, the wiring length, and the interval between the ground line and the signal line are also the same as in the above embodiment.

  As seen from the range of 10 MHz to 2 GHz from FIG. 18, the cross wiring of the comparative example has a transmittance of −4.3 dB to −4.8 dB, whereas the cross wiring of the example has a transmission of −2.2 dB to It can be seen that a high transmittance of -2.4 dB is obtained.

The wiring board 50 according to the first embodiment and the electronic device 30 using the wiring board 50 have been described above.
In the above description, FIG. 7 and FIG. 17 illustrate the electronic device 30 in a form in which the two semiconductor elements 41 and 42 are mounted on one wiring board 50. A wiring board having a cross wiring such as the wiring board 50 is widely applicable as a wiring board for mounting at least one semiconductor element.

  7 and 17 exemplify the electronic device 30 in which the semiconductor elements 41 and 42 are flip-chip mounted on the wiring board 50. In addition, the wiring board having the cross wiring such as the wiring board 50 can be applied to a wiring board in which at least one semiconductor element is connected by wire bonding. In that case, an electrode (terminal) for wire bonding electrically connected to the wiring including the cross wiring may be provided around the semiconductor element mounting region of the wiring substrate.

Next, a second embodiment will be described.
FIG. 19 is a schematic perspective view of the main part of the wiring according to the second embodiment. 20 is a schematic cross-sectional view taken along X19-X19 in FIG. 19, and FIG. 21 is a schematic cross-sectional view taken along Y19-Y19 in FIG.

  In the second embodiment, as shown in FIGS. 19 to 21, the first and second wirings 531 and 532 are connected in the intersection area AR1. In the intersection area AR1, an upper layer portion 535a including a portion where the upper layer portions 531a and 532a are integrated with each other and a lower layer portion 535b including a portion where the lower layer portions 531b and 532b are integrated with each other are connected by a conductor portion 535c. Has been. Other configurations are the same as those in the first embodiment.

  The first and second wirings 531 and 532 connected as in the second embodiment are used as ground lines, for example. The third and fourth wirings 533 and 534 are used as signal lines, for example.

  The wiring board including the cross wiring of the second embodiment can also reduce the wiring resistance as in the first embodiment, and can effectively reduce the attenuation of the transmission signal due to the wiring resistance. It becomes possible. By using such a wiring board, a high-performance and high-quality electronic device can be realized.

  The wiring board including the cross wiring and the electronic device using the wiring board have been described above. In the above description, the coplanar wiring has been described as an example. However, the cross wiring can be similarly applied to a microstrip type wiring board. In that case, another insulating layer may be provided below or above the layer group forming the cross wiring, and a flat electrode layer may be provided via the insulating layer.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Supplementary note 1) having a first layer, a second layer, and a third layer between the first layer and the second layer;
A first wiring formed in the first layer in the first region, a first wiring formed in the first layer, the second layer, and the third layer in the second region around the first region;
The first region intersects the first wiring, is formed in the second layer in the first region, and is formed in the first layer, the second layer, and the third layer in the second region. Two wires,
A wiring board comprising:

(Supplementary Note 2) The first wiring includes a first portion extending in the first layer of the first region and the second region, and a second portion of the second region in parallel with the first portion. An extended second part; and a third part provided in the third layer of the second region and connecting the first part and the second part;
The second wiring extends in parallel with the fourth part on the first layer of the second region and the fourth part extending on the second layer of the first region and the second region. The wiring board according to claim 1, further comprising a fifth part and a sixth part provided in the third layer of the second region and connecting the fourth part and the fifth part.

(Additional remark 3) The said 3rd part and the said 6th part contain the conductor layer, The wiring board of Additional remark 2 characterized by the above-mentioned.
(Supplementary Note 4) The wiring board according to Supplementary Note 2, wherein the third part and the sixth part include vias.

(Supplementary Note 5) The wiring board according to any one of Supplementary Notes 1 to 4, wherein the third layer includes one layer or two or more layers.
(Supplementary Note 6) Crossing the first wiring in the first region, formed in the second layer in the first region, and formed in the first layer, the second layer, and the third layer in the second region. The wiring board according to any one of appendices 1 to 5, further comprising a third wiring formed.

  (Supplementary Note 7) The first region intersects with the first wiring, is formed in at least the first layer and the second layer in the first region, and is connected to the first wiring. In the second region, the first region The wiring board according to any one of appendices 1 to 5, further comprising a fourth wiring formed in the first layer, the second layer, and the third layer.

  (Supplementary note 8) In any one of supplementary notes 1 to 7, further comprising a flat electrode layer disposed above or below the first wiring and the second wiring via a fourth layer. The wiring board described.

(Supplementary note 9) having a first layer, a second layer, and a third layer between the first layer and the second layer;
A first wiring formed in the first layer in the first region, a first wiring formed in the first layer, the second layer, and the third layer in the second region around the first region;
The first region intersects the first wiring, is formed in the second layer in the first region, and is formed in the first layer, the second layer, and the third layer in the second region. Two wires,
A wiring board including:
A semiconductor element electrically connected to the wiring board;
An electronic device comprising:

11, 111, 121, 531 First wiring 12, 112, 122, 532 Second wiring 11a, 12a, 531a, 532a, 533a, 534a, 535a Upper layer portion 11b, 12b, 531b, 532b, 533b, 534b, 535b Lower layer portion 11c, 12c, 531c, 532c, 533c, 534c, 535c Conductor portion 11d, 12d, 61, 65, 123 Via 21, 541 First insulating layer 22, 542 Second insulating layer 23, 543 Third insulating layer 30 Electronic device 41 , 42 Semiconductor element 43, 60, 64 Terminal 44, 63, 67 Protective film 45, 69 Bump 50 Wiring board 51 Inter-element wiring 53 Element-terminal wiring 55 Silicon substrate 56 Underlying insulating layer 61a Via groove 62, 66 Pad 68 Under bump metal 531ba, 531ab, 531 b lands 533 third wire 534 fourth wire 541A, 542A, 543A groove 544 fourth insulating layer AR1 intersection area AR2 peripheral region L1 first layer L2 second layer L3 third layer D1, D2, D3 region

Claims (6)

A first layer, a second layer, and a third layer between the first layer and the second layer;
A first wiring formed in the first layer in the first region, a first wiring formed in the first layer, the second layer, and the third layer in the second region around the first region;
The first region intersects the first wiring, is formed in the second layer in the first region, and is formed in the first layer, the second layer, and the third layer in the second region. Two wires,
A wiring board comprising: The first wiring extends in parallel with the first part on the first layer in the first region and the second layer in the first region and on the second layer in the second region. A second part, and a third part provided in the third layer of the second region and connecting the first part and the second part,
The second wiring extends in parallel with the fourth part on the first layer of the second region and the fourth part extending on the second layer of the first region and the second region. The wiring board according to claim 1, further comprising a fifth part and a sixth part provided in the third layer of the second region and connecting the fourth part and the fifth part.   The wiring board according to claim 2, wherein the third part and the sixth part include a conductor layer.   The wiring board according to claim 2, wherein the third part and the sixth part include vias.   The wiring board according to claim 1, wherein the third layer includes one layer or two or more layers. A first layer, a second layer, and a third layer between the first layer and the second layer;
A first wiring formed in the first layer in the first region, a first wiring formed in the first layer, the second layer, and the third layer in the second region around the first region;
The first region intersects the first wiring, is formed in the second layer in the first region, and is formed in the first layer, the second layer, and the third layer in the second region. Two wires,
A wiring board including:
A semiconductor element electrically connected to the wiring board;
An electronic device comprising:

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