JP2011188323A - Pll circuit - Google Patents

Abstract

An object of the present invention is to provide a PLL circuit capable of suppressing the capacitance value of a loop filter and stabilizing the operation.
A phase comparator that compares a phase of an input signal with a phase of an output signal of a voltage controlled oscillation circuit and outputs a signal corresponding to a phase difference, and a charge / discharge current according to the output signal of the phase comparator A charge pump circuit that generates a first control voltage by smoothing an output of the charge pump circuit, and a first control voltage that is output from the loop filter so that the first control voltage is a predetermined voltage. A control voltage generation circuit for generating a second control voltage, and the first control voltage and the second control voltage are input to the voltage controlled oscillation circuit.
[Selection] Figure 6

Description

  The present invention relates to a PLL circuit that suppresses the capacitance value of a loop filter and stabilizes the operation.

  FIG. 1 is a diagram for explaining a conventional PLL (Phase-locked loop) circuit. A conventional PLL circuit 10 includes frequency dividing circuits 2 and 3, a phase comparator 4, a charge pump 5, a loop filter 6, and a voltage control transmission circuit 7.

  In the PLL circuit 10, an input clock is input from the outside, and the frequency dividing circuit 2 divides the frequency. In the PLL circuit 10, the output clock of the voltage controlled oscillation circuit 7 is divided by the frequency dividing circuit 3. The phase comparator 4 compares the phase difference and the frequency difference between the input clock divided by the frequency dividing circuit 2 and the output clock (feedback clock) divided by the frequency dividing circuit 3. From the phase comparator 4, an up pulse signal UP and a down pulse signal DN corresponding to the phase / frequency difference are output to the charge pump 5. A pulse current corresponding to the up pulse signal UP and the down pulse signal DN from the phase comparator 4 flows through the charge pump 5. This pulse current is converted into a voltage by charging or discharging a charge in the capacity of the loop filter 6. From the loop filter 6, the voltage converted as described above is output as a control voltage for controlling the oscillation frequency of the voltage controlled oscillation circuit 7.

  FIG. 2 is a diagram illustrating a charge pump included in a conventional PLL circuit. The charge pump 5 includes transistors M1 and M2. A signal obtained by inverting the up pulse signal UP is input to the gate of the transistor M1. The down pulse signal DN is input to the gate of the transistor M2.

  FIG. 3 is a diagram illustrating a loop filter included in a conventional PLL circuit. The loop filter 6 includes a resistor R and capacitive elements C1 and C2.

  FIG. 4 is a diagram showing a Bode diagram of a conventional PLL circuit. In FIG. 4, zero point F1 = 1 / (2π × R × C1) and pole point F2 = 1 / (2π × R × C2). The loop band Fc of the PLL circuit 10 is expressed as follows, where Kv is the gain of the voltage controlled oscillation circuit 7, Icp is the current flowing through the charge pump 6, and N is the frequency dividing number of the frequency dividing circuit 3. .

Fc = Kv × Icp × R / (2π × N)
In order for the PLL circuit 10 to achieve stable convergence, the condition of F1 <Fc <F2 must be satisfied, and F1 and F2 must be set so that the phase margin is sufficiently large.

  In the PLL circuit 10, when the comparison frequency of the phase comparator 4 is lowered, the loop band is lowered in order to ensure the stability of the loop. When the loop band is lowered, the capacitance values (C1, C2) of the loop filter 6 are increased. For example, when the capacitive elements C1, C2 are constituted by capacitors, the layout area of the circuit is increased.

  Therefore, in order to reduce the layout area, the capacitor element of the loop filter 6 is generally composed of a MOS (Metal-Oxide-Semiconductor) transistor. However, since the output of the charge pump 5 is variable, the gate voltage of the MOS transistor MOS which is the capacitive element of the loop filter 6 is also variable. For this reason, the capacitance value obtained by the MOS transistor changes. The change in the capacitance value due to the change in the gate voltage is particularly large in the vicinity of the threshold voltage Vth of the MOS transistor as shown in FIG. FIG. 5 is a diagram showing the capacitance-gate voltage characteristics of the MOS transistor.

  As another method for reducing the layout area, there is a method for reducing the capacitance value of the loop filter 6. In this method, the pulse current flowing through the charge pump 5 is reduced, but the control voltage of the voltage controlled oscillation circuit 7 fluctuates due to the leakage current of the capacitive element of the loop filter 6 and causes deterioration of jitter characteristics.

  As such an unspecified measure, for example, Patent Document 1 discloses that the fluctuation of the control voltage of the voltage control circuit due to the leakage current is prevented. Patent Document 2 describes a delay locked loop circuit that supplies a stable clock signal.

  However, in order to compensate for a minute voltage difference due to leakage current, a highly accurate operational amplifier is required. In Patent Document 1, a sample-and-hold circuit is used, and the switch transistor itself in the sample-and-hold circuit also generates off-leakage, so that a current error increases. Further, when the compensation circuit is switched, noise is mixed into the control voltage, which causes jitter characteristic deterioration.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a PLL circuit capable of suppressing the capacitance value of a loop filter and stabilizing the operation.

  The present invention employs the following configuration in order to achieve the above object.

  The PLL circuit of the present invention compares the phase of the input signal with the phase of the output signal of the voltage controlled oscillation circuit, and outputs a signal corresponding to the phase difference, and according to the output signal of the phase comparator A charge pump circuit that generates a charge / discharge current; a loop filter that smoothes an output of the charge pump circuit to generate a first control voltage; and the first control voltage output from the loop filter is set to a predetermined voltage. A control voltage generation circuit for generating a second control voltage so that the first control voltage and the second control voltage are input to the voltage controlled oscillation circuit.

  Also, in the PLL circuit of the present invention, the voltage controlled oscillation circuit includes a bias circuit and a ring oscillator, and the bias circuit converts the first control voltage into a current and supplies a current to the delay circuit of the ring oscillator. A first bias circuit for supplying the second bias voltage; and a second bias circuit for converting the second control voltage into a current and supplying the current to the delay circuit of the ring oscillator.

  In the PLL circuit of the present invention, the response of the control voltage generation circuit is slower than the response of the first control voltage.

  In the PLL circuit of the present invention, the voltage-controlled oscillation circuit has a fluctuation rate of an output frequency with respect to the fluctuation of the first control voltage smaller than a fluctuation ratio with respect to the fluctuation of the second control voltage.

  In the PLL circuit of the present invention, the control voltage generation circuit includes an operational amplifier circuit that controls the first control voltage by applying a negative feedback so as to be a predetermined voltage, and outputs the same to the voltage controlled oscillation circuit.

  In the PLL circuit of the present invention, the loop filter has a capacitive element formed of a MOS transistor, and the first control voltage is controlled to a voltage that becomes a saturation capacitance of the MOS transistor.

  According to the present invention, the capacitance value of the loop filter can be suppressed and the operation can be stabilized.

It is a figure explaining the conventional PLL (Phase-locked loop) circuit. It is a figure which shows the charge pump which the conventional PLL circuit has. It is a figure which shows the loop filter which the conventional PLL circuit has. It is a figure which shows the Bode diagram of the conventional PLL circuit. It is a figure which shows the capacitance value-gate voltage characteristic of a MOS transistor. It is a figure which shows the PLL circuit of this invention. It is a figure which shows the voltage control oscillation circuit which the PLL circuit of this invention has. It is a figure which shows the bias circuit which the PLL circuit of this invention has. It is a figure explaining the ring oscillator which the PLL circuit of this invention has.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 6 is a diagram showing a PLL circuit of the present invention.

  The PLL circuit 100 according to the present embodiment includes frequency dividing circuits 110 and 120, a phase comparator 130, a charge pump 140, a loop filter 150, a voltage controlled oscillation circuit (hereinafter referred to as VCO) 160, and an operational amplifier circuit 170.

  The frequency dividing circuits 110 and 120 of the present embodiment perform multiplication setting of the PLL circuit 100. The frequency dividing circuit 110 receives a reference input clock signal. A signal output from the VCO 160 is input to the frequency dividing circuit 120. Outputs of the frequency dividing circuits 110 and 120 are input to the phase comparator 130.

  The phase comparator 130 compares the phases of the reference signal frequency-divided by the frequency divider circuit 110 and the feedback signal frequency-divided by the frequency divider circuit 120. The charge pump 140 generates charge / discharge current according to the output signal of the phase comparator 130.

  Loop filter 150 smoothes the output of charge pump 140. The output of the loop filter 150 is supplied to the VCO 160 as the first control voltage VCOIN1.

  The VCO 160 outputs an output signal having a frequency corresponding to the input control voltage VCOIN1 and the control voltage VCOIN2 supplied from the operational amplifier circuit 170.

  The control voltage VCOIN1 that is the output of the loop filter 150 is supplied to one input of the operational amplifier circuit 170 of the present embodiment. A reference voltage VREF is supplied to the other input of the operational amplifier circuit 170. The reference voltage VREF is a fixed voltage generated inside the PLL circuit 100. The operational amplifier circuit 170 of the present embodiment outputs the control voltage VCOIN2 so that the control voltage VCOIN1 becomes the reference voltage VREF, and feeds back the output of the VCO 160 corresponding to the control voltage VCOIN2 to the phase comparator 130. The control voltage VCOIN1 is corrected. That is, the operational amplifier circuit 170 of this embodiment plays a role of a control voltage generation circuit that generates the control voltage VCOIN2 by making the control voltage VCOIN1 the same voltage as the reference voltage VREF.

  Next, the VCO 160 of this embodiment will be described with reference to FIG. FIG. 7 is a diagram showing a voltage controlled oscillation circuit included in the PLL circuit of the present invention.

  The VCO 160 of this embodiment includes a bias circuit 161, a ring oscillator 162, and a differential-single conversion circuit 163.

  Control signals Pcnt and Ncnt are output from the bias circuit 161 and supplied to the ring oscillator 162. The output of the ring oscillator 162 is supplied to the input of the differential-single conversion circuit 163.

  The bias circuit 161 of the present embodiment outputs the control signals Pcnt and Ncnt so as to increase the amount of current supplied to the ring oscillator 162 as the control voltages VCOIN1 and VCOIN2 rise. Further, the bias circuit 161 according to the present embodiment outputs the control signals Pcnt and Ncnt so as to reduce the amount of current supplied to the ring oscillator 162 due to the decrease of the control voltages VCOIN1 and VCOIN2. The ring oscillator 162 includes a plurality of differential amplifiers 164, outputs a signal having a frequency corresponding to the amount of current supplied from the bias circuit 161, and outputs a single clock by the differential-single conversion circuit 163. .

  Hereinafter, the bias circuit 161 of the present embodiment will be described with reference to FIG. FIG. 8 is a diagram showing a bias circuit included in the PLL circuit of the present invention.

  The bias circuit 161 according to the present embodiment adds the control voltage VCOIN1 obtained by voltage-current conversion and the control voltage VCOIN2 obtained by voltage-current conversion, and returns the control signal Pcnt supplied to the ring oscillator 162 by a current mirror. , Ncnt.

  The bias circuit 161 of this embodiment includes transistors M10 to M14 and resistors R1 and R2. The transistors M10 and M11 are PMOS transistors, and the transistors M12 to M14 are NMOS transistors.

  The gate of the transistor M10 and the gate of the transistor M11 are connected to the drain of the transistor M12 and the drain of the transistor M13. A control voltage VCOIN1 is supplied to the gate of the transistor M12, and the control voltage VCOIN1 is converted into a current. A control voltage VCOIN2 is supplied to the gate of the transistor M13, and the control voltage VCOIN2 is converted into a current. A resistor R1 is connected between the source of the transistor M12 and the ground. A resistor R2 is connected between the source of the transistor M13 and the ground.

  The voltage at the connection point between the gate of the transistor M10 and the gate of the transistor M11 is output as the control signal Pcnt.

  The drain of the transistor M11 is connected to the drain of the transistor M14. The drain of the transistor M14 is connected to the gate of the transistor M14. The voltage of the gate of the transistor M14 is output as the control signal Ncnt.

  In the bias circuit 161 of the present embodiment, the resistance value of the resistor R2 connected between the source of the transistor M13 to which the control voltage VCOIN2 is supplied and the ground is made smaller than the resistance value of the resistor R1. With this configuration, the bias circuit 161 of the present embodiment can make the variation rate of the output frequency of the VCO 160 with respect to the variation of the control voltage VCOIN1 smaller than the variation rate of the output frequency of the VCO 160 with respect to the variation of the control voltage VCOIN2.

  Further, the operational amplifier circuit 170 that generates the control voltage VCOIN2 of the present embodiment is formed so as to be slower than the response of the control voltage VCOIN1. That is, the response of the operational amplifier circuit 170 of this embodiment is slower than the response of the loop filter 150.

  As a result, the PLL circuit 100 can perform phase correction for the reference input clock signal based on the control voltage VCOIN1, and can perform slow fluctuation phase correction caused by temperature or the like based on the control voltage VCOIN2. Therefore, the control voltage VCOIN1 can be controlled to be a predetermined voltage.

  Next, the ring oscillator included in the PLL circuit of this embodiment will be described with reference to FIG. FIG. 9 is a diagram illustrating a ring oscillator included in the PLL circuit of the present invention.

  The ring oscillator 162 according to the present embodiment includes a plurality of differential amplifiers 164 that are delay elements. FIG. 9A shows the differential amplifier 164, and FIG. 9B shows the differential amplifier in more detail.

  As shown in FIG. 9B, the differential amplifier 164 includes transistors M20 to M24. The transistors M20 and M22 are PMOS transistors, and the other transistors are NMOS transistors.

  A control signal Pcnt is supplied to the gates of the transistors M20 and M22. The drain of the transistor M20 and the drain of the transistor M21 are connected, and the voltage at this connection point becomes one output O− of the differential amplifier 164. One input I + of the differential amplifier 164 is supplied to the gate of the transistor M21.

  The drain of the transistor M22 and the drain of the transistor M23 are connected, and the voltage at this connection point becomes the other output O + of the differential amplifier 164. The other input I− of the differential amplifier 164 is supplied to the gate of the transistor M23. The source of the transistor M21 and the source of the transistor M23 are connected to the drain of the transistor M24. A control signal Ncnt is supplied to the gate of the transistor M24.

  In the conventional PLL circuit, especially in the comparison of the frequency by the phase comparator, the capacitance value of the loop filter becomes large if the comparison frequency is low. Further, in the specification where the output frequency of the PLL circuit is high and the specification which requires a wide frequency range, the gain of the VCO is large, but when the loop band cannot be increased, the capacitance value of the loop filter is large. For this reason, when the loop filter is built in the chip, there is a problem that the chip size increases.

  According to the present embodiment, the bias circuit 161 and the operational amplifier circuit 170 are provided. According to this configuration, in the present embodiment, the variation rate of the output frequency of the VCO 160 with respect to the variation of the control voltage VCOIN 1 can be made smaller than before, and the output of the charge pump 140 can be stabilized and the gate of the MOS transistor constituting the loop filter 150 can be stabilized. Stabilizes the supplied voltage. Therefore, in this embodiment, a stable capacitance value can be obtained in the transistors constituting the loop filter 150, and the operation of the PLL circuit 100 can be stabilized.

  In this embodiment, the reference voltage VREF input to the operational amplifier circuit 170 is set to a value such that the control voltage VCOIN1 is a voltage at which the MOS transistor forming the loop filter 150 has a saturation capacity. In this embodiment, with this configuration, the output voltage of the charge pump 140 is controlled to be constant, and a stable capacitance value can always be obtained. In addition, even when characteristics are varied in the manufacturing process of the MOS transistor forming the loop filter 150, the influence of changing the CV characteristics of the capacity of the MOS transistor (the characteristics of the change in capacity when a voltage is applied to the gate). Can be prevented.

  As mentioned above, although this invention has been demonstrated based on each embodiment, this invention is not limited to the requirements shown in the said embodiment. With respect to these points, the gist of the present invention can be changed without departing from the scope of the present invention, and can be appropriately determined according to the application form.

100 PLL circuit 110, 120 Frequency divider circuit 130 Phase comparator 140 Charge pump 150 Loop filter 160 Voltage controlled oscillator (VCO)
170 Operational amplifier circuit

JP 2001-184778 A JP 2008-72597 A

Claims (6)

A phase comparator that compares the phase of the input signal with the phase of the output signal of the voltage controlled oscillation circuit and outputs a signal according to the phase difference;
A charge pump circuit for generating a charge / discharge current according to an output signal of the phase comparator;
A loop filter for smoothing the output of the charge pump circuit and generating a first control voltage;
A control voltage generation circuit that generates a second control voltage so that the first control voltage output from the loop filter becomes a predetermined voltage, and
A PLL circuit in which the first control voltage and the second control voltage are input to the voltage controlled oscillation circuit. The voltage controlled oscillation circuit is
A bias circuit and a ring oscillator;
The bias circuit includes:
A first bias circuit for converting the first control voltage into a current and supplying a current to a delay circuit of the ring oscillator;
The PLL circuit according to claim 1, further comprising: a second bias circuit that converts the second control voltage into a current and supplies the current to a delay circuit of the ring oscillator.   The PLL circuit according to claim 1, wherein a response of the control voltage generation circuit is slower than a response of the first control voltage. The voltage controlled oscillation circuit is
4. The PLL circuit according to claim 1, wherein a variation rate of an output frequency with respect to a variation in the first control voltage is smaller than a variation rate with respect to a variation in the second control voltage. 5. The control voltage generation circuit includes:
5. The PLL circuit according to claim 1, further comprising an operational amplifier circuit that controls the first control voltage by applying negative feedback so as to be a predetermined voltage and outputs the first control voltage to the voltage controlled oscillation circuit. 6. The loop filter has a capacitive element formed of a MOS transistor,
6. The PLL circuit according to claim 1, wherein the first control voltage is controlled to a voltage that becomes a saturation capacity of the MOS transistor. 7.

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