JP2011180409A - Electrophoretic display device and method of driving display panel - Google Patents

Abstract

An electrophoretic display device capable of performing display using intermediate gradations is provided.
A plurality of transistors, each of the plurality of transistors having a gate electrode connected to one of the plurality of gate lines, and one of a source electrode and a drain electrode connected to one of the plurality of data lines; A display panel in which the other of the source electrode and the drain electrode is connected to one of the two pixel electrodes for sandwiching the electrophoretic display material, and the brightness of the pixel of the image to be displayed on the display panel in one frame period There is provided an electrophoretic display device comprising: a control unit that applies voltage pulses of a number of times corresponding to a level between the pixel electrodes corresponding to the pixels.
[Selection] Figure 1

Description

  The present invention relates to an electrophoretic display device using an electrophoretic display material, a method for driving a display panel using the electrophoretic display material, and the like. In particular, the present invention relates to an electrophoretic display device capable of intermediate gray scale display using an electrophoretic display material, a driving method of a display panel using the electrophoretic display material, and the like.

  There is known an electrophoretic display device in which an electrophoretic display material in which charged particles are dispersed in a solvent is sandwiched between electrodes and an electric field is generated between the electrodes to move the charged particles and perform display (for example, , See Patent Document 1).

  Such an electrophoretic display device can be used as a reflective display device for electronic paper or the like. Such an electrophoretic display device has features such as a wide viewing angle compared to a display device using liquid crystal and low power consumption because memory characteristics can be stably obtained. Utilizing this feature, the electrophoretic display device is used for digital signage that displays information such as display devices such as electronic price tags, POP (Point of purchase advertising) advertisements in places such as transportation, stores, and public facilities. This display device is applied to an electronic book reader that takes in the contents of a book as electronic contents using a communication function whose market is rapidly expanding recently.

  In general, books can include illustrations and photographs. In addition, when displaying an advertisement or the like, there is a case where video information of a photograph is displayed. For this reason, the electrophoretic display device needs to display not only a monochrome binary image such as a character but also an intermediate gradation image.

  Intermediate gradation display is an indispensable display form in the field of electrophoretic display devices as well as in the field of liquid crystal display devices, but in general, pulse width modulation methods and voltage modulation methods are known. (For example, refer nonpatent literature 1.).

JP 2008-139738 A

R. Zehner, K .; Amundson, A.M. Knian, B .; Zion, M.C. Johnson and G. Zhou: SID '03 Symp. Digest, 126-129 (2002)

  In an electrophoretic display device, when active matrix driving is performed using a thin film transistor or the like, if the volume resistivity of the electrophoretic display material is small, the charge supplied with the thin film transistor turned on turns the thin film transistor off. Then, the inventors of the present invention have found that there is a problem in that an image cannot be sufficiently written with a good black-and-white contrast and an intermediate gradation due to leakage through the electrophoretic display material. Therefore, there is a problem that a conventionally known gradation display method cannot always be used effectively.

  One of the objects of the present invention is to solve the problem of insufficient image writing when the leakage current of an electrophoretic display material is large, and to provide a novel halftone display device and display panel driving method. is there.

  As one embodiment of the present invention, a plurality of transistors are provided, each of the plurality of transistors having a gate electrode connected to one of the plurality of gate lines, and one of the source electrode and the drain electrode being one of the plurality of data lines. A display panel connected to the other of the two electrode electrodes for sandwiching an electrophoretic display material between the source electrode and the drain electrode, and an image to be displayed on the display panel in one frame period An electrophoretic display device including a control unit that applies a voltage pulse corresponding to the lightness level of the pixel between the pixel electrodes corresponding to the pixel is disclosed.

  In one embodiment of the present invention, a plurality of transistors are provided, each of the plurality of transistors having a gate electrode connected to one of the plurality of gate lines, and one of the source electrode and the drain electrode being one of the plurality of data lines. A display panel driving method in which the other of the source electrode and the drain electrode is connected to one of two pixel electrodes for sandwiching an electrophoretic display material. Disclosed is a method for driving a display panel, wherein a writing voltage pulse is applied between the pixel electrodes corresponding to the pixels a number of times corresponding to the brightness level of the pixels of an image to be displayed on the display panel. .

  According to the present invention, an electrophoretic display device can be used to perform display using intermediate gradation as well as display using monochrome contrast. This is especially the case when the current leaked through the electrophoretic display material is large and the charge supplied from the drive power supply through the thin film transistor or the like is reduced, so that halftone display cannot be obtained without sufficient image writing. However, a good halftone display can be obtained.

1 is a functional block diagram of an electrophoretic display device according to Embodiment 1 of the present invention. 2A and 2B are a schematic view and a cross-sectional view of a crossing portion of a gate line and a data line in a display panel of an electrophoretic display device according to Embodiment 1 of the invention. It is a schematic diagram of the pixel in the display panel of the electrophoretic display device according to the first embodiment of the present invention. FIG. 3 is an equivalent circuit diagram of pixel elements in the display panel of the electrophoretic display device according to the embodiment of the invention. It is a figure which shows the relationship between the volume resistivity and holding time of the electrophoretic display material of the electrophoretic display device which concerns on embodiment of this invention. It is a graph which shows an example of the time change of the holding voltage in the display panel of the electrophoretic display device concerning the embodiment of the present invention. FIG. 6 is a diagram for explaining processing for calculating the number of times of applying a voltage according to the brightness of a pixel in the electrophoretic display device according to the first embodiment of the invention. 5 is a flowchart for explaining a driving process of the electrophoretic display device according to the first embodiment of the invention. 4 is a timing chart of pulses applied to gate lines and data lines in the display panel of the electrophoretic display device according to the first embodiment of the invention. It is a functional block diagram of the electrophoretic display device according to the second embodiment of the present invention. 6 is a timing chart of pulses applied to gate lines and data lines in a display panel of an electrophoretic display device according to a second embodiment of the invention. It is a functional block diagram of the electrophoretic display device according to the third embodiment of the present invention. 6 is a timing chart of pulses applied to gate lines and data lines in a display panel of an electrophoretic display device according to Embodiment 3 of the present invention. 6 is a graph showing changes in reflectance and contrast when an electrophoretic display device according to an embodiment of the present invention is actually operated. It is a figure which shows arrangement | positioning of the gate line in Example 1-6 of this invention, a data line, and a pixel element. It is a figure which shows the application of the voltage in Example 1 of this invention. It is a figure which shows the application of the voltage in Example 2 of this invention. It is a figure which shows the application of the voltage in Example 3 of this invention. It is a figure which shows application of the voltage in Example 4 of this invention. It is a figure which shows application of the voltage in Example 5 of this invention. It is a figure which shows application of the voltage in Example 6 of this invention.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described as embodiments and examples with reference to the drawings. The present invention is not limited to the embodiments and examples described below, and various modifications can be made without departing from the spirit of the invention.

(Embodiment 1)
FIG. 1 shows an example of a functional block diagram of an electrophoretic display device according to Embodiment 1 of the present invention. The electrophoretic display device 100 includes a display panel 101 and a control unit 102.

  The display panel 101 is an electrophoretic display panel in which an electrophoretic display material is sandwiched between a pair of substrates. In FIG. 1, the display panel 101 has gate lines G1, G2,..., Gm and data lines D1, D2,. One end of each of the gate lines G1, G2,..., Gm is connected to the gate line drive circuit 1021, and the voltage applied to each is controlled by the gate line drive circuit 1021. One end of each of the data lines D 1, D 2,..., D 1 is connected to the data line driving circuit 1022, and the voltage applied to each is controlled by the data line driving circuit 1022. On the other hand, an electrode is formed on the other substrate of the display panel 101 (not shown). Hereinafter, this electrode is referred to as a “substrate electrode” below. The substrate electrode is connected to the substrate electrode drive circuit 1023 via a bridge electrode (not shown), and the voltage applied to the substrate electrode is controlled by the substrate electrode drive circuit 1023. Note that the number of substrate electrodes formed on one side of the substrate need not be one. One of the substrates can be divided, and the number of substrate electrodes corresponding to the division can be appropriately formed.

  A plurality of transistors 104 are arranged on the display panel 101. The transistor 104 is disposed at a crossing position between the gate line and the data line. For example, a thin film transistor (thin film transistor) is used as the transistor 104. The gate electrode of the transistor 104 is connected to the gate line located at the crossing position, and the pixel electrode of the pixel element 105 described later is connected to the data line through the transistor 104. In other words, one of the source electrode and the drain electrode is connected to the data line located at the crossing position. The other of the source electrode and the drain electrode is connected to an electrode at one end of the pixel element 105. The other electrode (substrate electrode) of the pixel element 105 is connected to the substrate electrode drive circuit 1023. The electrode at one end (pixel electrode) of the pixel element 105 and the electrode at the other end (substrate electrode) opposite to the electrode are collectively referred to as “pixel electrode”. Each of the pair of pixel electrodes is formed on each opposing surface of the pair of substrates, and the electrophoretic display material is sandwiched therebetween. Therefore, by applying a voltage between the pixel electrodes, a predetermined voltage is applied to the electrophoretic display material sandwiched between the pixel electrodes. Note that the pixel electrode need not be in direct contact with the electrophoretic display material. For example, an electrophoretic display material may be enclosed in a capsule, and the capsule may be disposed between pixel electrodes.

FIG. 2A is an example of an enlarged schematic diagram of a crossing portion of a gate line and a data line. One end of the pixel element 105 is connected to the transistor 104. The pixel element 105 is connected to one of the data lines D1, D2,. When the voltage applied to the gate line is controlled by the gate line driver circuit 1021 and the transistor 104 is turned on, the voltage applied to the data line by the data line driver circuit 1022 and the other end of the pixel element by the substrate electrode driver circuit 1023 A difference from the voltage applied to the pixel element (hereinafter referred to as “write voltage”) is applied to the pixel element 105. A period during which the transistor 104 is turned on (hereinafter referred to as “gate selection time”) can be set in consideration of the number (m) of the gate lines G1, G2,. On the other hand, the gate selection time is also limited by the carrier mobility of the transistor. This is because the higher the carrier mobility, the faster the carrier can be injected from the transistor into the pixel electrode. Since the mobility of a general amorphous silicon transistor is 0.6 to 0.8 cm ² / (V · s), it is known that the gate selection time can be shortened to about 10 microseconds.

  As shown in FIG. 2A, the pixel element 105 includes a pixel 201 and an auxiliary capacitor 202. Further, the pixel 201 and the auxiliary capacitor 202 are connected in parallel. The pixel 201 is configured using two pixel electrodes and an electrophoretic display material sandwiched between the pixel electrodes. The auxiliary capacitor 202 is a capacitor. The auxiliary capacitor 202 makes it possible to continuously apply a predetermined voltage to the pixel 201 even when a transistor connected to one end of the pixel element 105 is in an off state and no data line voltage is applied to the pixel element 105. Used for. Note that in the case where the pixel 201 also functions as a capacitor, the auxiliary capacitor 202 may not be used.

  FIG. 2B illustrates an example of a cross section of the transistor 104 in the case where the display panel is cut in parallel to the data lines. A source / drain electrode 214 and a drain / source electrode 215 are formed on the substrate 211. “Source / drain electrode” and “drain / source electrode” mean that one electrode operates as a source electrode and the other operates as a drain electrode. The source / drain electrode 214 is connected to one of the plurality of data lines D1 to Dl, and the drain / source electrode 215 is connected to one of the pixel electrodes.

  The source / drain electrode 214 and the drain / source electrode 215 are formed separately, and a channel region is formed in the semiconductor thin film therebetween. An insulating film 212 is stacked over the source / drain electrode 214, the drain / source electrode 215, and the channel, and a gate electrode 216 is formed over the channel region. The gate electrode 216 is connected to one of the plurality of gate lines G1 to Gm.

  An insulating protective layer 213 is formed on the source / drain electrode 214, the drain / source electrode 215, the channel region, and the gate electrode, and one of the pixel electrodes is formed thereon. Note that in FIG. 2B, the structure of the thin film transistor is a top gate type in which the gate electrode is disposed above the channel region. However, the structure of the thin film transistor is not limited to the top gate type, and may be a bottom gate type in which the gate electrode is disposed below the channel region. The thin film transistor may be a silicon thin film transistor such as amorphous silicon, an oxide thin film transistor, or an organic thin film transistor.

  A substrate electrode 218 which is the other of the pixel electrodes is formed on the substrate 217 facing the substrate 211. The substrate electrode 218 is connected to the substrate electrode drive circuit 1023. Further, an electrophoretic display material is disposed and sealed between the pixel electrodes 219. Thus, the electrophoretic display material is sandwiched between the two pixel electrodes.

  3A and 3B are schematic views of a cross section of the pixel 201. FIG. 3A and 3B, for example, the pixel electrode 301 is connected to the substrate electrode driver circuit 1023, and the pixel electrode 302 is connected to the drain / source electrode 215 of the transistor 104 (pixel electrode). 301 may be connected to the drain / source electrode 215 of the transistor 104, and the pixel electrode 302 may be connected to the substrate electrode driver circuit 1023). Further, an electrophoretic display material is sandwiched and held between the pixel electrode 301 and the pixel electrode 302. At least one of the pixel electrode 301 and the pixel electrode 302 is a transparent electrode, and the electrophoretic display material is visible from the outside of the display panel 101. For example, a pixel electrode that is not connected to the drain / source electrode 215 and a substrate (not shown) on which the electrode is formed become transparent.

  The electrophoretic display material is obtained by dispersing a plurality of charged particles in a solvent such as a liquid. Each of the plurality of charged particles has a color such as black or white, and the charged particles of the same color are charged by the charges having the same polarity. If there are other charged particles of different colors, those charged particles of different colors are charged with different polar charges. Therefore, when a writing voltage is applied between the pixel electrode 301 and the pixel electrode 302 and an electric field is generated between the pixel electrode 301 and the pixel electrode 302, a charged particle of a certain color is generated by the electric field. Moves to one side of the pixel electrode 301 and the pixel electrode 302 and moves. Further, if charged particles of different colors are present, they migrate and move to the other side of the pixel electrode 301 and the pixel electrode 302. In addition, when an electric field having a reverse direction is generated between the pixel electrode 301 and the pixel electrode 302, charged particles of a certain color migrate to the other side of the pixel electrode 301 and the pixel electrode 302. Moving. If charged particles of different colors are present, they migrate to one of the pixel electrode 301 and the pixel electrode 302 and move.

  3A and 3B, for example, it is assumed that the pixel electrode 301 and the substrate (not shown) on which the pixel electrode 301 is formed are transparent. It is assumed that the charged particle 303 has a black color and is charged by a positive polarity charge. Further, it is assumed that the charged particles 304 are white and are charged with a negative polarity charge. When a voltage is applied to the pixel electrode 301 and the pixel electrode 302 and the voltage of the pixel electrode 301 is made larger than the voltage of the pixel electrode 302, an electric field in the direction from the pixel electrode 301 to the pixel electrode 302 is generated. As shown in FIG. 3A, the charged particles 303 move to the pixel electrode 302 side, and the charged particles 304 move to the pixel electrode 301 side. Thereby, when the electrophoretic display material is viewed from the pixel electrode 301 side, it looks white. That is, the pixel displayed by the pixel electrode 301 appears white. On the other hand, when the potential of the pixel electrode 302 is made higher than the potential of the pixel electrode 301, an electric field in the direction from the pixel electrode 302 to the pixel electrode 301 is generated, and as shown in FIG. Moves to the pixel electrode 301 side, and the charged particles 304 move to the pixel electrode 302 side. Thus, when the electrophoretic display material is viewed from the pixel electrode 301 side, it looks black. That is, the pixel displayed by the pixel electrode 301 appears black.

  In FIG. 3, when black charged particles 303 are present on the pixel electrode 302 side, white charged particles 304 are present on the pixel electrode 301 side, and black charged particles 303 are present on the pixel electrode 302. When present on the 301 side, the white charged particles 304 are shown to be present on the pixel electrode 302 side. However, the aspect of the presence of charged particles is not limited to these cases. For example, depending on the condition for applying the voltage, the black charged particles 303 and the white charged particles 304 may be mixed on the same electrode side. For example, when the black charged particles 303 and the white charged particles 304 are located on the pixel electrode 301 side, when the electrophoretic display material is viewed from the pixel electrode 301 side, it may appear gray.

  In addition, according to the number of charged particles having, for example, white color existing on the pixel electrode 301 side, how much white is determined when the electrophoretic display material is viewed from the pixel electrode 301 side. . In other words, the reflectance for white is determined. The number of charged particles existing on the pixel electrode 301 side is generally determined by the distribution of charged particles before the voltage is applied to the pixel electrode 301 and the pixel electrode 302, and the pixel electrode 301 and the pixel. Depends on the magnitude and time of the voltage applied to the working electrode 302. Therefore, the reflectance corresponding to the color of the charged particles of the electrophoretic display material changes. Therefore, the “response time” of the electrophoretic display material is defined as follows. That is, by applying a first DC voltage between two electrodes sandwiching the electrophoretic display material, the color displayed on one electrode side is set to the first color (for example, white), and then The first DC voltage is cut off. And after letting a state where there is no voltage difference between the two electrodes for a certain time or longer, a second DC voltage is applied between the two electrodes, and the color displayed on the one electrode side is Transition to the second color (for example, black). At this time, the time until the reflectance of the electrophoretic display material sandwiched between the two electrodes takes the maximum value or the minimum value by applying the second DC voltage is referred to as “response time”. Here, the reflectance refers to the reflectance of the color displayed by the electrophoretic display material. In other words, the time until the color displayed by the electrophoretic display material transitions from the first color to the second color by applying the second DC voltage is referred to as “response time”.

FIG. 4 shows an equivalent circuit of the pixel element 105. That is, FIG. 4 shows the pixel 201 shown in FIGS. 2 and 3 as a parallel circuit of a pixel capacitance and an electrical resistance made of an electrophoretic display material. Accordingly, when the transistor is turned off after the writing voltage is applied to the equivalent circuit in FIG. 4, a voltage (hereinafter, “ "Retained voltage" and "VH") is added, and the charged particles are moved to realize white or black color display. Such a transient phenomenon can be numerically analyzed using an equivalent circuit. According to this, the magnitude of the holding voltage varies depending on the magnitude of the electric resistance R. That is, the magnitude of the holding voltage is the sum of the auxiliary capacitor 202 (hereinafter referred to as “Cs”) and the electric capacitance of the pixel (hereinafter referred to as “C”) and the electric resistance of the pixel (hereinafter referred to as R). The decay time “TCR” that is the product of
TCR = (Cs + C) × R (Formula 1)
Using,
VH = VH0 × EXP (−t / TCR) (Formula 2)
It can be expressed as. In Expression 2, “VH0” is the magnitude of the holding voltage immediately after the transistor is turned off, and is substantially equal to the writing voltage, and “t” is an elapsed time starting from when the transistor is turned off. It is. Accordingly, both the writing voltage and the holding voltage are voltages applied to the pixel 201, whereas the writing voltage is a voltage applied to the pixel 201 during the gate selection time, whereas the holding voltage is the transistor This is an effective voltage applied to the pixel 201 when is turned off. The decay time corresponds to a time during which the charge of the pixel disappears due to a current that leaks through the electrophoretic display material (hereinafter referred to as “leakage current”). Therefore, as shown in Equation 2, the holding voltage (VH) decreases in a shorter time as the decay time is shorter.

  As shown in FIG. 5, when the elapsed time t is 0, VH / VH0 is 1 and the holding voltage is an initial value according to Equation 2. For example, when the elapsed time t is TCR, VH / VH0 is 0. 37, and when the elapsed time t is 5 × TCR, it is almost 0. Therefore, the charged particles are not subjected to any voltage due to the holding voltage at the time longer than 5 × TCR, and the electric field of the charged particles until then. If the migration due to the response is not completed, the image cannot be sufficiently written to the electrophoretic display panel.

Therefore, the magnitude of the decay time (TCR) becomes a problem. In general, when the electrical resistivity R of Equation 1 is used as the volume resistivity ρ,
R = ρ × d / S (Formula 3)
It can be expressed as. In Expressions 2 and 3, d is the thickness of the electrophoretic display material, and S is the area of the pixel electrode. From Equation 3, the larger the volume resistivity ρ, the longer the decay time, so that a constant holding voltage for a long time can be continuously applied to the electrophoretic display material.

The relationship between the time during which the magnitude of the holding voltage holds a predetermined value (for example, 90% of the initial value) (hereinafter referred to as “holding time”) and the volume resistivity is expressed by Equations 1 to 3. The obtained result is shown in FIG.
As shown in FIG. 6, when the volume resistivity is a certain value (for example, 10 ¹² Ωcm) or more, the response time (for example, 400 milliseconds) of the electrophoretic display material and the holding time are approximately the same. Therefore, since the holding voltage is maintained at a predetermined value or more during the response time period, for example, if one frame period is set as the response time, the gate lines G1, G2,. Only a selective scanning is performed, and a voltage is applied to each data line in synchronism therewith, so that a normal active matrix driving method can sufficiently write an image on the electrophoretic display panel.

  In this case, halftone display can be performed by controlling the amount of charge accumulated in the pixel capacitor and the auxiliary capacitor. The charge amount can be controlled by a conventional method such as a voltage modulation method or a pulse width modulation method.

On the other hand, when the volume resistivity (ρ) is 10 ¹² Ωcm or less, particularly about 10 ⁹ Ωcm, the holding time is about 1 millisecond (FIG. 6). Since it is significantly smaller than the response time (for example, 400 milliseconds), the holding voltage is almost zero during most of the response time. Therefore, even if one frame period is a response time (for example, 400 milliseconds), the gate selection time is shorter than the response time (for example, 100 microseconds), so that the gate lines G1, G2,. The image writing to the electrophoretic display panel cannot be sufficiently performed by a normal active matrix driving method in which selective scanning is performed only once and voltage is applied to each data line in synchronization therewith. Further, since the volume resistivity is as small as 10 ¹² Ωcm or less, for example, when the holding voltage decreases within the response time, it is difficult to control the brightness level of white display. For this reason, gradation control by the voltage modulation method or pulse width modulation method cannot be performed.

According to one embodiment of the present invention, an operation of applying a voltage pulse in the order of the gate lines G1, G2,..., Gm in one frame period, which is a time required to finish displaying one screen image, is performed a plurality of times ( n times), if a voltage pulse is applied to the pixel 201 in synchronization with the selection of the gate lines G1, G2,..., Gm, the pixel is charged according to the number of times the voltage is applied to the pixel 201. Since it is supplied continuously, the brightness level can be controlled. Therefore, even when the volume resistivity is small (for example, 10 ¹² Ωcm or less), the writing voltage of the number corresponding to the brightness level of the pixel of the image to be displayed on the display panel is applied for the pixel in one frame period. Since the brightness level can be controlled by applying between the electrodes, even if the volume resistivity is small (for example, 10 ¹² Ωcm or less), the gradation of the voltage modulation method or the pulse width modulation method is not used. Halftone display can be performed.

The volume resistivity of the electrophoretic display material according to one embodiment of the present invention is preferably 10 ⁷ Ωcm or more and 10 ¹² Ωcm or less. When the volume resistivity is less than 10 ⁷ Ωcm, the leakage current is large, and therefore the holding time is shortened, so that a sufficient monochrome display contrast cannot be obtained. In addition, when the volume resistivity is larger than 10 ¹² Ωcm, as described above, the leakage current is small, so that a gradation control method using a normal voltage modulation method or pulse width modulation method can be used effectively.

  In one embodiment of the present invention, for example, the reflectance of a predetermined color is set to a minimum or maximum state or a predetermined value, and the write voltage is applied between the pixel electrode 301 and the pixel electrode 302. The reflectance of the color can be controlled according to the number of times applied. One of the features of the present embodiment is that, for example, white reflectance is controlled by controlling the number of times that the voltage is applied for a shorter time than the length of the response time. The change in voltage from the start of application of the write voltage to the end of application is referred to as “write voltage pulse”. In general, the magnitude of the voltage with respect to the time of the write voltage pulse is preferably a square, but depending on the operation of the voltage generation circuit or the like, it may not be a strict square due to overshoot or undershoot. The pulse width of the write voltage pulse is usually the gate selection time described above.

  In addition, if the reflectance of the color of each pixel is calculated using the history of the voltage applied between the pixel electrodes, each pixel has the reflectance of the color and the like at the next time point. It is also possible to apply the write voltage by calculating the number of times that the write voltage pulse should be applied between the pixel electrodes using the reflectivity of the power color and the like.

  Note that one of the pixel electrode 301 and the pixel electrode 302 is a pixel electrode corresponding to the pixel, and the other of the pixel electrode 301 and the pixel electrode 302 is a substrate electrode corresponding to the pixel. In general, the substrate electrode is transparent, and an image can be seen from above the substrate electrode. In many cases, the pixel electrode is connected to the transistor 104. In many cases, the substrate electrode is connected to the substrate electrode driving circuit 1023. Therefore, by controlling the voltages of the gate lines G1, G2,..., Gm and the data lines D1, D2,..., Dl, different voltages can be applied to the pixel electrodes for each individual pixel element. On the other hand, a common voltage is applied to the substrate electrode. It is not essential that a common voltage is applied to all substrate electrodes. For example, when a plurality of substrate electrodes are formed, different voltages can be applied to the substrate electrodes.

  The control unit 102 applies a write voltage pulse of the number of times corresponding to the brightness level of the pixel of the image to be displayed on the display panel 101 between the pixel electrodes corresponding to the pixel in one frame period.

  The “one frame period” is a period during which control for displaying one still image on the display panel 101 is performed. In one embodiment of the present invention, the selection of the gate lines G1 to Gm is performed a predetermined number of times in order to display one still image. The time required to continuously select the gate lines G1 to Gm a predetermined number of times is one frame period. In other words, the “one frame period” is a period from the start to the end of the image writing process for displaying one image. That is, it is a period in which the gate lines G1, G2,..., Gm are selected a plurality of times, each being a predetermined number (n). In other words, this is the time required for the total number of voltage pulses that turn on the transistor 104 to be applied to the gate lines G1, G2,... Gm to be m × n. It does not include time for selecting pixels almost simultaneously and performing a predetermined process. Further, “one image” is an image to be displayed using the display panel 101. Usually, it is one still image.

  The “image pixel brightness level” is the brightness level of each pixel position on the display panel 101 when the image is displayed on the display panel 101. For example, if the pixel information represents an image using 8 bits for the brightness of each pixel, there are brightness levels from 0 to 255.

  “Number of times according to the lightness level of image pixels” means that when the electrophoretic display material can display a range from white to black, for example, the color of the pixels of the display panel 101 is white at the start of one frame period. In some cases, the smaller the lightness of the pixels of the image, the greater. Further, when the color of the pixel of the display panel 101 is black at the start of one frame period, it increases as the brightness of the pixel increases. “Brightness of image pixels” refers to the brightness of image pixels. For example, it is the brightness when the color of the pixel of the image is expressed by hue, brightness, and saturation.

  As an example of the configuration of the control unit 102, there is an example in which the control unit 102 includes an applied voltage control circuit 1025 and an application frequency control circuit 1024 described below.

  The applied voltage control circuit 1025 is a circuit that generates voltage pulses between the plurality of gate lines and the plurality of data lines and applies them between pixel electrodes.

  The control unit 102 (applied voltage control circuit 1025) causes the substrate electrode drive circuit 1023 to set the substrate electrode voltage to 0 V, for example, and causes the gate line drive circuit 1021 to turn on the transistor 104 to the gate lines G1, G2,. The voltage pulse to be applied is sequentially applied, and the data line driver circuit 1022 is made to apply a voltage pulse to the source electrode or the drain electrode of the transistor to which the pulse is applied by the gate line, and the pixel electrode 301, the pixel electrode 302, A write voltage pulse of a predetermined magnitude is applied during the period. For example, one frame period can be taken as the response time. At this time, the gate selection time is shorter than the response time. For example, the gate selection time can be greater than 0 and less than or equal to the length of time obtained by dividing the response time by the value of n × m. Here, n × m is the number of times a gate line is selected during one frame time. Further, one frame period can be longer than the response time or shorter. The voltage of the substrate electrode can be set to a constant value (for example, 0 V), or can be changed according to time such as an alternating voltage.

  For example, when displaying a black color or a color close to it when viewed from the substrate electrode side in the pixel at the intersection position of the gate line G1 and the data line D1 of the image to be displayed on the display panel 101, the gate line When a voltage pulse is applied to G1, the data line driving circuit 1022 applies a voltage pulse that keeps the black charged particles away from the pixel electrode of the pixel connected to the data line D1. If the black charged particles 303 are charged with a positive charge, a high voltage is applied to the data line D1 so that a voltage higher than the voltage of the substrate electrode is applied to the pixel electrode. For example, if the voltage of the pixel electrode is 0V, a positive voltage (for example, 15V) is applied to the data line D1. If the color of the solvent is black and the charged particles are white, a voltage is applied to keep the charged particles away from the substrate electrode.

  The application frequency control circuit 1024 applies the voltage pulse a number of times corresponding to the brightness level of the pixel of the image to the pixel electrode corresponding to the pixel in one frame period.

  The image can also be displayed in full color using the halftone display by forming a color filter on the substrate on which the substrate electrode is formed by a predetermined method. The charged particles are not limited to black charged particles, and for example, charged particles of any color such as red charged particles may be used. By using charged particles of each color such as red, blue, and green as the charged particles, an area color or full color display is performed by arranging charged particles of each color on a part of the display panel or a part of the pixels. You can also.

  FIG. 7 shows an example in which the control unit 102 (application number control circuit 1024) calculates the number of times that the application voltage control circuit 1025 applies a voltage pulse according to the brightness level of the pixel of the acquired image information. In a state before the voltage pulse is applied, the reflectance of a predetermined color such as white is in a minimum state, and by applying the voltage pulse a plurality of times, the reflectance of the color gradually increases. Therefore, for example, if the brightness level of the pixel is 0 or more and 63 or less, the applied voltage control circuit 1025 is used to apply no voltage to the corresponding pixel. If it is 64 or more and 127 or less, the applied voltage control circuit 1025 is used to apply a voltage once to the corresponding pixel. If it is 128 or more and 191 or less, the applied voltage control circuit 1025 is used to apply the voltage twice to the corresponding pixel, and if it is 192 or more and 225 or less, the application voltage control circuit 1025 is used. The number of times of voltage application is calculated such that the voltage is applied to the pixel to be applied three times. However, although “not applied with voltage” is described, there is a case where a voltage that does not substantially change the reflectance of the color is applied as in an embodiment described later.

  In the above example, the number of times of application of the voltage at which the maximum brightness can be obtained is three for convenience of explanation, but it may be several tens to several hundreds. The number of application times of the voltage at which the maximum brightness can be obtained also varies depending on the magnitude of the write voltage or the length of the gate selection time. For example, the gate selection time can be set to a value obtained by dividing one frame period by m × n if the number of repetitions of sequentially applying the voltage pulse by selecting the gate lines G1, G2,. it can. As an example, when one frame period is a response time (for example, 400 milliseconds), the number of gate lines (m) is 240, and the number of repetitions n is 30, the gate selection time is about 55 microseconds. Note that, when one frame period is fixed to the response time or the like, the number of gate lines can be increased as the gate selection time is shorter, so that higher-definition display is possible. Generally, in an amorphous silicon transistor, the gate selection time can be shortened to about 10 microseconds as described above. The gate selection time can be further shortened by using a thin film transistor (for example, a polycrystalline silicon transistor, an oxide transistor, or the like) having higher mobility. In addition, the number of repetitions (n) of sequentially selecting the gate lines G1, G2,..., Gm and applying the voltage pulse can be made equal to or larger than the number of application times of the voltage that can obtain the maximum brightness. For example, when the number of repetitions is 30 and the voltage is applied 10 times to obtain a predetermined brightness, the voltage is applied 10 times out of the 30 repetitions, and the remaining 20 times In such a case, no voltage is applied. In the above example, four gradation levels are illustrated, but the present invention can be applied to any gradation level.

  When the color reflectance is not in the minimum state, the brightness level of the pixel may be lower than the reflectance in that state. In this case, the negative number can be calculated according to the difference between the brightness level of the pixel and the level. In this case, when the absolute value of the negative number is large, the writing voltage is applied between the pixel electrodes so that the color reflectance becomes small. For example, the application number control circuit 1024 uses the application voltage control circuit 1025 to apply a positive number of voltages to the negative number of times and a potential difference opposite to the potential difference between the pixel electrode and the substrate electrode. Thus, a writing voltage is applied to the pixel electrode and the substrate electrode. In addition, the number of times of application at that time may be an absolute value of a negative number. As a specific example, it is assumed that the application number control circuit 1024 applies 15 V to the pixel electrode and 0 V to the substrate electrode by using the application voltage control circuit 1025 for each positive number. When -3 is calculated as the negative number of times, 0V is applied to the pixel electrode and 15V is applied to the substrate electrode three times.

  FIG. 8 is an example of a flowchart for explaining the flow of processing executed by the electrophoretic display device 100 according to this embodiment. In step S501, image information representing an image is acquired. The image information may be transmitted from the outside of the electrophoretic display device 100 or read from a storage circuit (not shown) of the electrophoretic display device 100. In step S502, the brightness level of each pixel of the image represented by the acquired image information is calculated. In step S503, the number of times of applying the write voltage pulse between the pixel electrode corresponding to each pixel and the substrate electrode is calculated using the calculated brightness level. In step S505, the application voltage control circuit 1025 is used to apply the number of write voltage pulses calculated in step S504 to the pixel electrode and the substrate electrode corresponding to each pixel.

  FIG. 9 shows an example of a timing chart of voltages applied to the gate lines G1, G2, G3,..., Gm and the data lines D1, D2,. In FIG. 9, T corresponds to one frame period. The gate lines G1, G2, G3,..., Gm are sequentially selected once during a time of T / n obtained by dividing T by n, and one write voltage pulse is applied. Therefore, each gate line is selected n times during one frame period, and the number of write voltage pulses calculated according to the brightness level of the pixel is applied to the pixel electrode and the substrate electrode.

  Referring to FIG. 9, in the first application, pulses P11, P21, P31,..., Pm1 are applied to the gate lines G1, G2, G3,. Similarly, in the n-th application, pulses P1n, P2n, P3n,..., Pmn are applied to the gate lines G1, G2, G3,.

  Further, each of the data lines D1, D2,..., Dl is applied with the voltage of d111, d121,..., D111, while P11 is applied to the gate line G1, and while P21 is applied to the gate line G2. d211, d221,..., d2l1 are applied. Therefore, for example, when the number-of-applications control circuit 1024 calculates the number of times k or −k for the pixel at the intersection position of the gate line G3 and the data line D2, d321, d322, d323,. Of these, k are voltages that change the reflectance of the pixel (for example, 15V or -15V depending on the sign of k), and the rest are voltages that do not substantially change the reflectance of the pixel (for example, 0V). Become. The first k pieces of d321, d322, d323,..., D32n may be the voltages that change the reflectance of the pixel. Alternatively, the last k may be used. Alternatively, k pieces may be selected at random from d321, d322, d323, ..., d32n.

  All of the gate lines G1, G2, G3,..., Gm may be selected once, and then all of the gate lines G1, G2, G3,. , Gm are all selected once, and after a predetermined time has elapsed, all of the gate lines G1, G2, G3,. You may come to be. A period in which all of the gate lines G1, G2, G3,..., Gm are selected once may be referred to as “one field period”.

Referring to FIG. 9, each gate line is selected a plurality of times within a time period T which is one frame period. This is because the volume resistivity (for example, 10 ⁹ Ωcm) of the electrophoretic display material is small only by selecting each gate line once in one frame period by normal active matrix driving, and therefore the leakage current of the electrophoretic display material is small. This is because when the voltage increases, the charge injected from the data line when the gate line is selected decreases, and the effective voltage (the above-mentioned holding voltage) applied to the electrophoretic display material decreases. For this reason, the change in reflectance becomes insufficient.

  As described above, the inventor of the present application pays attention to the phenomenon that the reflectivity of the electrophoretic display material changes according to the holding voltage, and applies the writing voltage between the pixel electrode corresponding to each pixel and the substrate electrode. The inventors have conceived that the holding voltage can be increased according to the number of times, and have found that halftone display can be performed.

  In this embodiment, the number of write voltage pulses corresponding to the brightness level of the pixel to be displayed is applied between the pixel electrode and the substrate electrode (between the pixel electrodes). It is possible to display gradation brightness and various colors.

(Embodiment 2)
As Embodiment 2 of the present invention, an electrophoretic display device that applies a voltage for erasing a displayed image before applying a write voltage pulse by a control unit will be mainly described.

  FIG. 10 shows an example of a functional block diagram of an electrophoretic display device according to Embodiment 2 of the present invention. The electrophoretic display device 700 includes a display panel 101 and a control unit 701. As an example of the configuration of the control unit 701, there is an example in which the image erasing circuit 702 is included, and an application voltage control circuit 1025 and an application frequency control circuit 1024 are used. Further, the electrophoretic display device 700 may include an applied voltage control circuit 1025, a gate line driving circuit 1021, a data line driving circuit 1022, and a substrate electrode driving circuit 1023 as necessary. Therefore, it can be explained that the electrophoretic display device according to the present embodiment has a configuration in which the electrophoretic display device according to the first embodiment further includes the image erasing circuit 702.

  In the present embodiment, an erasing voltage of any polarity is applied between the pixel electrodes before the writing voltage pulse is applied by the control unit 701. In this case, the erase voltage may be applied to all of the pixel electrodes almost simultaneously. This is because the display contents of all the pixels can be erased at a time and the application time of the erase voltage can be shortened.

  In the case where the image erasing circuit 702, the applied voltage control circuit 1025, and the applied number control circuit 1024 are provided in the control unit 701, a plurality of pixels are handled before voltage application by the applied number control circuit 1024. An erasing voltage that causes a potential difference is applied between the pixel electrode and the substrate electrode. Due to the erase voltage, a potential difference of any polarity is generated between the pixel electrode and the substrate electrode. The polarity, magnitude, and application time of the potential difference due to the erase voltage are appropriately set depending on how to set the color reflectance in the entire pixel of the display panel 101 after the erase voltage is applied.

  For example, if the entire pixel is to be black after applying the erasing voltage, if the black charged particles are charged with a positive charge, the potentials of all the substrate electrodes are made lower than all the pixel electrodes. The gate line driver circuit 1021, the data line driver circuit 1022, and the substrate electrode driver circuit 1023 are operated. For example, the substrate electrode driver circuit 1023 applies 0 V, the data line driver circuit 1022 applies 15 V to all data lines, and the gate line driver circuit 1021 turns on the transistors 104 to all gate lines. Apply voltage. Thereby, the erase voltage is applied to all the pixel electrodes almost simultaneously. The length of time during which the gate line driver circuit 1021 applies a voltage for turning on the transistor 104 to all the gate lines is preferably equal to or longer than the response time. This is because the charged particles cannot normally move from one electrode (for example, a pixel electrode) to the other electrode unless the application time of the erase voltage is equal to or longer than the response time. However, depending on the application state of the voltage before the erase voltage is applied, the length of time for applying the voltage for turning on the transistor 104 may be shorter than the response time.

  The image erasing circuit 702 may apply the erasing voltage in one or more times. For example, the erase voltage is applied five times every 100 milliseconds with a time interval of 50 milliseconds. Alternatively, when an erase voltage having a length of 500 milliseconds is applied, there is a time in which an erase voltage of 250 milliseconds is applied and a voltage of 100 milliseconds is not applied, and then an erase voltage of 250 milliseconds is applied. Good. Alternatively, an erase voltage of 200 milliseconds may be applied, and after an elapse of a time during which no voltage is applied, an erase voltage of 300 milliseconds longer than 200 milliseconds may be applied. Or, conversely, an erase voltage of 300 milliseconds is first applied, and after a time during which no voltage is applied, an erase voltage of 200 milliseconds is applied. In addition, when the erase voltage is applied in one or a plurality of times, the sum of the application time length of the erase voltage is preferably a response time or more, or depending on the voltage application situation before applying the erase voltage, etc. Less than response time may be preferred. A case where the erasing voltage is applied in a plurality of times by inserting a pause time during which no voltage is applied during voltage application is referred to as “applying the erasing voltage intermittently”.

  In addition, based on the voltage of the substrate electrode, “applying an erasing voltage that causes a potential difference between the pixel electrode corresponding to a plurality of pixels and the substrate electrode” means that the pixel electrode has any polarity. In other words, an erasing voltage is applied.

  FIG. 11 shows an example of a timing chart of voltages applied to the gate lines G1, G2, G3,..., Gm and the data lines D1, D2,. In accordance with the timing chart shown in FIG. 9, each gate line G1, G2, G3,..., Gm is applied before voltage is applied to the gate lines G1, G2, G3,..., Gm and the data lines D1, D2,. In addition, pulses pe 1, pe 2, pe 3,. At the same time, pulses de1, de2,..., Del are applied to the data lines D1, D2,. By applying such pulses pe1, pe2, pe3,..., Pem, de1, de2,..., Del, the display panel 101 displays an image of only a predetermined color, and pulses pe1, pe2, pe3,. , De1, de2,..., Del are erased. Et is preferably equal to or longer than the response time as described above, but may be preferably less than the response time in a predetermined case.

  After applying the pulses pe1, pe2, pe3,..., Pem, de1, de2,..., Del, the brightness level of the pixel of the acquired image information is calculated according to the flowchart of FIG. The number of times of applying the write voltage pulse is calculated, and the write voltage pulse is applied.

  According to the present embodiment, prior to displaying an image, the image displayed on the display panel before that is erased and a specific single color is displayed, so the influence of the image displayed before is eliminated. Thus, it is possible to easily display an image including an intermediate gradation.

(Embodiment 3)
As Embodiment 3 of the present invention, an electrophoretic display device that applies an alternating voltage between a pixel electrode and a substrate electrode before application of a write voltage pulse by a control unit will be described.

  FIG. 12 shows an example of functional blocks of an electrophoretic display device according to Embodiment 3 of the present invention. The electrophoretic display device 900 includes a display panel 101 and a control unit 901. As an example of the configuration of the control unit 901, there is an example further including an alternating voltage application circuit 902, an application voltage control circuit 1025, and an application frequency control circuit 1024. Further, the electrophoretic display device 700 may include a gate line driving circuit 1021, a data line driving circuit 1022, and a substrate electrode driving circuit 1023 as necessary. Therefore, the electrophoretic display device according to the present embodiment can be described as the configuration in which the electrophoretic display device according to the first embodiment further includes an alternating voltage application circuit 902.

  In the present embodiment, an alternating voltage is applied between the pixel electrodes prior to the application of the write voltage pulse. An alternating voltage is a voltage at which a positive voltage and a negative voltage alternate at a predetermined frequency. In general, the absolute values of the positive voltage and the negative voltage are substantially equal. However, the absolute values of the positive voltage and the negative voltage may be different. For example, it is a potential in which 15 V and −15 V are alternately repeated at 10 Hz. The alternating voltage may be applied to all of the pixel electrodes almost simultaneously.

  When the control unit 901 includes the alternating voltage application circuit 902, the alternating voltage application circuit 902 is substantially connected between the pixel electrodes corresponding to each pixel before the application voltage control circuit 1024 applies the write voltage pulse. A voltage that causes an alternating voltage is applied.

  In this embodiment, for example, the substrate electrode drive circuit 1023 applies 0 V, the data line drive circuit 1022 applies an alternating voltage to all the data lines, and the gate line drive circuit 1021 applies a transistor to all the gate lines. A voltage for turning on 104 may be applied. Thereby, an alternating voltage is applied between all the pixel electrodes almost simultaneously.

  In addition, on the basis of the voltage of the substrate electrode, “applying a voltage that generates an alternating voltage to the pixel electrode and the substrate electrode” can be said to apply an alternating voltage to the pixel electrode.

  The magnitude, frequency, pulse width, and application time of the positive voltage and the negative voltage of the alternating voltage are used to determine the color reflectance in the entire pixel of the display panel 101 after applying the alternating voltage, It is set appropriately depending on the above.

  FIG. 13 shows an example of a timing chart of voltages applied to the gate lines G1, G2, G3,..., Gm and the data lines D1, D2,. In accordance with the timing chart shown in FIG. 9, each gate line G1, G2, G3,..., Gm is applied before voltage is applied to the gate lines G1, G2, G3,..., Gm and the data lines D1, D2,. In addition, pulses pa1, pa2, pa3,..., Pam having a width of time Pt are applied almost simultaneously. At the same time, alternating voltages dp1, dp2,..., Dpl are applied to the data lines D1, D2,. By applying such pulses pa1, pa2, pa3,..., Pam, dp1, dp2,..., Dpl, the color reflectance of the display panel 101 changes at a predetermined frequency. After the application of the alternating voltage, the display panel 101 displays one color of reflectance according to the frequency of the alternating voltage, the maximum voltage, the minimum voltage, the application time, and the potential of the last pulse.

  The application time of the alternating voltage pulse is preferably equal to or shorter than the response time. However, when the application time of the alternating voltage pulse is less than or equal to the response time of the electrophoretic display material, the polarity of the last pulse of the alternating voltage may be selected when the pixel is selected to be black, for example. Since the charged particle response becomes insufficient and the migration distance of the charged particle becomes short, the black reflectance becomes higher than that after applying an erasing voltage to make the pixel black as in the second embodiment. There is a case. Therefore, as described in Embodiment 1, in the operation of the application number control circuit 1024, a negative number or the like needs to be used.

  Note that, by applying the alternating voltage, charged particles and ions existing around the charged particles respond to the alternating voltage. For this reason, the dispersibility of the charged particles and the like of the electrophoretic display material is enhanced, the aggregation of the charged particles is suppressed, and the movement of the charged particles between the pixel electrode and the substrate electrode is improved.

  Further, the electrophoretic display device according to the present embodiment may have an image erasing circuit like the electrophoretic display device according to the second embodiment. In this case, before the application voltage control circuit 1024 applies the write voltage pulse, the erase voltage and the alternating voltage are applied. An alternating voltage may be applied after the erasing voltage is applied, or an erasing voltage may be applied after the alternating voltage is applied. However, it is preferable to apply the alternating voltage before applying the erase voltage.

  Alternatively, instead of using an image erasing circuit, the last pulse of the alternating voltage can be erased by applying the fact that the display history of all pixels can be erased by applying the first several voltage pulses of the alternating voltage. Can be applied as a pulse. The application of the alternating voltage and the erase voltage is performed by applying the last pulse of the voltage pulse train when a voltage pulse train in which a positive voltage and a negative voltage applied alternately before the application of the write voltage pulse is applied. It can also be explained that the voltage pulse train to be excluded is an alternating voltage, and the last pulse of the voltage pulse train is a pulse of the erasing voltage. Therefore, the polarity of the last pulse of the alternating voltage is opposite to the polarity of the erase voltage.

  By applying the last pulse of the alternating voltage as a pulse that becomes an erasing voltage, the application of the alternating voltage includes the application of the erasing voltage, so that it is not necessary to further apply the erasing voltage exemplified in the second embodiment. Image writing on the display panel can be performed at higher speed. Here, the absence of display history means that the brightness of a pixel after application of an alternating voltage is not affected according to the brightness of the pixel immediately before application of the alternating voltage.

  In addition, when the last voltage pulse of the alternating voltage is caused to act as the erase voltage pulse as described above, the application time of the erase voltage is the same as the application time of the last voltage pulse of the alternating voltage. It may be long or long. If the application time of the erase voltage is the same as the application time of the last voltage pulse of the alternating voltage, the erase voltage can be applied as an alternating voltage and the circuit and other components can be simplified. . In addition, since the dispersibility of the charged particles is improved due to the influence of the alternating voltage applied before the erase voltage, the erase voltage is applied to the pixel in black or white with an application time equal to or shorter than the response time. Therefore, the length of the response time of the electrophoretic display material can be reduced.

  In the present embodiment, since an alternating voltage is applied, the movement of the charged particles between the pixel electrode and the substrate electrode becomes good. Further, since the last voltage pulse of the alternating voltage can be used as an erasing voltage, high-speed display such as intermediate gradation display of a higher quality image is possible.

(Measurement example)
Measurements were actually performed on changes in reflectance and contrast when the electrophoretic display device according to the embodiment described above was actually operated. That is, a general electrophoretic display material is held and sealed so as to be sandwiched between a pixel electrode and a substrate electrode, black charged particles are present on the substrate electrode side, and white charged particles are present on the pixel electrode. The black charged particles and the white charged particles are moved so that the white charged particles are present on the substrate electrode side and the black charged particles are present on the pixel electrode side. For this purpose, a predetermined write voltage pulse was applied between the pixel electrode and the substrate electrode. That is, applying a voltage pulse having a gate selection time of 100 microseconds to the gate line is repeated a predetermined number of times with a time interval of 100 milliseconds, and the data line has a predetermined voltage in synchronization with the selection of the gate line. The pulse was applied repeatedly.

  FIG. 14 shows the black reflectance, which is the black reflectance, the white reflectance, which is the white reflectance, and the white reflectance relative to the black reflectance, with respect to the number of times such voltage pulses are applied to the gate line. The graph of a change with the contrast which is a magnitude | size is shown.

  As shown in the graph of FIG. 14, it can be seen that the white reflectance increases as the number of times the voltage pulse having a gate selection time of 100 microseconds is applied to the gate line. It can also be seen that the contrast has also increased.

(Example)
Various embodiments of the present invention will be described with reference to FIGS.

  FIG. 15 is a schematic view of a display panel used in common with the embodiments of FIGS. Referring to FIG. 15, three gate lines G1, G2, and G3 are disposed, and two data lines D1 and D2 are disposed substantially orthogonal to the gate lines G1, G2, and G3. Pixel elements 1, 2, 3, 4, 5, and 6 are arranged at crossing positions of G1 and D1, G2 and D1, G3 and D1, G1 and D2, G2 and D2, and G3 and D2, respectively. In the embodiment shown in FIGS. 16 to 21, one frame period T includes nine field periods. Accordingly, pixel elements 1, 2, 3, 4, 5, and 6 are selected in the order of pixel elements 1 and 4, pixel elements 2 and 5, and pixel elements 3 and 6 in the first scan of the gate line. Scanning is performed repeatedly.

  Therefore, in the embodiment described below, for example, the application number control circuit 1024 can apply a maximum of nine write voltage pulses to each pixel element using the application voltage control circuit 1025. Also, before and after the application of the write voltage pulse for a maximum of nine times, the pixel element 1 has the largest change in the reflectance of the predetermined color, and then the pixel elements 2 and 5 have the pixel element 3 the next. The number of application of the write voltage pulse is controlled so that 4 continues. The pixel element 6 is controlled so that the reflectance does not change. For example, after application of a maximum of nine write voltage pulses, pixel element 1 becomes white, pixel elements 2 and 5 become slightly light gray, pixel elements 3 and 4 become gray, and pixel element 6 becomes black. To be controlled. In the following example, the case where the white charged particles are positively charged and the black charged particles are negatively charged is described as an example. However, the case where the polarity of the charge is reversed is the same as the method of the present invention. The method is applied.

Example 1
FIG. 16 is a diagram for explaining a case where the erase voltage is applied before the write voltage pulse of each number is applied to each pixel element. That is, it mainly corresponds to the second embodiment.

  As shown in FIG. 16, an erase voltage (denoted as a reset pulse in FIG. 16) is applied before the application of up to nine write voltage pulses. For example, as described above, the erasing voltage is applied by applying a voltage pulse to all the gate lines at the same time to apply the voltage pulse for turning on the transistor 104 between the pixel electrodes, and in synchronism with this, applying to all the data lines. This is done by applying an erase voltage. In addition, if the period during which the erase voltage is applied becomes longer, the gate selection time can be lengthened accordingly. For example, if the time for applying the erase voltage is about the response time, the gate selection time can be about the response time. The magnitude of the erase voltage is −V. By applying this erase voltage, all the pixel elements are black. Note that the erase voltage is preferably applied for a period of about the response time. For example, the erase voltage is applied for a response time or longer. This is because the reflectance is substantially minimized or substantially maximized by applying the erase voltage for a period of about the response time. Thereby, after application of the erase voltage, intermediate gradation display can be favorably performed by applying the write voltage pulse by the control unit. However, depending on the state of voltage application before applying the erase voltage, the dispersibility of the charged particles varies, so the erase voltage application period may be less than the response time.

  After the erase voltage is applied, the gate lines G1, G2, and G3 are sequentially scanned during T / 9, and a desired voltage is applied to each pixel element in synchronization with the data lines D1 and D2. In addition, a predetermined write voltage pulse is applied, and this is repeated nine times. The pixel element 1 is applied with a V write voltage pulse each time, the pixel elements 2 and 5 are applied with a 6 V write voltage pulse, and the pixel elements 3 and 4 are applied with 3 V The write voltage pulse is applied. Further, the pixel element 6 may be applied with 0V or −V may be applied each time. This is because the voltage of −V was applied as the erasing voltage, and therefore no substantial movement of the charged particles occurred even when 0V was applied or −V was applied.

  Note that the average voltage values obtained by applying the write voltage pulse after applying the erase voltage are V, 2V / 3, V / 3, and V / 3 for the pixel elements 1 to 6 as shown in FIG. 2V / 3, 0 or -V. The brightness of each pixel element is the brightness according to this average voltage value.

(Example 2)
FIG. 17 is a diagram for explaining a case where the control unit intermittently applies the erase voltage one or more times before applying the respective number of write voltage pulses to each pixel element. That is, it mainly corresponds to the second embodiment.

  As shown in FIG. 17, the application of the erase voltage -V and the non-application of the erase voltage are alternately repeated before the application of the maximum of 9 write voltage pulses. For example, as described above, the erase voltage is applied by applying a voltage pulse for turning on the transistor 104 to all the gate lines, and applying a voltage pulse to all the data lines in synchronization with this, between the pixel electrodes. The erasing voltage is applied alternately and the erasing voltage is not applied alternately. By applying a pulsed erase voltage (or intermittent erase voltage), all pixel elements are black.

  The reason why the intermittent erasing voltage is used is that when a DC voltage is continuously applied for a long time, the contrast is lowered due to so-called image sticking or solvent convection. By applying the erase voltage intermittently, the application time of the DC voltage can be shortened, and the deterioration of the contrast due to display burn-in and solvent convection can be suppressed, and the display quality can be improved.

  Further, it is preferable that the total application time of the intermittent erase voltage is about the response time. For example, the application time of the intermittent erase voltage is made longer than the response time. This is because the reflectance becomes substantially minimum or substantially maximum by applying such an intermittent erase voltage. As a result, halftone display can be satisfactorily performed by applying voltage pulses by the application frequency control circuit 1024. However, since the dispersibility of charged particles varies depending on the state of voltage application before the erase voltage is applied, the total erase voltage application period may be less than the response time.

  After the erase voltage is intermittently applied one or more times, the gate lines G1, G2, and G3 are sequentially scanned during T / 9, and in synchronization therewith, the data lines D1 and D2 have a desired pixel element. A predetermined voltage pulse is applied so that a voltage is applied, and this is repeated nine times. The pixel element 1 is applied with a V write voltage pulse each time, the pixel elements 2 and 5 are applied with a 6 V write voltage pulse, and the pixel elements 3 and 4 are applied with 3 V The write voltage pulse is applied. Further, the pixel element 6 may be applied with 0V or −V may be applied each time.

(Example 3)
FIG. 18 is a diagram illustrating a case where an alternating voltage is applied before the control unit applies each number of write voltage pulses to each pixel element. That is, it mainly corresponds to the third embodiment.

  As shown in FIG. 18, the voltages of V and -V are alternately applied before the voltage is applied nine times at the maximum. For example, as described above, the alternating voltage is applied by applying a voltage pulse for turning on the transistor 104 to all the gate lines, and applying a voltage pulse to all the data lines in synchronization with this, thereby alternating between the pixel electrodes. This is done by applying a voltage. Thereafter, the gate lines G1, G2, and G3 are sequentially scanned during T / 9, and a predetermined voltage is applied to the data lines D1 and D2 so that a desired voltage is applied to each pixel element in synchronization therewith. A pulse is applied and this is repeated nine times. The pixel element 1 is applied with a V write voltage pulse each time, the pixel elements 2 and 5 are applied with a 6 V write voltage pulse, and the pixel elements 3 and 4 are applied with 3 V The write voltage pulse is applied. Further, the pixel element 6 may be applied with 0V or −V may be applied each time.

  Since the alternating voltage is a voltage pulse that alternately transitions between positive polarity and negative polarity, the charged particles of the electrophoretic display material react to the polarity of the alternating voltage, for example, white charged particles and black charged particles Move in different electrode directions. Therefore, the electrophoretic display material has a predetermined reflectance according to the polarity of the last voltage pulse of the alternating voltage. The reflectivity of the electrophoretic display material realized by the voltage pulse with the last polarity of the alternating voltage has the same effect as when the erasing voltage is applied, so the alternating voltage is applied prior to the application of the write voltage pulse. When selecting the polarity of the last pulse of the alternating voltage as the polarity at which the image is to be erased, that is, by setting the polarity of the last pulse of the alternating voltage to the polarity of the erasing voltage, a new erasing voltage is obtained. Applying can be omitted. For this reason, intermediate gradation display can be performed in a short time.

  The frequency of the alternating voltage is preferably in the range of 10 hertz to 200 hertz, and more preferably in the range of 20 hertz to 100 hertz. If the frequency of the alternating voltage is small, for example, less than 10 Hz, it may be visually recognized that flicker is displayed on the display panel, and display quality may be impaired. In addition, since the ionic substance contained in the electrophoretic display material responds to a high frequency of about several tens of kilohertz, if the frequency of the alternating voltage is high, for example, exceeds 200 hertz, the effect of improving the dispersibility of charged particles may occur However, the followability of the charged particles to the alternating voltage is reduced. For this reason, intermediate gradation display may not be satisfactorily performed by application of the write voltage pulse.

Example 4
FIG. 19 shows a case where an alternating voltage is applied and an erasing voltage is applied in the order of the alternating voltage and the erasing voltage before the controller applies the writing voltage pulse of each number of times to each pixel element. It is a figure explaining about. That is, this corresponds mainly to the third embodiment, for example, when the electrophoretic display device according to the third embodiment has an image erasing circuit.

  As shown in FIG. 19, before applying a maximum of nine write voltage pulses per pixel element, first, an alternating voltage is applied by alternately applying voltages of V and -V, and erasing of -V. A voltage is applied. For example, as described above, the alternating voltage and the erasing voltage are applied by applying a voltage pulse for turning on the transistor 104 to all the gate lines, and applying a voltage pulse to all the data lines in synchronization with the voltage pulse. This is done by applying an alternating voltage and an erasing voltage in this order. Thereafter, the gate lines G1, G2, and G3 are sequentially scanned during T / 9, and a predetermined voltage pulse is applied to the data lines D1 and D2 so that a desired voltage is applied to each pixel element in synchronization therewith. Is applied and this is repeated nine times. The pixel element 1 is applied with a V write voltage pulse each time, the pixel elements 2 and 5 are applied with a 6 V write voltage pulse, and the pixel elements 3 and 4 are applied with 3 V The write voltage pulse is applied. Further, the pixel element 6 may be applied with 0V or −V may be applied each time.

  In this embodiment, it is preferable that the application time of the -V erase voltage applied after the application of the alternating voltage is shorter than the response time. Even if the erase voltage is not applied for about the response time, the alternating voltage is applied before the erase voltage is applied, so that the uniform dispersibility of the charged particles is increased. For this reason, within one frame period immediately after the application of the -V alternating voltage, it is considered that the movement of the charged particles by the application of the -V erasing voltage is improved, and the application of the erasing voltage smaller than the response time is applied. However, the reflectance can be made substantially minimum or substantially maximum. By applying an erasing voltage by the application number control circuit 1024, intermediate gradation display can be performed satisfactorily. If the application time of the erasing voltage becomes longer, convection of the solvent of the electrophoretic display material occurs, and the reflectance increases from the minimum reflectance or decreases from the maximum reflectance. In addition, by making the erase voltage application time shorter than the response time, the time required to display an image on the display panel can be shortened.

(Example 5)
FIG. 20 shows that the controller applies an alternating voltage and applies a pulsed erase voltage in order of the alternating voltage and the erase voltage before applying each number of write voltage pulses to each pixel element. It is a figure explaining the case where it performs. That is, it mainly corresponds to the third embodiment, for example, when the electrophoretic display device according to the third embodiment has an image erasing circuit, and the image erasing circuit applies a pulsed erasing voltage as a modification of the second embodiment. Corresponds to the case.

  As shown in FIG. 20, the voltages of V and -V are alternately applied before the application of a maximum of nine write voltage pulses per pixel element. Then, the erase voltage of −V is applied intermittently. For example, as described above, the intermittent application of the alternating voltage and the erasing voltage is performed by applying a voltage pulse that turns on the transistor 104 to all the gate lines and applying a voltage pulse to all the data lines in synchronization with this. This is performed by intermittently applying an alternating voltage and an erasing voltage between the electrodes. Thereafter, the gate lines G1, G2, and G3 are sequentially scanned during T / 9, and a predetermined voltage pulse is applied to the data lines D1 and D2 so that a desired voltage is applied to each pixel element in synchronization therewith. Is applied and this is repeated nine times. The pixel element 1 is applied with a V write voltage pulse each time, the pixel elements 2 and 5 are applied with a 6 V write voltage pulse, and the pixel elements 3 and 4 are applied with 3 V The write voltage pulse is applied. Further, the pixel element 6 may be applied with 0V or −V may be applied each time.

  Note that the sum of the intermittent erase voltage application times is preferably smaller than the response time. Even if the intermittent erasing voltage is not applied for a response time, the alternating voltage is applied before the erasing voltage is applied, so that the uniform dispersibility of the charged particles is increased. For this reason, it is considered that the movement of charged particles by application of an erasing voltage is improved, and the reflectance can be substantially minimized or substantially maximized even when an erasing voltage smaller than the response time is applied. As a result, halftone display can be satisfactorily performed by applying voltage pulses by the application number control circuit 1024. Further, by reducing the intermittent erasing voltage application time, the time required to display an image on the display panel can be shortened.

(Example 6)
FIG. 21 is a diagram illustrating a case where the control unit applies an alternating voltage before applying each number of write voltage pulses to each pixel element, and then applies a −V voltage pulse a predetermined number of times. is there. That is, this corresponds mainly to the third embodiment, for example, when the electrophoretic display device according to the third embodiment has an image erasing circuit.

  As shown in FIG. 21, the voltages of V and -V are alternately applied before the application of the write voltage pulse of up to nine times per pixel element. Then, a voltage pulse of −V is applied a predetermined number of times, and the alternating voltage is applied, for example, as described above, by applying a voltage pulse that turns on the transistor 104 to all the gate lines, and in synchronization with this, This is done by applying a voltage pulse to the data line and applying an alternating voltage between the pixel electrodes. Thereafter, the gate lines G1, G2, and G3 are sequentially scanned during T / 12, and a predetermined voltage pulse is applied to the data lines D1 and D2 so that a desired voltage is applied to each pixel element in synchronization therewith. Is applied and this is repeated 11 times. In the first two scans of the gate line, a −V write voltage pulse is applied to each pixel element a predetermined number of times (twice), and then a V write voltage pulse is applied to the pixel element 1 each time. Then, six V write voltage pulses are applied to the pixel elements 2 and 5, and three V write voltage pulses are applied to the pixel elements 3 and 4. The pixel element 6 may be applied with 0V each time or with a −V write voltage pulse.

  Voltage pulses of positive polarity and negative polarity are alternately applied by the alternating voltage. For this reason, the electrophoretic display material reacts to the polarity of the alternating voltage, and the white charged particles and the black charged particles move in opposite directions. Therefore, the electrophoretic display material has a predetermined reflectance according to the polarity of the last voltage pulse of the alternating voltage. That is, the reflectance set by the last voltage pulse of the alternating voltage has the same effect as the application of the erasing voltage, and the polarity of the plurality of voltage pulses applied by the application number control circuit 1024 is the alternating voltage. When the polarity of the last voltage pulse is reversed, it is not necessary to apply a new erase voltage. Therefore, it is possible to efficiently perform intermediate gradation display in a shorter time.

  However, depending on the configuration of the electrophoretic display device or the like, the reflectance obtained by the last voltage pulse of the alternating voltage does not reach a predetermined reference. The desired black state may not be obtained by the voltage pulse. Even in this case, according to the present embodiment, the first several times among the plurality of voltage pulses applied by the application number control circuit 1024 without newly applying the erase voltage to all the pixel elements almost simultaneously. The polarity of the write voltage is set to the same polarity as the last voltage pulse of the alternating voltage, and the polarity of the subsequent voltage pulse is reversed from the polarity of the last voltage pulse of the alternating voltage. As a result, it is possible to efficiently display intermediate gradations. Since the alternating voltage is applied by the application number control circuit 1024 prior to the application of a plurality of voltage pulses, the dispersibility of the white charged particles and the black charged particles of the electrophoretic display material is increased, and the application number control circuit applies the alternating voltage. The desired black state is obtained by the first few voltage pulses of the applied voltage pulse.

  In this embodiment, since the alternating voltage is first applied, the movement of the charged particles between the pixel electrode and the substrate electrode is caused by a phenomenon such as ions that existed around the charged particles are separated from the charged particles. It becomes good. Therefore, the time for applying the erase voltage is shorter than the response time. The same applies to other embodiments in which the alternating voltage is first applied.

    DESCRIPTION OF SYMBOLS 100 Electrophoretic display device, 101 Display panel, 102 Control part, 1021 Gate line drive circuit, 1022 Data line drive circuit, 1023 Substrate electrode drive circuit, 103 Application frequency control circuit, 1024 Application frequency control circuit, 1025 Application voltage control circuit

Claims (20)

A plurality of transistors, wherein each of the plurality of transistors has a gate electrode connected to one of the plurality of gate lines, one of the source electrode and the drain electrode connected to one of the plurality of data lines, and the source electrode and the drain A display panel in which the other electrode is connected to one of the two pixel electrodes for sandwiching the electrophoretic display material;
An electrophoretic display device comprising: a control unit that applies a voltage pulse of a number of times according to a lightness level of a pixel of an image to be displayed on the display panel in one frame period, between the pixel electrodes corresponding to the pixel. The electrophoretic display device according to claim 1, wherein the electrophoretic display material has a volume resistivity of 10 ¹² Ωcm or less.   2. The electrophoretic display device according to claim 1, wherein an erasing voltage of any polarity is applied between all the pixel electrodes substantially simultaneously before the application of the voltage pulse by the control unit. .   4. The electrophoretic display device according to claim 3, wherein the erase voltage is applied as one voltage pulse or a plurality of intermittent voltage pulses having the same polarity.   The electrophoretic display device according to claim 4, wherein a sum of application times of the plurality of voltage pulses is equal to or less than a response time of the electrophoretic display material.   The electrophoretic display device according to claim 1, wherein an alternating voltage is applied between all the pixel electrodes substantially simultaneously before the application of the voltage pulse by the control unit. 2. The erasing voltage of any polarity is applied after applying an alternating voltage between all of the pixel electrodes substantially simultaneously before applying the voltage pulse by the control unit. The electrophoretic display device described. The erase voltage is applied as one voltage pulse or a plurality of intermittent voltage pulses having the same polarity, and a sum of application times of the plurality of voltage pulses is equal to or less than a response time. Item 8. The electrophoretic display device according to Item 7.   The electrophoretic display device according to claim 7, wherein the polarity of the erasing voltage is opposite to the polarity of the last pulse of the alternating voltage.   The electrophoretic display according to claim 7, wherein the application time of the erasing voltage is equal to or longer than the application time of the last pulse of the alternating voltage and is equal to or shorter than the response time of the electrophoretic display material. apparatus. A plurality of transistors, wherein each of the plurality of transistors has a gate electrode connected to one of the plurality of gate lines, one of the source electrode and the drain electrode connected to one of the plurality of data lines, and the source electrode and the drain A display panel driving method in which the other electrode is connected to one of two pixel electrodes for sandwiching an electrophoretic display material,
In the display panel, a writing voltage pulse is applied between the pixel electrodes corresponding to the pixel in a number of times corresponding to a brightness level of a pixel of an image to be displayed on the display panel in one frame period. Driving method. 12. The display panel driving method according to claim 11, wherein the electrophoretic display material has a volume resistivity of 10 < ¹² > [Omega] cm or less.   12. The method of driving a display panel according to claim 11, wherein an erasing voltage having any polarity is applied between all the pixel electrodes substantially simultaneously before the application of the write voltage pulse. .   14. The display panel driving method according to claim 13, wherein the erase voltage is applied as one voltage pulse or a plurality of intermittent voltage pulses having the same polarity.   The display panel driving method according to claim 14, wherein a sum of application times of the plurality of voltage pulses is equal to or less than a response time of the electrophoretic display material.   12. The display panel driving method according to claim 11, wherein an alternating voltage is applied between all of the pixel electrodes substantially simultaneously before the writing voltage pulse is applied. The erasing voltage of any polarity is applied after applying an alternating voltage between all the pixel electrodes substantially simultaneously before applying the write voltage pulse. , Display panel drive method. The erase voltage is applied as one voltage pulse or a plurality of intermittent voltage pulses having the same polarity, and a sum of application times of the plurality of voltage pulses is equal to or less than a response time. Item 18. A display panel driving method according to Item 17.   The method of claim 17, wherein the polarity of the erase voltage is opposite to the polarity of the last pulse of the alternating voltage.   18. The display panel according to claim 17, wherein the application time of the erasing voltage is equal to or longer than the application time of the last pulse of the alternating voltage and equal to or shorter than the response time of the electrophoretic display material. Driving method.

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