JP2011165248A - Test system of semiconductor memory device and test program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To properly set the timing of generating a strobe signal in testing the operation of a semiconductor memory device. <P>SOLUTION: A test system 100 is configured to test the operation of a semiconductor memory device. A receiving section 110 receives data transmitted from the semiconductor memory device (DUT). A detection trial section 116 tries to detect data when the strobe signal is generated. A timing control section 112 changes the timing of generating the strobe signal. A detection range recording section 118 records the range of generation timing in which data are successfully detected, as a detection range. An operation test section 120 tests the operation after setting the timing of generating the strobe signal in the detection range. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a test system and a test program for a semiconductor memory device, and more particularly to a test system that controls a strobe signal.

  A large number of semiconductor memory devices such as a DRAM (Dynamic Random Access Memory) are simultaneously formed on a single silicon wafer. The formed DRAM group is subjected to a test for confirming the operation (hereinafter referred to as “operation test”), and is classified into a non-defective product and a defective product. A device that executes this operation test is called a “test system”.

  The test system normally supplies the same clock to a plurality of DRAMs formed on the same silicon wafer, operates the DRAMs simultaneously, and detects data transmitted from the DRAMs. The test system generates an internal signal called a strobe signal and tries to detect data at the timing when the strobe signal is generated.

JP 2008-210487A

  In the case of a DRAM having a DLL (Delay Locked Loop) circuit, the clock signal and the data signal are synchronized on the DRAM side. However, since the DLL circuit consumes a large amount of power, the mobile DRAM may not include the DLL circuit. Many. In such a DRAM, since the data signal and the clock signal are asynchronous, the time from when the test system instructs the DRAM to read data until the data reaches the test system (hereinafter referred to as “delay time”). Cause variations.

  In the case of a driving frequency band of about 400 Mbps, if the strobe signal generation timing is well set, data can be reliably captured even if the delay time varies somewhat. However, if the driving frequency of the DRAM is increased to 1000 Mbps or higher in the future, it is expected that the timing setting for generating the strobe signal will become severe.

  A test system according to the present invention is a system for executing an operation test of a semiconductor memory device. This system includes a detection trial unit that tries to detect data transmitted from a semiconductor memory device at a generation timing of a strobe signal, a timing control unit that changes the generation timing of the strobe signal, and a generation timing at which data detection is successful. A detectable range recording unit that records the range as a detectable range, and an operation test execution unit that executes an operation test after setting the generation timing of the strobe signal within the detectable range.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a recording medium, a computer program, and the like are also effective as an aspect of the present invention.

  According to the present invention, the generation timing of the strobe signal can be easily optimized for each operation test.

It is a hardware block diagram of a test system. It is a functional block diagram of a test system. It is a timing chart for demonstrating the relationship between general data reading and a strobe signal. It is a schematic diagram which shows the relationship between a drive frequency and an effective period. It is a schematic diagram of a data signal when the drive frequency is low. It is a schematic diagram of a data signal when the drive frequency is high. It is a flowchart which shows an operation | movement test process. It is a figure which shows an example of the data table which shows the result of a pretest.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a hardware configuration diagram of the test system 100. The test system 100 is connected to a plurality of DRAMs formed on a silicon wafer. Hereinafter, the DRAM that is the target of the operation test is referred to as “DUT”. The test system 100 in this embodiment simultaneously tests the operation of a total of 32 DRAMs DUT 1 to 32. A group of DUTs subject to one operation test is called a “DUT set”. It is needless to say that the number of DUTs included in the DUT set need not be limited to 32, and the optimum number may be appropriately determined in consideration of the test system 100 and DRAM design conditions, manufacturing conditions, and the like.

  The test system 100 supplies a common clock CLK to the DUT set and operates all the DUTs simultaneously. The test system 100 also issues various commands in common to all DUTs. For example, when “Read” is instructed to all DUTs, all DUTs send the data held at the designated address to the test system 100.

  When a predetermined delay time elapses after sending the read command, the test system 100 generates a strobe signal. The test system 100 attempts data detection at a timing at which a strobe signal is generated (hereinafter simply referred to as “strobe timing”). The delay time from when the read command is sent until the DUT sends data can be estimated in advance from the performance of the DUT. For this reason, generally, the strobe timing is fixedly set. The test system 100 executes an operation test of each DUT by transmitting a command and detecting data at the strobe timing.

  As will be described in detail later, when the drive frequency of the DUT increases, not only the setting of the strobe timing becomes severe but also it becomes difficult to set the strobe timing fixedly. Therefore, the test system 100 according to the present embodiment has a function of automatically optimizing the strobe timing.

  FIG. 2 is a functional block diagram of the test system 100. Each component of the test system 100 is centered on an arbitrary computer CPU, memory, a program that implements the components shown in the figure loaded in the memory, a storage unit such as a hard disk for storing the program, and a network connection interface. Realized by any combination of hardware and software. It will be understood by those skilled in the art that there are various modifications to the implementation method and apparatus. Each drawing described below shows a functional unit block, not a hardware unit configuration.

  The test system 100 includes an interface unit 102, a control unit 104, and a data holding unit 106. The interface unit 102 is a functional block that serves as an interface with the DUT. The control unit 104 is a functional block that performs overall control of data transmission / reception. The data holding unit 106 is a functional block that holds various data.

  The interface unit 102 includes a transmission unit 108 and a reception unit 110. The transmission unit 108 transmits a clock CLK and various commands to the DUT, and the reception unit 110 receives data transmitted from the DUT.

  The control unit 104 includes a timing control unit 112, a strobe signal generation unit 114, a detection trial unit 116, a detectable range recording unit 118, and an operation test execution unit 120. The strobe signal generation unit 114 generates a strobe signal. The timing control unit 112 controls the strobe timing. The detection trial unit 116 checks whether or not the receiving unit 110 has received data at the strobe timing. The detectable range recording unit 118 records the strobe timing and the success or failure of data detection in the data holding unit 106 in association with each other. Based on the recording result, a detectable range that is a strobe timing range in which data detection is possible is specified. The operation test execution unit 120 controls the operation test in an integrated manner.

  FIG. 3 is a timing chart for explaining the relationship between general data reading and strobe signals. A series A shown in the figure shows data read timing for a certain DUT set A. Series B shows the data read timing for DUT set B formed on a silicon wafer different from DUT set A.

  In the case of DUT set A, the data signals 0, 1, 2,... Reach the test system 100 when a predetermined delay time TDA has passed after the read instruction. According to the figure, the test system 100 can detect the data signal 0 during the effective period TE0A. In the following description, it is assumed that the DUT set A is the DUT set when the delay time is the shortest within the allowable delay time range. A DUT set having a delay time shorter than that of series A is determined as a defective product.

  In the case of DUT set B, the data signals 0, 1, 2,... Reach the test system 100 when a delay time TDB longer than the delay time TDA has elapsed after the read instruction. The test system 100 can detect the data signal 0 in the effective period TE0B. In the following description, it is assumed that DUT set B is the DUT set when the delay time is the longest within the allowable delay time range. A DUT set having a delay time longer than that of series B is determined as a defective product.

  The variation in delay time between DUTs included in the same DUT set is sufficiently smaller than the variation in delay time between DUTs included in different DUT sets.

  Since TDA <TDB, the effective period TE0B and the effective period TE0A are slightly shifted, but DUT set A and DUT set B share the effective period TE0. Therefore, if the strobe timing is set during the effective period TE0, the data signal 0 can be detected in either case of the DUT set A or B. Thus, even if the delay time varies for each DUT set, the strobe timing can be uniquely determined as long as there is a common effective period.

  FIG. 4 is a schematic diagram showing the relationship between the drive frequency and the effective period. The upper data signal D1 is a data signal at a certain driving frequency, and the lower data signal D2 indicates a data signal when the driving frequency is twice the data signal D1. The effective period TE1 is actually shorter than the length of D1, that is, the period in which the data signal transmitted from the DUT appears in the test system 100. This is because both ends of the data signal are cut off due to the influence of jitter or the like, and the effective period TE1 is shortened by the data undetectable period TX. The strobe timing ST1 is set during the effective period TE1.

  Since the drive frequency of the data signal D2 is twice the drive frequency of the data signal D1, the length of the data signal D2 is half the length of the data signal D1. Further, since the influence of the data non-detectable period TX is relatively greater than that of the data signal D1, the effective period TE2 is less than or equal to half of the effective period TE1. For this reason, in the case of the data signal D2, the setting of the strobe timing ST2 becomes extremely severe.

  FIG. 5 is a schematic diagram of a data signal when the drive frequency is low. As described with reference to FIG. 3, the data signal DA of the series A and the data signal DB of the series B can secure a sufficiently long common effective period TE although the effective period is narrowed by the data non-detectable period TX. . If the strobe timing ST is set during the effective period TE, either the data signal DA or DB can be handled. For this reason, the strobe timing can be set uniquely.

  FIG. 6 is a schematic diagram of a data signal when the driving frequency is high. In the case of a DRAM having a high driving frequency, the effective period is shortened as described with reference to FIG. For this reason, the effective period of the data signal DA and the effective period of the data signal DB do not overlap or only slightly overlap, and it becomes impossible to set the strobe timing corresponding to both the data signals DA and DB. In this case, the strobe timing STA for the data signal DA and the strobe timing STB for the data signal DB must be set separately.

  Further, when the drive frequency is increased, the variation in delay time between DUTs formed on the same silicon wafer cannot be ignored. The test system 100 collectively tests the 32 DUTs formed on the same silicon wafer. Although these DUTs are manufactured under the same manufacturing conditions, there is a slight variation in the threshold voltage of transistors due to variations in the silicon wafer surface. This slight variation causes delay time variation. When the drive frequency is low, the delay time variation between the DUTs included in the same DUT set hardly affects the operation test, but cannot be ignored when the drive frequency is high.

  FIG. 7 is a flowchart showing the operation test process. In the present embodiment, a pretest is executed before the operation test (S10). The purpose of the pretest is to find the optimum strobe timing for each DUT set. If the optimum value does not exist (N in S10), it is determined as a defective product without performing a subsequent operation test, and an out notification is made (S22). Details of the pretest will be described later with reference to FIG. If the optimum value of the strobe timing can be detected by the pretest (Y in S10), the strobe timing is determined (S12).

  Next, the operation test execution unit 120 sequentially executes an OPEN / LEAK test (S14), a COMMON test (S16), and a GRADE test (S18). S20). The OPEN / LEAK test is an electrical test for determining the presence or absence of insulation and a short circuit. The COMMON test is a logical test that sends a command to the DUT and measures whether it is operating as expected. The GRADE test is a performance test that ranks DUTs by measuring actual drive frequency, power consumption, and the like. Non-standard DUTs are determined to be defective. Also, rank notifications are made together with safe notifications for DUTs within the standard.

  In the COMMON test and the GRADE test, a strobe signal is used. The strobe timing for this purpose is set to an optimum value for each DUT set by pretest. The time required for a series of operation tests is about 60 seconds per time. Since the time required for the pretest is about 200 to 300 msec, the throughput of the operation test is hardly lowered by the pretest. Of course, when the drive frequency is low and the strobe timing can be fixed in advance, the pretest is unnecessary.

  FIG. 8 is a diagram illustrating an example of a data table indicating the result of the pretest. The timing control unit 112 changes the strobe timing by 0.02 nsec within a range of 2.00 to 6.00 nsec. Here, 2.00 to 6.00 nsec is a standard range acceptable as a strobe timing, and if an appropriate strobe timing cannot be found within this range, it is treated as a defective product.

  The timing control unit 112 first sets the strobe timing to 2.00 nsec. When 2.00 nsec has elapsed since the read command was transmitted (corresponding to CL: CAS Latency), the strobe signal generation unit 114 generates a strobe signal, and the detection trial unit 116 determines whether data has arrived from the DUT. Determine whether. If it has arrived, “P” is recorded in the corresponding part of the data table. According to FIG. 8, no data is detected for any of the 32 DUTs.

  Next, the timing control unit 112 sets the strobe timing to 2.02 nsec. The detection trial unit 116 tries data detection at a new strobe timing. Such processing is repeated until the strobe timing reaches 5.98 nsec.

  For example, in the case of DUT1, data is detected when the strobe timing is set to 5.00 to 5.28 nsec. This period is called the detectable range of DUT1. This detectable range corresponds to a valid period related to the data signal of DUT1. The detectable range of DUT2 is 4.96-5.24 nsec. Although DUT1 and DUT2 are formed on the same silicon wafer, their detectable ranges do not match. This is because a slight difference between DUT1 and DUT2 is obvious because the design drive frequency is high. Accordingly, in such a high frequency band, the DUT set formed on one silicon wafer and the DUT set formed on another silicon wafer usually have a large shift in the detectable range.

  The earliest data is detected in DUT4 (4.94 nsec), and the latest data is detected in DUT5 (5.06 nsec). Further, DUT4 (5.22 nsec) is the earliest data detected, and DUT4 (5.34 nsec) is the latest data detected. Therefore, when the strobe timing is in the range of 5.06 to 5.22 nsec, it is possible to detect data of all the DUTs included in this DUT set. Hereinafter, such a range is referred to as a “common detectable range”.

  The timing control unit 112 sets the strobe timing within this common detectable range (5.06 to 5.22 nsec). In the present embodiment, the median value is set to 5.14 nsec. Of the subsequent operation tests, the COMMON test and the GRADE test are executed at the strobe timing = 5.14 nsec. When the size of the common detectable range is equal to or smaller than a predetermined threshold value, or when the common detectable range is not found, the DUT set is determined as a defective product. Also, for example, when only DUT2 is out of the common detectable range, the other 31 DUTs are not treated as defective products, but all DUTs having a common detectable range (DUT1, 3 to 32 in the above) are used. ) May be set for the target.

  The test system 100 has been described above based on the embodiment. According to the test system 100, the optimum strobe timing is set for each DUT set. Further, the optimum setting is made in consideration of the variation between the DUTs included in the DUT set. In particular, even when the driving frequency is high and the effective period is shortened, the algorithm makes it easy to search for the optimum value of the strobe timing reasonably and precisely at high speed. Furthermore, since the high-speed pretest plays a role of a foot test, it is not necessary to perform a useless operation test, and as a result, the test process is made efficient as a whole.

  The present invention has been described based on some embodiments. Those skilled in the art will understand that these embodiments are examples, and that various modifications and changes are possible within the scope of the claims of the present invention, and that such modifications and changes are also within the scope of the claims of the present invention. It is where it is done. Accordingly, the description and drawings herein are to be regarded as illustrative rather than restrictive.

  100 test system, 102 interface unit, 104 control unit, 106 data holding unit, 108 transmission unit, 110 reception unit, 112 timing control unit, 114 strobe signal generation unit, 116 detection trial unit, 118 detectable range recording unit, 120 operation Test execution part.

Claims (6)

A system for executing an operation test of a semiconductor memory device,
A detection trial unit that attempts to detect data transmitted from the semiconductor memory device at the generation timing of the strobe signal;
A timing control unit for changing the generation timing of the strobe signal;
A detectable range recording unit that records a range of occurrence timing at which the data has been successfully detected as a detectable range;
An operation test execution unit that executes the operation test after setting the generation timing of the strobe signal within the detectable range;
A test system for a semiconductor memory device, comprising:   The test system according to claim 1, wherein the operation test execution unit sets a median value of the detectable range as a generation timing of the strobe signal. The detection trial unit collectively tries to detect data transmitted from a plurality of semiconductor memory devices based on the same strobe signal,
The detectable range recording unit, after specifying the detectable range for each of the plurality of semiconductor storage devices, further records a range where a plurality of types of detectable ranges overlap as a common detectable range,
The test system according to claim 1, wherein the operation test execution unit sets the generation timing of the strobe signal within the common detectable range.   The test system according to claim 1, wherein when the size of the detectable range is equal to or less than a predetermined threshold, the operation test is excluded from execution targets.   The test system according to claim 1, wherein when the detectable range does not fall within a predetermined range, the operation test is excluded from execution targets. A computer program for executing an operation test of a semiconductor memory device,
A function of trying to detect data transmitted from the semiconductor memory device at the generation timing of the strobe signal;
A function of changing the generation timing of the strobe signal;
A function of recording the range of occurrence timing at which the data is successfully detected as a detectable range;
A function for executing the operation test after setting the generation timing of the strobe signal within the detectable range;
A test program for a semiconductor memory device, characterized by causing a computer to exhibit the above.

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