JP2011146140A - Manufacturing method of flat-plate image display panel - Google Patents

Abstract

An object of the present invention is to provide a flat panel display panel suitable for enlargement of screen and high definition.
A method of manufacturing a flat panel display device comprising an envelope having a structure in which two substrates 2 and 3 are opposed to each other with a partition wall 10 interposed therebetween and the periphery thereof is sealed with a sealing layer 51. A step of applying a sealing material to at least one of the two substrates 2, 3; a step of forming a sealing layer 51 by fixing and pre-firing the applied sealing material; and the fixing The step of flattening the top portion of the sealing layer 51 in the pre-baked state and the two substrates 2 and 3 are overlapped via the flattened sealing layer 51, and the sealing layer is in that state. And a step of sealing by softening a flat image display panel.
[Selection] Figure 12

Description

  The present invention is a thin structure in which two substrates such as a plasma display panel (hereinafter referred to as PDP) and a field emission display (hereinafter referred to as FED) are opposed to each other with a partition wall and a screen (face) interposed therebetween. The present invention relates to a method for manufacturing a flat-panel image display panel (hereinafter also referred to as a display panel) having the envelope.

  Conventionally, PDP, FED, etc. are known as a display panel using a thin (flat plate type) envelope constituted by two opposing substrates. These display panels form a thin envelope by using a glass substrate as a substrate and sealing at least one outer peripheral portion of the two substrates with a glass sealing material made of low-melting glass.

  A manufacturing method for forming the envelope will be described with reference to FIGS. 7, 8, and 9.

  FIG. 7 shows the flow of the manufacturing process mainly for the part forming the envelope in the manufacturing method of the display panel. In FIG. 7, after the alignment (S32), a clip is attached ( FIG. 8 is a plan view showing the state after S34), and FIG. 9 is a cross-sectional view taken along line AA 'in FIG.

  First, after receiving the first substrate 2 and the second substrate 3, which are two opposing substrates, which the display panel 1 has (S 11 and S 21), the necessary structures as the display panel 1 are respectively provided. Steps for forming are carried out (not shown), and then the outer periphery of at least one of the substrates, for example, the outer periphery of the second substrate 3 in FIG. A sealing material 51 is formed by applying a paste of paste (S25) and fixing and baking it (S26).

  Next, these two substrates are placed opposite to each other on the stage 123 so as to sandwich the glass sealing material 51 (S31), aligned by the alignment mechanism 122 (S32), and then sandwiched by a certain amount with respect to the peripheral portion. A plurality of clips 121 having a force are pressed (S34) so as to be pressed and fixed in an aligned accuracy state, and the state is maintained.

  Then, the alignment mechanism 122 is removed. And after performing the sealing (S35) which heat-processes to the melting temperature of the glass sealing material 51 with the stage 123 in the state which mounted | wore with these several clips 121, a further required process is implemented (FIG. Not shown). Thereafter, the plurality of clips 121 are detached (S39), thereby completing the display panel 1 having the first substrate 2 and the second substrate 3 (S40) (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 1-211817

  However, the conventional techniques have the following problems. That is, the role of the plurality of clips 121 attached to the two substrates arranged opposite to each other was obtained by aligning the first substrate 2 and the second substrate 3 by the pressing force. It is to fix and maintain the relative positional accuracy in the opposing arrangement.

  For this purpose, in a display panel having a diagonal of more than 30 inches, the number of clips 121 must be at least 20 or more, and the number of clips must be increased as the size of the display panel increases. .

  However, in spite of mounting the clip 121 in this way, for example, after alignment (S32), in the next process and after, vibrations generated during conveyance, for example, during heat treatment in sealing (S35) Due to the unbalanced expansion and contraction of the first substrate 2 and the second substrate 3, there may be a relative displacement between the first substrate 2 and the second substrate 3.

  The influence of such a positional deviation becomes larger in the case of a large screen where high positional accuracy is required or in the case of high definition and a small pixel size, which adversely affects the quality of the displayed image.

  Such misalignment is caused when the sealing material paste is applied (S25) and fixed and pre-baked (S26), so that the glass sealing material 51 changes from the solid phase state to the liquid phase state and further from the liquid phase state. It is thought that this is largely due to factors that cause variations in shape at the stage of transition to the solid phase.

  The present invention has been considered in view of such a current situation, and an object of the present invention is to provide a method of manufacturing a display panel capable of suppressing a relative positional shift between two opposing substrates that occurs during manufacturing. And

  In order to achieve the above object, the flat image display panel manufacturing method of the present invention has an outer configuration in which two substrates are opposed to each other with a partition wall between them, and the periphery is sealed with a sealing layer. A method for producing a flat panel image display panel provided with a container, wherein a sealing layer is formed by applying a sealing material to at least one of two substrates, and fixing and firing the applied sealing material. A step of forming, a step of flattening a top portion of the sealing layer in the fixed and pre-fired state, and two substrates are overlapped via the flattened sealing layer, and the sealing is performed in that state. And a step of sealing by softening the adhesion layer.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the display panel which can suppress the relative positional shift of the two board | substrates which opposes which generate | occur | produces at the time of manufacture is realizable.

The perspective view which shows the principal part of PDP which is an example of the display panel manufactured by the manufacturing method of the display panel by one embodiment of this invention. Electrode arrangement of the PDP Circuit block diagram for driving the PDP Waveform diagram showing drive voltage waveform applied to each electrode of the PDP The exploded perspective view which shows the whole structure of the plasma display apparatus using the same PDP The top view which shows an example of arrangement | positioning which looked at the plasma display apparatus using the same PDP from the back side The figure which shows the manufacturing process flow of the display panel in a prior art The top view which shows the state which mounted | wore the clip after the alignment of the display panel in a prior art A-A 'sectional view in FIG. The figure which shows typically the cross section of the sealing layer before sealing in the PDP. The figure which shows the cross section before sealing in the conventional PDP typically Sectional drawing which shows typically the state in the sealing process in PDP which is an example of the display panel by one embodiment of this invention. Sectional drawing which shows the state in the sealing process in the conventional PDP typically Schematic for demonstrating an example of the method of planarizing the top part of the sealing layer in the PDP Schematic for demonstrating the manufacturing method of the display panel by other embodiment of this invention.

  Hereinafter, a method of manufacturing a display panel according to an embodiment of the present invention will be described with reference to the drawings. The embodiment of the present invention is not limited to this.

  First, a plasma display panel (PDP) will be described as an example of a display panel manufactured by a display panel manufacturing method according to an embodiment of the present invention.

  As shown in FIG. 1, a PDP 1 as an example of a display panel is configured by arranging a glass front substrate 2 and a back substrate 3 so as to face each other so as to form a discharge space therebetween. On the front substrate 2, a plurality of scanning electrodes 4 and sustaining electrodes 5 constituting display electrodes are formed in parallel with each other. A dielectric layer 6 is formed so as to cover the scan electrode 4 and the sustain electrode 5, and a protective layer 7 is formed on the dielectric layer 6.

  A plurality of data electrodes 9 covered with a base dielectric layer 8 are provided on the back substrate 3, and a grid-like partition wall 10 is provided on the insulator layer 8. A phosphor layer 11 is provided on the surface of the base dielectric layer 8 and the side surfaces of the barrier ribs 10. Further, the front substrate 2 and the rear substrate 3 are arranged to face each other with the partition wall 10 therebetween so that the scan electrode 4 and the sustain electrode 5 and the data electrode 9 cross each other. As the gas, for example, a mixed gas of neon and xenon is enclosed.

  The front substrate 2 and the back substrate 3 are bonded together by a sealing layer (not shown) formed in the peripheral part. Further, the structure of the panel is not limited to the above-described one, and for example, a light shielding layer (black stripe, black matrix) may be provided as necessary.

  FIG. 2 is an electrode array diagram of the PDP 1. N scan electrodes SC1 to SCn (scan electrode 4 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 5 in FIG. 1) are arranged in the row direction, and m data electrodes D1 to D1 are arranged in the column direction. Dm (data electrode 9 in FIG. 1) is arranged. A discharge cell is formed at a portion where a pair of scan electrode SCi and sustain electrode SUi (i = 1 to n) and one data electrode Dj (j = 1 to m) intersect, and the discharge cell is in the discharge space. M × n are formed.

  FIG. 3 is a circuit block diagram of a plasma display device using the PDP 1. The plasma display device includes a PDP 1, an image signal processing circuit 12, a data electrode drive circuit 13, a scan electrode drive circuit 14, a sustain electrode drive circuit 15, a timing generation circuit 16, and a power supply circuit (not shown).

  The image signal processing circuit 12 converts the image signal sig into image data for each subfield. The data electrode driving circuit 13 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm. The timing generation circuit 16 generates various timing signals based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to each drive circuit block. Scan electrode drive circuit 14 supplies drive voltage waveforms to scan electrodes SC1 to SCn based on timing signals, and sustain electrode drive circuit 15 supplies drive voltage waveforms to sustain electrodes SU1 to SUn based on timing signals. Here, the scan electrode drive circuit 14 and the sustain electrode drive circuit 15 include a sustain pulse generator 17.

  Next, a driving voltage waveform for driving the PDP 1 and its operation will be described with reference to FIG. FIG. 4 is a diagram showing drive voltage waveforms applied to the respective electrodes of the PDP 1.

  In the plasma display device according to the present embodiment, one field is divided into a plurality of subfields, and each subfield has an initialization period, a writing period, and a sustain period.

  In the initializing period of the first subfield, the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn are held at 0 (V), and from the voltage Vi1 (V) that is lower than the discharge start voltage with respect to the scan electrodes SC1 to SCn. A ramp voltage that gradually increases toward the voltage Vi2 (V) exceeding the discharge start voltage is applied. Then, the first weak initializing discharge is caused in all the discharge cells, negative wall voltages are stored on scan electrodes SC1 to SCn, and positive walls on sustain electrodes SU1 to SUn and data electrodes D1 to Dm. The voltage is stored. Here, the wall voltage on the electrode refers to a voltage generated by wall charges accumulated on the dielectric layer or the phosphor layer covering the electrode.

  Thereafter, sustain electrodes SU1 to SUn are maintained at positive voltage Vh (V), and a ramp voltage that gradually decreases from voltage Vi3 (V) to voltage Vi4 (V) is applied to scan electrodes SC1 to SCn. Then, the second weak initializing discharge is caused in all the discharge cells, the wall voltage between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn is weakened, and the wall voltage on data electrodes D1 to Dm is reduced. Is also adjusted to a value suitable for the write operation.

  In the subsequent writing period, scan electrodes SC1 to SCn are temporarily held at Vr (V). Next, negative scan pulse voltage Va (V) is applied to scan electrode SC1 in the first row, and data electrode Dk (k = 1 to 1) of the discharge cell to be displayed in the first row among data electrodes D1 to Dm. A positive write pulse voltage Vd (V) is applied to m). At this time, the voltage at the intersection between the data electrode Dk and the scan electrode SC1 is obtained by adding the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 to the externally applied voltage (Vd−Va) (V). And the discharge start voltage is exceeded. Then, a write discharge occurs between data electrode Dk and scan electrode SC1 and between sustain electrode SU1 and scan electrode SC1, and a positive wall voltage is accumulated on scan electrode SC1 of this discharge cell, and on sustain electrode SU1. And a negative wall voltage is also accumulated on the data electrode Dk.

  In this way, an address operation is performed in which an address discharge is caused in the discharge cells to be displayed in the first row and a wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the write pulse voltage Vd (V) is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so no write discharge occurs. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, positive sustain pulse voltage Vs (V) is applied to scan electrodes SC1 to SCn as a first voltage, and ground potential, that is, 0 (V) is applied to sustain electrodes SU1 to SUn as a second voltage. Apply. In the discharge cell in which an address discharge has occurred at this time, the voltage between scan electrode SCi and sustain electrode SUi is the sustain pulse voltage Vs (V), the wall voltage on scan electrode SCi and the wall on sustain electrode SUi. The voltage is added and exceeds the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and the phosphor layer emits light due to the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. At this time, a positive wall voltage is also accumulated on the data electrode Dk.

  In the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained. Subsequently, 0 (V) that is the second voltage is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs (V) that is the first voltage is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi, Negative wall voltage is accumulated on sustain electrode SUi, and positive wall voltage is accumulated on scan electrode SCi.

  Similarly, the sustain discharge continues in the discharge cells that have caused the write discharge in the write period by alternately applying the number of sustain pulses corresponding to the luminance weight to the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn. Done. Thus, the maintenance operation in the maintenance period is completed.

  The operations in the initialization period, the writing period, and the sustain period in the subsequent subfield are almost the same as those in the first subfield, and thus the description thereof is omitted.

  FIG. 5 shows an example of the overall configuration of the plasma display device incorporating the PDP 1 having the structure described above. FIG. 6 shows an example of the arrangement of the drive circuit blocks as viewed from the back side.

  The PDP 1 is bonded to the chassis member 21 with a heat radiating sheet (not shown in FIG. 5) interposed between the front surface of the chassis member 21 serving as a holding plate that also serves as a metal heat radiating plate such as aluminum. It is held by bonding with a material or the like. Further, as shown in FIG. 6, a plurality of drive circuit blocks for driving the display of the PDP 1 are arranged on the rear side of the chassis member 21, thereby constituting a module.

  Here, the heat-dissipating sheet is used for adhering and holding the PDP 1 to the front side of the chassis member 21, efficiently transferring the heat generated in the PDP 1 to the chassis member 21, and radiating heat, and has a thickness of 1 mm. About 2 mm. As this heat radiating sheet, an insulating heat radiating sheet in which a synthetic resin material such as acrylic, urethane, silicon resin, or rubber contains a filler that enhances thermal conductivity, a graphite sheet, a metal sheet, or the like can be used. In addition, the heat radiation sheet itself has an adhesive force, and the PDP 1 is bonded to the chassis member 21 with only the heat radiation sheet, or the heat radiation sheet has no adhesive force, and the PDP 1 is separately attached using a double-sided adhesive tape or the like. The structure etc. which adhere | attach on the chassis member 21 can be used.

  In addition, flexible wiring boards 22 as display electrode wiring members connected to the electrode lead portions of the scan electrodes 4 and the sustain electrodes 5 are provided on both side edges of the PDP 1, and on the back side through the outer peripheral portion of the chassis member 21. The drive circuit block 23 of the scan electrode drive circuit 14 and the drive circuit block 24 of the sustain electrode drive circuit 15 are connected via a connector.

  On the other hand, a plurality of flexible wiring boards 25 as data electrode wiring members connected to the electrode lead-out portions of the data electrodes 9 are provided on the lower and upper edges of the PDP 1. The plurality of data drivers 26 of the electrode driving circuit 13 are electrically connected to each other, routed to the back side through the outer periphery of the chassis member 21, and disposed at the lower and upper positions on the back side of the chassis member 21. The drive circuit block 27 of the data electrode drive circuit 13 is electrically connected.

  The control circuit block 28 is provided with an input terminal portion to which a connection cable for connecting to an external device such as a television tuner is detachably connected. Based on the video signal sent from the input signal circuit block 29, the control circuit block 28 receives image data. An image data signal corresponding to the number of pixels of the PDP 1 is converted and supplied to the drive circuit block 27 of the data electrode drive circuit, and a discharge control timing signal is generated, and the drive circuit block 23 and the sustain electrode of the scan electrode drive circuit 14 are generated. This is supplied to the drive circuit block 24 of the drive circuit 15 and performs display drive control such as gradation control, and is arranged at substantially the center of the chassis member 21.

  The power supply block 30 supplies a voltage to each of the circuit blocks. Like the control circuit block 28, the power supply block 30 is disposed at a substantially central portion of the chassis member 21, and is commercialized through a connector to which a power supply cable (not shown) is attached. A power supply voltage is supplied. These drive circuit blocks 23, 24, 27, control circuit block 28, input signal circuit block 29, and power supply block 30 are fixed to the boss portion provided on the back side of the chassis member 21 with screws or the like.

  Further, a cooling fan 31 is disposed in the vicinity of the drive circuit blocks 23 and 24 while being held at an angle 32 so that the drive circuit blocks 23 and 24 are cooled by the wind sent from the cooling fan 31. It is configured. Further, the drive circuit block 27 of the data electrode drive circuit 13 disposed at the upper position is cooled at the upper position of the chassis member 21, and on the rear side of the chassis member 21, the entire apparatus is moved from the lower portion toward the upper portion. Three cooling fans 33 are arranged to cool the inside of the apparatus by causing an air flow.

  Further, reinforcing angles 34 and 35 are fixed to the chassis member 21 in a horizontal direction and a vertical direction, and the angle 34 arranged in the horizontal direction is a stand for holding the apparatus in an upright state. The pole 36 is fixed with screws or the like.

  The module having the above-described structure includes a housing having a front protective cover 37 disposed on the front side of the PDP 1 and a metal back cover 38 disposed on the rear side of the chassis member 21. Thus, the plasma display device is completed. Here, the front protective cover 37 is attached to the front frame 39 made of a resin or metal having an opening 39a in which the image display area on the front side of the PDP 1 is exposed, and the opening 39a of the front frame 39, and is optical. A protective plate 40 made of glass or the like provided with a filter or an unnecessary radiation suppressing film for suppressing unnecessary radiation of electromagnetic waves. The peripheral portion is attached to the front frame 39 by sandwiching the peripheral portion between the peripheral portion of the opening 39a of the front frame 39 and a protective plate pressing metal fitting (not shown). Further, the back cover 38 is provided with a plurality of vent holes (not shown) for releasing heat generated by the module to the outside.

  In FIG. 5, reference numeral 41 denotes a screw for attaching the back cover 38 to the chassis member 21, and 42 denotes a gripping part attached to the back cover 38 with a screw or the like.

  Next, a method for manufacturing the PDP 1 having the above-described structure will be described below. First, the scanning electrode 4 and the sustain electrode 5 and, if necessary, a light shielding layer (black stripe, black matrix) are formed on one main surface of the front substrate 2.

Scan electrode 4 and sustain electrode 5 are configured by a transparent electrode made of indium tin oxide (ITO), tin oxide (SnO ₂ ), or the like, and a metal bus electrode made of silver paste or the like formed thereon. These electrodes are formed by patterning using a photolithography method or the like. These electrode material layers are fired and solidified at a desired temperature. Similarly, the light-shielding layer (not shown) is obtained by screen printing a paste containing a black pigment or by forming a black pigment on the entire surface of the glass substrate, patterning it using a photolithography method, and baking and solidifying it. It is formed.

  Next, a dielectric paste layer (dielectric material layer) is formed by applying a dielectric paste on the front substrate 2 by a die coating method or the like so as to cover the scan electrode 4, the sustain electrode 5 and the light shielding layer (not shown). To do. After the dielectric paste is applied, the surface of the applied dielectric paste is leveled by leaving it to stand for a predetermined time, so that a flat surface is obtained. Thereafter, the dielectric paste layer is baked and solidified to form the dielectric layer 6 that covers the scan electrode 4, the sustain electrode 5, and the light shielding layer. The dielectric paste is a paint containing a dielectric material such as glass powder, a binder and a solvent.

  Next, a protective layer 7 made of, for example, magnesium oxide (MgO) is formed on the dielectric layer 6 by, for example, a vacuum deposition method. Through the above steps, predetermined components (scanning electrode 4, sustaining electrode 5, light shielding layer, dielectric layer 6, and protective layer 7) are formed on front substrate 2.

  On the other hand, on the main surface of the back substrate 3, the structure for the data electrode 9 is formed by a method of screen printing a silver paste or a method of forming a metal film on the entire surface and then patterning using a photolithography method. A data electrode 9 is formed by forming a material layer and baking and solidifying the material layer at a desired temperature.

  Next, a dielectric paste is applied on the back substrate 3 on which the data electrodes 9 are formed so as to cover the data electrodes 9 by a die coating method or the like, thereby forming a dielectric paste layer. Thereafter, the base dielectric layer 8 is formed by firing the dielectric paste layer. The dielectric paste is a paint containing a dielectric material such as glass powder, a binder and a solvent.

  Next, a partition wall forming paste containing partition wall material is applied onto the underlying dielectric layer 8 and patterned into a predetermined shape to form a partition wall material layer, and then the partition wall 10 is formed by baking and solidifying. Here, as a method of patterning the partition wall paste applied on the underlying dielectric layer 8, a photolithography method or a sand blast method can be used.

  Next, the phosphor layer 11 is formed by applying a phosphor paste containing a phosphor material on the base dielectric layer 8 between the adjacent barrier ribs 10 and on the side faces of the barrier ribs 10 and baking and solidifying the phosphor material. Through the above steps, predetermined components (data electrode 9, base dielectric layer 8, barrier rib 10, phosphor layer 11) are also formed on back substrate 3.

  From the above-described steps, the front substrate 2 and the rear substrate 3 each having a predetermined component are disposed so as to face each other so that the scan electrode 4 / sustain electrode 5 and the data electrode 9 intersect. The periphery is sealed with a sealing layer 51 formed of glass frit 51a, and a discharge gas containing neon, xenon, or the like is sealed in the discharge space to complete the panel.

  Here, in forming the sealing layer 51 described above, a frit glass paste is prepared by kneading glass frit containing bismuth or lead with a resin and a solvent, and the frit glass paste is obtained by screen printing or an injection method. Then, it is applied to the front substrate 2 or the back substrate 3 as schematically shown in FIG. 10 (a), and then heated to such an extent that the resin component can be removed. A method of firing is adopted.

  At this time, the sealing layer 51 at the stage of fixing and pre-firing is flat so that the top portion thereof is schematically shown as the cross-sectional shape of the sealing layer 51 in FIGS. Forming. Here, as an example of a method of forming a flat film, as shown in FIG. 14, a wrapping film 52 having a predetermined particle size is applied to an elastic contact roll 54 having a rotation axis directed in a certain direction. And a method of performing polishing by scanning the applied front substrate 2 or back substrate 3 while pressing the film against the top of the sealing layer 51 that has been fixed and pre-fired. . According to this method, it is possible to efficiently polish and flatten the top of the sealing layer 51 at the stage of fixing and pre-firing.

  In this case, it is possible to adjust the height more accurately by measuring the top of the sealing layer 51 with a height measuring sensor and feeding back the value.

  Further, in the method using polishing as described above, if “scraping residue” generated by polishing is mixed in the image display area of the display panel, an abnormality occurs when displaying an image after the display panel is completed. It may cause discharge. When such abnormal discharge occurs, there is a risk of causing a fatal defect as a display panel such as dielectric breakdown.

  Thus, for example, if the substrate is moved in two steps parallel to the direction perpendicular to the long side of the substrate, only the top of the sealing layer 51 can be polished, In addition, it is possible to prevent “shaving residue” generated during polishing from entering the image display area.

  Another method is to cover the image display area with a cover film or the like during the polishing step.

  In addition, in order to polish the sealing layer at the stage of fixing and pre-firing, it is possible to use a wrapping film 52 having an abrasive particle size of No. 600 to 2000, which can be planarized efficiently in terms of time. It has been confirmed by the inventor's examination that this is possible.

  As described above, with respect to the so-called sealing step, which is a step of bonding the front substrate 2 and the rear substrate 3 with the sealing layer in the fixing pre-baking stage in which the top portion is flattened, This will be described below.

  First, a sealing process in a conventional display panel will be described. FIG. 11 is a diagram schematically showing a state of the sealing layer 151 before pasting (bonding) in a PDP which is an example of a display panel manufactured by a conventional display panel manufacturing method. 11A is a plan view schematically showing the back substrate 103, and FIGS. 11B and 11C are an AA sectional view and a BB sectional view in FIG. 11A, respectively. It is a figure which shows typically the cross-sectional shape of the sealing layer 151. FIG.

  Here, as shown in FIG. 11, the sealing layer 51 at the fixing and pre-firing stage is prepared by applying a frit glass paste obtained by kneading glass frit containing bismuth or lead with a resin and a solvent onto the back substrate 103 by screen printing or an injection method. It is applied and then heated to such an extent that the resin component can be removed and fixed and prefired, and the top is not flattened.

  13A, the sealing layer 151 in the state shown in FIG. 11 is overlapped with the front substrate 2 with the clip 121 between the front substrate 2 and the rear surface. The substrate 3 is sandwiched at the periphery. In this state, the front substrate 2 and the rear substrate 3 are pasted together by heating and melting to a temperature at which the sealing layer 151 in the fixed temporarily fired state is softened.

  Here, as shown in FIG. 11 and FIG. 13A, the top of the sealing layer 151 in the fixed pre-fired state is not flat but full of irregularities, and therefore the front substrate 2 and the rear substrate 3 are not sealed. It is in contact with only a part of the adhesion layer 151, and there are variations in the timing at which the sealing layer 151 dissolves at the time of heating, and even if the timing is the same, it is distributed over the area of the contact area. Therefore, as shown schematically in a cross-sectional view in FIG. 13B, an alignment shift of about 30 μm may occur between the front substrate 2 and the rear substrate 3 after sealing.

  As shown in (Table 1), in the conventional cell size (long side cell pitch (long side pitch): 600 to 700 μm), there is no increase in the discharge voltage if the deviation is about 30 μm. However, in the high-definition cell size (cell pitch on the long side: 200 to 300 μm), there has been a problem that the discharge voltage suddenly increases and the efficiency decreases accordingly.

  On the other hand, according to the method for manufacturing the display panel according to the embodiment of the present invention, the sealing layer 51 at the stage of being fixed and pre-fired as schematically shown in the sectional view of FIG. Since the top portion of the substrate is flattened, the ground contact area between the front substrate 2 and the sealing layer 51 is greatly increased. Therefore, the front substrate 2 and the rear substrate 3 are schematically shown in FIG. As shown in the cross-sectional view, it becomes difficult to shift from the state of being overlapped and sandwiched between clips. As a result, the present inventor confirmed that it is possible to suppress misalignment after sealing to 10 μm or less, thereby preventing an increase in discharge voltage. In order to suppress the misalignment to 10 μm or less, the range of the difference between the maximum value and the minimum value of the sealing layer 51 needs to be 10 μm or less.

  That is, as a result of the process of flattening the top portion of the sealing layer 51 at the stage of fixing and pre-firing, the sealing layer 51 in the pre-fixing pre-firing state is a substrate coated with a height (in the above description, Within the back substrate 3), the height is substantially the same. As a result, the bonded front substrate 2 and rear substrate 3 after sealing are sealed in a state in which misalignment is suppressed and in a state of being overlapped substantially in parallel.

  According to the study of the present inventor, the amount of misalignment was about 10 μm when the height of the sealing layer 51 in the fixed pre-fired state was about 150 μm higher than the partition wall height. On the other hand, when the height of the sealing layer 51 in the fixed pre-fired state is about 100 μm higher than the partition wall height, it has been found that the amount of misalignment can be reduced to 5 μm. . That is, in the polishing step for flattening the top of the sealing layer 51 in the fixed pre-fired state, the sealing layer 51 is polished so that the height of the sealing layer 51 is about 100 μm higher than the partition wall height. It is desirable from the viewpoint of suppressing alignment deviation.

  In addition, when the height of the sealing layer 51 is about 50 μm higher than the partition wall height, it is confirmed that after sealing, the airtightness cannot be secured and panel leakage occurs. Therefore, the lower limit is set to about 80 μm. It is desirable.

  Moreover, as a method for manufacturing a display panel according to another embodiment of the present invention, a method using a phosphor removing film 53 as shown in FIG. Details will be described below.

  In the PDP, when applying the phosphor material, some phosphor material may run on the top of the partition wall. In such a case, the performance is hardly affected by a normal PDP, but in the case of a high-definition PDP, charge loss occurs due to the phosphor material running on top of the partition walls. For this reason, it is preferable if the step of removing the phosphor material at the top of the partition wall can be introduced. In view of this, in the display panel manufacturing method according to another embodiment of the present invention, a cover is provided in the display device when the sealing layer 51 is polished in order to prevent mixing of shavings during polishing. A phosphor material removal film is used. By using such a phosphor material removal film, it is possible to simultaneously perform the phosphor material removal process on the top of the partition wall and the cover of the image display area of the display device, thereby reducing the number of processes.

  As described above, the present invention is useful for providing a large-screen, high-definition display panel.

DESCRIPTION OF SYMBOLS 1 Flat type image display panel 2 Front substrate 3 Back substrate 4 Scan electrode 5 Sustain electrode 6 Dielectric layer 7 Protective layer 8 Base dielectric layer 9 Data electrode 10 Partition 11 Phosphor layer 21 Chassis member 22, 25 Flexible wiring board 23, 24, 27 Drive circuit block 26 Data driver 43 Base plate 52 Wrapping film 53 Phosphor removal film 54 Elastic contact roll 121 clip

Claims (4)

A method for producing a flat panel image display panel comprising an envelope having a configuration in which two substrates are opposed to each other with a partition wall interposed therebetween and a peripheral portion thereof is sealed with a sealing layer,
Applying a sealing material to at least one of the two substrates;
Forming the sealing layer by fixing and pre-firing the applied sealing material; and
Flattening the top of the sealing layer in the fixed pre-fired state;
Overlaying the two substrates through the flattened sealing layer, and sealing by softening the sealing layer;
A method of manufacturing a flat panel display panel. Before the flattening step, a step of applying a phosphor material between the barrier ribs, and the step of flattening the top of the sealing layer in the fixed and prefired state is fixed and prefired The method for producing a flat panel display according to claim 1, wherein the step of polishing the top of the sealing layer and the step of removing the phosphor on the top of the partition wall are simultaneously performed. The flat image display panel manufacturing method according to claim 1, wherein a lapping film having an abrasive particle size of 600 to 2000 is used in the flattening step. The method for producing a flat panel display panel according to claim 1, wherein one pixel of the flat panel display panel is 300 μm or less.

Images