JP2011033678A - Light-emitting device, electronic equipment, and method for driving light emitting device - Google Patents

Abstract

A drive current error is suppressed for a plurality of gradations.
A light emitting device includes a pixel circuit including a light emitting element, a driving transistor, and a storage capacitor, and a control circuit. In the writing period PWR, the control circuit 30 supplies the data potential VD from the data line 14 to the gate of the driving transistor TDR. The control circuit 30 controls the current corresponding to the data potential VD to flow through the driving transistor TDR in the first period P1 within the second compensation period PCb. In the second period P2 within the second compensation period PCb, the control circuit 30 supplies a correction potential VC obtained by adding an offset voltage Vof proportional to the data potential VD to the data potential VD to the gate of the drive transistor TDR, thereby holding the storage capacitor. Increase the voltage across CST. Further, in the light emission period PDR, the potential of the source of the drive transistor TDR is changed so that the light emitting element E emits light.
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Description

  The present invention relates to a technique for driving a light emitting element such as an organic EL (Electroluminescence) element.

  In a light-emitting device in which a drive transistor controls the amount of drive current supplied to a light-emitting element, an error in electrical characteristics of the drive transistor (difference from a target value or variation among elements) becomes a problem. Japanese Patent Application Laid-Open No. 2004-151867 discloses that a threshold voltage of a driving transistor is set by changing a voltage between both ends of a capacitor interposed between a gate and a source of the driving transistor to a threshold voltage of the driving transistor and then changing the voltage to a voltage according to a gradation. A technique for compensating for an error in voltage and mobility (and thus an error in the amount of drive current) is disclosed.

JP 2007-310311 A

  However, the error of the drive current due to the characteristics of the drive transistor is effectively compensated under the technique of Patent Document 1 only when a specific gradation is designated. The error may not be compensated effectively. In view of the above circumstances, an object of the present invention is to suppress a drive current error caused by characteristics of a drive transistor for a plurality of gradations.

In order to solve the above problems, a light-emitting device according to the present invention includes a light-emitting element, a drive transistor connected in series to the light-emitting element, a storage capacitor disposed between a gate and a source of the drive transistor, A pixel circuit including a selection transistor disposed between the gate of the driving transistor and the data line, a correction potential generation unit connected to the data line corresponding to the pixel circuit,
A control unit that controls the pixel circuit and the offset voltage generation unit, and the control unit designates the gradation that the light emitting element should emit in the first period (for example, the writing period PWR shown in FIG. 3). The selection transistor is set to an on state so that a data potential corresponding to the gray level is supplied from the data line to the gate of the driving transistor, and a second period after the first period (for example, the second compensation period shown in FIG. 3). In the first period P1) in PCb, the current according to the data potential is controlled to flow through the drive transistor, and the voltage across the storage capacitor is set to a value reflecting the data potential and the characteristics of the drive transistor. In a third period after the second period (for example, the second period P2 in the second compensation period PCb), a correction potential obtained by adding an offset voltage proportional to the data potential to the data potential is supplied to the correction potential generation unit. The correction potential is generated and controlled so that the correction potential is supplied from the data line to the gate of the driving transistor, the voltage across the storage capacitor is increased, and the fourth period after the third period (for example, FIG. 3). In the light emission period PDR), the selection transistor is set to an OFF state, and the potential of the source of the driving transistor is changed so that the light emitting element emits light.

  In the above configuration, by supplying a current to the driving transistor in the second period, the characteristics (mobility μ) of the driving transistor are reflected in the voltage between the gate and the source. That is, an error in the current of the driving transistor due to the mobility of the driving transistor is compensated. However, the current error is effectively compensated for in the operation in the second period only when a specific gradation is designated. Therefore, in the third period, a correction potential obtained by adding an offset voltage proportional to the data potential to the data potential is supplied to the gate of the drive transistor, thereby increasing the gate-source voltage of the drive transistor. Accordingly, it is possible to effectively reduce the error in the current flowing through the driving transistor even for gradations other than the gradation in which the current error is effectively compensated for in the operation in the second period. In addition, since the voltage between the gate and the source of the driving transistor increases in the operation in the third period, the current value (luminance of the light emitting element) of the driving current increases as compared with the configuration in which the operation in the third period is not performed. There is also an advantage. Furthermore, in the present invention, since the correction potential generation unit that generates the above-described correction potential is provided in the data line, the scale of the pixel circuit is enlarged as compared with an aspect in which the correction potential generation unit is provided in the pixel circuit. It is suppressed. Thereby, there is an advantage that a high-definition light-emitting device can be provided.

  As a mode of the light emitting device according to the present invention, the light emitting device further includes a data line driving circuit that generates a data potential, and a first switch that is disposed between the data lines and switches between conduction and non-conduction, and the correction potential generation unit includes , A first capacitor having a first electrode and a second electrode connected to the power supply line, a second capacitor having a third electrode and a fourth electrode connected to the data line, a first electrode and a second electrode A second switch that is arranged between the three electrodes and switches between conduction and non-conduction between the electrodes, and the control unit sets the first switch to the on state in the data potential supply period before the first period. The data potential is supplied to the data line, and the data potential is controlled to be supplied to the first electrode, while the potential of the third electrode is set to a reference potential different from the data potential, and the second potential is set. Set the switch to the OFF state In the first period, the first switch is set to an off state to electrically float the data line, the potential associated with the data line is held at the data potential by a capacitor associated with the data line, and the second switch is turned off. The first switch and the second switch are kept off in the second period, and the second switch is turned on so that the data line potential changes from the data potential to the correction potential in the third period. While setting the state to change the potential of the third electrode, the first switch is maintained in the OFF state.

  According to this aspect, since the correction potential is generated by changing the data potential written to the data line in the data potential supply period using the capacitive coupling, the data potential and the correction potential are time-divisionally divided. Compared with the mode of outputting to the data line, the load on the drive circuit can be reduced. Further, as a specific aspect of the light emitting device according to the present invention, the correction potential generation unit includes a third switch that switches between conduction and non-conduction between the data line and the first electrode, a power supply line to which a reference potential is supplied, And a fourth switch that switches between conduction and non-conduction with the third electrode, and the control unit sets the third switch and the fourth switch to an on state in the data potential supply period, and the first period and the second period In the third period and the fourth period, the third switch and the fourth switch are set to the off state.

  As an aspect of the light emitting device according to the present invention, the capacitance value of the second capacitor is variably controlled in accordance with a control signal supplied from the control unit. More specifically, the second capacitor has a plurality of unit capacitors having different capacitance values and connected in parallel to the data line, and a plurality of units each disposed between each unit capacitor and the second switch. The control unit has a fifth switch (for example, switches SS1 to SSk shown in FIG. 14), and the control unit controls the on / off of the fifth switch for each of the plurality of fifth switches (for example, in FIG. 14). Control signals E1 to Ek) are supplied. The change amount (offset voltage) of the potential of the data line in the third period is a value corresponding to the data potential, the first capacitor, the second capacitor, and the capacitor associated with the data line, and the capacitance value of the second capacitor is variable. This control has the advantage that the offset voltage value can be adjusted to the optimum value.

  As an aspect of the light emitting device according to the present invention, the pixel circuit further includes a control transistor connected in series to the light emitting element and the driving transistor, and the control unit sets the control transistor to the on state in the second period, In three periods, the control transistor is set to an off state. In the second period, the mobility compensation operation is performed by setting the control transistor to the on state and passing a current through the driving transistor. On the other hand, when the control transistor is set to the ON state also in the third period, a current flows through the drive transistor and the same operation as in the second period is performed, and the voltage between the gate and the source of the drive transistor is lowered. However, the current error (variation) may increase, which is not preferable. On the other hand, if the control transistor is set to the OFF state in the third period, no current flows through the driving transistor, so that the gate-source voltage of the driving transistor can be increased. Accordingly, the error of the current flowing through the driving transistor can be effectively reduced and the current value of the driving current (the luminance of the light emitting element) can be effectively reduced for gradations other than the gradation in which the current error is effectively compensated for in the second period operation. ) Can be increased.

  The above light-emitting devices are used in various electronic devices. A typical example of an electronic device is a device that uses a light-emitting device as a display device. Examples of the electronic apparatus according to the present invention include a personal computer and a mobile phone.

  The present invention is also specified as a method of driving a pixel circuit. A driving method according to the present invention is a driving method of a pixel circuit including a light emitting element, a driving transistor connected in series to the light emitting element, and a storage capacitor disposed between a gate and a source of the driving transistor. In the first period, a data potential corresponding to the designated gradation designating the gradation to be emitted by the light emitting element of the pixel circuit is supplied from the data line to the gate of the driving transistor, and the second period after the first period. , The current according to the data potential is controlled to flow through the driving transistor, the voltage across the storage capacitor is set to a value reflecting the data potential and the characteristics of the driving transistor, and after the second period In the third period, a correction potential obtained by adding an offset voltage proportional to the data potential to the data potential is supplied from the data line to the gate of the driving transistor, so that the voltage across the storage capacitor is Is pressurized, in the fourth period after the third period, by setting the select transistor in the OFF state, the source potential of the driving transistor, the light emitting element is varied to emission. According to the above driving method, the same operation and effect as the light emitting device according to the present invention are realized.

1 is a block diagram of a light emitting device according to a first embodiment of the present invention. It is a circuit diagram of a pixel circuit and a correction potential generation unit. It is a timing chart of operation | movement of a light-emitting device. It is a figure which shows the state of an initialization period. It is a circuit diagram which shows the state of a 1st compensation period. It is a figure which shows the state of a data potential supply period. It is a figure which shows the state of a writing period. It is a figure which shows the state of the 1st period among 2nd compensation periods. It is a figure which shows the state of the 2nd period among 2nd compensation periods. It is a figure which shows the state of the light emission period. It is a figure which shows the relationship between a gradation electric potential and the electric current which flows through a drive transistor. It is a graph for demonstrating the effect of 1st Embodiment. It is a graph for demonstrating the effect of 1st Embodiment. FIG. 6 is a circuit diagram of a pixel circuit in a second embodiment. It is a circuit diagram of the pixel circuit in a modification. It is a perspective view of an electronic device (personal computer). It is a perspective view of an electronic device (cellular phone). It is a perspective view of an electronic device (personal digital assistant).

<A: First Embodiment>
FIG. 1 is a block diagram of a light emitting device 100 according to the first embodiment of the present invention. The light emitting device 100 is mounted on an electronic device as a display body that displays an image. As shown in FIG. 1, the light emitting device 100 includes an element portion (display area) 10 in which a plurality of pixel circuits PX are arranged, a drive circuit 20 that drives each pixel circuit PX, and a control circuit 30. The drive circuit 20 includes a scanning line drive circuit 22 and a data line drive circuit 24. Note that the drive circuit 20 may be composed of a plurality of integrated circuits (chips). The control circuit 30 is a means for outputting a signal defining the operation of the light emitting device 100 to the drive circuit 20. In the present embodiment, the control circuit 30 outputs a control signal (not shown) such as an image signal or a clock signal to the drive circuit 20.

  In the element portion 10, M sets of wiring groups 12 extending in the X direction and N data lines 14 extending in the Y direction intersecting the X direction are formed (M and N are natural numbers). The plurality of pixel circuits PX are arranged in a matrix of vertical M rows × horizontal N columns corresponding to the intersections of the wiring groups 12 and the data lines 14. As shown in FIG. 1, a plurality of correction potential generation units 40 are provided between the element unit 10 and the data line driving circuit 24. More specifically, N correction potential generation units 40 are provided in one-to-one correspondence with the N data lines 14. Each correction potential generator 40 is connected to the corresponding data line 14.

  The scanning line driving circuit 22 is means for sequentially selecting a plurality of pixel circuits PX in units of rows. The data line driving circuit 24 generates a data potential VD (VD [1] to VD [N]) corresponding to a gradation to be emitted by the light emitting element of each pixel circuit PX (hereinafter referred to as “designated gradation”). To each data line 14. The data potential VD [n] output to the data line 14 in the nth column (n = 1 to N) in the horizontal scanning period in which the mth row (m = 1 to M) is selected is the mth row. It is set to a potential corresponding to the designated gradation of the pixel circuit PX located in the nth column. The designated gradation of each pixel circuit PX is designated by an image signal supplied from the control circuit 30.

  FIG. 2 is a circuit diagram of the pixel circuit PX and the correction potential generation unit 40. In FIG. 2, the pixel circuit PX located in the m-th row and the n-th column and the n-th correction potential generation unit 40 connected to the data line 14 in the n-th column are representatively shown. In the present embodiment, N first switches SW 1 are provided between the N data lines 14 and the data line driving circuit 24. As shown in FIG. 2, the nth first switch SW1 is interposed between the data line 14 in the nth column and the data line driving circuit 24.

  As shown in FIG. 2, the pixel circuit PX includes a light emitting element E, a drive transistor TDR, a storage capacitor CST, and a plurality of transistors (QEL, QWR, R1, and R2). The wiring group 12 illustrated as one straight line in FIG. 1 includes a scanning line 120 and a plurality of control lines (130, 132, 134) as shown in FIG.

  The light emitting element E is disposed on a path connecting the potential line 31 and the potential line 33, and emits light with luminance according to the current value of the drive current IDR. For example, an organic EL element in which a light emitting layer of an organic EL material is interposed between an anode and a cathode is suitably used as the light emitting element E. The potential line 31 is supplied with the higher potential VDD. The potential line 33 is supplied with a lower potential VCT lower than the higher potential VDD. The cathode of the light emitting element E is connected to the potential line 33. As shown in FIG. 2, the light emitting element E is accompanied by a capacitor C0 (capacitance value cp0).

  The drive transistor TDR is an N-channel transistor connected in series to the light emitting element E on a path connecting the potential line 31 and the potential line 33. The drive transistor TDR generates a drive current IDR having a current value corresponding to a voltage VGS (VGS = VG−VS) which is a difference between its gate potential VG and source potential VS. The source of the driving transistor TDR is connected to the anode of the light emitting element E.

  A selection transistor QWR is interposed between the gate of the driving transistor TDR and the data line 14 in the nth column. The gate of the select transistor QWR in each pixel circuit PX in the m-th row is connected to the m-th row scanning line 120. A control transistor QEL is interposed between the drain of the driving transistor TDR and the potential line 31. The control transistor QEL is a P-channel transistor that determines whether or not the drive current IDR can be supplied to the light emitting element E. The gate of the control transistor QEL in each pixel circuit PX in the m-th row is connected to the control line 134 in the m-th row.

  A storage capacitor CST (capacitance value cp1) is interposed between the gate and source of the drive transistor TDR (the anode of the light emitting element E). An N-channel transistor R2 is interposed between the source of the driving transistor TDR and the power supply line 37. An initialization potential VINI2 is supplied to the power supply line 37. The gate of the transistor R2 in each pixel circuit PX in the m-th row is connected to the control line 132 in the m-th row.

  An N-channel transistor R 1 is interposed between the node ND interposed between the gate of the driving transistor TDR and the selection transistor QWR and the power supply line 35. The power supply line 35 is supplied with an initialization potential VINI1. The gate of the transistor R1 in each pixel circuit PX in the m-th row is connected to the control line 130 in the m-th row.

  The correction potential generation unit 40 is a means for generating a correction potential by adding an offset voltage proportional to the data potential VD [n] to the data potential VD [n]. As shown in FIG. 2, the correction potential generation unit 40 includes a first capacitor C1, a second capacitor C2, and a plurality of switches (SW2, SW3, SW4). The first capacitor C1 is a capacitor element (capacitance value Ca) in which a dielectric (not shown) is interposed between the first electrode e1 and the second electrode e2. The second electrode e2 is connected to the power supply line 39. A reference potential VSS is supplied to the power supply line 39. The second capacitor C2 is a capacitive element (capacitance value Cb) in which a dielectric (not shown) is interposed between the third electrode e3 and the fourth electrode e4. The fourth electrode e4 is connected to the data line 14 in the nth column.

  Between the third electrode e3 in the second capacitor C2 and the first electrode e1 in the first capacitor C1, a second switch SW2 for switching between conduction and non-conduction is interposed. Further, a third switch SW3 for switching between conduction and non-conduction is interposed between the first electrode e1 and the data line 14 in the n-th column in the first capacitor C1. Further, a fourth switch SW4 that switches between conduction and non-conduction is interposed between the third electrode e3 and the power supply line 39 in the second capacitor C2. As shown in FIG. 2, the control signal GSEL from the drive circuit 20 is commonly supplied to the gates of the first switch SW1, the third switch SW3, and the fourth switch SW4. The control signal GOF from the drive circuit 20 is supplied to the gate of the second switch SW2.

  The scanning line driving circuit 22 in FIG. 1 generates scanning signals GWR [1] to GWR [M] for sequentially scanning (selecting) the plurality of pixel circuits PX in units of rows, and outputs them to the scanning lines 120. . As shown in FIG. 3, the scanning signal GWR [m] output to the m-th scanning line 120 has an active level (high level) within the m-th horizontal scanning period H [m] in each vertical scanning period. ). The scanning line driving circuit 22 controls the control signals GEL [1] to GEL [M], the control signals GINI1 [1] to GINI1 [M], the control signals GINI2 [1] to GINI2 [M], the control signal GSEL and the control signal GSEL. A signal GOF is generated and output. As shown in FIG. 2, the control signal GEL [m] is supplied to the m-th row control line 134, the control signal GINI1 [m] is supplied to the m-th row control line 130, and the control signal GINI2 [m] is This is supplied to the control line 132 of the m-th row. The control signal GSEL is supplied in common to each of the first switch SW1, the third switch SW3, and the fourth switch SW4 in each correction potential generation unit 40. Further, the control signal GOF is commonly supplied to the second switch SW2 in each correction potential generation unit 40.

  As shown in FIG. 3, an initialization period PRS and a first compensation period PCa are set before the start of the horizontal scanning period H [m]. The gate-source voltage VGS of the driving transistor TDR is initialized to a predetermined voltage in the initialization period PRS, and is set to the threshold voltage VTH of the driving transistor TDR in the first compensation period PCa after the initialization period PRS has elapsed. Asymptotically. As shown in FIG. 3, the horizontal scanning period H [m] includes a data potential supply period PS, a writing period PWR, and a second compensation period PCb. In the data potential supply period PS, the data potential VD is supplied from the data line driving circuit 24 to the data line 14. The voltage VGS of the driving transistor TDR is set to a voltage corresponding to the data potential VD in the writing period PWR, and the data potential VD and the characteristics (mobility μ) of the driving transistor TDR are reflected in the second compensation period PCb. Set to the correct voltage. The second compensation period PCb is divided into a first period P1 and a second period P2. Further, in the light emission period PDR after the elapse of the horizontal scanning period H [m], the drive current IDR according to the voltage of the drive transistor TDR is supplied to the light emitting element E. Hereinafter, a specific operation in each period will be described focusing on the pixel circuit PX located in the mth row and the nth column.

(1) Initialization period PRS (Fig. 4)
As shown in FIG. 3, in the initialization period PRS, the control signal GINI1 [m], the control signal GINI2 [m], and the control signal GEL [m] are set to the high level, and the scanning signal GWR [m] and the control signal are controlled. The signal GSEL and the control signal GOF are set to low level. That is, as shown in FIG. 4, the transistor R1 and the transistor R2 are controlled to be in an on state, and the selection transistor QWR, the control transistor QEL, and the first switch SW1 to the fourth switch SW4 are controlled to be in an off state. Accordingly, the gate potential VG of the drive transistor TDR is set to the initialization potential VINI1 of the power supply line 35 via the transistor R1, and the source potential VS of the drive transistor TDR is set to the initialization potential of the power supply line 37 via the transistor R2. Set to VINI2. As described above, the gate-source voltage VGS of the drive transistor TDR is initialized to the difference (VINI1-VINI2) between the initialization potential VINI1 and the initialization potential VINI2.

The initialization potential VINI1 and the initialization potential VINI2 have a difference (voltage VGS) between them exceeding the threshold voltage VTH of the driving transistor TDR as shown in the following formula (1), and the light emitting element E as shown in the formula (2). Is set to be lower than the threshold voltage VTH_E of the light emitting element E. Therefore, in the initialization period PRS, the driving transistor TDR is controlled to be in an on state and the light emitting element E is controlled to be in an off state (non-light emitting state).
VINI1-VINI2> VTH (1)
VINI2−VCT <VTH_E …… (2)
By the way, when the control transistor QEL is set to the ON state in the initialization period PRS, a current flows from the potential line 31 to the power supply line 37 through the control transistor QEL, the driving transistor TDR, and the transistor R2, and the electric power is generated. Although consumed, there is an advantage that the power consumption can be reduced if the control transistor QEL is set to the OFF state in the initialization period PRS as in this embodiment.

(2) First compensation period PCa (FIG. 5)
As shown in FIG. 3, in the first compensation period PCa, the control signal GINI2 [m] and the control signal GEL [m] change to a low level. Therefore, as shown in FIG. 5, the transistor R2 changes from the state of the initialization period PRS to the off state (that is, the supply of the initialization potential VINI2 to the source of the drive transistor TDR is stopped) and the control transistor QEL is turned on. Transition to the state. Since the drive transistor TDR is turned on in the initialization period PRS, in the first compensation period PCa, the current IDS from the potential line 31 via the control transistor QEL flows between the drain and source of the drive transistor TDR.

  When the current IDS flows through the driving transistor TDR, the storage capacitor CST and the capacitor C0 are charged. Therefore, as shown in FIG. 3, the potential VS of the source of the drive transistor TDR increases with time. On the other hand, since the gate potential VG of the drive transistor TDR is maintained at the initialization potential VINI1 from the initialization period PRS, the gate-source voltage VGS of the drive transistor TDR gradually decreases within the first compensation period PCa. Asymptotically approaches the threshold voltage VTH. The time length of the first compensation period PCa is set so that the voltage VGS of the drive transistor TDR sufficiently approaches (ideally matches) the threshold voltage VTH at the end point of the first compensation period PCa. Therefore, the drive transistor TDR is almost turned off at the end point of the first compensation period PCa.

  As shown in FIG. 3, the control signal GEL [m] changes to a high level and the control transistor QEL transitions to an off state (the current IDS is cut off), whereby the first compensation period PCa ends. At the end point of the first compensation period PCa, the control signal GINI1 [m] changes to a low level, so that the transistor R1 transitions to an off state. That is, the supply of the initialization potential VINI1 to the gate of the drive transistor TDR is stopped.

(3) Data potential supply period PS (FIG. 6)
As shown in FIG. 3, in the horizontal scanning period H [m] (data potential supply period PS, writing period PWR, and second compensation period PCb), the data potential VD [n] output from the data line driving circuit 24 is The gradation potential VDATA corresponding to the designated gradation of the pixel circuit PX located in the mth row and the nth column is set. As shown in FIGS. 3 and 6, in the data potential supply period PS, the first switch SW1, the third switch SW3, and the fourth switch SW4 transition to the on state when the control signal GSEL changes to the high level. Therefore, the data potential VD [n] (gradation potential VDATA) from the data line driving circuit 24 is supplied to the data line 14 in the nth column via the first switch SW1. Since the first electrode e1 of the first capacitor C1 in the correction potential generator 40 is electrically connected to the data line 14 via the third switch SW3, the potential of the first electrode e1 is set to the gradation potential VDATA. Further, since the third electrode e3 of the second capacitor C2 in the correction potential generation unit 40 is conducted to the power supply line 39 via the fourth switch SW4, the potential of the third electrode e3 is set to the reference potential VSS.

  As shown in FIG. 3, the control signal GSEL is changed to a low level, and the first switch SW1, the third switch SW3, and the fourth switch SW4 are turned off, so that the data potential supply period PS ends. When the first switch SW1 is turned off, the supply of the data potential VD [n] from the data line driving circuit 24 to the data line 14 is stopped, and the data line 14 is in an electrically floating state. As shown in FIG. 6, since the data line 14 is accompanied by a capacitor Cd (capacitance value Cdl), the gradation potential VDATA supplied to the data line 14 in the data potential supply period PS is held in the data line 14. .

(4) Write period PWR (FIG. 7)
In the writing period PWR, the control circuit 30 turns on the selection transistor QWR so that the data potential VD [n] (grayscale potential VDATA) held in the data line 14 is supplied to the gate of the driving transistor TDR. Set. More specifically, as shown in FIG. 3, in the writing period PWR, the control circuit 30 changes the scanning signal GWR [m] to a high level. As a result, as shown in FIG. 7, the selection transistor QWR is turned on. Accordingly, since the gate of the drive transistor TDR is conducted to the data line 14 via the selection transistor QWR, the potential VG of the gate of the drive transistor TDR changes from the initialization potential VINI1 to the gradation potential VDATA. Since the source coupled to the gate of the driving transistor TDR via the storage capacitor CST is in an electrically floating state in the writing period PWR, the potential VS of the source of the driving transistor TDR is set to the gate potential as shown in FIG. Changes (increases) in conjunction with the potential VG. The change amount of the potential VS in the write period PWR is a voltage (ΔV0 · cp1 / (cp0 + cp1) obtained by dividing the change amount ΔV0 (ΔV0 = VDATA−VINI1) of the potential VG according to the capacitance ratio of the capacitor C0 and the holding capacitor CST. ). Therefore, the voltage VGS of the drive transistor TDR is set to the voltage VGS0 of the following formula (3) in the writing period PWR.
VGS0 = VTH + ΔV0 · cp0 / (cp0 + cp1)
= VTH + k · ΔV0 (3) (k = cp0 / (cp0 + cp1))

  Since the amount of change in the source potential VS of the driving transistor TDR at this time is less than the amount of change in the gate potential VG, the gate-source voltage VGS of the driving transistor TDR after the supply of the gradation potential VDATA is the first compensation. It exceeds the voltage (threshold voltage VTH) after setting in the period PCa. Therefore, the drive transistor TDR is turned on. However, since the control transistor QEL is kept off during the write period PWR, no current flows through the drive transistor TDR.

(5a) Second compensation period PCb (first period P1)
In the first period P1 in the second compensation period PCb, the control circuit 30 controls the current corresponding to the data potential VD [n] to flow through the drive transistor TDR, and thereby the voltage across the storage capacitor CST (drive) The voltage VGS of the transistor TDR) is set to a value reflecting the data potential VD [n] and the characteristics of the driving transistor TD. More specifically, it is as follows. In the first period P1 of the second compensation period PCb, as shown in FIG. 3, the control circuit 30 controls the control signal GEL [m] to change to the low level from the state of the writing period PWR. As a result, as shown in FIG. 8, the control transistor QEL transitions to the ON state. Since the voltage between the gate and the source of the driving transistor TDR is maintained at the voltage VGS0 (that is, the voltage corresponding to the data potential VD [n]) set in the writing period PWR, the data potential VD is set in the first period P1. A current IDS corresponding to [n] (gradation potential VDATA) flows through the driving transistor TDR. Therefore, as the capacitor C0 and the holding capacitor CST are charged by the current IDS, the source potential VS (voltage across the capacitor C0) of the drive transistor TDR gradually increases.

  On the other hand, since the selection transistor QWR is set to the ON state even in the first period P1, the gate potential VG of the drive transistor TDR is maintained at the gradation potential VDATA of the data line 14 continuously from the writing period PWR. Therefore, the gate-source voltage VGS of the drive transistor TDR decreases from the voltage VGS0 after setting in the write period PWR as the potential VS is increased by the current IDS.

The first period P1 ends when the control signal GEL [m] changes to the high level and the control transistor QEL changes to the off state (the current IDS is cut off). At the end point of the first period P1, the voltage VGS of the drive transistor TDR is set to the voltage VGS1 of Formula (4), which is lower than the voltage VGS0 of Formula (3) by the voltage ΔV1. The voltage ΔV1 corresponds to the increase amount of the potential VS in the first period P1. The voltage ΔV1 (the amount of change in the voltage VGS in the first period P1) depends on the mobility μ of the driving transistor TDR, and the voltage ΔV1 increases as the mobility μ of the driving transistor TDR increases. As described above, in the first period P1, the voltage across the storage capacitor CST (the voltage VGS between the gate and the source of the driving transistor TDR) is the characteristic (mobility) of the data potential VD [n] and the driving transistor TDR. μ) and the value reflected.
VGS1 = VGS0−ΔV1
= VTH + k ・ ΔV0−ΔV1
= VTH + VA (4) (VA = k · ΔV0-ΔV1)

(5b) Second compensation period PCb (second period P2)
In the second period P2 within the second compensation period PCb, the control circuit 30 generates a correction potential VC by adding an offset voltage Vof proportional to the data potential VD [n] to the data potential VD [n]. The correction potential VC is controlled to be supplied from the data line 14 to the gate of the driving transistor TDR, and the voltage across the storage capacitor CST is increased. More specifically, it is as follows. In the second period P2 of the second compensation period PCb, as shown in FIG. 3, the control circuit 30 changes the control signal GOF to the high level. As a result, as shown in FIG. 9, since the second switch SW2 is turned on, the first electrode e1 of the first capacitance C1 (capacitance value Ca) and the second capacitance C2 (capacitance) in the correction potential generation unit 40. The third electrode e3 having the value Cb) is conducted through the second switch SW2. If the potential of the first electrode e1 at this time is Va and the potential of the third electrode e3 is Vb, both are expressed by the following formula (5).
Va = Vb = Ca * VDATA + {(Cb * Cdl) / (Cb + Cdl)} * VSS / {(Ca + Cb) * Cdl / (Ca + Cb + Cdl)} (5)

In the second period P2, since the data line 14 is in an electrically floating state, the potential of the fourth electrode e4 connected to the data line 14 (that is, the potential of the data line 14) is linked to the potential of the third electrode e3. Then change (rise). The amount of change in the potential of the fourth electrode at this time corresponds to the offset voltage Vof. The offset voltage Vof is obtained by changing the amount of change (Vb−VSS) of the third electrode e3 with the second capacitor C2 (capacitance value Cb) and the data line 14. The voltage is divided in accordance with the capacitance ratio with the capacitance Cd (capacitance value Cdl) associated with. The offset voltage Vof (the amount of change in the potential of the data line 14 due to capacitive coupling in the second period P2) is expressed by the following equation (6).
Vof = (Vb−VSS) × Cb / (Cb + Cdl)
= Ca x Cb x (VDATA-VSS) / [{(Ca + Cb) x Cdl / (Ca + Cb + Cdl)} x (Cb + Cdl)] ... (6)

As understood from the equation (6), the offset voltage Vof is a value proportional to the gradation potential VDATA (data potential VD [n]). Furthermore, the offset voltage Vof is set to a value corresponding to the gradation potential VDATA, the capacitance value Ca of the first capacitor C1, the capacitance value Cb of the second capacitor C2, and the capacitance value Cdl of the capacitor Cd associated with the data line 14. Is done. In the second period P2, the potential of the data line 14 is set to a correction potential VC obtained by adding the offset voltage Vof to the gradation potential VDATA. The correction potential VC is expressed by the following formula (7).
VC = VDATA + Ca * Cb * (VDATA-VSS) / [{(Ca + Cb) * Cdl / (Ca + Cb + Cdl)} * (Cb + Cdl)]
...... (7)

  In the second period P2, since the selection transistor QWR is kept on, the gate of the drive transistor TDR is conducted to the data line 14 via the selection transistor QWR. When the potential of the data line 14 changes from the gradation potential VDATA to the correction potential VC, the gate potential VG of the drive transistor TDR also changes from the gradation potential VDATA to the correction potential VC. The amount of change in the gate potential VG of the driving transistor TDR at this time corresponds to the offset voltage Vof.

On the other hand, since the source of the drive transistor TDR is in an electrically floating state in the second period P2, the potential VS of the source of the drive transistor TDR changes (rises) in conjunction with the potential VG as shown in FIG. . The change amount of the potential VS in the second period P2 is a voltage (VOF · cp1 / (cp0 + cp1)) obtained by dividing the change amount of the gate potential VG (offset voltage VOF) according to the capacitance ratio between the capacitance C0 and the capacitance C1. It corresponds to. Therefore, the voltage VGS of the drive transistor TDR is set to the voltage VGS2 of the following formula (8) in the second period P2.
VGS2 = VTH + VA + k · VOF
= VTH + VA + VB (8) (VB = k · VOF)

  As shown in Expression (8), the voltage VGS2 after setting in the second period P2 corresponds to a voltage obtained by changing (increasing) the voltage VGS1 in the first period P1 by the change amount VB. As shown in FIG. 3, when the control signal GOF changes to the low level and the second switch SW2 changes to the off state, the writing of the correction potential VC is completed, and the second period P2 is completed.

(6) Light emission period PDR
In the light emission period PDR, the control circuit 30 sets the selection transistor QWR to the OFF state, and changes the source potential VS of the drive transistor TDR so that the light emitting element E emits light. More specifically, it is as follows. In the light emission period PDR, as shown in FIGS. 3 and 10, the control circuit 30 changes the scanning signal GWR [m] to a low level to cause the selection transistor QWR to transition to the OFF state, and the control signal GEL [m ] Is changed to a low level to change the light emission control switch QEL to the ON state. Therefore, a current IDS corresponding to the voltage VGS2 set in the second period P2 flows between the drain and source of the driving transistor TDR, and the potential VS of the source of the driving transistor TDR rises with time. Since the gate of the drive transistor TDR is in an electrically floating state by setting the selection transistor QWR to the off state, the voltage VGS of the drive transistor TDR is the voltage at the end point of the second period P2, as shown in FIG. While being maintained at VGS2, the voltage across the capacitor C0 (the source potential VS of the driving transistor TDR) increases with time (bootstrap operation).

  When the voltage across the capacitor C0 reaches the threshold voltage VTH_E of the light emitting element E, the current IDS having a current value corresponding to the voltage VGS (VGS2) of the driving transistor TDR flows through the light emitting element E as the driving current IDR. As described above, since the drive current IDR is set to a current value corresponding to the voltage VGS2 reflecting the gradation potential VDATA, the light emitting element E emits light with a luminance corresponding to the gradation potential VDATA. Light emission of the light emitting element E continues until the control signal GEL [m] changes to high level at the start point of the next initialization period PRS in the m-th row.

  Next, the effect of the operation (Formula (8)) for increasing the gate-source voltage VGS of the drive transistor TDR by the change amount VB in the second period P2 within the second compensation period PCb will be described. In the following, a configuration (hereinafter referred to as “proportional”) in which the second period P2 is omitted is illustrated for comparison with the first embodiment. In contrast, the voltage VGS1 set in the first period P1 is maintained in the light emission period PDR and applied to the setting of the current value of the drive current IDR.

  Part (A) of FIG. 11 is a graph showing the change over time of the current IDS (vertical axis) in the first period P1. The change of the current IDS flowing through the driving transistor TDR_A and the driving transistor TDR_B is illustrated in a plurality of cases where the gradation potential VDATA is changed (VDATA_1 <VDATA_2 <VDATA_3). The mobility μ of the driving transistor TDR_A is higher than the mobility μ of the driving transistor TDR_B. Further, the time of the first period P1 is also written on the horizontal axis of the portion (A) in FIG. In the first period P1, since the voltage VGS of the driving transistor TDR gradually decreases, the drain-source current IDS decreases with time as shown in part (A) of FIG.

  As understood from part (A) of FIG. 11, the higher the mobility μ, the higher the temporal change rate (change speed) of the current IDS within the first period P1. Further, since the current IDS is set according to the gradation potential VDATA, the point in time when the current IDS of the driving transistor TDR_A and the current IDS of the driving transistor TDR_B match within the first period P1 depends on the gradation potential VDATA. Is different. For example, in the case of the gradation potential VDATA_1, the current IDS of the driving transistor TDR_A and the current IDS of the driving transistor TDR_B match at the time t1 (end point of the first period P1), whereas in the case of the gradation potential VDATA_2. Are matched at time t2 before the arrival of time t1, and in the case of the gradation potential VDATA_3, they are matched at time t3 before the arrival of time t2.

  Therefore, under the comparative 1 with the second period P2 omitted, the error of the current IDS (drive current IDR) caused by the mobility μ of the drive transistor TDR can be effectively compensated when a specific gradation is designated. There is a problem of being limited. For example, as understood from the part (A) of FIG. 11, when the gradation corresponding to the gradation potential VDATA_1 is designated, it is caused by the difference in mobility μ between the driving transistor TDR_A and the driving transistor TDR_B. It is possible to compensate for the error of the current IDS. However, when the gradation corresponding to the gradation potential VDATA_2 or the gradation potential VDATA_3 is designated, the current IDS of the driving transistor TDR_A and the current IDS of the driving transistor TDR_B are different at the end point of the first period P1. That is, the difference in mobility μ is not effectively compensated. As shown in part (A) of FIG. 11, basically, the higher the gradation potential VDATA, the greater the difference δ in the current value of the current IDS at the end point of the first period P1.

  Therefore, in the present embodiment, the difference δ is reduced by increasing the voltage VGS of the drive transistor TDR by the change amount VB in the second period P2 after the elapse of the first period P1 (VGS1 → VGS2). Part (B) of FIG. 11 is a graph showing the relationship between the change amount VB (horizontal axis) and the current IDS (vertical axis). The current IDS when the change amount VB is zero corresponds to the current IDS (that is, the drive current IDR in proportion) of each drive transistor TDR (TDR_A, TDR_B) at the end point of the first period P1. The difference δ in the current IDS at the end point of the first period P1 is that the voltage VGS between the gate and source of the drive transistor TDR is increased in the second period P2, and the voltage VGS is changed to the current IDS caused by the mobility μ. This error is reduced by approaching a value that effectively compensates the error (a value in which the current IDS of the driving transistor TDR_A and the current IDS of the driving transistor TDR_B match). As can be understood from the portion (B) of FIG. 11, the larger the difference δ of the current IDS at the end point of the first period P1, the larger the value of the change amount VB necessary for eliminating the difference δ.

  As described above, the difference δ of the current IDS at the end point of the first period P1 increases as the gradation potential VDATA increases. Therefore, the higher the gradation potential VDATA (that is, the current IDS at the end point of the first period P1). If the change amount VB of the voltage VGS within the second period P2 is set larger, the error of the current IDS can be reduced over a plurality of gradations. For example, as shown in part (B) of FIG. 11, in the case of the gradation potential VDATA_2, the change amount VB is set to the voltage VB_2, and in the case of the gradation potential VDATA_3 (> VDATA_2), the change amount VB is set to the voltage VB_3. (> VB_2).

  In consideration of the above tendency, the present embodiment employs a configuration in which the voltage VGS of the driving transistor TDR is increased in the second period P2 by a change amount VB (proportional) corresponding to the gradation potential VDATA. That is, as the gradation potential VDATA is higher, the change amount VB of the voltage VGS in the second period P2 is set to a higher voltage. Therefore, according to the present embodiment, there is an advantage that the error of the drive current IDR caused by the mobility μ of the drive transistor TDR can be effectively compensated over a plurality of gradations.

  FIG. 12 shows the results of actual measurement of the target value (horizontal axis) of the driving current IDR and the actual variation (error) of the driving current IDR when the error of the mobility μ of the driving transistor TDR is ± 20%. It is a graph shown about a proportionality and 1st Embodiment. The variation (%) on the vertical axis is an index value indicating the relative ratio between the maximum value and the minimum value of the actual drive current IDR. As can be seen from FIG. 12, in the proportionality in which the voltage VGS does not change after the first period P1, the error of the drive current IDR is reduced only when a specific gradation (drive current IDR) is specified. According to the present embodiment in which the voltage VGS is changed by the change amount VB corresponding to the gradation potential in the second period P2, the error of the drive current IDR is reduced over a wide range of gradations.

  FIG. 13 is a graph showing the relationship between the gradation potential VDATA (horizontal axis) and the drive current IDR (vertical axis) in comparison with this embodiment. In the first period P1, the voltage VGS set to the voltage VGS0 in the immediately preceding write period PWR drops to the voltage VGS1. Therefore, in the proportionality in which the voltage VGS1 set in the first period P1 is maintained even in the light emission period PDR, the current value (upper limit value) of the drive current IDR is limited to a predetermined range (further, the light emitting element E The brightness may be insufficient. On the other hand, in the present embodiment, the voltage VGS increases (VGS1 → VGS2) after the first period P1 has elapsed, so that the current value of the drive current IDR corresponding to each gradation potential VDATA is proportional to each other as shown in FIG. Big compared to. Therefore, there is an advantage that the luminance of the light emitting element E can be sufficiently secured.

  By the way, unlike the present embodiment, a mode in which the configuration for generating the above-described correction potential VC (offset voltage Vof) is provided in each pixel circuit PX (hereinafter referred to as “proportional 2”) may be employed. However, in contrast 2, there is a problem that the circuit scale of the pixel circuit PX is enlarged because it is necessary to add many capacitance elements and switches to each pixel circuit PX. On the other hand, according to the present embodiment, since the correction potential generation unit 40 that generates the correction potential VC is provided on the data line 14, it is possible to suppress an increase in the size of the pixel circuit PX as compared with the comparative example 2. Is done. Thereby, there is an advantage that a high-definition light-emitting device can be provided.

  Unlike the present embodiment, the data line driving circuit 24 is not provided with the above-described correction potential generation unit 40 and the first switch SW1, and the data line drive circuit 24 operates in the horizontal scanning period H [m]. To the data line 14 in a time-sharing manner (hereinafter referred to as “comparative 3”) may be employed. However, in contrast 3, it is necessary to execute the operation of setting the potential of the data line 14 to the gradation potential VDATA and the operation of changing the gradation potential VDATA to the correction potential VC every horizontal scanning period H [m]. For this reason, the data line driving circuit 24 is required to operate at high speed. Therefore, there is a problem that the configuration of the data line driving circuit 24 becomes complicated and the cost increases. Since it is necessary to shorten the time of the horizontal scanning period H [m] in order to increase the definition of the image (increase in the pixel circuit PX), the above problem becomes more serious.

  In the present embodiment, the correction potential VC is generated by changing the gradation potential VDATA written to the data line 14 in the data potential supply period PS using capacitive coupling. Only needs to output the gradation potential VDATA to the data line 14 in the data potential supply period PS in the horizontal scanning period H [m], and in the horizontal scanning period H [m] as in the comparative example 3, It is not necessary to output the adjustment potential VDATA and the correction potential VC to the data line 14 in a time division manner. That is, it is possible to reduce the speed required for the operation of the data line driving circuit 24 as compared with the proportional 3. Therefore, the configuration of the data line driving circuit 24 can be simplified and the cost can be reduced, and further, there is an advantage that it is easy to increase the definition of an image.

<B: Second Embodiment>
The offset voltage VOF, which is the basis of the change amount VB of the voltage VGS in the second period P2, is the capacitance value Ca of the first capacitor C1, the capacitance value Cb of the second capacitor C2, and the capacitance value Cdl of the capacitor Cd associated with the data line 14. (See formula (6)). In the present embodiment, the second capacitor C2 is different from the first embodiment in that the capacitance value is variably controlled in accordance with a control signal supplied from the control circuit 30. Since the other configuration is the same as that of the first embodiment, the description of the overlapping parts is omitted.

FIG. 14 is a circuit diagram (corresponding to FIG. 2) of the correction potential generation unit 40 in the second embodiment.
As shown in FIG. 14, the second capacitor C2 has a plurality of (k) unit capacitors (Cs1 to Csk) connected in parallel to the data line 14 and having different capacitance values, and each unit capacitor (Cs1 to Cs1). Csk) and a plurality of (k) switches (SS1 to SSk) each disposed between the second switch SW2. Control signals E1 to Ek from the control circuit 30 are supplied to the gates of the switches (SS1 to SSk). Each switch (SS1 to SSk) is controlled to be turned on / off according to a control signal supplied to the switch.

  In the second embodiment, the control circuit 30 can control the control signals E1 to Ek to variably control the capacitance value of the second capacitor C2. Therefore, there is an advantage that the value of the offset voltage Vof can be adjusted to an optimum value. In the second embodiment, the capacity values of the plurality of unit capacities (Cs1 to Csk) are different from each other. However, the capacity values of the plurality of unit capacities (Cs1 to Csk) can be arbitrarily set. is there. For example, the capacitance values of the plurality of unit capacities (Cs1 to Csk) may be the same value. In addition, the number of unit capacities (Cs1 to Csk) can be arbitrarily set.

<C: Modification>
Various modifications are added to the above embodiments. Specific modifications are exemplified below. Two or more aspects arbitrarily selected from the following examples may be merged.

(1) Modification 1
In each of the above-described embodiments, the conductivity type of each transistor (TDR, QWR, QEL, R1, and R2) constituting the pixel circuit PX is arbitrary. For example, a configuration in which the control transistor QEL is an N-channel type and a configuration in which the drive transistor TDR is a P-channel type are also employed. In the configuration employing the P-channel type driving transistor TDR, the relationship between the voltage levels is reversed as compared with the case of the N-channel type, but the essential operation is the same as in each of the above-described embodiments. Description of the detailed configuration and operation is omitted.

(2) Modification 2
In the second embodiment, the second capacitor C2 is variably controlled according to a control signal supplied from the control circuit 30. For example, as shown in FIG. It is also possible to adopt a mode in which the capacitance value is variably controlled according to the control signal supplied from the control circuit 30. In FIG. 15, the first capacitor C1 includes a plurality (k) of unit capacitors (Cz1 to Czk) and a plurality of switches (Sz1 to Cz1) provided in a one-to-one correspondence with the plurality of unit capacitors (Cz1 to Czk). Szk). The plurality of unit capacitors (Cz1 to Czk) have different capacitance values and are connected in parallel to the feeder line 39. Each of the plurality of switches (Sz1 to Szk) is disposed between a unit capacity corresponding to the switch and a path from the second switch SW2 to the third switch SW3. Control signals Ez1 to Ezk from the control circuit 30 are supplied to the gates of the switches (Sz1 to Szk). Each switch (Sz1 to Szk) is controlled to be turned on / off according to a control signal supplied to the switch. When the control circuit 30 controls the control signals Ez1 to Ezk, the capacitance value of the first capacitor C1 can be variably controlled. In addition, the number of each unit capacity | capacitance (Cz1-Czk) and a capacitance value can be set arbitrarily.

(3) Modification 3
In each of the embodiments described above, the data potential supply period PS and the write period PWR are set as separate periods. For example, the data potential supply period PS and the write period PWR partially overlap, and the operation is performed. It can also be set as the aspect performed in the same period. Further, the first potential switch SW1, the third switch SW3, the fourth switch SW4, and the selection transistor QWR are operated (on or off) at the same timing with the data potential supply period PS and the writing period PWR as one period. May be.

(4) Modification 4
In each of the above-described embodiments, the initialization period PRS and the first compensation period PCa are set before the start of the horizontal scanning period H [m]. However, the present invention is not limited to this. For example, the initialization period PRS and the first compensation period P It is also possible to adopt a mode in which the compensation period PCa is not set.

(5) Modification 5
The organic EL element is only an example of the light emitting element E. For example, the present invention is applied to the light emitting device 100 in which the light emitting elements E such as inorganic EL elements and LED (Light Emitting Diode) elements are arranged in the same manner as the above embodiments. The light-emitting element in the present invention is a current-driven driven element that is driven by supply of a driving current (typically, luminance is controlled).

<D: Application example>
Next, an electronic apparatus using the light emitting device 100 according to each of the above aspects will be described. FIGS. 16 to 18 show forms of electronic devices that employ the light emitting device 100 as a display device.

  FIG. 16 is a perspective view illustrating a configuration of a mobile personal computer that employs the light emitting device 100. The personal computer 2000 includes a light emitting device 100 that displays various images, and a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed.

  FIG. 17 is a perspective view illustrating a configuration of a mobile phone to which the light emitting device 100 is applied. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and a light emitting device 100 that displays various images. By operating the scroll button 3002, the screen displayed on the light emitting device 100 is scrolled.

  FIG. 18 is a perspective view illustrating a configuration of a personal digital assistant (PDA) to which the light emitting device 100 is applied. The portable information terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and a light emitting device 100 that displays various images. When the power switch 4002 is operated, various kinds of information such as an address book and a schedule book are displayed on the light emitting device 100.

  Electronic devices to which the light-emitting device according to the present invention is applied include, in addition to the devices illustrated in FIGS. 16 to 18, a digital still camera, a television, a video camera, a car navigation device, a pager, an electronic notebook, electronic paper, Examples include calculators, word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with touch panels, and the like.

DESCRIPTION OF SYMBOLS 100 ... Light-emitting device, 10 ... Element part, PX ... Pixel circuit, TDR ... Drive transistor, QWR ... Selection transistor, QEL ... Control transistor, R1, R2 ... Transistor, SW1 ... First switch, SW2: Second switch, SW3: Third switch, SW4: Fourth switch, C0: Capacity, CST: Holding capacity, C1: First capacity, C2: Second capacity, E: Light emission Element 12... Wiring group 14... Data line 20... Drive circuit 22... Scan line drive circuit 24 24 data line drive circuit 30 ... control circuit 31 and 33. 35, 37, 39... Feeder line, 120... Scanning line, 130, 132, 134.

Claims (8)

A light emitting element; a driving transistor connected in series to the light emitting element; a storage capacitor disposed between a gate and a source of the driving transistor; and a gate between the driving transistor and a data line. A pixel circuit including a selection transistor;
A correction potential generator connected to the data line corresponding to the pixel circuit;
A control unit for controlling the pixel circuit and the offset voltage generation unit,
The controller is
In the first period, the selection transistor is set to an on state so that a data potential corresponding to a designated gradation designating a gradation to be emitted by the light emitting element is supplied from the data line to the gate of the driving transistor. And
In a second period after the first period, a current according to the data potential is controlled to flow through the driving transistor, and a voltage between both ends of the storage capacitor is determined as a characteristic of the data potential and the driving transistor. And set the value to reflect
In a third period after the second period, a correction potential obtained by adding an offset voltage proportional to the data potential to the data potential is generated by the correction potential generation unit, and the correction potential is generated from the data line. Control to be supplied to the gate of the driving transistor, increase the voltage across the storage capacitor,
In a fourth period after the third period, the selection transistor is set to an off state, and the source potential of the driving transistor is changed so that the light emitting element emits light.
Light emitting device. A data line driving circuit for generating the data potential;
A first switch disposed between the data line driving circuit and the data line and switching between conduction and non-conduction between the data line driving circuit and the data line;
The correction potential generation unit
A first capacitor having a first electrode and a second electrode connected to the feed line;
A second capacitor having a third electrode and a fourth electrode connected to the data line;
A second switch disposed between the first electrode and the third electrode to switch between conduction and non-conduction between the two,
The controller is
In a data potential supply period prior to the first period, the first switch is set to an on state to supply the data potential to the data line, and the data potential is supplied to the first electrode. On the other hand, the potential of the third electrode is set to a reference potential different from the data potential, and the second switch is set to an off state,
In the first period, the first switch is set to an off state to electrically float the data line, and the potential associated with the data line is held at the data potential by a capacitor associated with the data line. Maintaining the second switch in an off state;
Maintaining the first switch and the second switch in an off state in the second period;
In the third period, the second switch is turned on to change the potential of the third electrode so that the potential of the data line changes from the data potential to the correction potential. Keep the switch off,
The light emitting device according to claim 1. The correction potential generation unit
A third switch that switches between conduction and non-conduction between the data line and the first electrode;
The power supply line to which the reference potential is supplied, and a fourth switch that switches between conduction and non-conduction with the third electrode,
The controller is
In the data potential supply period, the third switch and the fourth switch are set to an on state,
In the first period, the second period, the third period, and the fourth period, the third switch and the fourth switch are set to an off state.
The light emitting device according to claim 2. The capacitance value of the second capacitor is variably controlled according to a control signal supplied from the control unit.
The light-emitting device of Claim 2 or Claim 3. The second capacitor has a plurality of unit capacitors having different capacitance values and connected in parallel to the data line, and a plurality of fifth capacitors each disposed between each unit capacitor and the second switch. A switch,
The controller is
A control signal for controlling on / off of the fifth switch is supplied to each of the plurality of fifth switches.
The light emitting device according to claim 5. The pixel circuit includes:
A control transistor connected in series to the light emitting element and the driving transistor;
The controller is
6. The light-emitting device according to claim 1, wherein the control transistor is set to an on state during the second period, and the control transistor is set to an off state during the third period.   An electronic apparatus comprising the light-emitting device according to claim 1. A driving method of a pixel circuit, comprising: a light emitting element; a driving transistor connected in series to the light emitting element; and a storage capacitor disposed between a gate and a source of the driving transistor,
In a first period, a data potential corresponding to a designated gradation designating a gradation to be emitted by the light emitting element of the pixel circuit is supplied from a data line to the gate of the drive transistor
In a second period after the first period, a current according to the data potential is controlled to flow through the driving transistor, and the voltage across the storage capacitor is set to the data potential and the characteristics of the driving transistor. Is set to a value that reflects
In a third period after the second period, a correction potential obtained by adding an offset voltage proportional to the data potential to the data potential is supplied from the data line to the gate of the driving transistor, and between both ends of the storage capacitor. Increase the voltage of
In a fourth period after the third period, the selection transistor is set to an off state, and the source potential of the driving transistor is changed so that the light emitting element emits light.
A driving method of a pixel circuit.

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