JP2011029314A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To produce a Ti-Al alloy when a barrier layer is sputtered directly on an electrode pad of a wire bond connecting electrode part, and there is a problem that a bonding strength of the gold wire is lowered when a gold wire is wire-bonded on the Ti-Al alloy.
A step of covering a wire connection electrode pad 151b with a pad covering insulating film 154b made of polyimide before wire bonding to the wire bond connecting electrode portion 122b with a gold wire 161, on a substrate 150 including the pad covering insulating film 154b. A step of forming a barrier layer 155 and a common electrode layer 156 made of titanium / tungsten alloy, and a step of plating other bumps (for example, solder bumps) 158 and 159 or elements (for example, a magnetic sensor) by the common electrode layer 156. , A step of removing the barrier layer 155 and the common electrode layer 156, and a step of wire bonding with the gold wire 161 after removing the pad covering insulating film 153.
[Selection] Figure 3

Description

  The present invention relates to a method of manufacturing a semiconductor device having a bonding pad portion and a protrusion formed by plating such as a bump or a sensor on the active surface side of a semiconductor substrate.

  After forming a UBM (under bump metal), which is a laminated film of a barrier layer and a common electrode layer on an aluminum electrode pad, removing the UBM again and forming a wire bond on the exposed aluminum electrode pad, the adhesion strength of the wire bond There is a problem that decreases. For example, Patent Document 1 discloses an electrical connection processing method having both wire bond and solder connection electrode pads. A method for manufacturing the semiconductor device described in Patent Document 1 will be described with reference to the cross-sectional views of FIGS.

First, referring to FIG. 14A, a barrier layer 426 and a gold layer are formed on the electrode pads (hereinafter also referred to as “aluminum pads”) of the solder connection electrode portion 422a and the wire bond connection electrode portion 422b of Patent Document 1 and around the electrode pads. A manufacturing method until the layer 428 is formed and the gold layer 428a of the solder connection electrode portion 422a is exposed will be described. (In addition, the whole surface coating layer is indicated by a symbol without a and b. The same applies hereinafter.)
In the substrate 420 having the electrode pad (aluminum pad) 424a of the solder connection electrode part 422a and the electrode pad (aluminum pad) 424b of the wire bond connection electrode part 422b, Ti− which is a barrier layer on the aluminum pad 424a and the aluminum pad 424b. The W layer 426 and the gold layer 428 are continuously sputtered.

  Photoresist is spin-coated on the gold layer 428, and a photolithographic technique is used to leave a photoresist on the gold layer 428 on the aluminum pad 424a and the aluminum pad 424b. Using this photoresist as a mask, the aluminum pad 424a and The gold layer 428 around 424b is removed by wet etching. Next, the photoresist and the patterned gold layer 428a and gold layer 428b are used as etching masks, the Ti—W layer 426 is removed by wet etching, and the Ti—W layer 426a and the Ti—W layer 426b are patterned. After exposing the periphery of the aluminum pad, the photoresist is dissolved in a resist stripper and removed.

  Next, polyimide 430 is spin-coated and then cured, and an aluminum layer 432 is formed on the polyimide 430 by sputtering. Photoresist 434 is spin-coated on the aluminum layer 432, and the photoresist 434 in the solder connection electrode portion 422a region is opened by photolithography. Further, the aluminum layer 432 in the solder connection electrode portion 422a region is removed by etching using the photoresist 434 as an etching mask. Next, the polyimide 430 in the solder connection electrode portion 422a region is etched using the photoresist 434 as an etching mask (see FIG. 14A), and then the photoresist 434 is dissolved and stripped with a resist stripping solution.

  Next, a method for forming a solder layer on the solder connection electrode portion 422a will be described with reference to FIG. The substrate 420 is exposed to a molten solder bath, and a solder layer 438 is formed on the polyimide 430 and the exposed gold layer 428a from which the photoresist 434 and the aluminum layer 432 have been removed. At this time, since the gold layer 428a diffuses into the molten solder in the solder connection electrode portion 422a, the solder layer 438 is formed on the Ti-W layer 426a of the solder connection electrode portion 422a.

  Next, as shown in FIG. 15C, a manufacturing method until the wire bond connection electrode portion 422b is exposed and the solder layer 452 is formed on the electrode pad 424a for solder connection will be described. First, excess solder other than on the wire bond connection electrode part 422b and the solder connection electrode part 422a for which wire bonding is desired is removed with a hot air knife, thereby forming a bump solder layer 452 on the solder connection electrode part 422a. To do.

  Next, a photoresist is spin-coated on the substrate 420, the photoresist of the wire bond connection electrode portion 422b is removed by photolithography, and the polyimide 430 is exposed. Then, using the photoresist as an etching mask, the polyimide 430 of the wire bond connection electrode portion 422b is etched to expose the gold layer 428b. Thereafter, when the photoresist is dissolved and stripped with a resist stripper, an opening is formed in the polyimide 430 of the wire bond connection electrode portion 422b shown in FIG. 15C, and a connection electrode portion capable of wire bonding is obtained.

Such a manufacturing method of Patent Document 1 has a drawback that the process is long and the cost is increased because there is a process of covering the pad with a gold layer. Thus, for example, Japanese Patent Application Laid-Open No. H10-228707 is a technique that can shorten the manufacturing process and omit the gold layer. The manufacturing method of patent document 2 is demonstrated using sectional drawing of Fig.16 (a) to FIG.19 (h).
First, a mounting cross-sectional view of a semiconductor substrate in which the solder connection electrode portion and the wire bond connection electrode portion of Patent Document 2 are present on the same surface will be described with reference to FIG. The second semiconductor chip 551 is mounted face down on the surface of the first semiconductor chip 550, and the solder 503 and the solder 504 are electrically connected.

  On the other hand, a package having pads for wire bond connection is provided around the first semiconductor chip 550, and the wire bond connection electrode portion of the first semiconductor chip 550 and the lead terminal of the package 560 is wire-bonded with a wire 559. Reference numeral 505 denotes a circuit board, and the first semiconductor chip 550 is mounted on the die bond pattern 506. Reference numeral 561 denotes a sealing resin, and the first semiconductor chip 550, the second semiconductor chip 551, and the circuit board 505 are sealed by the sealing resin 561 from the outside air.

FIG. 16B and subsequent figures are enlarged views of the first semiconductor chip 550 in the A part of FIG. A method for manufacturing the solder connection electrode portion 522a and the wire bond connection electrode portion 522b will be described with reference to FIGS. 16 (b) to 19 (h).
In FIG. 16B, a solder connection electrode portion 522a and a wire bond connection electrode portion 522b are formed on the first semiconductor chip 550, and a solder connection electrode pad 551a and a wire bond connection electrode pad 551b are formed. . Then, an opening of the first insulating film 552 is formed so that each central portion of the electrode pad 551a and the electrode pad 551b formed in the first semiconductor chip 550 is exposed. These electrode pads are input / output terminals of the semiconductor device, and are an electrode pad 551a for solder connection and an electrode pad 551b for wire bond connection. The material of each connection electrode pad 551a, 551b contains aluminum. Examples of the material of the first insulating film 552 covering the periphery of the electrode pads 551a and 551b include a silicon nitride film, a silicon oxide film, and polyimide.

  Next, in FIG. 17C, a barrier layer 553 is formed on the entire surface of the wafer including the first insulating film 552 and the electrode pads 551a and 551b by sputtering or the like. Next, as shown in FIG. 17D, a common electrode layer 554 is formed on the barrier layer 553. At this time, it is preferable to form by continuous sputtering without breaking the vacuum. The barrier layer 553 is made of, for example, titanium, a titanium / tungsten alloy, chromium, or the like, and the common electrode layer 554 is made of gold, copper, or the like.

  When titanium or a titanium / tungsten alloy is formed on the aluminum material of the electrode pads 551a and 551b, aluminum and titanium are alloyed to form a titanium / aluminum alloy layer 551c. The titanium / aluminum alloy layer 551c is formed when Ti atoms collide with the aluminum pad at high speed when the barrier layer of titanium or titanium / tungsten alloy is formed by sputtering, so that the Ti atoms lose kinetic energy. This is because the thermal energy is increased and the temperature of the aluminum pad rises and titanium and aluminum are alloyed.

  In FIG. 18E, first, a photoresist 555 is formed on the entire surface of the wafer on the common electrode layer 554 by spin coating. Then, an opening is formed in the solder connection electrode portion 522a of the photoresist 555 by patterning with photolithography. Then, as shown in FIG. 18 (f), the opening is plated with copper as the first plating 556 and the solder layer as the second plating 557 by electrolytic plating. At this time, if plating exceeds the thickness of the photoresist 555, the plating grows isotropically, resulting in a mushroom-like plating shape.

  In FIG. 19G, the photoresist 555 is immersed in a resist stripping solution made of an organic solvent to dissolve and remove the photoresist in the resist stripping solution to expose the common electrode layer 554. After that, the first insulating film 552 is exposed by etching and removing the common electrode layer 554 and the barrier layer 553 by wet etching. At this time, the titanium / aluminum alloy layer 551c remains in the aluminum pads 551a and 551b.

  Next, in FIG. 19H, the flux is spin-coated, the solder layer 557 is heated to the melting point or higher in a reflow furnace, and the solder layer 557 is rounded by the surface tension of the flux to form the protruding electrode 558. Further, the wire bond connection electrode portion 522b is wire-bonded to the vicinity of the center of the wire bond connection electrode portion 522b with the wire 559, and the wire 559 is electrically connected to the wire bond connection electrode portion 522b of the first semiconductor chip 550.

  In Patent Document 2 described above, in a semiconductor substrate in which a solder connection electrode portion and a wire bond connection electrode portion exist on the same surface, a titanium / tungsten alloy layer on an aluminum (Al) pad of the wire bond connection electrode portion and The common electrode layer is removed to expose the Al pad. However, when a gold wire is wire bonded to the exposed Al pad, there is a problem that the adhesion strength is lowered. The reason for this is that the exposed Al electrode of the wire bond connection electrode part is irradiated with argon ions to cause ion bombardment, and the Auger electron spectroscopic analysis is performed by causing the ejected Auger electrons to enter the spectrometer. The element Ti of the barrier layer was detected from the surface.

  This Ti forms a thin film by argon ions colliding with the target Ti by sputtering, blowing off Ti atoms and depositing on the semiconductor substrate facing the target. When Ti atoms collide with the Al pad surface of the semiconductor substrate at high speed, the kinetic energy is lost and converted into heat energy, and the Al pad is heated. Since the collision energy is large, the temperature rise of the Al pad is also large. Therefore, Al and Ti are alloyed. When an Al—Ti alloy is formed, even if a gold wire is wire-bonded to an Al pad, Ti atoms are present on the surface of the aluminum pad. The area is reduced. For this reason, the problem that the adhesive strength of a wire bond fell occurred.

  Also in Patent Document 3 of the next prior art, after forming a UBM (under bump metal) which is a laminated film of a titanium / tungsten alloy (Ti-W) and copper on an aluminum pad, the UBM is removed and exposed again. When gold wire bonds or gold sudden bumps are formed on an aluminum pad, there is a problem that the adhesion strength is lowered. A method of manufacturing the semiconductor device described in Patent Document 3 will be described with reference to the cross-sectional views of FIGS. 20 (a) to 22 (e).

  As shown in FIG. 20A, by patterning an insulating layer (polyimide) 613 on the semiconductor substrate 610, the polyimide is formed on the semiconductor thin film 611 having the magnetic sensitive portion 611a except for the metal electrode (Al pad) 612 portion. A protective film 613a which is an insulating layer made of is formed.

  Next, as shown in FIG. 20B, the barrier layer 614a is common on the protective film 613a and the metal electrode (Al pad) 612 on the active surface side of the magnetic sensitive part 611a as a base layer for the plating process. The electrode layer 614b is formed, and the base layer 615 is formed on the semiconductor substrate 610 and on the non-active surface side that is the back side of the magnetic sensitive part 611a. The barrier layer 614a and the common electrode layer 614b are laminated films made of Ti—W and Cu, and can be formed by a sputtering method or the like. At this time, in order to form the barrier layer 614a by a sputtering method, an alloy layer 612a of Al and Ti is formed on the metal electrode (Al pad) 612.

  Next, as shown in FIG. 21C, a photoresist 616 is formed on the common electrode layer 614b, and the photoresist 616 is photolithography so that the common electrode layer 614b is exposed on the central portion of the magnetic sensitive portion 611a. Resist patterning is performed by a technique to form the opening 616a. Then, the first magnetic body 617 having a magnetic amplification function is formed in the opening 616a removed by photoresist patterning on the common electrode layer 614b, and the first magnetic body 617 is magnetically formed on the underlayer 615 on the back surface. A second magnetic body 618 having an amplification function is formed by plating.

  Next, as shown in FIG. 21D, the photoresist 616 is immersed in a resist stripping solution and dissolved and removed. Next, as shown in FIG. 22E, using the first magnetic body 617 as an etching mask, the common electrode layer 614b is removed by etching leaving the lower layer of the first magnetic body 617, and then the barrier layer 614a is also formed. Remove by etching. Thereafter, the plurality of magnetic sensor chips are separated into single chips by dicing. Finally, the gold wire 619 is wire-bonded to the central portion of the metal electrode 612, and the gold wire 619 and the metal electrode 612 are electrically connected. At this time, the surface of the metal electrode 612 is covered with an alloy layer 612a of Al and Ti.

Japanese Patent Laid-Open No. 6-89919 (paragraph 0009 to page 5, paragraph 0021 from page 4 and FIGS. 3 (a) to 4 (d)) Japanese Patent Application Laid-Open No. 11-54695 (2nd page paragraph 0007 to 4th page paragraph 0018 and FIGS. 1 to 2) JP 2007-108011 (8th page paragraph 0043 to 9th page paragraph 0051 and FIG. 2 (a) to FIG. 3 (g))

  In the method of manufacturing a semiconductor device described in Patent Document 1, there is no decrease in wire bond strength, but the steps of gold layer formation, polyimide patterning, aluminum layer patterning and solder replacement, and removal of excess solder are performed. Since it is necessary, the number of steps is long, and an expensive gold layer is required.

Moreover, in the manufacturing method of the semiconductor device described in Patent Document 2 and Patent Document 3, there is a problem that an Al—Ti alloy described later is formed on the Al pad of the wire bond connection electrode portion where wire bonding is desired. . That is, UBM (under bump metal) is a laminated film of a barrier layer (Ti, Ti-W, Cr) and a common electrode layer (Cu, Au), but generally a metal is formed by sputtering. . Sputtering equipment causes argon ions to collide with target Ti at a high speed to eject Ti atoms, and when colliding with aluminum on the Al pad, the kinetic energy of Ti atoms is lost at the time of collision and converted to thermal energy. The aluminum temperature of the pad reaches a high temperature and Ti and Al are alloyed.

  The Ti—Al alloy can remove the Al—Ti alloy even if the common electrode layer (copper layer or gold layer) is wet etched and then the barrier layer (Ti—W layer or Ti layer) is wet etched. Since this is not possible, there arises a problem that the Ti—Al alloy remains on the Al pad. In this way, if an Al-Ti alloy is present on the surface of the Al pad, Ti atoms remain, so even if a gold wire is wire-bonded or a gold sudat bump is bonded, it is inhibited by Ti and becomes an Al-Au alloy. Since it is difficult, there exists a problem that the joint strength of a wire bond falls.

  The object of the present invention is to solve the above problems, eliminate the need for a gold layer, shorten the process, reduce the cost, prevent the formation of an Al-Ti alloy layer on the Al pad, It is an object of the present invention to provide a method for manufacturing a semiconductor device in which the mechanical strength of the bond is not deteriorated.

  In order to achieve the above object, a semiconductor device manufacturing method according to the present invention includes a bonding pad portion and a protrusion formed by plating on an active surface side of a semiconductor substrate. Forming a pad covering protective film covering the entire surface of the electrode pad; forming a barrier layer and a common electrode layer on the active surface side of the semiconductor substrate including the protective film; and a protrusion using the common electrode layer A step of forming the protrusion in a formation region by plating; a step of removing the barrier layer and the common electrode layer other than the protrusion formation region; and the pad covering protective film on the electrode pad of the bonding pad portion. It comprises a step of removing and a step of bonding to the electrode pad of the bonding pad portion with a wire.

  The method further includes a passivation film having an opening in the electrode pad of the bonding pad portion, and a first protective film formed on the passivation film and having an opening in the electrode pad of the bonding pad portion.

  Both the first protective film and the pad covering protective film are formed of polyimide or PBO (polybenzoxazole).

  The pad covering protective film is formed of a film thinner than the first protective film.

  The barrier layer includes titanium or a titanium alloy.

  The barrier layer includes chromium.

  The wire is a gold wire or a gold alloy wire.

  Wire bonding or stud bump bonding is formed on the bonding pad portion.

  The protrusion formed by the plating is a solder bump electrode portion.

According to the manufacturing method of the present invention, since there is a pad covering protective film on an Al pad for which wire bonding is desired, aluminum of the Al pad and Ti of the barrier layer are not in direct contact. Therefore,
Al and Ti are not alloyed. Since Ti and TiW on the pad covering protective film on the Al pad desired by the wire bond do not become an Al—Ti alloy, they can be easily removed by etching. Also, polyimide and PBO as a pad covering protective film can be easily removed by ashing. That is, since the Al pad that does not contain Ti can be exposed before the wire bonding step, there is no problem that the wire bond strength is lowered.

It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention, (a) And (b) process is shown. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention, (c) And (d) process is shown. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention, (e) And (f) process is shown. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention, (g) And (h) process is shown. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention, (i) And (j) Process is shown. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention, (k) and (l) process are shown. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention, (m) A process is shown. It is a flowchart figure which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is sectional drawing which shows the (d) process of the manufacturing method of the semiconductor device as a modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention, (a) And (b) process is shown. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention, (c) And (d) process is shown. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention, (e) And (f) process is shown. It is a flowchart figure which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device described in patent document 1 which is a prior art, (a) And (b) process is shown. It is sectional drawing which shows the manufacturing method of the semiconductor device described in patent document 1 which is a prior art, (c) A process is shown. It is sectional drawing which shows the manufacturing method of the semiconductor device described in patent document 2 which is a prior art, (a) And (b) process is shown. It is sectional drawing which shows the manufacturing method of the semiconductor device described in patent document 2 which is a prior art, and shows process (c) and (d). It is sectional drawing which shows the manufacturing method of the semiconductor device described in patent document 2 which is a prior art, and (e) and (f) process are shown. It is sectional drawing which shows the manufacturing method of the semiconductor device described in patent document 2 which is a prior art, and shows (g) and (h) process. It is sectional drawing which shows the manufacturing method of the semiconductor device described in patent document 3 which is a prior art, and shows process (a) and (b). It is sectional drawing which shows the manufacturing method of the semiconductor device described in patent document 2 which is a prior art, and shows process (c) and (d). It is sectional drawing which shows the manufacturing method of the semiconductor device described in patent document 2 which is a prior art, and (e) process is shown.

In the drawings illustrating the embodiments of the present invention, the size and film thickness of each component are appropriately enlarged or reduced to an easily understandable size and film thickness, and are different from the actual size and film thickness of the component. Further, in the drawings illustrating the embodiments of the present invention, active elements such as transistors and diodes formed inside a semiconductor substrate, passive elements such as resistors and capacitors, contact holes, and a plurality of metal layers are not illustrated. Omitted.
A method for manufacturing a semiconductor device according to a first embodiment for carrying out the present invention will be described below with reference to the drawings. FIGS. 1A to 7M are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 8 shows the semiconductor device according to the first embodiment of the present invention. It is a flowchart figure of a manufacturing method. A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1A to 7M and FIG.

  First, in FIG. 1A and step S01 of the flowchart, electrode pads 151a and 151b which are input / output terminals of the semiconductor device are formed in each part of the solder connection electrode part 122a and the wire bond connection electrode part 122b on the semiconductor substrate 150. . An active element and a passive element are connected to the electrode pads 151a and 151b by a metal layer. The electrode pads 151a and 151b are formed on the periphery of the semiconductor substrate 150 and on an inter-element isolation insulating film (not shown). The electrode pads 151a and 151b are made of aluminum or aluminum alloy which is the same material as the metal layer. A first insulating film 152 is formed on the entire surface of the semiconductor substrate 150 including the electrode pads 151a and 151b. Thereafter, the first insulating film 152 is patterned using photolithography technology and etching technology so that the central regions of the electrode pads 151a and 151b are opened.

  In order to prevent moisture from entering from the peripheral portions of the electrode pads 151a and 151b, the peripheral portions of the electrode pads 151a and 151b are preferably covered with the first insulating film 152. The first insulating film 152 is also called a passivation film, and is formed of an inorganic insulating film such as a silicon nitride film or a silicon oxide film, or an organic insulating film such as polyimide resin or PBO (polybenzoxazole) resin. The active elements and passive elements formed on the semiconductor substrate 150 are also covered with the insulating film 152. Although the sectional shape of the opening of the insulating film 152 is not illustrated, it is preferable that the opening top surface dimension is larger than the opening bottom surface dimension and the opening sidewall is tapered. When the sectional shape of the opening of the first insulating film 152 is tapered, the step coverage of the under bump metal to be formed in the next step is improved, and the opening side wall can be formed with the same film thickness as the flat portion. It is possible to prevent disconnection and resistance increase at the stepped portion.

  Next, in step S02 of FIG. 1B and the flowchart, the second insulating film (polyimide layer) 153 is exposed in the central region of the electrode pads 151a and 151b so as to cover the first insulating film 152. Form. The film thickness of the second insulating film 153 is desirably 2 μm to 5 μm. The second insulating film 153 prevents moisture from entering by filling the pinholes of the first insulating film 152 with polyimide, prevents corrosion of the aluminum wiring of the semiconductor substrate 150, and improves reliability. In addition, when the semiconductor substrate 150 is handled, the insulating film has a two-layer thickness to prevent scratches on the surface of the semiconductor substrate 150, so that it is less likely to be damaged and reliability is improved. The second insulating film 153 made of polyimide or PBO is preferably formed on the first insulating film 152, but it is omitted if the first insulating film 152 has few pinholes and the cost is to be reduced. Also good.

From here on is the technology that is the point of the manufacturing method of the present invention. The third insulating film 154 is patterned in order to form a pad covering protective film 154b, which is a third insulating film, in the opening of the aluminum electrode pad 151b of the wire bond connecting electrode portion 122b where wire bonding is desired.

  In the negative photosensitive polyimide coating process as the third insulating film 154, a negative photosensitive polyimide varnish is dropped onto the center of the stationary semiconductor substrate 150 using a spin coater. The dripping amount is about 3 g when the semiconductor substrate 150 is a 6-inch wafer. The coating is applied to the entire surface by setting the rotation speed of the spin coater to about 2000 to 5000 rpm. The film thickness of the negative photosensitive polyimide after the curing process described later is reduced to about half of the film thickness applied by the spin coater. Therefore, the rotation speed and rotation time of the spin coater are adjusted so that the film thickness about twice that after curing is the film thickness after spin coating.

FIG. 2C is a diagram in which the third insulating film 154 is applied to the entire surface of the substrate 150 on the electrode pads 151a and 151b and the second insulating film 153 of the solder connection electrode portion 122a and the wire bond connection electrode portion 122b. This is shown in step S03 of the flowchart.
When a negative photosensitive polyimide varnish is applied as the third insulating film 154, the negative photosensitive polyimide varnish is exposed to ultraviolet rays. The monomer in the varnish has a property that the crosslinking reaction proceeds three-dimensionally by the photosensitive agent contained in the varnish, and the varnish becomes insoluble in the developer in the subsequent development step. The negative photosensitive polyimide is used because of its high heat resistance.

  Next, as shown in FIG. 2 (d) and step S04 in the flowchart, the negative photosensitive polyimide exposure step uses an exposure apparatus to selectively transmit ultraviolet rays through a photomask to expose the negative photosensitive polyimide. . Exposure apparatuses are roughly classified into proximity type batch exposure apparatuses and steppers. The proximity type batch exposure apparatus is an apparatus that exposes with a gap of about 10 to 50 μm between a semiconductor substrate and a photomask. In order to open the proximity gap, the negative photosensitive polyimide does not come into contact with the photomask and therefore is less likely to be contaminated. However, there is a disadvantage that the resolution of the UV light is reduced because the UV light wraps around the light shielding portion of the photomask due to the light diffraction phenomenon.

On the other hand, the stepper projects a photomask image on a semiconductor substrate using a projection lens, so that the diffraction phenomenon is small and the resolution is high, but the apparatus is expensive. When the required resolution is high, that is, when the pattern size of the pad covering protective film is small and is about 20 μm or less, exposure is performed with a stepper with high resolution.
In the negative photosensitive polyimide exposure, the photomask 131b is used to block the incident ultraviolet ray 130a by the photomask 131b, and the emitted ultraviolet ray 130b causes the third insulating film 153 that is the wire bond electrode 151b to be in the opening of the third insulating film 153. Ultraviolet rays enter only the insulating film 154 and the varnish is exposed.

Next, as shown in FIG. 3 (e) and step S05 of the flowchart, in the negative photosensitive polyimide developing step, the semiconductor substrate 150 after the exposure of the negative photosensitive polyimide is immersed in a developer, and a photomask The varnish that is shielded from ultraviolet rays by 131b and is not exposed to light is dissolved in a developing solution and removed. The development may be a method of spraying the developer in a mist form from a two-fluid nozzle in addition to the method of immersing in the developer. In the two-fluid development, a developer and nitrogen are mixed and atomized from a nozzle and sprayed. The developer pressure is 0.5 to 1 kg / cm ² , the nitrogen pressure is about ² to 5 kg / cm ² , and the flow rate is about 50 to 100 mL / min, and the semiconductor substrate 150 is rotated at about 1000 to 3000 rpm. While spraying, spray the mist developer. The non-photosensitive varnish dissolves in the developer and is scattered and removed to the outside of the semiconductor substrate 150 by centrifugal force.

Rinse after development. The rinsing liquid is atomized from the two-fluid nozzle and sprayed to replace the developer. The rinsing conditions such as the number of rotations of the semiconductor substrate 150 and the pressure / flow rate of the two-fluid nozzle are set to the same level as the developing conditions. Thereafter, the semiconductor substrate 150 is rotated at about 3000 rpm,
After the rinsing liquid is scattered on the outer periphery of the semiconductor substrate 150, the rinsing liquid is evaporated to complete the rinsing. Two-fluid development is desirable for the development of negative photosensitive polyimide having poor solubility of the unphotosensitized varnish.

Next, as in step S06 of the flowchart, the negative photosensitive polyimide that is the third insulating film 154b is cured. For curing polyimide and PBO, nitrogen gas is introduced into the furnace using a hot-air circulating furnace or vertical furnace, low oxygen, that is, 100 ppm or less, temperature is 350 ° C. to 450 ° C., and time is 1 to 2 hours. It is desirable to leave it alone. Note that when the second insulating film 153 is omitted, the third insulating film 154b becomes the second insulating film. The thickness of the third insulating film 154 b is preferably 0.2 μm to 0.5 μm, and is preferably about 1/10 of the thickness of the second insulating film 153.
Thus, the third insulating film 154b formed in the opening of the second insulating film 153 and on the electrode pad 151b is the pad covering protective film which is a feature of the present application.

  Thereafter, as shown in FIG. 3 (f) and step S07 in the flowchart, a barrier layer serving as an under bump metal is formed on the entire surface of the second insulating film 153, the third insulating film 154b, and the electrode pad 151a on the semiconductor substrate 150. 155 and the common electrode layer 156 are formed using a sputtering apparatus. When the barrier layer 155 and the common electrode layer 156 are formed using this sputtering apparatus, they are continuously formed on the semiconductor substrate 150 without releasing the reduced pressure state of the sputtering apparatus. By forming the film in this manner, an oxide film or an impurity layer that inhibits adhesion is not formed between the barrier layer 155 and the common electrode layer 156.

Further, before the barrier layer 155 is formed, argon (Ar) gas is introduced into a sputtering apparatus so that the semiconductor substrate 150 serves as a cathode, and a natural oxide film formed on the surface of the electrode pad 151a is sputter-etched (reverse sputtering). It is preferable to remove by. In the sputter etching, ionized argon is made to collide with the electrode pad 151a, and etching is performed while blowing off atoms of the natural oxide film (Al ₂ O ₃ ) from the surface of the electrode pad 151a. As a result, in the solder connection electrode portion 122a, the adhesion between the electrode pad 151a and the barrier layer 155 is improved, and the contact resistance between the two films can be reduced.

In the wire connection electrode portion 122b, the third insulating film 154b is also etched by sputter etching. However, since the film thickness of the natural oxide film (Al ₂ O ₃ ) is about 100 mm, the natural oxide film (Al ₂ O ₃ ) can be completely removed by etching with the etching amount adjusted to about 200 mm. In addition, the film loss of the third insulating film 154b can be ignored. The barrier layer 155 is a titanium-tungsten (Ti-W) alloy and has a thickness of 20 nm to 50 nm. The titanium / tungsten alloy which is the barrier layer 155 is an alloy containing 5% to 20% by weight of titanium and the balance being tungsten.

  Next, the common electrode layer 156 is copper having a thickness of 0.2 μm to 1.0 μm. Under bump metal prevents mutual diffusion, improves adhesion between coatings and reduces contact resistance, and also functions as a plating electrode when forming post and protruding electrodes to be described later by electrolytic plating. It also has. Note that an Al—Ti alloy layer 151c is formed on the electrode pad 151a of the solder connection electrode portion 122a because aluminum and titanium are in direct contact with each other at high speed by sputtering. This will be described later.

After the sputter etching, the barrier layer Ti—W is sputtered without breaking the vacuum. At this time, an Al-Ti alloy layer 151c is formed on the electrode pad 151a of the solder connection electrode 122a. The Al—Ti alloy layer is an alloy layer diffused between the Al pad and the Ti—W layer by sputtering of the barrier layer. Since the kinetic energy of sputtering Ti and W is large, the Al-Ti alloy layer and the Al pad Al or barrier layer T
Adhesion with i-W layer is high. Therefore, there is no adverse effect on adhesion and electrical resistance.

  On the other hand, in the wire bond connection electrode portion 122b, a pad covering protective film 154b is formed on the electrode pad 151b. For this reason, even if Ti and W atoms collide with the polyimide film which is the pad covering protective film 154b by sputtering, the polyimide film can withstand the high heat of sputtering, and the Al atoms and Ti atoms on the electrode pad 151b are in contact with each other. Functions as a protective film to prevent. Therefore, an Al—Ti alloy layer is not generated on the electrode pad 151b of the wire bond connection electrode portion 122b.

  Thereafter, as shown in FIG. 4G and step S08 of the flowchart, a photosensitive resist 157 is formed on the entire surface of the common electrode layer 156 with a thickness of 5 μm to 20 μm by spin coating. The photosensitive resist 157 is preferably a positive resist having good peelability. Negative resists can also be used as photosensitive resists, but the releasability is slightly poor, so that the stripping treatment requires immersion at a high temperature for the stripping solution. Thereafter, patterning is performed by exposure processing and development processing which are photolithography techniques, and openings 157a are formed in the photosensitive resist 157 so that the common electrode layer 156 of the solder connection electrode portions 122a is exposed. The opening 157a functions as a plating mask having a role of selectively forming posts and protruding electrodes in the region of the electrode pad 151a.

  Thereafter, as shown in FIG. 4 (h) and step S09 of the flowchart, a post 158 and a solder layer 159 are formed on the common electrode layer 156 of the opening 157a as projections formed by plating of the present application. The post 158 is made of copper and is formed by electrolytic plating. In this electrolytic plating process, the barrier layer 155 and the common electrode layer 156 are used as plating electrodes.

  The post 158 is preferably formed with a thickness of 5 μm to 25 μm. The post 158 is formed below the thickness of the photosensitive resist 157 and the side wall portion is formed in a straight wall shape perpendicular to the surface of the semiconductor substrate 150, or exceeds the thickness of the photosensitive resist 157, and the top portion protrudes from the base portion. The cross-sectional shape of either mushroom shape is good. With a straight wall shape, the pitch dimension between the electrode pads 151a and 151b can be reduced, and the pitch of the bump electrodes can be reduced. Moreover, when the mushroom-shaped post 158 is used, the bonding area with the solder is increased, and the bonding strength of the protruding electrode can be increased.

  The post 158 increases the gap size between the semiconductor device and the circuit board to reduce the stress generated due to the difference in thermal expansion coefficient between the mounted semiconductor device and the substrate, and the bump electrode bonding caused by this stress. In addition to preventing the destruction of the portion, it also serves as a barrier layer that prevents mutual diffusion between the solder layer 159 and the common electrode layer 156 formed in the process described later. As a material for the post 158, nickel or a nickel alloy having an excellent anti-diffusion function can be used in addition to copper. The solder layer 159 is formed on the post 158 in the opening 157a of the photosensitive resist by electrolytic plating using the barrier layer 155 and the common electrode layer 156 as plating electrodes.

In FIG. 4H, the post 158 is formed with a thickness exceeding the film thickness of the photosensitive resist 157. Since the post 158 formed beyond the thickness of the photosensitive resist 157 is isotropically formed with a plating film, the cross-sectional shape is a mushroom shape. The solder layer 159 is lead-free solder. For example, it is made of a tin (96.5 wt%)-silver (3.5 wt%) alloy. A lead-free solder that generates environmental pollution is used as the solder layer 159. The solder layer 159 may be formed by a method of mounting solder balls on the posts 158 in the openings 157a in addition to forming solder by a plating method, or by using a solder paste for the posts 158 in the openings 157a.
You may form using the method of filling with a squeegee on the top.

  Thereafter, as shown in FIG. 5I and step S10 of the flowchart, the photosensitive resist 157 used as the plating mask for forming the solder layer 159 and the post 158 is peeled off.

  Next, as shown in FIG. 5J and step S11 of the flowchart, the common electrode layer 156 and the barrier layer 155 exposed from the post 158 are removed by etching. At this time, since the third insulating film 154b formed in the electrode pad 151b of the wire bond connecting electrode portion 122b is not corroded by the etching solution for the common electrode layer 156 and the barrier layer 155 described later, it remains without being removed. .

  First, the etching of the common electrode layer 156 made of copper is performed by immersing the semiconductor substrate 150 in an etchant that selectively etches the common electrode layer 156 using the post 158 as an etching mask. As the copper etching solution, a potassium dichromate solution acidified with sulfuric acid was used. When the material of the post 158 and the material of the common electrode layer 156 are the same copper, the post 158 is etched simultaneously with the common electrode layer 156. Therefore, by setting the thickness of the common electrode layer 156 as thin as about 1 μm or less, the etching time of the common electrode layer 156 can be shortened, and the etching amount of the post 158 can be reduced.

Etching of the barrier layer 155 made of titanium / tungsten alloy is performed by immersing the semiconductor substrate 150 in an etchant that selectively etches the barrier layer 155 using the common electrode layer 156 as an etching mask. As an etching solution for the titanium / tungsten alloy, a mixed solution in which ammonia (NH ₄ OH) was mixed with hydrogen peroxide solution (H ₂ O ₂ ) was used.

  Next, as shown in FIG. 6K and step S12 of the flowchart, the protruding electrode 160 is formed by performing a reflow process (wet back process) for melting the solder layer 159. In this reflow process, a flux is formed on the surface of the semiconductor substrate 150 on which the solder layer 159 is formed by spin coating to a thickness of 10 μm to 50 μm, and then the temperature exceeding the melting point (221 ° C.) of the solder layer 159 is 250 ° C. to 270 ° C. Heat treatment is performed at ℃. By the reflow process, the solder layer 159 is melted and rounded by the surface tension, and the spherical protruding electrode 160 is obtained. The spherical protruding electrode 160 formed by this reflow process is formed to a height of about 100 μm.

  Further, the outer dimension of the spherical protruding electrode 160 is larger than the outer dimension of the post 158. That is, the protruding electrode 160 is formed in a volume sufficient for the outer peripheral portion of the protruding electrode 160 to project on the post 158 in an eave shape. Thereafter, the flux is removed by performing a cleaning process. In this reflow process, the solder layer 159 may be melted by heat treatment in a hydrogen reducing atmosphere without performing flux spin coating.

  Thereafter, as shown in FIG. 6L and step S13 in the flowchart, the polyimide layer, which is the third insulating film 154b formed on the electrode pad 151b of the wire bond connecting electrode portion 122b, is ashed with oxygen plasma. Remove. When the thickness of the third insulating film 154b is 0.2 μm to 0.5 μm, the removal amount, which is an ashing condition, is about 1.25 times the thickness of the insulating film 154b. Therefore, when the removal amount by ashing is set to 0.25 μm to 0.625 μm, the third insulating film 154b can be completely removed, and the film loss of the second insulating film 153 can be reduced.

As described above, the polyimide layer 154b as the third insulating film is formed on the electrode pad 151b.
Since the polyimide layer 154b can withstand a high temperature when sputtered and can prevent thermal diffusion due to contact between titanium and aluminum, since it is between the aluminum and the titanium / tungsten alloy of the barrier layer 155, Formation of the Al—Ti alloy layer can be prevented.

  Finally, as shown in FIG. 7M and step S14 of the flowchart, the semiconductor substrate 150 is cut into individual IC chips by dicing, and then a gold wire is placed on the electrode pad 151b of the wire bond connection electrode portion 122b of the semiconductor substrate 150. 161 is wire-bonded. As a result, the electrode pad 151b and the gold wire 161 are electrically connected. At this time, since the aluminum of the electrode pad 151b is not alloyed with titanium, the gold wire 161 is firmly connected to the aluminum material of the electrode pad 151b.

  This is the end of the description of the first embodiment of the present invention. Next, a method for manufacturing a semiconductor device as a modification of the first embodiment of the present invention will be described. In the first embodiment, a negative type polyimide material is used as the third insulating layer. However, in the modification, a manufacturing method using a positive type polyimide material as the third insulating layer will be described. Note that the flowchart is exactly the same as that in FIG. 8, and the manufacturing process is only described in FIG.

  FIG. 9D illustrates an exposure process for the third insulating layer. When the varnish of polybenzoxazole (PBO), which is a positive photosensitive resin, is applied to the third insulating film 154, the varnish of PBO is exposed to ultraviolet rays. The resin in the varnish has a property that the photochemical reaction proceeds by the photosensitive agent contained in the resin, and the varnish becomes soluble in the developer in the subsequent development process.

  As shown in FIG. 9 (d) and step S04 of the flowchart, the exposure process when using this positive type PBO material includes a photomask 131b that blocks light only on the electrode pad 151b on the upper surface of the substrate 150. When the incident ultraviolet ray 130a is irradiated from above the photomask 131b by the photolithography technique, the positive PBO material other than the electrode pad 151b changes to be soluble in the developer by the photochemical reaction.

  Next, PBO development is performed as in step S05 of the flowchart. Development of PBO is performed by dipping in a developing solution or by paddle development. In paddle development, a developer is deposited on the semiconductor substrate 150, the semiconductor substrate 150 and the developer are kept stationary during development, and the exposed varnish is diffused and dissolved in the developer. Development conditions are a room temperature of about 23 ° C. and a development time of about 1 minute.

  Rinse after development. The rinsing is performed by displacing the semiconductor substrate 150 with pure water while rotating the semiconductor substrate 150 at about 1000 rpm, and then rinsing the semiconductor substrate 150 at about 3000 rpm. Evaporate after scattering to the outer periphery. Paddle development is generally performed by immersion because the developer is stationary. Since the developing speed is difficult to change due to the uneven flow rate of the developing solution on the semiconductor substrate 150 due to the swinging, the film thickness and pattern dimensions of the PBO after the development are easily constant. The PBO development is preferably paddle development.

  Next, as in step S06 of the flowchart, the positive photosensitive polyimide is cured on the third insulating film 154b. Cure is the same as the method described in the first embodiment. Thus, by forming the third insulating film 154b in the opening of the second insulating film 153 and on the electrode pad 151b, the pad covering protective film which is a feature of the present application can be formed.

Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to the cross-sectional views of FIGS. 10A to 12F and the flowchart of FIG.
The manufacturing method described with reference to FIGS. 10A to 12F and FIG. 13 is a method for forming a magnetic sensor, for example, an element described in Patent Document 3, and a wire is used with a pad for which a wire bond is desired. This embodiment is an embodiment to which the method for manufacturing a semiconductor device of the present invention without a decrease in bond strength is applied.
Reference numeral 211 on the semiconductor substrate 210 is a semiconductor thin film, and a passivation film omitted in the drawing described in Patent Document 3 is denoted by reference numeral 212.

  As shown in FIG. 10A and step U01 of the flowchart, a second insulating film (first photosensitive polyimide) 213a as a protective film is patterned on the entire surface of the semiconductor substrate 210 including the passivation film 212 on the semiconductor substrate 210. The polyimide film is formed on the passivation film 212, which is the first insulating film having the magnetosensitive portion 211a, except for the metal electrode (Al pad) 202 portion formed on the wire bond connection electrode portion 222b. A second insulating film 213a is formed.

  Next, as shown in FIG. 10B and step U02 of the flowchart, the third insulating film (second polyimide) 213b is spun on the second insulating film (polyimide) 213a and the metal electrode (Al pad) 202. A third insulating film 213b made of polyimide is formed on the second insulating film 213a and the metal electrode 202 by coating and curing. The third insulating film 213b is a pad-covered insulating film that is a feature of the present application.

  The third insulating film (polyimide) 213b exists between the metal electrode (Al pad) 202 and a barrier layer 214a, which will be described later, and the third insulating film (polyimide) 213b has no pinhole and can be easily ashed. The film thickness is removable. Note that the ashing causes a film loss of the second insulating film (polyimide) 213a. For this reason, the film thickness of polyimide needs to be the relationship of 2nd insulating film 213a> 3rd insulating film 213b. Specifically, the film thickness of the second insulating film 213a is desirably 3 μm to 7 μm, and the film thickness of the third insulating film 213b is desirably 0.2 μm to 0.5 μm.

  Next, as shown in FIG. 11C and step U03 in the flowchart, the entire surface of the active surface of the semiconductor substrate 210 including the metal electrode (Al pad) 202 and the magnetic sensing portion 211a is used as a base layer for plating. The barrier layer 214 a and the common electrode layer 214 b are formed, and the base layer 215 is formed on the entire back surface, which is the inactive surface side of the semiconductor substrate 210. The barrier layer 214a and the common electrode layer 214b are laminated films made of Ti—W / Cu and can be formed by a sputtering method or the like. The underlayer 215 is formed so that a second magnetic body, which will be described later, adheres to the semiconductor substrate with good adhesion. Although not shown, the underlayer 215 is a laminated film of a barrier layer 214a and a common electrode layer 214b. This is because a later-described first magnetic body 217 and second magnetic body 218 are formed by electrolytic plating, and the common electrode layer 214b is Cu. Therefore, if there is no barrier layer 214a, the underlying Si and Cu are formed. Since a copper silicide is formed by alloying at a high temperature during sputtering, it is preferable to have a barrier layer.

  Next, as shown in FIG. 11D and step U04 of the flowchart, a photoresist 216 is spin-coated on the common electrode layer 214b, and a predetermined portion on the magnetic sensitive portion 211a is exposed by a photolithography technique. The resist is patterned to form the opening 216a. Then, a first magnetic body 217 having a magnetic amplification function as a protrusion formed by plating of the present application is formed on the exposed portion by plating using the common electrode layer 214b as an electrode, and an underlying layer on the back surface of the semiconductor substrate 210 A second magnetic body 218 having a magnetic amplification function simultaneously with the first magnetic body 217 is formed on the plate 215 by plating. The material of the first magnetic body 217 and the second magnetic body 218 is preferably permalloy or super permalloy (Fe—Ni alloy material).

Next, as shown in FIG. 12E and step U05 of the flowchart, the photoresist 2
16 is immersed and dissolved in a resist stripping solution, and then the common electrode layer 214b and the barrier layer 214a except for the lower layer of the first magnetic body 217 are removed by wet etching using the first magnetic body 217 as a mask. At this time, the back surface of the semiconductor substrate 210 is not etched using the second magnetic body 218 as a mask.

  Next, in FIG. 12F and step U06 in the flowchart, first, the third insulating film 213b is removed. The removal of the third insulating film 213b is performed in an oxygen plasma atmosphere. About the removal film thickness at the time of removing the 3rd insulating film 213b, it is good to set it as about 1.25 times the film thickness of the insulating film 213b. That is, it is preferable to remove the polyimide film so that it slightly bites into the second insulating film 213a.

  This is due to the following reason. The variation of the removal film thickness in a general ashing apparatus is about ± 5%, and the removal film thickness is set with a margin more than that. When the removal film thickness is increased, there is a disadvantage that the film thickness of the second insulating film 213a increases. On the other hand, if the removal film thickness is equal to or less than the film thickness of the third insulating film 213b, the third insulating film 213b remains on the metal electrode (Al pad) 202, and thus the problem of lowering the strength of the wire bond occurs.

  Thereafter, the semiconductor substrate is diced into chips for individual magnetic sensors, wire-bonded to the electrode pads of the wire bond connection electrode portion 222b with gold wires 219, and the electrode pads and the wires 219 are electrically coupled.

  As described above, in the present invention, the polyimide layer which is the third insulating film 213b is interposed between the aluminum of the electrode pad of the wire bond connection electrode portion 222b where the wire bond is desired and the titanium of the barrier layer 214a. Since the polyimide layer as the third insulating film 213b can withstand high temperatures when the barrier layer 214a is sputtered by a sputtering apparatus, it functions as a protective layer that prevents titanium and aluminum from contacting and thermally diffusing. .

  Further, since the polyimide layer of the third insulating film 213b can be easily removed in an oxygen plasma atmosphere by an ashing apparatus, no polyimide material remains on the surface of the electrode pad. That is, there are no titanium atoms on the aluminum surface of the metal electrode (Al pad) 202 of the wire bond connecting electrode portion 222b where wire bonding is desired. Therefore, since a titanium-aluminum alloy is not generated, even if the metal electrode (Al pad) 202 is wire-bonded with a gold wire 219, the total area of the bonding surface of the wire-bonded metal electrode (Al pad) 202 is gold- Since it becomes an aluminum alloy, the problem that wire bond intensity | strength falls does not generate | occur | produce.

150, 210, 550, 610 Semiconductor substrate 420 Substrate 505 Circuit board 506 Die bond pattern 550 First semiconductor chip 122a, 422a, 522a Solder connection electrode portion 122b, 222b, 422b, 522b Wire bond connection electrode portion 151a, 424a, 551a Electrode Pad (solder connection)
151b, 424b, 551b Electrode pads (wire bonds)
152, 212, 552 First insulating film 153, 213a, 430 Second insulating film (polyimide)
613a Protective films 154, 154b, 213b Third insulating film (polyimide)
154b Pad coating insulation film (polyimide)
155, 214a, 426a, 426b, 553, 614a Barrier layer 426a, 426b Ti-W layer 156, 214b, 554, 614b Common electrode layer 157, 216, 434, 555, 616 Photosensitive resist (photoresist)
157a, 216a, 616a Opening 131b Photomask 130a Incident ultraviolet ray 130b Emission ultraviolet ray 158, 556 Post 159, 438, 452, 557 Solder layer 503, 504 Solder 161, 219, 559, 619 Wire 211, 611 Semiconductor thin film 211a, 611a Magnetic part 202, 612 Metal electrode (Al pad)
215, 615 Underlayer 217, 617 First magnetic body 218, 618 Second magnetic body

Claims (9)

In a manufacturing method of a semiconductor device having a bonding pad portion and a protrusion formed by plating on an active surface side of a semiconductor substrate,
Forming a pad covering protective film covering the entire surface of the electrode pad of the bonding pad portion;
Forming a barrier layer and a common electrode layer on the active surface side of the semiconductor substrate including the protective film;
Forming the protrusions by plating in the protrusion formation region using the common electrode layer;
Removing the barrier layer and the common electrode layer other than the protrusion forming region;
Removing the pad covering protective film on the electrode pad of the bonding pad portion;
Bonding with an electrode pad of the bonding pad portion with a wire;
A method for manufacturing a semiconductor device, comprising: A passivation film having an opening in the electrode pad of the bonding pad portion, and a first protective film formed on the passivation film and having an opening in the electrode pad of the bonding pad portion. 2. A method for manufacturing a semiconductor device according to 1. 3. The method of manufacturing a semiconductor device according to claim 1, wherein each of the first protective film and the pad covering protective film is formed of polyimide or PBO (polybenzoxazole). 4. The method of manufacturing a semiconductor device according to claim 2, wherein the pad covering protective film is formed of a film thinner than the first protective film. The method for manufacturing a semiconductor device according to claim 1, wherein the barrier layer contains titanium or a titanium alloy. The method for manufacturing a semiconductor device according to claim 1, wherein the barrier layer contains chromium. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the wire is a gold wire or a gold alloy wire. The method of manufacturing a semiconductor device according to claim 1, wherein wire bonding or stud bump bonding is formed on the bonding pad portion. The method for manufacturing a semiconductor device according to claim 1, wherein the protrusion formed by plating is a solder bump electrode portion.

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