CN102496603A - Chip level packaging structure - Google Patents

Abstract

The invention discloses a chip level packaging structure which comprises a chip, a bump lower metal layer and a solder bump, wherein a bonding pad and a passivation layer are arranged on the chip; the passivation layer surrounds the periphery of the bonding pad; the bump lower metal layer is positioned on the bonding pad; the solder bump is positioned on the bump lower metal layer; and the bump lower metal layer comprises a heat-resistant metal layer, a metal infiltration layer, a blocking layer and a solder protection layer which are positioned on the chip bonding pad in turn from bottom to top. According to the invention, the electrical performance and reliability of a product are improved.

Description

A Chip Scale Package Structure

technical field

The invention relates to the field of packaging of semiconductor devices, in particular to an under-bump metal layer and a packaging structure of a Wafer Level chip Scale Package (WLCSP).

Background technique

In recent years, since the microcircuit manufacturing of chips is developing toward high integration, the chip packaging also needs to develop in the direction of high power, high density, thinness and miniaturization. Chip packaging means that after the chip is manufactured, the chip is wrapped in plastic or ceramic materials to protect the chip from external moisture and mechanical damage. The main functions of chip packaging are power distribution, signal distribution, heat dissipation and protection support.

Since today's electronic products are required to be light, thin, small and highly integrated, the fabrication of integrated circuits will be miniaturized, resulting in an increase in the number of logic circuits contained in the chip, which will further increase the number of I/O (input/output) pins on the chip. To meet these requirements, many different packaging methods have been produced, such as Ball grid array (BGA), Chip Scale Package (CSP), Multi Chip Module package (MCM package) , Flip Chip Package, Tape Carrier Package (TCP) and Wafer Level Package (WLP), etc.

Regardless of the packaging method in any form, most of the packaging methods are a process of separating the wafer into independent chips and then completing the packaging process. Wafer-level packaging is a trend in semiconductor packaging methods. Wafer-level packaging takes the entire wafer as the packaging object, so packaging and testing must be completed before the wafer is cut. It is a highly integrated packaging technology. , so that the glue filling, assembly, die bonding and wire bonding can be saved, so the labor cost can be greatly reduced and the manufacturing time can be shortened.

Chinese patent application number 200410049093.3 introduces a chip-level packaging structure. 1A to 1F are schematic diagrams of a conventional solder bump formation process. As shown in FIG. 1A , a passivation layer 106 is formed on the substrate 102 of the bonding pad 104 . Then, a heat-resistant metal layer 108 (usually chromium Cr or titanium Ti) and a metal wetting layer 110 (usually copper Cu) are successively deposited on the surface of the pad 104 and the passivation layer 106, as shown in FIG. 1B . Then apply a photoresist 112 and pattern the photoresist to form a groove 114 at a position corresponding to the pad, as shown in FIG. 1C . Next, as shown in FIG. 1D, the filling material in the trench 114 is tin (Sn) or tin-silver (SnAg) solder, and after removing the photoresist 112, a mushroom-shaped solder bump 120 as shown in FIG. 1E is formed. . Afterwards, the heat-resistant metal layer 108 and the metal wetting layer 110 are etched, and finally the solder bumps are melted into spherical solder bumps 120 as shown in FIG. 1F through a terminal electrode reflow process.

In the process of forming a chip-level package in the prior art, since the solder bump material is in direct contact with the metal wetting layer, the copper in the metal wetting layer easily diffuses into the tin of the solder bump to form a copper-tin alloy, which affects the soldering quality. In addition, before solder is formed on the metal wetting layer, the exposed wetting layer is easily oxidized, which reduces the performance and reliability of the subsequently formed solder bumps.

Contents of the invention

The problem to be solved by the present invention is to provide a chip-level packaging structure to prevent the electrical performance and reliability of the chip from being reduced.

In order to solve the above problems, the present invention provides a chip-level packaging structure, including: a chip, an UBM layer and a solder bump, the chip is provided with a pad and a passivation layer, and the passivation layer surrounds the around the pad, the UBM layer is located on the pad, the solder bump is located on the UBM layer; Heat-resistant metal layer, metal wetting layer, barrier layer and solder protection layer above the pad.

Optionally, the material of the heat-resistant metal layer is titanium.

Optionally, the material of the heat-resistant metal layer is titanium, chromium, tantalum or a combination thereof.

Optionally, the material of the metal wetting layer is copper.

Optionally, the material of the metal wetting layer is copper, aluminum, nickel or a combination thereof.

Optionally, the material of the barrier layer is nickel.

Optionally, the nickel barrier layer has a thickness of 1.5-3 μm.

Optionally, the solder protection layer is pure tin or tin alloy.

Optionally, the thickness of the solder protection layer is 1-2 μm.

Optionally, the material of the solder paste is consistent with that of the solder protection layer.

Compared with the prior art, in the UBM layer formed by the present invention, the barrier layer (Ni) with an appropriate thickness can avoid the disappearance of itself due to the diffusion effect on the one hand, and then effectively prevent the gap between the solder and the metal wetting layer due to the metal The pores generated by the formation of inter-compounds; at the same time, the resistivity will not increase due to the excessive thickness of the nickel barrier layer, which will affect the electrothermal performance of the product.

In addition, the solder protection layer in the UBM layer can not only protect the barrier layer from oxidation, but also improve the adhesion between the barrier layer and the solder bump, and the solder protection layer has a good wettability during the reflow process. The chemical effect improves the quality of solder bump formation.

Description of drawings

1A to 1F are schematic diagrams of the existing solder bump formation process;

Fig. 2 is a schematic diagram of the chip-scale packaging structure of the present invention;

Fig. 3 is a flow chart of a specific embodiment of the present invention forming a chip-scale packaging structure

4A to 4G are process schematic diagrams of an embodiment of forming a chip-scale package structure according to the present invention.

Detailed ways

The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

2 is a schematic diagram of a chip-level packaging structure of the present invention, said packaging structure comprising: a chip 300, an UBM layer and a solder bump 309, said chip 300 is provided with a pad 301 and a passivation layer 302, said The passivation layer 302 surrounds the pad 301, the UBM layer is located on the pad 301, and the solder bump 309 is located on the UBM layer, characterized in that: The UBM layer includes a heat-resistant metal layer 303, a metal wetting layer 304, a barrier layer 306 and a solder protection layer 307 located above the pad 301 of the chip 300 from bottom to top; the material of the heat-resistant metal layer 303 is Titanium, chromium, tantalum or their combination, the material of the metal wetting layer 304 is copper, aluminum, nickel or their combination, the material of the barrier layer 306 is nickel metal with a thickness of 1.5 μm to 3 μm, the solder protection The layer 307 is made of pure tin or tin alloy with a thickness of 1 μm˜2 μm, such as tin-silver alloy, tin-copper alloy or tin-silver-copper alloy.

In the above packaging structure, the barrier layer (Ni) with an appropriate thickness can prevent itself from disappearing due to the diffusion effect, thereby effectively preventing the pores between the solder and the metal wetting layer due to the formation of intermetallic compounds; If the nickel barrier layer is too thick, the resistivity will increase and the electrothermal performance of the product will be affected. The solder protection layer above the barrier layer can not only protect the barrier layer from oxidation, but also improve the adhesion between the barrier layer and solder bumps, and the solder protection layer has a good wetting effect during the reflow process. The formation quality of solder bumps is improved.

In order to further illustrate the advantages of the packaging structure of the present invention, the packaging structure of the present invention will be further introduced below in combination with a specific packaging method embodiment.

As shown in Figure 3, in one embodiment of the present invention, a chip-scale packaging method is provided, comprising steps:

S101, sequentially forming a heat-resistant metal layer and a metal wetting layer on the chip pad and the passivation layer;

S102, forming a photoresist on the metal wetting layer, the photoresist is provided with an opening to expose the metal wetting layer above the chip pad;

S103, sequentially forming a barrier layer and a solder protection layer on the metal wetting layer in the opening;

S104, forming a solder paste on the solder protection layer;

S105, removing the photoresist;

S106, etching the heat-resistant metal layer and the metal wetting layer on the passivation layer until the passivation layer is exposed;

S107 , reflowing the solder paste to form solder bumps.

In this embodiment, step S101 is first performed, and a heat-resistant metal layer and a metal wetting layer are sequentially formed on the pad of the chip and the passivation layer to form a structure as shown in FIG. 4A .

In this step, the chip 300 is provided with a pad 301 and a passivation layer 302, the pad 301 is the functional output terminal of the chip 300, and finally realizes the conductive transition of the electrical function through the subsequently formed solder bump 309; The material of the silicon oxide layer 302 includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, polyimide, butylene tributylene, or their mixtures, which are used to protect the circuits in the chip 300 .

In this embodiment, the material of the heat-resistant metal layer 303 may be titanium Ti, chromium Cr, tantalum Ta or a combination thereof, and Ti is preferred in the present invention. The material of the metal wetting layer 304 may be one of copper Cu, aluminum Al, nickel Ni or a combination thereof, wherein the preferred metal wetting layer 304 is Cu. The method of forming the heat-resistant metal layer 303 and the metal wetting layer 304 can also use the existing methods of evaporation or sputtering or physical vapor deposition, and the preferred method is sputtering. Of course, according to the common knowledge of those skilled in the art, the forming method is not limited to the sputtering method, other applicable methods can be applied to the present invention, and the thickness of the formed heat-resistant metal layer 303 and metal wetting layer 304 is also based on the actual Depends on process requirements.

Then step S102 is implemented to form a photoresist on the metal wetting layer, and the photoresist is provided with an opening to expose the metal wetting layer above the chip pad, forming a structure as shown in FIG. 4B .

In this embodiment, the method for forming the photoresist 305 may be spin coating, and the specific steps of these methods are well known to those skilled in the art, and will not be repeated here. After the photoresist 305 is formed, the shape of the pad 301 can be defined specifically by the existing photolithography and developing technology, so that an opening is formed in the photoresist 305 to expose the metal wetting layer 304 on the pad 301 .

Step S103 is then implemented to sequentially form a barrier layer and a solder protection layer on the metal wetting layer in the opening to form a structure as shown in FIG. 4C .

In this step, using the remaining photoresist 305 on the chip 300 as a mask, a barrier layer 306 and a solder protection layer are sequentially formed in the opening of the photoresist 305 formed in the previous step and above the metal wetting layer 304. 307. The specific process can be through electroplating. Of course, according to the common knowledge of those skilled in the art, the forming method is not limited to electroplating, and other suitable methods can be applied to the present invention. The material of the barrier layer 306 is nickel Ni, and the material of the solder protection layer 307 is consistent with the subsequent formation of the solder bump 309, which is pure tin or tin alloy, such as tin-silver alloy, tin-copper alloy, tin-silver-copper alloy, etc. .

In this embodiment, the nickel barrier layer 306 has a thickness of 1.5 μm˜3 μm, specifically 1.5 μm, 2 μm, 2.5 μm or 3 μm. The function of the barrier layer 306 is to prevent the material that subsequently forms the bump from diffusing into the metal wetting layer 304. When the thickness of the Ni layer is less than 1.5 μm, the Ni will eventually disappear due to the diffusion effect between adjacent metals, and thus cannot effectively block the subsequent bumps. The bumps diffuse into the metal wetting layer 304; when the thickness of the Ni layer is greater than 3 μm, the electrical resistivity of the Ni metal itself is poor, resulting in an increase in resistivity, thereby affecting the electrical and thermal properties of the final product.

In this embodiment, the thickness of the solder protection layer 307 is 1 μm˜2 μm, and the specific thickness is, for example, 1 μm, 1.5 μm or 2 μm. The function of the solder protection layer 307 is to prevent the barrier layer 306 below from being oxidized, which improves the electrical performance and reliability of the barrier layer 306. At the same time, the solder protection layer 307 also has a good wetting effect, which can effectively improve the solder bump. Point 309 for the quality of the formation.

So far, that is to say, a multi-layer metal layer is formed on the pad 301, including a heat-resistant metal layer 303, a metal wetting layer 304, a barrier layer 306, and a solder protection layer 307 from the bottom up. These multi-layer metal layers constitute The UBM (Under Bump Metallurgy) layer commonly known in this technical field is formed.

Then step S104 is implemented to form solder paste on the solder protection layer to form a structure as shown in FIG. 4D .

In this step, the photoresist 305 is still used as a mask to form a solder paste 308 on the solder protection layer 307, and the solder paste 308 is consistent with the material for forming the solder protection layer 307, which is pure tin or a tin alloy. Such as tin-silver alloy, tin-copper alloy, tin-silver-copper alloy, etc. The method for forming the solder paste 308 may be electrolytic plating, screen printing, or direct implantation of prefabricated solder balls. The specific steps of these methods are well known to those skilled in the art and will not be repeated here.

Step S105 is then implemented to remove the photoresist to form the structure shown in FIG. 4E .

After the above process is completed, the photoresist 305 can be removed by wet method or stripping. The specific steps of these methods are well known to those skilled in the art and will not be repeated here.

Then step S106 is implemented, etching the heat-resistant metal layer and the metal wetting layer on the passivation layer until the passivation layer is exposed, forming a structure as shown in FIG. 4F .

In this embodiment, the metal wetting layer 304 and the heat-resistant metal layer 303 on the surface of the chip 300 other than the solder paste 308 can be removed by spraying acid or immersing the wafer in acid, thereby exposing the passivation layer. 302.

Finally, step S107 is implemented to reflow the solder paste to form bumps, that is, to form a chip-scale package structure as shown in FIG. 4G .

In this embodiment, the solder paste 308 is melted by reflow heating to form the solder bump 309, and the solder paste 308 and the solder bump 309 are of the same material in different forms, and finally the function pad 301 of the chip 300 is drawn out to the Package transition on solder bump 309 .

Although the present invention is disclosed above with preferred embodiments, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (10)

1. A chip-level packaging structure, comprising a chip, an UBM layer and a solder bump, the chip is provided with a pad and a passivation layer, and the passivation layer surrounds the pad, so The UBM layer is located on the pad, and the solder bump is located on the UBM layer, and it is characterized in that: the UBM layer includes: heat-resistant metal layer, metal wetting layer, barrier layer and solder protection layer. 2. A chip-scale package structure according to claim 1, characterized in that the material of the heat-resistant metal layer is titanium. 3. The chip-scale package structure according to claim 1, wherein the material of the heat-resistant metal layer is titanium, chromium, tantalum or a combination thereof. 4. The chip scale package structure according to claim 1, wherein the material of the metal wetting layer is copper. 5. The chip scale package structure according to claim 1, wherein the material of the metal wetting layer is copper, aluminum, nickel or a combination thereof. 6 . The chip scale package structure according to claim 1 , wherein the material of the barrier layer is nickel. 7 . The chip scale package structure according to claim 6 , wherein the nickel barrier layer has a thickness of 1.5-3 μm. 8. The chip scale package structure according to claim 1, wherein the solder protection layer is pure tin or tin alloy. 9 . The chip scale package structure according to claim 8 , wherein the thickness of the solder protection layer is 1-2 μm. 10. The chip scale package structure according to claim 1 or 8, wherein the material of the solder paste is consistent with that of the solder protection layer.

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