JP2011086883A - Insulated gate bipolar transistor, and method for designing the same - Google Patents

Abstract

An insulated gate bipolar transistor having a simple lifetime control structure, small tail loss and capable of high-speed switching, and a design method thereof are provided.
A first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer formed on a main surface side surface layer portion, and a surface layer portion of the second semiconductor layer are selectively used. Between the formed first semiconductor layer 3 of the first conductivity type, the fourth semiconductor layer 4 of the second conductivity type formed in the surface layer portion on the back surface side, and between the first semiconductor layer 1 and the fourth semiconductor layer 4. An insulated gate bipolar transistor 100 having a fifth semiconductor layer 5 of the first conductivity type formed and having an impurity concentration higher than that of the first semiconductor layer 1, wherein the recombination center lattice defect has one density distribution peak. The insulated gate bipolar transistor 100 is arranged in the first semiconductor layer 1 so that the peak position Dc is located inside the width W of the non-depleted region at the end of turn-off.
[Selection] Figure 2

Description

  The present invention relates to an insulated gate bipolar transistor and a design method thereof.

  Insulated gate bipolar transistors (IGBTs), which are vertical power devices, are disclosed in, for example, Japanese Patent Laid-Open Nos. 10-50724 (Patent Document 1) and 2004-103982 (Patent Document 2). ing. IGBT can be grasped as a composite structure of MOS field effect transistor (MOS-FET) and bipolar transistor (BJT), and is one of high-current / high-voltage power devices, from industrial to household appliances. It has been widely applied.

  IGBTs can be broadly classified into so-called punch-through (PT) type IGBTs, non-punch-through (NPT) type IGBTs, and field stop (FS) type IGBTs that are intermediate between the two. A PT-type IGBT (for example, Patent Document 1) uses a thick substrate of P conductivity type (P +) as a collector layer, and inserts an N conductivity type (N +) buffer layer between the drift layer of N conductivity type (N−) It has a structure. An NPT type IGBT (for example, Patent Document 1) has a structure in which a collector layer of P conductivity type (P +) is formed on the back surface of a thin N conductivity type (N−) substrate (body layer) functioning as a drift layer. Yes. In addition, an FS type IGBT (for example, Patent Document 2) inserts a buffer layer designed to have a low N conductivity type carrier concentration called a field stop (FS) layer between a drift layer and a collector layer of an NPT type IGBT, The N-conductivity type (N−) substrate (body layer) which is a drift layer is further thinned. The IGBT, which is a vertical power device, has been reduced in thickness for the purpose of reducing loss. In recent years, the FS type IGBT that can be thinned most is becoming the mainstream structure.

  FIG. 13 is a typical example of the FS type IGBT and is a schematic cross-sectional view of the IGBT 90.

  The IGBT 90 shown in FIG. 13 is formed on an N conductivity type (N−) semiconductor substrate 10. The IGBT 90 includes a first semiconductor layer 1 made of an N-conductivity type (N−) semiconductor substrate 10, and a P-conductivity type (P) second semiconductor layer 2 formed in a surface layer portion on the main surface side of the semiconductor substrate 10. And an N conductivity type (N +) third semiconductor layer 3 selectively formed in the surface layer portion of the second semiconductor layer 2. Note that a portion indicated by reference numeral G formed so as to penetrate the second semiconductor layer 2 is a gate electrode (insulating trench gate) having a trench structure, and the second semiconductor layer 2 is a channel formation region called a base layer. The third semiconductor layer 3 is an emitter region. The emitter electrode E is formed on the semiconductor substrate 10 on the main surface side so as to be commonly connected to the second semiconductor layer 2 and the third semiconductor layer 3 via the interlayer insulating film 6.

  The IGBT 90 includes a P-conductivity type (P +) fourth semiconductor layer 4 formed in the surface layer portion on the back surface side of the semiconductor substrate 10, and an N formed between the first semiconductor layer 1 and the fourth semiconductor layer 4. The fifth semiconductor layer 5 has a conductivity type (N) and an impurity concentration higher than that of the first semiconductor layer 1. The fourth semiconductor layer 4 is a collector region, and a collector electrode C is formed on the semiconductor substrate 10 on the back surface side so as to be connected to the fourth semiconductor layer 4. The fifth semiconductor layer 5 is a so-called FS layer, and the first semiconductor layer 1 is a carrier drift region in the IGBT 90.

Japanese Patent Laid-Open No. 10-50724 JP 2004-103982 A

  FIG. 14 is a diagram schematically showing characteristics at turn-off of a general IGBT. FIG. 14A is a diagram illustrating waveforms of the gate voltage Vg, the collector voltage Vc, and the collector current Ic at the time of turn-off, and FIG. 14B is a waveform of the power Vc × Ic related to the loss at the time of turn-off. FIG.

  As shown in FIG. 14A, in the IGBT, after the gate is turned off, the collector current Ic decreases with a delay after the discharge of the gate capacitance is completed, and the collector voltage Vc increases accordingly. The collector current Ic suddenly drops to about 20% of the on state, and then begins to tail (start tail). This phenomenon in which the collector current Ic has a tail (tail current) is peculiar to the IGBT and is affected by residual holes in the drift layer. In FIG. 14 (b), the IGBT turn-off loss (total loss at turn-off) corresponds to the integrated area of the waveform of the work factor Vc × Ic, but the tail loss (of the turn-off loss) indicated by hatching in FIG. The loss after the start of the tail) accounts for about 40% of the turn-off loss.

  In order to reduce the tail current peculiar to the IGBT shown in FIG. 14, to reduce the loss accompanying the tail current, and to increase the switching speed, various methods have been studied.

For example, Patent Document 1 discusses a method of quickly eliminating residual holes by controlling the lifetime of residual holes in a drift layer that causes a tail current in PT-type IGBTs and NPT-type IGBTs. According to Patent Document 1, an N− type base layer that is a drift layer is formed so that the width of the non-depleted region is 40 μm or more, and then H ²⁺ is irradiated in two portions. As a result, the first low lifetime layer having a relatively deep recombination order at about 20 μm from the P-type collector layer in the N− type base layer is relatively formed at about 60 μm from the P-type collector layer. A second low lifetime layer having a shallow recombination order is formed respectively. In this way, almost the entire remaining non-depleted region can be reduced in lifetime, and the tail current at the time of a low power supply voltage can be suppressed without causing deterioration of breakdown voltage or increase in leakage current and on-voltage.

  On the other hand, in place of the PT-type IGBT and NPT-type IGBT disclosed in Patent Document 1, the FS-type IGBT, which is becoming a mainstream structure in recent years, has been developed on the assumption that lifetime control of residual holes is not performed. This is because it is difficult to realize a complicated lifetime control structure as disclosed in Patent Document 1 in the FS-type IGBT in which thinning is the greatest merit.

  As a technique for reducing the tail loss and increasing the device speed in addition to the lifetime control of the residual holes, for example, the P + type collector layer (fourth semiconductor layer 4) and the N type FS layer (fifth semiconductor layer) of the IGBT 90 in FIG. A method of suppressing the hole injection efficiency by appropriately controlling the impurity concentration of the semiconductor layer 5) can be used. However, although the method of suppressing the hole injection efficiency can reduce the tail current, for example, the contact resistance with the collector electrode C is increased by reducing the concentration of the P + type collector layer, or the current driving capability of the IGBT is decreased. Problems occur.

  Therefore, the present invention is an FS-type insulated gate bipolar transistor that can be thinned and a design method thereof, and has a simple lifetime control structure capable of precisely controlling the lifetime of residual holes. An object of the present invention is to provide an insulated gate bipolar transistor with low tail loss and capable of high-speed switching, and a design method thereof.

  The invention according to claim 1 is a first semiconductor layer formed of a first conductivity type semiconductor substrate, a second conductivity type second semiconductor layer formed in a surface layer portion on a main surface side of the semiconductor substrate, A third semiconductor layer of a first conductivity type selectively formed on a surface layer portion of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type formed on a surface layer portion on the back side of the semiconductor substrate; An insulated gate bipolar transistor comprising a fifth semiconductor layer having a first conductivity type and an impurity concentration higher than that of the first semiconductor layer formed between the first semiconductor layer and the fourth semiconductor layer, In the cross-sectional direction of the semiconductor substrate, the recombination center lattice defect having one density distribution peak is located on the inner side of the width of the non-depleted region at the end of turn-off determined by simulation from the back surface of the semiconductor substrate. In the first half It is characterized in that are arranged in a body layer.

  The insulated gate bipolar transistor (IGBT) has a first semiconductor layer as a drift layer (body layer), a second semiconductor layer as a channel formation layer, a third semiconductor layer as an emitter layer, and a fourth semiconductor layer as a collector layer. In the FS type IGBT in which the fifth semiconductor layer is a field stop (FS) layer, the fourth semiconductor layer and the fifth semiconductor layer are thin layers of about 1 μm. Also, the first semiconductor layer that is the drift layer (body layer) may be, for example, 200 μm or less.

  In the IGBT, generally, after the gate is turned off and the collector current Ic is rapidly reduced to about 20% of that at the time of on, a phenomenon (tail current) is generated due to the influence of residual holes in the drift layer. . In order to reduce the tail current, reduce tail loss associated with the tail current, and increase the switching speed, the FS-type IGBT has a recombination center lattice having one density distribution peak in the cross-sectional direction of the semiconductor substrate. Defects (so-called lifetime killer of residual holes) are arranged in the first semiconductor layer so that the peak position comes inside the width of the non-depleted region at the end of turn-off determined from the back surface of the semiconductor substrate by simulation. ing. Specifically, the recombination center lattice defect is locally formed by irradiating ions such as proton, deuterium (dutron), and helium from the back side of the semiconductor substrate.

  The recombination center lattice defect in the FS-type IGBT has a simple structure having one density distribution peak in the cross-sectional direction of the semiconductor substrate, and can be easily realized even in a thin FS-type IGBT. it can. The distribution of the recombination center lattice defects can be accurately determined by simulation, and the peak position of the recombination center lattice defects is determined in the non-depleted region where the electric field strength at the end of turn-off determined by the simulation is zero. By disposing the first semiconductor layer so as to be inward of the width, tail loss can be reduced and switching speeded up without causing an increase in on-voltage compared to the case where the recombination center lattice defect is not introduced. Can do.

  The lifetime control of residual holes due to the recombination center lattice defect of the FS-type IGBT is different from, for example, a method of suppressing the hole injection efficiency by appropriately controlling the impurity concentration of the fourth semiconductor layer and the fifth semiconductor layer. The contact resistance with the collector electrode connected to the layer does not increase, and the current driving capability of the FS type IGBT does not decrease.

  As described above, the insulated gate bipolar transistor is an FS-type insulated gate bipolar transistor that can be thinned, and has a simple lifetime control structure that can precisely control the lifetime of residual holes. Thus, an insulated gate bipolar transistor with small tail loss and capable of high-speed switching can be obtained.

  In the insulated gate bipolar transistor, as described in claim 2, the recombination center lattice defect has a main surface side half-width position located on the inner side of the width of the non-depleted region from the back surface of the semiconductor substrate. Further, it is preferable that the first semiconductor layer is disposed. Furthermore, as described in claim 3, the first recombination center lattice defect is arranged such that the main surface side skirt tip position is located inside the width of the non-depleted region from the back surface of the semiconductor substrate. More preferably, it is arranged in the semiconductor layer.

  According to this, the distribution of recombination center lattice defects is more surely contained in the non-depleted region, and the tail loss can be reduced and the switching speed can be increased more stably.

  As described above, the insulated gate bipolar transistor is intended for a FS-type IGBT that can be reduced in thickness, and as described in claim 4, the semiconductor substrate has a thickness of 120 μm or more and 200 μm or less. It is suitable in some cases.

  The insulated gate bipolar transistor may be a trench gate type IGBT having an insulated trench gate formed so as to penetrate the second semiconductor layer, for example, as recited in claim 5. .

  The invention described in claims 6 to 10 is an invention concerning a design method of the insulated gate bipolar transistor according to a design procedure of the insulated gate bipolar transistor.

  The design method according to claim 6, wherein a first semiconductor layer made of a first conductivity type semiconductor substrate, a second conductivity type second semiconductor layer formed in a surface layer portion on a main surface side of the semiconductor substrate, A third semiconductor layer of a first conductivity type selectively formed in a surface layer portion of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type formed in a surface layer portion on the back surface side of the semiconductor substrate; A fifth semiconductor layer having a first conductivity type formed between the first semiconductor layer and the fourth semiconductor layer and having an impurity concentration higher than that of the first semiconductor layer; A method of designing an insulated gate bipolar transistor in which a recombination center lattice defect having one density distribution peak is disposed in the first semiconductor layer, and first, in a cross-sectional direction of the semiconductor substrate by simulation, Power at the end of turn-off Determining the width of the non-depleted region where the intensity becomes zero, and then, the recombination center lattice defect, the peak position is located on the inner side from the back surface of the semiconductor substrate than the width of the non-depleted region It is characterized by being arranged in the first semiconductor layer. Thereby, the insulated gate bipolar transistor according to claim 1 can be designed easily.

  Similarly, the insulated gate bipolar transistor according to claims 2 to 5 can be easily designed by the design method according to claims 7 to 10.

  The effect of the insulated gate bipolar transistor designed by the above design method is as described above, and the description thereof is omitted.

  As described above, the above-described insulated gate bipolar transistor and its design method are an FS type insulated gate bipolar transistor that can be thinned and its design method, and it is possible to precisely control the lifetime of residual holes. An insulated gate bipolar transistor that has a simple lifetime control structure that can be performed, has low tail loss, and can perform high-speed switching, and a design method thereof.

FIG. 13A is an example of a simulation result of the IGBT 90 shown in FIG. 13, and FIG. 13A is a diagram showing a distribution of electric field strength in the cross-sectional direction of the semiconductor substrate 10, and FIG. It is a figure which shows distribution. It is the figure which showed the basic structure of the insulated gate bipolar transistor (IGBT) which concerns on this invention, and is typical sectional drawing of IGBT100. FIG. 3 is a diagram showing an example of the simulation of the IGBT 100 shown in FIG. 2, wherein the peak position Dc of the recombination center lattice defect D and the hole lifetime value at the peak position Dc are constant, and the Gaussian distribution of the recombination center lattice defect D It is a figure which shows each simulation model at the time of changing the half width on one side. FIG. 3 shows an example of the result of verifying the coincidence of each simulation model shown in FIG. 3 when the recombination center lattice defect D is formed in the actual IGBT 100. When the recombination center lattice defect D is irradiated with helium (He) ions. It is the figure which showed the spreading | diffusion resistance value in a silicon (Si) board | substrate. FIG. 4 is a diagram obtained by plotting the relationship between the on-voltage and the turn-off loss by changing the impurity concentration of the fourth semiconductor layer 4 as the collector layer for each model in the simulation result for each model shown in FIG. 3. It is the figure which extracted and showed a part of data shown in FIG. 5, and is the figure which showed the relationship between the half value width of one side and the turn-off loss in the ON voltage 2.3V. The figure showing the relationship between the peak position Dc of the recombination center lattice defect D and the turn-off loss. The half-value width on one side is 5 μm, and the hole lifetime values at the peak position Dc are 3.0e ⁻⁸ sec and 6.0e ⁻ , respectively. ^In the case of ⁸ sec, the relationship between the peak position Dc and the turn-off loss when the on-voltage is 2.3V is shown. Each simulation model when the half-value width (and its peak position Dc) is changed by making the main surface side skirt tip position Des of the recombination center lattice defect D coincide with 108 μm which is the end of the non-depleted region. FIG. FIG. 9 is a diagram showing a relationship between a half-value width at one side and a turn-off loss at an ON voltage of 2.3 V as a result of simulation for each model shown in FIG. 8. The figure shows the relationship between the hole lifetime value at the peak position Dc and the turn-off loss. The hole position when the peak position Dc of the recombination center lattice defect D is 125 μm, the half width at one side is 5 μm, and the ON voltage is 2.3V. The relationship between lifetime value and turn-off loss is shown. FIG. 14 is a diagram plotting the on-voltage and the turn-off loss obtained by simulation for the case where the design target value of the turn-off loss is 9.5 mJ and the structural parameters of the IGBT 100 of FIG. 2 and the IGBT 90 of FIG. 13 are changed. . FIG. 14 is a diagram in which a simulation similar to that of FIG. 11 is performed by setting turn-off loss design target values to 8.5 mJ and 9.5 mJ, respectively, and ON-voltage characteristic variations are compared for the IGBT 100 of FIG. 2 and the IGBT 90 of FIG. . It is a typical example of FS type IGBT, and is a schematic cross-sectional view of IGBT90. It is the figure which showed typically the characteristic at the time of turn-off about general IGBT. (A) is the figure which showed the waveform of the gate voltage Vg at the time of turn-off, the collector voltage Vc, and the collector current Ic, (b) is the figure which showed the waveform of the work rate VcxIc concerning the loss at the time of turn-off It is.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  First, in order to analyze the phenomenon (tail current) in which the collector current Ic peculiar to the IGBT described in FIG. 14 has a tail, a simulation of the IGBT 90 shown in FIG. 13 was performed.

  FIG. 1 is an example of a simulation result of the IGBT 90. FIG. 1A is a diagram showing a distribution of electric field strength in the cross-sectional direction of the semiconductor substrate 10, and FIG. 1B is a cross-sectional direction of the semiconductor substrate 10. It is a figure which shows distribution of the hole density in. FIGS. 1A and 1B show the electric field strength distribution and the hole density distribution at each stage of collector current Ic = 180, 100, 50, 30, 15, 5, 0 [A] during turn-off, respectively. ing. The collector current Ic when the IGBT 90 is in a conductive state is set to 200 [A]. In the simulation of FIG. 1, the thickness of the semiconductor substrate 10 is 165 μm, and the specific resistance of the N conductivity type (N−) first semiconductor layer 1 which is a carrier drift region is 60 Ωcm. The thicknesses of the fourth semiconductor layer 4 and the fifth semiconductor layer 5 are both 1 μm.

  When the IGBT 90 turns off and Ic decreases, the electric field strength increases from the main surface side to the back surface side of the semiconductor substrate 10 as shown in FIG. As shown in b), the depletion region (region where the hole density on the main surface side in each stage of Ic is low) also extends toward the back surface side. That is, when the IGBT 90 is turned off, the gate applied voltage is zero-biased, the injection of electrons from the MOS transistor on the main surface side is stopped, Ic decreases, and the system voltage applied between the collector and emitter of the IGBT 90 As a result, the depletion region expands from the junction surface of the P-conductivity type (P) second semiconductor layer 2 and the N-conductivity type (N-) first semiconductor layer 1 toward the back surface side. In each stage of Ic, in the depletion region, holes are immediately swept out to the emitter on the main surface side by the electric field strength shown in FIG. On the other hand, in the region where the electric field intensity in FIG. 1A on the back side of the semiconductor substrate 10 is zero, holes remain only during the lifetime in silicon (Si) (residual holes). The phenomenon (tail current) in which the collector current Ic has a tail as shown in FIG. 14A appears as a tail current until the hole disappears after the lifetime.

  As can be seen from FIG. 1A, in the IGBT 90, even if Ic = 0 [A], a region where the electric field strength indicated by the double-pointed arrow in the drawing is zero remains on the back side of the semiconductor substrate 10, The region can be defined strictly as a non-depleted region. In FIG. 1A, the depth of the front end of the electric field strength at Ic = 0 [A] is 108 μm, and the width of the non-depleted region is 55 μm.

  As described above, in the field stop (FS) type IGBT 90 shown in FIG. 13, tail current is generated due to residual holes as in the punch-through (PT) type and non-punch-through (NPT) type IGBTs. I was able to confirm. Therefore, the introduction of lifetime control of residual holes was examined based on the simulation results of FIG. 1 for the FS type IGBT, which is the greatest merit of thinning and it is difficult to realize a lifetime control structure.

  FIG. 2 is a diagram showing a basic structure of an insulated gate bipolar transistor (IGBT) according to the present invention, and is a schematic cross-sectional view of the IGBT 100. In the IGBT 100 shown in FIG. 2, the same parts as those of the IGBT 90 shown in FIG.

  The IGBT 100 shown in FIG. 2 is different from the IGBT 90 shown in FIG. 13 in that a recombination center lattice defect (so-called residual hole lifetime killer) D having one density distribution peak is arranged.

  That is, the IGBT 100 in FIG. 2 is formed in the first semiconductor layer 1 composed of the N-conductivity type (N−) semiconductor substrate 10 and the surface layer portion on the main surface side of the semiconductor substrate 10 in the same manner as the IGBT 90 in FIG. 13. It has a second semiconductor layer 2 of P conductivity type (P) and a third semiconductor layer 3 of N conductivity type (N +) selectively formed on the surface layer portion of the second semiconductor layer 2. Note that a portion indicated by reference numeral G formed so as to penetrate the second semiconductor layer 2 is a gate electrode (insulating trench gate) having a trench structure, and the second semiconductor layer 2 is a channel formation region called a base layer. The third semiconductor layer 3 is an emitter region. The emitter electrode E is formed on the semiconductor substrate 10 on the main surface side so as to be commonly connected to the second semiconductor layer 2 and the third semiconductor layer 3 via the interlayer insulating film 6.

  The IGBT 100 includes a fourth semiconductor layer 4 of P conductivity type (P +) formed in the surface layer portion on the back surface side of the semiconductor substrate 10, and N formed between the first semiconductor layer 1 and the fourth semiconductor layer 4. The fifth semiconductor layer 5 has a conductivity type (N) and an impurity concentration higher than that of the first semiconductor layer 1. The fourth semiconductor layer 4 is a collector region, and a collector electrode C is formed on the semiconductor substrate 10 on the back surface side so as to be connected to the fourth semiconductor layer 4. The fifth semiconductor layer 5 is a so-called FS layer, and the first semiconductor layer 1 is a carrier drift region in the IGBT 90.

  On the other hand, unlike the IGBT 90 in FIG. 13, the IGBT 100 in FIG. 2 is a turn-off in which a recombination center lattice defect D having one density distribution peak is determined by simulation from the back surface of the semiconductor substrate 10 in the cross-sectional direction of the semiconductor substrate 10. It is arranged in the first semiconductor layer 1 so that the peak position Dc indicated by the alternate long and short dash line in the drawing of the recombination center lattice defect D comes inside the width W of the non-depleted region at the end. In FIG. 2, the main surface side half-value width position Dhs and the back surface side half-value width position Dhb of the recombination center lattice defect D having a Gaussian distribution are indicated by broken lines in the figure, and the lifetime value of the hole at the peak position Dc. The main surface side skirt tip position Des and the back surface side skirt tip position Deb, which become 100 times the lifetime value and substantially fail to exhibit the lifetime killer function, are indicated by dotted lines in the figure.

  As described above, the IGBT 100 of FIG. 2 includes the first semiconductor layer 1 as a drift layer (body layer), the second semiconductor layer 2 as a channel formation layer, the third semiconductor layer 3 as an emitter layer, and the fourth semiconductor layer. 4 is a collector layer and the fifth semiconductor layer 5 is a field stop (FS) layer. The fourth semiconductor layer 4 and the fifth semiconductor layer 5 are thin layers of about 1 μm. Also, the first semiconductor layer 1 that is a drift layer (body layer) may be, for example, 200 μm or less.

  As described with reference to FIG. 14, in the IGBT, generally, after the gate is turned off and the collector current Ic is suddenly reduced to about 20% at the time of on, the tail is pulled by the influence of residual holes in the drift layer. A phenomenon (tail current) occurs. In order to reduce the tail current, reduce tail loss associated with the tail current, and increase the switching speed, the FS-type IGBT 100 of FIG. 2 has a single density distribution peak in the cross-sectional direction of the semiconductor substrate 10. The first semiconductor layer 1 is such that the bond center lattice defect D is located on the inner side of the width W of the non-depleted region at the end of turn-off determined from the back surface of the semiconductor substrate 10 by the simulation shown in FIG. Is placed inside. Specifically, the recombination center lattice defect D is locally formed by irradiating ions such as proton, deuterium (dutron), and helium from the back surface side of the semiconductor substrate 10.

  The recombination center lattice defect D in the FS type IGBT 100 of FIG. 2 has a simple structure having one density distribution peak in the cross-sectional direction of the semiconductor substrate 10, and even the thin FS type IGBT 100 can be easily formed. Can be realized. In addition, when the recombination center lattice defect D is formed by ion irradiation as described above, the recombination center lattice defect D having one density distribution peak can be formed by one ion irradiation, so that the cost is low. is there.

  The distribution of the recombination center lattice defect D can be accurately determined by simulation as described later, and the peak position Dc of the recombination center lattice defect D is determined at the end of turn-off determined by the simulation shown in FIG. By arranging the first semiconductor layer 1 in the first semiconductor layer 1 so as to be inside the width W of the non-depleted region where the electric field strength is zero, as will be described later, the recombination center lattice defect D is not introduced. Thus, tail loss can be reduced and switching can be speeded up without causing an increase in on-voltage.

  The lifetime control of residual holes due to the recombination center lattice defect D of the FS-type IGBT 100 is different from, for example, a method of appropriately controlling the impurity concentration of the fourth semiconductor layer 4 and the fifth semiconductor layer 5 to suppress the hole injection efficiency. The contact resistance with the collector electrode connected to the fourth semiconductor layer 4 does not increase, and the current driving capability of the FS IGBT does not decrease.

  3 to 5 are diagrams illustrating an example of the simulation of the IGBT 100 illustrated in FIG.

  FIG. 3 shows various simulations when the half-value width of the recombination center lattice defect D having a Gaussian distribution is changed while the hole lifetime values at the peak position Dc and the peak position Dc of the recombination center lattice defect D are constant. It is a figure which shows a model. In the simulation of FIG. 3 as well, as in the simulation of FIG. 1, the thickness of the semiconductor substrate 10 is 165 μm, and the specific resistance of the first semiconductor layer 1 of N conductivity type (N−), which is a carrier drift region. Is set to 60 Ωcm. The thicknesses of the fourth semiconductor layer 4 and the fifth semiconductor layer 5 are both 1 μm.

  FIG. 4 is an example of a result of verifying the coincidence situation when each simulation model shown in FIG. 3 and the recombination center lattice defect D are formed in the actual IGBT 100. Helium (He) ions are used as the recombination center lattice defect D. It is the figure which showed the spreading | diffusion resistance value in a silicon | silicone (Si) board | substrate when irradiated.

  FIG. 5 is a simulation result for each model shown in FIG. 3, in which the impurity concentration of the fourth semiconductor layer 4 as the collector layer is changed for each model, and the relationship between the on-voltage and the turn-off loss is plotted. is there. In FIG. 5, the relationship between the on-voltage and the turn-off loss is shown by a broken line (no lifetime control) in the drawing for the simulation result of the IGBT 90 in which the recombination center lattice defect D shown in FIGS. 13 and 1 is not arranged. Is shown.

In each simulation model of FIG. 3, the peak position Dc of the recombination center lattice defect D is set to a position where the depth from the main surface of the substrate is 120 μm, and the turn-off end determined from the back surface of the semiconductor substrate 10 by the simulation of FIG. The recombination center lattice defect D is arranged in the first semiconductor layer 1 so that the peak position Dc is located inside the width W = 55 μm of the non-depleted region at the time. Further, assuming that the hole lifetime value τh at the peak position Dc is 3.0e ⁻⁸ sec, the half-width parameters on one side of the Gaussian recombination center lattice defect D are 5.0, 7.5, 10. 0, 12.5, 15.0, 17.5 μm. In FIG. 3, as in FIG. 2, the peak position Dc of the recombination center lattice defect D is indicated by a one-dot chain line, and the half width width Dhs on the main surface side when the half width at one side is 5.0 μm is indicated by a broken line. The main surface side hem tip position Des when the value width is 5.0 μm is indicated by a dotted line in the drawing.

  The spreading resistance value of silicon (Si) when irradiated with helium (He) ions shown in FIG. 4 has a generally Gaussian distribution, the half-value width on one side is about 5 μm, and the resistance value is stabilized from the peak of the spreading resistance value. The distribution up to the tip end position on the main surface side is approximately 20 μm, and the distribution of hole lifetime values for the simulation model shown in FIG. Although it is generally difficult to create a distribution of spreading resistance values with a half-width of less than 5 μm by He ion irradiation, other simulation models with a half-width of 5.0 μm larger than that shown in FIG. Regarding the distribution of the same spreading resistance value, a distribution of 5 to 15 μm can be formed by changing the irradiation condition of He ions.

  As shown in FIG. 5, the on-voltage and the turn-off loss, which are the characteristics of the IGBT, generally have a trade-off relationship, and the turn-off loss increases as the on-voltage decreases. On the other hand, the characteristics of the IGBT are better as it is in the lower left region of FIG. 5 where both the on-voltage and the turn-off loss are lower. As can be seen from FIG. 5, the peak position Dc of the recombination center lattice defect D is set at a depth of 120 μm from the main surface of the substrate so that the peak position Dc is inside the non-depleted region width W = 55 μm. As for each simulation model of FIG. 3 arranged in FIG. 3, any one-sided half-value width simulation model has better characteristics than the case of no lifetime control indicated by a broken line in the figure.

  As described above, the insulated gate bipolar transistor (IGBT 100) illustrated in FIGS. 2 and 3 is an FS-type insulated gate bipolar transistor that can be reduced in thickness, and precisely controls the lifetime of residual holes. Therefore, it is possible to provide an insulated gate bipolar transistor that has a simple lifetime control structure and that can perform high-speed switching with low tail loss.

  Next, a more preferred embodiment of the above-described IGBT 100 will be described.

  FIG. 6 is a diagram showing a part of the data shown in FIG. 5 and showing the relationship between the half width at one side and the turn-off loss at the ON voltage of 2.3V.

  As exemplified by the data at an on-voltage of 2.3 V in FIG. 6, in each simulation model of FIG. 3, the turn-off loss is stable at a small value when the half width at one side is 10 μm or less. At 12.5 μm or more, the turn-off loss increases as the half width on one side increases.

  As shown in FIG. 3, roughly, when the half width at one side is 10 μm or less, the main surface half width position Dhs is inside the width W of the non-depleted region, whereas when the half width at one side is 12.5 μm or more, The main surface side half-value width position Dhs is outside the width W of the non-depleted region. Therefore, the result shown in FIG. 6 shows that when the half width on one side is 10 μm or less, the main surface half width position Dhs is inside the width W of the non-depleted region, so that the ON resistance does not increase and the turn-off loss is small. When the half-width on one side is 12.5 μm or more, the main surface half-width position Dhs is outside the width W of the non-depleted region, the on-resistance increases, and the turn-off loss increases due to the trade-off relationship. Can be considered.

  As described above, in the IGBT 100 described above, the first semiconductor has the recombination center lattice defect D such that the main surface side half-value width position Dhs comes inside the width W of the non-depleted region from the back surface of the semiconductor substrate 10. It is preferable to be disposed in the layer 1. According to this, the distribution of the recombination center lattice defect D is more surely contained in the non-depleted region, and the tail loss can be reduced and the switching speed can be increased more stably.

FIG. 7 is a diagram showing the relationship between the peak position Dc of the recombination center lattice defect D and the turn-off loss. The half-value width at one side is 5 μm, and the hole lifetime value at the peak position Dc is 3.0e− ⁸ sec. The relationship between the peak position Dc and the turn-off loss when the on-voltage is 2.3 V is shown for the case of 6.0e- ⁸ sec. In the simulation of FIG. 7, the thickness of the semiconductor substrate 10 is 165 μm, and the specific resistance of the first semiconductor layer 1 is 60 Ωcm.

As shown in FIG. 7, if the peak position Dc of the recombination center lattice defect D is within the width W of the non-depleted region, the peak values of the hole lifetime are 3.0e ⁻⁸ sec and 6.0e ⁻⁸ sec. In either case, the turn-off loss can be lower than 10.9 mJ when the lifetime control is not performed. On the other hand, when the peak position Dc of the recombination center lattice defect D is outside the width W of the non-depleted region, the turn-off loss increases rapidly. Thus, the recombination center lattice defect D having one density distribution peak in the cross-sectional direction of the semiconductor substrate 10 is determined from the width W of the non-depleted region at the end of turn-off determined from the back surface of the semiconductor substrate 10 by simulation. It is necessary to arrange in the first semiconductor layer 1 so that the peak position Dc comes inside. In FIG. 7, when the peak position Dc is disposed at a depth of about 125 μm from the main surface of the substrate, the turn-off loss is minimized, and the peak values of the hole lifetime are 3.0e ⁻⁸ sec and 6.0e ⁻⁸ sec. The minimum values are 9.3 mJ and 9.8 mJ, respectively.

  FIG. 8 shows a case where the half-value width (and its peak position Dc) is changed by making the main surface side skirt tip position Des of the recombination center lattice defect D coincide with 108 μm which is the end of the non-depleted region. It is a figure which shows each simulation model. FIG. 9 is a simulation result for each model shown in FIG. 8 and shows the relationship between the half width at one side and the turn-off loss at an on-voltage of 2.3V.

  As shown in FIG. 8, the main surface side skirt tip position Des of the recombination center lattice defect D is made to coincide with the end of the non-depleted region so that the entire recombination center lattice defect D has a width W To be inside. In this case, as shown in FIG. 9, the turn-off loss hardly changes at 9.2 to 9.3 mJ, and a low turn-off loss having no dependency on the half width on one side can be obtained.

  As described above, in the IGBT 100 described above, the first semiconductor has the recombination center lattice defect D such that the main surface side skirt tip position Des is located inside the width W of the non-depleted region from the back surface of the semiconductor substrate 10. More preferably, it is arranged in the layer 1. According to this, the distribution of the recombination center lattice defect D is more reliably ensured in the non-depleted region as compared with the case where the main surface side half-value width position Dhs described in FIG. 6 is inside the width W of the non-depleted region. Therefore, tail loss can be reduced and switching speed can be increased more stably.

  FIG. 10 is a diagram showing the relationship between the hole lifetime value at the peak position Dc and the turn-off loss. The peak position Dc of the recombination center lattice defect D is 125 μm, the half width at one side is 5 μm, and the ON voltage is 2.3 V. The relationship between the hole lifetime value and the turn-off loss is shown.

As shown in FIG. 10, with respect to the hole lifetime value at the peak position Dc, if the peak value is in a range of about 2.0e ⁻⁷ sec or less, the turn-off loss is lower than that in the case where lifetime control is not performed. be able to. In addition, when the peak value is in the range of 1.0 to 2.0e- ⁸ sec, a turn-off loss of 9.1 mJ, which is the minimum value, is obtained. By setting the peak value within this range, a lower turn-off loss can be achieved. It can be realized stably.

  As described above, each of the above-described insulated gate bipolar transistors has a simple lifetime control structure capable of precisely controlling the lifetime of residual holes, and has low tail loss and high speed switching. Possible insulated gate bipolar transistors.

  As described above, the insulated gate bipolar transistor is intended for a FS type IGBT that can be thinned, and is suitable when the thickness of the semiconductor substrate 10 shown in FIG. 2 is 120 μm or more and 200 μm or less. is there.

  The insulated gate bipolar transistor may be a trench gate type IGBT having an insulated trench gate G formed so as to penetrate through the second semiconductor layer 2 as shown in FIG.

  The design method of the insulated gate bipolar transistor according to the design procedure of the insulated gate bipolar transistor described above is as follows. That is, by simulation, first, in the cross-sectional direction of the semiconductor substrate 10 shown in FIG. 2, as described with reference to FIG. 1, the width W of the non-depleted region where the electric field strength at the end of turn-off is zero is determined. Further, the recombination center lattice defect D is more preferably located on the main surface side from the back surface of the semiconductor substrate 10 so that the peak position Dc is inside the width W of the non-depleted region. It arrange | positions in the 1st semiconductor layer 1 so that the main surface side skirt tip position Des may come inside the width W of a non-depletion area | region so that the half value width position Dhs may come. As a result, it is possible to easily design the above-described insulated gate bipolar transistor that has a small tail loss and can perform high-speed switching.

  Next, in the case where the IGBT 100 shown in FIG. 2 and the IGBT 90 shown in FIG. 13 are designed, characteristic variations when the structural parameters are changed to obtain predetermined characteristics will be described.

  FIG. 11 plots the on-voltage and turn-off loss obtained by simulation for the case where the design target value of the turn-off loss is 9.5 mJ and the structural parameters of the IGBT 100 in FIG. 2 and the IGBT 90 in FIG. 13 are changed. FIG.

  In the IGBT 100 shown in FIG. 2, the peak position Dc of the recombination center lattice defect D is set to a position where the depth from the substrate main surface is 125 μm, and the half width on one side is set to 5.0 μm. Each point of the IGBT 100 surrounded by a solid line in the figure is related to the manufacturing process. (1) Carrier concentration variation due to ion implantation of the fourth semiconductor layer 4 as the collector layer and the fifth semiconductor layer 5 as the FS layer: ± 5 %, (2) Ion irradiation depth variation when forming recombination center lattice defect D: ± 7.5 μm, (3) Ion irradiation amount variation when forming recombination center lattice defect D: ± 5% It is a value obtained by carrying out a simulation using an experimental design method with a variation factor and a variation range. In addition, each point of the IGBT 90 surrounded by a broken line in the figure is a value obtained by using only the above (1) as a variation factor and a variation range.

  As shown in FIG. 11, the IGBT 100 in which the recombination center lattice defect D for lifetime control is arranged is designed to have the same turn-off loss of 9.5 mJ as compared with the IGBT 90 that is not subjected to lifetime control. Even so, it is possible to reduce both variations in on-voltage and turn-off loss characteristics with respect to variations in manufacturing processes.

  FIG. 12 shows simulation results similar to those in FIG. 11 with the turn-off loss design target values set to 8.5 mJ and 9.5 mJ, respectively, and shows a comparison of on-voltage characteristic variations for the IGBT 100 in FIG. 2 and the IGBT 90 in FIG. It is a figure. The on-voltage variation [%] shown in FIG. 12 is calculated as (maximum value−minimum value) / 2 * average value with respect to each variation of the on-voltage with respect to the IGBT 100 and the IGBT 90 in FIG.

  As shown in FIG. 12, as the design target value of the turn-off loss is decreased to increase the speed of the IGBT, the difference in the characteristic variation regarding the on-voltage between the IGBT 100 and the IGBT 90 increases. When the design target value of turn-off loss is 9.5 mJ, the characteristic variation of the IGBT 100 can be reduced by 44% with respect to the characteristic variation of the on-voltage of the IGBT 90, whereas the design target value of the turn-off loss is 8.5 mJ. In this case, the characteristic variation of the IGBT 100 can be reduced by 60% with respect to the characteristic variation of the on-voltage of the IGBT 90.

  As shown in FIG. 11 and FIG. 12, in the IGBT 100 in which the recombination center lattice defect D for lifetime control is arranged, it is turned on with respect to the variation in the manufacturing process as compared with the IGBT 90 without lifetime control. Although both the voltage and turn-off loss characteristic variations can be reduced, it is considered that this is caused by the difference in carrier concentration between the IGBT 100 and the IGBT 90. That is, in the IGBT 90 that is not subjected to lifetime control, in order to suppress the hole injection efficiency, the P-type impurity concentration of the fourth semiconductor layer 4 that is the collector layer is lowered, and the N of the fifth semiconductor layer 5 that is the FS layer is reduced. It is necessary to increase the type impurity concentration. For this reason, the fourth semiconductor layer 4 and the fifth semiconductor layer 5 are designed so that the carrier concentrations are close to each other, and the characteristic variation tends to increase. In contrast, in the IGBT 100 in which the recombination center lattice defect D for lifetime control is arranged, the carrier concentration of the fourth semiconductor layer 4 that is the collector layer is changed to the carrier concentration of the fifth semiconductor layer 5 that is the FS layer. Since it can be set larger than this, it is considered that this reduces the characteristic variation.

  As described above, the above-described insulated gate bipolar transistor and its design method are an FS type insulated gate bipolar transistor that can be thinned and its design method, and it is possible to precisely control the lifetime of residual holes. An insulated gate bipolar transistor that has a simple lifetime control structure that can be performed, has low tail loss, and can perform high-speed switching, and a design method thereof.

90,100 Insulated gate bipolar transistor (IGBT)
10 Semiconductor substrate 1 First semiconductor layer (drift layer)
2 Second semiconductor layer (channel formation layer)
3 Third semiconductor layer (emitter layer)
4 Fourth semiconductor layer (collector layer)
5 Fifth semiconductor layer (field stop layer)
D Recombination center lattice defect Dc Peak position Dhs Main surface half width position Des Main surface side hem tip position

Claims (10)

Selected as a first semiconductor layer made of a semiconductor substrate of a first conductivity type, a second semiconductor layer of a second conductivity type formed in a surface layer portion on the main surface side of the semiconductor substrate, and a surface layer portion of the second semiconductor layer First-conductivity-type third semiconductor layer, a second-conductivity-type fourth semiconductor layer formed in a surface layer portion on the back side of the semiconductor substrate, the first semiconductor layer, and the fourth semiconductor An insulated gate bipolar transistor comprising a fifth semiconductor layer of a first conductivity type formed between the layers and having an impurity concentration higher than that of the first semiconductor layer,
In the cross-sectional direction of the semiconductor substrate, the recombination center lattice defect having one density distribution peak has a peak position inside the width of the non-depleted region at the end of turn-off determined from the back surface of the semiconductor substrate by simulation. As described above, the insulated gate bipolar transistor is arranged in the first semiconductor layer.   The recombination center lattice defect is arranged in the first semiconductor layer so that the half-width position on the main surface side is located inside the width of the non-depleted region from the back surface of the semiconductor substrate. The insulated gate bipolar transistor according to claim 1.   The recombination center lattice defect is arranged in the first semiconductor layer so that a main surface side skirt tip position is located inside the width of the non-depleted region from the back surface of the semiconductor substrate. The insulated gate bipolar transistor according to claim 2.   4. The insulated gate bipolar transistor according to claim 1, wherein a thickness of the semiconductor substrate is 120 μm or more and 200 μm or less. 5.   5. The trench gate type IGBT according to claim 1, wherein the insulated gate bipolar transistor has an insulated trench gate formed so as to penetrate the second semiconductor layer. 6. The insulated gate bipolar transistor according to Item. Selected as a first semiconductor layer made of a semiconductor substrate of a first conductivity type, a second semiconductor layer of a second conductivity type formed in a surface layer portion on the main surface side of the semiconductor substrate, and a surface layer portion of the second semiconductor layer First-conductivity-type third semiconductor layer, a second-conductivity-type fourth semiconductor layer formed in a surface layer portion on the back side of the semiconductor substrate, the first semiconductor layer, and the fourth semiconductor A fifth semiconductor layer having a first conductivity type formed between the layers and having an impurity concentration higher than that of the first semiconductor layer;
A method for designing an insulated gate bipolar transistor in which a recombination center lattice defect having one density distribution peak in the cross-sectional direction of the semiconductor substrate is disposed in the first semiconductor layer,
Simulation
First, in the cross-sectional direction of the semiconductor substrate, determine the width of the non-depleted region where the electric field strength at the end of turn-off is zero,
Next, the recombination center lattice defect is arranged in the first semiconductor layer so as to have a peak position inside the width of the non-depleted region from the back surface of the semiconductor substrate. Transistor design method.   The recombination center lattice defect is arranged in the first semiconductor layer so that a main surface side half-value width position is located inside a width of the non-depleted region from a back surface of the semiconductor substrate. 7. A method for designing an insulated gate bipolar transistor according to 6.   The recombination center lattice defect is arranged in the first semiconductor layer such that a main surface side skirt tip position comes inside a width of the non-depleted region from a back surface of the semiconductor substrate. 8. A method for designing an insulated gate bipolar transistor according to 7.   The method for designing an insulated gate bipolar transistor according to any one of claims 6 to 8, wherein the semiconductor substrate has a thickness of 120 µm or more and 200 µm or less.   10. The trench gate type IGBT according to claim 6, wherein the insulated gate bipolar transistor has an insulated trench gate formed so as to penetrate the second semiconductor layer. 11. A method for designing an insulated gate bipolar transistor according to the item.

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