JP2001144293A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the problem, where at a trench IGBT, an element is broken by current concentration at turn-off with generation of high temperature and large current. SOLUTION: The interface for a trench 62 between a gate oxide film 64 and a p-base layer 56 acts as a channel, when the positive hole accumulated at an n- epitaxial layer 54 flows to an emitter electrode 72. The concentration at specific points of the positive hole through the interface breaks an element. So, a p+ isolation region 68 is so provided as to adjoin the sidewall of the trench. The p+ isolation region 68 is formed to a depth such as to partially cut into the n- epitaxial layer 54 under the p-base layer 56. The p+ separation regions 68 are provided at prescribed intervals or less in the longitudinal direction of the trench 62. Thus the interface which acts as a channel is subdivided. Since the positive hole cannot move to the interface of an adjacent p-base layer 56 across the p+ isolation region 68, the current concentrating on a specific point is limited to prevent the element from breakdown.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of performing high-voltage, large-current switching control.

[0002]

2. Description of the Related Art An inverter device is used to generate a desired current and voltage for driving a motor such as an electric vehicle from a given power supply. This inverter includes a configuration in which a switching element and a reflux diode connected in anti-parallel to the switching element are paired.

A switching element used in such an inverter is required to have a characteristic that a voltage drop during current conduction is small, that is, an ON voltage is small. In addition, the switching element is required to have a high-speed switching operation in order to realize a high-speed operation of the inverter, and is required to have a small switching loss accompanying the switching operation. In addition, the current that can flow per unit area of the switching element, that is, the controllable current density is improved, so that the size of the switching element is reduced and the cost of the switching element is reduced as the number of chips obtained from one wafer increases. Efforts are being made.

As an element that can meet these requirements, an insulated gate transistor (IGBT) is used.
ar Transisto). IGBT is power MOSFET
This is a semiconductor element in which T and a bipolar transistor are combined in one chip, and has both high-speed switching performance by a MOS gate and high breakdown voltage and high conduction characteristics by a bipolar transistor operation. In particular, a trench IGBT in which a gate has a trench structure has attracted attention as an element that can satisfy both requirements for on-voltage and high-speed switching performance.

FIG. 6 is a schematic perspective view showing a three-dimensional structure of a conventional trench IGBT. FIG. 7 is a top view schematically showing the structure of a conventional trench IGBT. 6 is a cross section along the line AA 'shown in FIG. 7, while the element cross section shown as a side surface in FIG. 6 is a cross section along the line BB' shown in FIG. is there.

In the semiconductor portion of the device, the p base layer 4, n ⁻ epitaxial layer 6, n ⁺
Buffer layer 8 and p ⁺ collector layer 10 are formed. Further, on the surface side of p base layer 4, n ⁺ emitter region 12 is formed. The n ⁺ emitter region 12 is formed so as to leave a portion where the p base layer 4 is exposed on the surface. The trench 14 extends from the surface of the semiconductor portion to the n ⁺ emitter region 12,
The p base layer 4 is shaved to a depth reaching the n ⁻ epitaxial layer 6. A gate electrode 18 is buried in the trench 14 via a gate oxide film 16. An emitter electrode 20 is provided on the surface of the semiconductor portion to be in contact with p base layer 4 and n ⁺ emitter region 12. Note that an interlayer insulating film 22 is provided on the trench 14, and an emitter electrode 20 is formed thereon, thereby ensuring insulation between the gate electrode 18 and the emitter electrode 20.

In this configuration, n ⁺ emitter region 1
2, the p base layer 4, the n ⁻ epitaxial layer 6 and the gate electrode 18 constitute a MOSFET. When a positive voltage is applied to the gate electrode 18, a channel is formed in a region of the p base layer 4 in contact with the gate electrode 18, and the n ⁺ Electrons flow from emitter region 12 to n ⁻ epitaxial layer 6.

The p base layer 4, n ⁻ epitaxial layer 6, n ⁺ buffer layer 8, and p ⁺ collector layer 10 form a pnp bipolar transistor. In this pnp bipolar transistor, the conductivity of the n ⁻ epitaxial layer 6 and the n ⁺ buffer layer 8 decreases due to the operation of the MOSFET portion, and holes flow from the p ⁺ collector layer 10 to the p base layer 4.

For example, a conventional trench IGBT having a rated voltage of 600 V has a thickness of 10 to 15 μm on one main surface of ap ⁺ substrate.
N ⁺ buffer layer 8 having a carrier concentration of about 1 × 10 ¹⁷ cm ⁻³
Is formed, and an n ⁻ epitaxial layer 6 having a thickness of 50 to 70 μm and a carrier concentration of about 2 × 10 ¹⁴ cm ⁻³ is formed thereon. Further n ^- depth on the surface side of the epitaxial layer 6 of 3
A p base layer 4 of about 6 μm is formed by thermal diffusion, and an n ⁺ emitter region 12 is formed in the p base layer 4 by diffusion. The diffusion depth of this n ⁺ emitter region 12 is 0.5 to 1
It is about μm. The trench 14 is 1 to 1 from the p base layer 4.
The trenches 14 have a depth of about 3 μm, a width of 1 μm, and a length of 1 mm. The trenches 14 are arranged in parallel at intervals of 4 μm. A gate electrode 18 is provided inside the trench 14 via a gate oxide film 16. Gate oxide film 16 has a thickness of 80 to 100 nm. This conventional trench IGBT has a current density of 250 A /
The on-voltage is about 1.4 V at cm ² .

[0010]

As a configuration of a semiconductor element used for controlling a large current, it is conceivable to increase the sectional area of a current passage. However, in this method, even if a large cross-sectional area of the flow passage is ensured in design, there is a place where current concentrates in the flow passage due to variations and non-uniformity in manufacturing and the like, and the element is destroyed at the place. There was a problem.

For example, when switching the inductance load in the conventional trench IGBT at a current density of 400 A / cm ² , the conventional trench IGBT cannot be turned off, the wiring is melted, and the chip is broken.

In particular, the current density at which such breakdown occurs is
As the chip temperature increases, it tends to decrease. For example, the above-mentioned conventional trench IGBT was broken at a chip temperature of 125 ° C. at a current density of 100 A / cm ² .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a highly reliable semiconductor device which is not destroyed at the time of a large current switching operation regardless of normal temperature or high temperature.

[0014]

8 and 9 show a conventional IG.
FIG. 8 and FIG. 9 illustrate a mechanism that causes destruction at the time of turn-off in the BT.
A ′, a cross section along a straight line BB ′. Gate electrode 18
Is turned off, a reverse bias is applied between the first conductivity type base layer (p base layer 4 in FIGS. 8 and 9) and the second conductivity type base layer (n ⁻ epitaxial layer 6 in FIG. 8), and the boundary between these regions The depletion layer 30 spreads on both sides of.
As a result of the formation of the depletion layer 30, an inversion layer 32 is formed at the interface between the first conductivity type base layer and the gate electrode insulating film (gate oxide film 16 in the figure) of the trench 14. The minority carriers accumulated in the second conductivity type base layer flow along the gate electrode insulating film interface (conductive interface) where the inversion layer 32 is formed, and reach the emitter electrode 20.
In the figure, the flow of the minority carrier is indicated by an arrow. Here, the conductance of the channel formed at the conduction interface depends on factors such as subtle deviation of the effective turn-off timing and manufacturing variations, and is not necessarily uniform at each part of the conduction interface. . As a result, as shown in FIG. 9, when a portion where the current concentrates from the second conductivity type base layer to the first conductivity type base layer occurs, latch-up occurs at that portion due to the operation of the parasitic transistor, and the current concentration increases. Accelerated and the device can be destroyed. Current concentrated at some point on the conduction interface collects via the conduction interface. Therefore, it is considered that the larger the range of the second conductivity type base layer covered by the conduction boundary surface, that is, the longer the horizontal length of the conduction boundary surface, the larger the amount of concentrated current.

The present invention solves the problem of avoiding destruction of a semiconductor device by suppressing current concentration on a specific portion of a first conductivity type base layer, which is considered to be caused by such a mechanism. Is to achieve.

First, according to the present invention, a first conductivity type collector layer connected to a collector electrode, a second conductivity type base layer formed on the first conductivity type collector layer, and a second conductivity type base layer A first electrode formed above and connected to the emitter electrode;
A conductive type base layer, a trench formed from a surface of the first conductive type base layer and having a depth reaching halfway of the second conductive type base layer, and a trench along a surface of the first conductive type base layer. A second conductive type emitter region selectively formed by the second conductive type and connected to the emitter electrode, and buried in the trench via an insulating film, and the second conductive type base layer via the first conductive type base layer. A semiconductor device for controlling current flowing between the emitter electrode and the collector electrode, the semiconductor device having a gate electrode for controlling a current flowing between the base emitter layer and the second conductivity type base layer; The horizontal length along the trench of each conduction boundary formed by contacting the insulating film and the first conductivity type base layer is a target controllable current between the emitter electrode and the collector electrode. Dense It is those formed below the upper limit value in accordance with.

According to the present invention, the horizontal length of the conduction boundary along the trench is equal to or less than a predetermined value. This imposes an upper limit on the current concentrated at a point within the conduction interface, even if the turn-off at the conduction interface is non-uniform. The predetermined value of the horizontal length along the trench at the conduction boundary is determined according to how much current the semiconductor device is used to control, and basically, the larger the controllable current density becomes, the more the conduction boundary becomes larger. It is preferable to set the horizontal length to be small. One way to control the horizontal length of the conductive interface is to control the length of the trench itself.
In this method, for example, instead of forming each of the long trenches on the substrate, the trenches are formed in a plurality of divided short trenches.

A semiconductor device according to the present invention has an isolation region provided in contact with a side wall of the trench to divide the conductive boundary surface.

According to the present invention, the horizontal length of the conduction boundary can be suppressed without making the trench itself short. According to the present invention, the isolation region is formed in contact with the side wall of the trench. The isolation region hinders the formation of the inversion layer in the portion of the gate electrode insulating film with which the isolation region contacts, thereby dividing the conduction boundary surface formed facing the side wall of the common trench into a plurality of portions. . By arranging the isolation region along the trench at a predetermined interval or less, the horizontal length of the conduction boundary along the trench is suppressed, and current control up to a target current density can be performed while avoiding destruction of the semiconductor device. It becomes possible.

In a preferred aspect of the present invention, the separation region is
This is a semiconductor device that is a first conductivity type low resistance region. According to this aspect, since the isolation region is a low-resistance region formed by introducing a large amount of impurities of the first conductivity type, for example, no inversion layer is formed at a portion in contact with the trench, and the separation of the conduction boundary surface is prevented. Done.

In the semiconductor device according to the present invention, the second conductive type base layer includes a second conductive type low resistance layer on a side in contact with the first conductive type collector layer.

According to the present invention, it is possible to prevent minority carriers in the collector region of the first conductivity type from being injected into the base layer of the second conductivity type. This suppresses the amount of current flowing to the emitter electrode via the conduction boundary surface at the time of turn-off, so that breakdown due to current concentration hardly occurs.

In the semiconductor device according to the present invention, the second conductivity type base layer has a minority carrier for reducing the lifetime of minority carriers in the second conductivity type base layer on the side in contact with the first conductivity type collector layer. It has a suppression layer.

According to the present invention, the injection of minority carriers in the first conductivity type collector region into the second conductivity type base layer is suppressed by the minority carrier suppression layer. This suppresses the amount of current flowing to the emitter electrode via the conduction boundary surface at the time of turn-off, so that breakdown due to current concentration hardly occurs.

A preferred embodiment of the present invention is a semiconductor device in which the minority carrier suppressing layer is formed by irradiating at least one of protons and helium ions to introduce recombination centers. By performing ion implantation, lattice defects serving as recombination centers are introduced. In particular, protons and helium have shorter ranges than electron beams. Therefore, by implanting these ions from the back surface of the substrate on which the first conductivity type collector layer is disposed, lattice defects can be exclusively distributed on the side of the second conductivity type base layer which is in contact with the first conductivity type collector layer, Injection of minority carriers of the first conductivity type collector layer into the second conductivity type base layer can be effectively suppressed.

[0026]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic perspective view showing a three-dimensional structure of a trench IGBT according to the present invention. FIG. 2 is a top view schematically showing the structure of the trench IGBT according to the present invention. 1 is a cross section taken along a line AA ′ shown in FIG. 2, while FIG.
2 is a cross section taken along a straight line BB ′ shown in FIG. FIG. 3 is a cross-sectional view schematically showing a structure of the trench IGBT according to the present invention, which is a cross-section along a straight line BB ′ shown in FIG.

On a p ⁺ substrate (thickness: 500 μm, carrier concentration: 1 × 10 ¹⁸ cm ^-3 or more) constituting the p ⁺ collector layer 50, an n ⁺ buffer layer 52 (constituting a second conductivity type base layer) is formed. Thickness 10-15 μm) and n ⁻ epitaxial layer 54 (55-70 μm thick, carrier concentration 2 × 10 ¹⁴ c)
m ⁻³ ) is formed by the epitaxial growth method. The n ⁺ buffer layer 52 has a carrier concentration of 1
It is a low resistance layer of about × 10 ¹⁷ cm ⁻³ . On the other hand, the carrier concentration of n ⁻ epitaxial layer 54 is about 2 × 10 ¹⁴ cm ⁻³ .

The p base layer 56 (thickness 3 to 6 μm, carrier concentration of the order of 1 × 10 ¹⁷ cm ⁻³ ) is formed on the surface of the n ⁻ epitaxial layer 54 by thermally diffusing impurities. A photoresist film is formed on the surface of p base layer 56, and the photoresist film is patterned to form a mask for forming an n ⁺ region. n ⁺
The region is formed by ion-implanting an impurity from above the mask. The diffusion depth of the n ⁺ region is 0.5 to 1
It is about μm.

The pattern of the n ⁺ region has a width of several μm and a length of 1.
n ⁺ emitter region 5 in the form of an elongated stripe of about mm
8 is included. In order to enable large current control, many IGBTs are arranged in parallel in this device. Correspondingly, a plurality of n ⁺ emitter regions 58 are also arranged in parallel.
Further, the n ⁺ region includes a contact region 60 bridging between adjacent n ⁺ emitter regions 58. This contact region 60 is provided solely for ensuring electrical contact between n ⁺ emitter region 58 and emitter electrode 72.

A trench 62 is formed along the longitudinal center line of n ⁺ emitter region 58. This trench 62
Has a depth of about 1 to 3 μm deeper than the p base layer 56, and has a width of 1 μm and a length of the n ⁺ emitter region 58.
And about 1 mm. N ⁺ trench 62
Forming along the center line of emitter region 58 divides each n ⁺ emitter region 58 into two regions adjacent to trench 62. A gate electrode 66 is buried inside the trench 62 via a gate oxide film 64.
The thickness of the gate oxide film 64 is 80 to 100 nm. Note that the gate electrodes 66 are configured so as to have an interval of about 4 μm, for example.

In the present IGBT, ap ⁺ isolation region 68 having the same depth as trench 62 is formed perpendicular to the longitudinal direction of trench 62. This p ⁺ isolation region 68 has a width of 1 to 5
μm, and is formed by using, for example, a high energy ion implantation method or a thermal diffusion method. The p ⁺ isolation region 68 has a low resistance (for example, a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more). The p ⁺ isolation region 68 is, for example, 50 to 200 μm
It is arranged so as to be orthogonal to the trench 62 at intervals. Further, p ⁺ isolation region 68 is formed so as to be in contact with the side surface of trench 62, that is, gate oxide film 64.

Thereafter, a striped interlayer insulating film 70 is provided on the trench 62 so as to cover the trench 62. The interlayer insulating film 70 is for ensuring insulation between the emitter electrode 72 provided on the film and the gate electrode 66 formed below the film.

After the interlayer insulating film 70, the emitter electrode 7
2 are formed. The emitter electrode 72 includes a p base layer 56 exposed in a gap between the interlayer insulating films 70 and an n ⁺ emitter region 58.
And an electrode that electrically contacts the p ⁺ isolation region 68 and keeps them at a common potential. By providing the interlayer insulating film 70 as described above, the emitter electrode 72 is
In addition to the portion where the semiconductor layer is exposed, the gate electrode 6
6 can also be stacked in the area where the 6 is arranged. That is, basically, the emitter electrode 72 is formed on the entire surface including the p base layer 56, the n ⁺ emitter region 58 and the p ⁺ isolation region 68, so that fine patterning of the emitter electrode 72 becomes unnecessary.

The n ⁺ emitter region 58 is at least partially covered with the interlayer insulating film 70, and the area of the n ⁺ emitter region 58 exposed in the gap between the interlayer insulating films 70 is reduced. The above-described contact region 60 is provided to supplement this.

FIG. 4 shows a measurement circuit used for measuring the turn-off characteristic, which has an inductance as a load. Using the measurement circuit, tests of the trench IGBT according to the present embodiment and the conventional trench IGBT were performed.
FIG. 5 is a graph schematically showing the test results. In the figure, the horizontal axis is time, and the vertical axis is the current between the emitter and the collector. The gate drive pulse power supply 80 is turned on at time t _0.
When a voltage is applied to the gate electrode 66 of the trench IGBT 82 to turn on the gate, the emitter-collector of the trench IGBT 82 connected to the power supply 84 becomes conductive. Since the inductance 86 is connected to the emitter terminal, the current flowing between the emitter and the collector gradually increases in a transient process. FIG. 5 shows the current behavior when the gate is turned off at a certain timing during the transition process. In FIG. 5, the solid line is the trench IGBT according to the present embodiment, and the dotted line is p ⁺
The behavior of a conventional trench IGBT basically configured the same as the present embodiment except that it does not have an isolation region 68 is shown.

For a conventional IGBT, the current density is at a certain level (for example, about 10% at a high temperature of 125 ° C.).
0A / cm ² ), the turn-off was attempted at timing t ₁ . However, in the conventional device, after the current decreased slightly,
It turned into an increase and the device was destroyed. The mechanism of this turn-off failure is understood as follows. That is, the holes accumulated in n ⁻ epitaxial layer 54 are
In the process of being absorbed by the emitter through the inversion layer at the interface between the p-base layer 56 and the gate oxide film 64 at the time of turn-off, a portion of the interface at which holes easily pass through the interface extends from a wide range through the interface. Hole current concentrates. It is considered that the concentration of the hole current caused the latch-up of the parasitic transistor, and the current could not be cut off.

On the other hand, for the IGBT according to this embodiment, the timing t ₂ at which the current density becomes higher (for example, about 150 A / cm ² at a high temperature of 125 ° C.).
Also, the turn-off operation was possible. It is considered that this is because the p ⁺ isolation region 68 prevents the hole current from concentrating on a certain portion of the interface between the gate oxide film 64 and the p base layer 56. That is, during the process in which the holes accumulated in n ⁻ epitaxial layer 54 are absorbed by the emitter through the inversion layer at the interface between p base layer 56 and gate oxide film 64 at the time of turn-off, the holes become p ⁺
It is prevented that the separation region 68 and the gate oxide film 64 move beyond the boundary surface portion in contact with each other. As a result, even if there is a portion where holes easily pass through at the interface between the p base layer 56 and the gate oxide film 64, the hole current hardly concentrates there, and thus the latch-up of the parasitic transistor hardly occurs. Incidentally, in FIG. 3, the flow of holes is indicated by arrows.

The trench IGBT according to the present embodiment
As in the case of the related art, a characteristic of an on-state voltage of 1.4 V at a current density of 250 A / cm ² and a device withstand voltage (750 to 800 V) substantially the same as the related art were obtained. in this way,
By providing the p ⁺ isolation region 68, the turn-off characteristics were improved, while other characteristics were not impaired.

The ^{p.sup. +} Isolation region 68, which is a major feature of this embodiment, can be formed by using a high-energy ion implantation apparatus as described above. In this case, for example, by performing ion implantation while changing the acceleration energy, the p ⁺ isolation region 68 in which impurities are distributed at a suitable concentration from a depth substantially equal to that of the trench to near the surface while suppressing the spread of the width is suppressed. Can be realized. Thus, the p ⁺ isolation region 68 can be formed without significantly changing the conventional process.

The effect of improving the turn-off characteristics of the present IGBT is that the channel surface of holes formed at the boundary between the p base layer 56 and the gate oxide film 64 has a plurality of partial channel surfaces in the horizontal direction due to the p ⁺ isolation region 68. This is based on the division. As a result, the amount of hole current that can be concentrated on a certain portion of the channel surface is limited to the amount of hole current that can flow on the partial channel surface including that portion. Therefore, p
⁺ The arrangement interval of the isolation region 68 is reduced, the smaller the partial channel surface, the hole current may concentrate on a certain portion is suppressed, the effect of improving the turn-off characteristics is expected to be higher. On the other hand, if the arrangement interval of the p ⁺ isolation region 68 is reduced, the n ⁺ emitter region 58 and the p base layer 5
6, the area of the NMOS transistor formed of the n ⁻ epitaxial layer 54 and the gate electrode 66 is reduced. As a result, it becomes difficult to inject sufficient electrons from the emitter electrode 72 side in the ON state, and the ON voltage increases. Therefore, considering not only the turn-off characteristics but also the on-voltage characteristics, a suitable range may exist for the arrangement intervals of the p ⁺ isolation regions 68. For example, in the above-described embodiment, the arrangement interval of the p ⁺ isolation regions 68 should be larger than 50 μm, and preferably 100 μm, in order to avoid deterioration of the ON voltage. On the other hand, the interval is 500μ
If it is about m or more, the effect of improving the turn-off characteristics is diminished.

Here, the n ^- epitaxial layer 5
4 and p ⁺ collector layer 50, n ⁺ buffer layer 52 was arranged. The n ⁺ buffer layer 52, p ⁺ collector layer 50
The purpose of this is to suppress the injection of holes from the holes and shorten the turn-off time. Instead of the n ⁺ buffer layer 52, a layer into which recombination centers are introduced by implantation of protons or helium ions is provided on the p ⁺ collector layer 50 side of the n ⁻ epitaxial layer 54, and the life of holes as minority carriers is reduced. The turn-off time can also be reduced by shortening the time. Further, a configuration in which both the recombination center introduction layer and the n ⁺ buffer layer 52 are provided is also suitable.

In the above embodiment, the p ⁺ isolation region 68 is formed so as to extend between the adjacent trenches 62. This is intended to secure the electrical contact with the emitter electrode 72 by providing the p ⁺ isolation region 68 exposed exclusively between the interlayer insulating films 70. Essentially, the p ⁺ isolation region 68 sufficiently achieves the effect of improving the turn-off characteristics as long as the boundary surface where the side wall of the trench 62 and the p base layer 56 are in contact is separated, and the p base layer 56 itself is not necessarily separated. I don't think you need to. Therefore, a configuration in which the p ⁺ isolation region 68 is not bridged between the adjacent trenches 62 is also possible unless electrical contact with the emitter electrode 72 is considered. Further, it is not essential that the p ⁺ isolation region 68 is arranged perpendicularly to the trench 62, and it is possible to arrange the p ⁺ isolation region 68 obliquely.

[0044]

According to the semiconductor device of the present invention, the element is prevented from being destroyed when the turn-off operation is performed in a state where a large current is conducted, and the effect that the turn-off is reliably realized is obtained. This effect can be obtained even when the chip temperature increases. Further, in a semiconductor device used for driving a motor requiring a large output such as an electric vehicle, there is also an effect that destruction due to a large surge voltage or the like generated at the time of switching can be prevented. As described above, by using the semiconductor device according to the present invention, a highly reliable switching circuit can be realized. In particular, according to the present invention, a semiconductor device suitable for forming an inverter used in a severe environment such as an electric vehicle can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view showing a three-dimensional structure of a trench IGBT according to an embodiment.

FIG. 2 is a top view schematically showing a structure of a trench IGBT according to the embodiment.

FIG. 3 is a cross-sectional view schematically showing a structure of a trench IGBT according to the embodiment.

FIG. 4 is a schematic diagram of a measurement circuit used for measuring a turn-off characteristic.

FIG. 5 is a schematic diagram illustrating test results of turn-off characteristics of the trench IGBT according to the embodiment and the conventional trench IGBT.

FIG. 6 is a schematic perspective view three-dimensionally showing a structure of a conventional trench IGBT.

FIG. 7 is a top view schematically showing a structure of a conventional trench IGBT.

FIG. 8 is a schematic view of a cross section of a conventional trench IGBT in a direction perpendicular to a trench.

FIG. 9 is a schematic view of a cross section of a conventional trench IGBT in a direction parallel to a trench.

[Explanation of symbols]

50 p ⁺ collector layer, 52 n ⁺ buffer layer, 54 n
^- epitaxial layer, 56 p base layer, 58 n ⁺ emitter region, 62 trench, 64 a gate oxide film, 66
Gate electrode, 68p ⁺ isolation region, 70 interlayer insulating film, 72 emitter electrode.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Toshio Murata 41-cho, Yokomichi, Nagakute-machi, Aichi-gun, Aichi-gun, 1st place, Toyota Central Research Laboratory Co., Ltd. No. 41, Chochu-Yokomichi 1 Toyota Central Research Laboratory Co., Ltd. (72) Inventor Tomoyoshi Kushida 1 Toyota Town, Toyota City, Aichi Prefecture Inside Toyota Motor Corporation (72) Inventor Kimimori Hamada 1 Toyota City Toyota City, Aichi Prefecture Address Toyota Motor Corporation

Claims (6)

[Claims] A first conductive type collector layer connected to a collector electrode; a second conductive type base layer formed on the first conductive type collector layer; and a second conductive type base layer formed on the second conductive type base layer. A first conductivity type base layer connected to an emitter electrode, a trench formed from a surface of the first conductivity type base layer and having a depth reaching halfway of the second conductivity type base layer; A second conductivity type emitter region selectively formed on the surface of the layer along the trench and connected to the emitter electrode; and a first conductivity type base formed buried in the trench via an insulating film. A gate electrode for controlling a current flowing between the second conductivity type emitter region and the second conductivity type base layer via a layer,
In the semiconductor device for controlling current between the emitter electrode and the collector electrode, the semiconductor film may be formed on a side wall of the trench where the insulating film and the first conductive type base layer are in contact with each other at the conductive boundary surface. The semiconductor device according to claim 1, wherein a horizontal length along the horizontal axis is equal to or less than an upper limit corresponding to a target controllable current density between the emitter electrode and the collector electrode. 2. The semiconductor device according to claim 1, further comprising an isolation region provided in contact with a side wall of said trench to divide said conductive boundary surface. 3. The semiconductor device according to claim 2, wherein said isolation region is a first conductivity type low resistance region. 4. The semiconductor device according to claim 1, wherein the second conductivity type base layer has a second conductivity type low resistance layer on a side in contact with the first conductivity type collector layer. A semiconductor device characterized by including: 5. The semiconductor device according to claim 1, wherein said second conductivity type base layer is provided on a side of said second conductivity type base layer which is in contact with said first conductivity type collector layer. A semiconductor device having a minority carrier suppressing layer for reducing the minority carrier lifetime. 6. The semiconductor device according to claim 5, wherein the minority carrier suppression layer is formed by irradiating at least one of protons and helium ions to introduce recombination centers. .