JP2011082332A - Structure of high electron mobility transistor, device including structure of the same, and method of manufacturing the same - Google Patents

Abstract

Disclosed is a MOS-PHEMT structure suitable for use as a semiconductor device, such as an MMIC SPDT switch, and a method for manufacturing the same.
The MOS-PHEMT structure is characterized by having a gate dielectric layer 107 made of a material selected from the group consisting of Al ₂ O ₃ , HfO ₂ , La ₂ O ₃ and ZrO _2. A semiconductor structure such as a high-frequency switch device including a MOS-PHEMT structure can prevent loss of direct current and insertion loss, and can improve isolation.
[Selection] Figure 1E

Description

  The present invention relates to a structure manufactured on a group III-V compound semiconductor wafer suitable for use as a semiconductor device, such as a switch or an amplifier of a MMIC (Monolithic Microwave Integrated Circuit).

  Conventional compound semiconductor devices (for example, a high electron mobility transistor (HEMT)) generally perform current modulation using a Schottky gate, but have a drawback of large gate leakage current. Therefore, there is a need for an improved HEMT structure and method for manufacturing the same that solves the problems of the prior art.

  Therefore, in view of the above-mentioned drawbacks, the object of the present invention is to provide a semiconductor device that can be applied to the field of microwaves and radars with low gate leakage current, direct current loss and insertion loss, and good isolation. It is to disclose an improved structure to manufacture.

  The present invention discloses a structure manufactured on a group III-V compound semiconductor wafer (used for a semiconductor device), a semiconductor device including the structure, and a manufacturing method thereof.

In a first aspect of the invention, a GaAs MOS-PHEMT structure is provided. The structure includes a substrate, a III-V compound semiconductor, a gate dielectric covering the III-V compound semiconductor by ALD, an ohmic contact bonded to the III-V compound semiconductor, and a gate dielectric. And a gate electrode. In one embodiment, the gate dielectric is a thin film Al ₂ O ₃ with a thickness of about 8 nm to 20 nm.

  In a second aspect of the present invention, a method for manufacturing the above structure is provided. The method uses a step of forming a group III-V compound semiconductor on a substrate, a step of forming a gate dielectric on the group III-V compound semiconductor by an ALD method, and a group III-V compound using an electron gun. Forming an ohmic contact coupled to the semiconductor, and forming a gate electrode by forming a layer of metal on the gate dielectric.

  In a third aspect of the present invention, a GaAs MOS-PHEMT SPDT including a GaAs MOS-PHEMT includes a GaAs MOS-PHEMT structure fabricated by the method described above. This MOS-PHEMPT SPDT switch is characterized in that it has less gate leakage current, direct current loss and insertion loss, and better isolation than the conventional PHEMT switch.

  These and other features, aspects and advantages of the present invention will be better understood with reference to the following description and appended claims.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawing
It is sectional drawing which shows a state when manufacturing the GaAs MOS-PHEMT structure by one Example of this invention. It is sectional drawing which shows a state when manufacturing the GaAs MOS-PHEMT structure by one Example of this invention. It is sectional drawing which shows a state when manufacturing the GaAs MOS-PHEMT structure by one Example of this invention. It is sectional drawing which shows a state when manufacturing the GaAs MOS-PHEMT structure by one Example of this invention. It is sectional drawing which shows a state when manufacturing the GaAs MOS-PHEMT structure by one Example of this invention. It is a graph which shows the relationship between the gate leakage current of a (a) conventional PHEMT device, and (b) the MOS-PHEMT device manufactured by one Example of this invention, and a voltage. It is a graph which shows the relationship between the control current of a conventional PHEMT device and (b) the MOS-PHEMT device manufactured by one Example of this invention, and a control voltage. It is a graph which shows the relationship between the insertion loss and frequency of the (a) conventional PHEMT device and the (b) MOS-PHEMT device manufactured by one Example of this invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to describe the common elements.

  The present invention relates to a MOS-PHEMT structure manufactured on a III-V compound semiconductor wafer applied to a semiconductor device (for example, a MOS-PHEMT SPDT switch) and a manufacturing method thereof.

In a preferred embodiment of the present invention, a GaAs MOS-PHEMT (Metal Oxide Semiconductor High Electron Mobility Transistor) structure fabricated on a III-V compound semiconductor wafer is formed by an ALD (Atomic Layer ₂ ) method. It has an O ₃ gate dielectric layer. This high dielectric constant (high-k) Al ₂ O ₃ can provide low gate leakage current and thermal stability, thus reducing the direct current loss of the manufactured semiconductor device (eg, MOS-PHEMT SPDT switch). In addition to reducing the insertion loss, the isolation effect of the high-frequency switch device can be increased.

  The MOS-PHEMT device 10 of this example is manufactured on a III-V group compound semiconductor wafer. The device is manufactured using conventional lithography and lift-off methods (including mesa etching, recess etching, dielectric deposition, ohmic formation and gate formation). Table 1 details the specific examples of GaAs MOS-PHEMT structures on III-V compound semiconductor wafers. Each column in Table 1 shows the function, nominal thickness (Å), and mole fraction of each layer in the specific example.

FIG. 1A is a cross-sectional view showing a partially completed GaAs MOS-PHEMT structure. In this embodiment, various epitaxial layers are sequentially grown on the substrate 100. The substrate 100 may be made of a III-V group material (for example, GaAs, InP, etc.), and is preferably made of GaAs or a GaAs-based material. The epitaxial layer may be grown on the substrate 100 using well-known techniques (eg, metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE)). In one embodiment of the present invention, first, the buffer layer 101 is formed over the substrate 100. In the embodiment of FIG. 1A, the specific buffer layer 101 is an undoped GaAs layer. Subsequently, an epitaxial layer including an undoped InGaAs layer 102 having a thickness of 13 nm and an undoped AlGaAs layer 103 having a thickness of 40 nm including delta doping is sequentially formed on the buffer layer 101. The delta doping 106 is indicated by a dotted line. In the particular embodiment of FIG. 1A, the undoped InGaAs layer 102 is an undoped In _0.2 Ga _0.8 As layer, and the undoped AlGaAs layer 103 is an undoped Al _0.25 Ga _{0. 75} As layer. Subsequently, in the particular embodiment of FIG. 1A, other layers, including the AlAs layer 104 of about 1.5 nm may be grown before the n-type GaAs layer 105 of about 60 nm is grown.

Subsequently, the structure of FIG. 1A is etched to form the recesses or grooves of FIG. 1B. The etching step may be performed by a well-known standard technique such as wet etching or dry etching. Subsequently, a gate dielectric layer 107 is deposited on the structure of FIG. 1B using ALD. The gate dielectric is selected from the group consisting of Al ₂ O ₃ , HfO ₂ , La ₂ O ₃ , ZrO ₂ , Ga ₂ O ₃ , Y ₂ O ₃ , TiO ₂ , Ta ₂ O ₅ , HfAlO, TiAlO and LaAlO. Made of material. The gate dielectric is preferably made of a material selected from the group consisting of Al ₂ O ₃ , HfO ₂ , La ₂ O ₃ and ZrO ₂ . In the structure shown in FIG. 1C, Al ₂ O ₃ of about 8 nm to ₂₀ nm is deposited at about 300 ° C. using the ALD method. Preferably, Al ₂ O ₃ having a thickness of 16 nm is deposited by a source gas containing trimethylaluminum (TMA) and water vapor. For example, the gas cycle times of TMA, N ₂ , H ₂ O and N ₂ are 1 second, 10 seconds, 1 second and 10 seconds, respectively, and the deposition rate of aluminum oxide is about 1.3 mm per cycle. is there. The ALD method performed in the present embodiment is provided by Instrument Technology Research Center (ITRC) in Taiwan, but tools provided by other manufacturers may be used. . The method of depositing the Al ₂ O ₃ layer by the ALD method is superior in quality to conventional methods such as sputtering, chemical vapor deposition, and oxidation of a pure aluminum film. The ALD method is an ultra-thin thin film deposition technique that sequentially uses gas phase reactants. When the growth surface is repeatedly exposed to the reaction gas, the amount of the film material grown for each cycle can be maintained constant, and thus the film thickness can be adjusted on an atomic scale. In this example, the Al ₂ O ₃ gate dielectric film has a very low leakage current density of about 10 ⁻⁸ A / cm ^{2 in} a film layer having a thickness of about 16 nm.

  Subsequently, in this embodiment, the active region 109 defined in the III-V group compound semiconductor structure is bonded to a compound substrate (for example, the substrate 100 and an epitaxial layer thereon) adjacent to each other in close proximity to each other. 108 is formed (shown in FIG. 1D). The ohmic contact is formed by depositing a metal selected from the group consisting of Ni, Ge, Cu, Pd, Au, and combinations thereof by an electron gun. In this embodiment, an ohmic contact is formed using Ge—Au. Further, using an electron gun, a gate metal electrode 110 is formed on the gate dielectric layer 107, and Ti, Pt, Cu are formed in the same manner as the materials used in forming the gate metal contact described above. , Al, TaN, Au and a material selected from the group consisting of combinations thereof are deposited. In this embodiment, the gate electrode 110 is made of Ti—Au.

  This embodiment disclosed here can be applied to all III-V semiconductor wafers. Various MMICs including SPDT switches may be fabricated using compound semiconductor structures formed by the methods of the embodiments of the present invention. HEMT produced by the method described above, PHEMT (Pseudomorphic High Electron Mobility Transistor), MOS-PHEMT (Metal-Oxide-Semiconductor Pseudomorphic High Electron Mobility Transistor), MESFET (Metal-Semiconductor Field Effect Transistor) and MHEMT (Metamorphic High Electron Mobility Transistor), but is not limited to these.

In a preferred embodiment, a MOS-PHEMT structure with a gate length of about 0.5 μm is fabricated by the method described above. In this embodiment, the MOS-PHEMT structure is characterized by an Al ₂ O ₃ gate dielectric having a thickness of about 16 nm. Leak current, control current, and frequency (Radio-Frequency) characteristics are measured (measurement results are shown in FIG. 2), and the manufactured switch is evaluated.

As shown in FIG. 2, the switch including the MOS-PHEMT of the present invention has a large gate bias tolerance (shown in FIG. 2) under various voltages as compared to a switch having a conventional PHEMT structure, and V _GD = Although there is almost no leakage current at −25 V, the leakage current of the switch having the conventional PHEMT structure is as high as about −0.5 mA / mm.

  FIG. 3 is a graph showing the relationship between the control current and control voltage of the SPDT switch. The SPDT switch including the MOS-PHEMT structure of the present invention has a small control current over the entire measurement range of 1.5V to 5.0V, compared to a switch having a conventional PHEMT structure.

  FIG. 4 is a graph showing insertion loss and isolation effect of the SPDT switch. The switch including the MOS-PHEMT structure of the present invention has an insertion loss of 0.3 dB and a isolation effect of 33.4 dB under 2.5 GHz (control voltage = + 3/0 V). In addition, when the MOS-PHEMT structure of the present invention is used, it can be seen from the result of frequency characteristics that the switch isolation effect can be improved and the insertion loss can be reduced. That is, another MMIC may be manufactured by using the MOS-PHEMT structure of the present invention.

  While the preferred embodiments of the present invention have been disclosed above, as may be appreciated by those skilled in the art, they are not intended to limit the invention in any way. Various changes and modifications can be made without departing from the spirit and scope of the present invention. Accordingly, the scope of the claims of the present invention should be construed broadly including such changes and modifications.

10 MOS-PHEMT device 100 substrate 101 buffer layer 102 undoped InGaAs layer 103 undoped AlGaAs layer 104 AlAs layer 105 n-type GaAs layer 106 delta doping 107 gate dielectric layer 108 ohmic contact 109 active region 110 gate metal electrode

Claims (10)

A substrate,
A group III-V compound semiconductor;
A gate dielectric covering the III-V compound semiconductor by ALD and made of a material selected from the group consisting of Al ₂ O ₃ , HfO ₂ , La ₂ O ₃ and ZrO ₂ ;
An ohmic contact bonded to the group III-V compound semiconductor;
A MOS-PHEMT structure comprising: a gate electrode provided on the gate dielectric. Wherein the gate dielectric and _Al 2 _{O 3,} the structure of the MOS-PHEMT of claim 1.   The MOS-PHEMT structure of claim 1, wherein the gate dielectric has a thickness of about 8 nm to 20 nm.   4. The MOS-PHEMT structure of claim 3, wherein the gate dielectric is about 16 nm thick.   The ohmic contact is made of a material selected from the group consisting of Ni, Ge, Cu, Pd, Au and combinations thereof, and the gate electrode is made of Ti, Pt, Cu, Al, TaN, Au and combinations thereof. The MOS-PHEMT structure according to claim 1, wherein the structure is made of a material selected from the group consisting of:   2. The MOS-PHEMT structure according to claim 1, wherein the substrate is GaAs.   2. The MOS-PHEMT structure according to claim 1, wherein the III-V compound semiconductor includes InGaAs and AlGaAs. The MOS-PHEMT according to claim 7, wherein the InGaAs is undoped In _0.2 Ga _0.8 As, and the AlGaAs is Al _0.25 Ga _0.75 As including delta doping. Structure.   The MOS-PHEMT structure according to claim 1, wherein the MOS-PHEMT structure is used as a transistor of an MMIC SPDT switch. A GaAs MOS-comprising structure according to claim 1, characterized in that it comprises a structure of a gate dielectric Al ₂ O _{3 with} a thickness of about 16 nm and a switch with a gate length of about 0.5 μm. PHEMT switch.

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