TWI446532B - A structure of high electron mobility transistor, a device comprising the structure and a metnod of producing the same - Google Patents

Description

Structure for manufacturing highly electromigrating transistor, component including the same, and manufacturing method thereof

The present invention generally relates to a structure fabricated on a Group III-V composite semiconductor wafer, and a method of fabricating the same; the wafer described above is suitable for use as a semiconductor component, for example as a switch or a single rock microwave product An amplifier of a monolithic microwave integrated circuit (MMIC).

Conventional composite semiconductor components, such as high electron mobility transistors (HEMTs), typically use Schottky diode gates for current regulation. However, such components have the disadvantage of having a higher gate leakage current. Accordingly, there is a need in the art for an improved structure that overcomes the above disadvantages, and a method of making such an improved structure.

Based on the above disadvantages, one of the objects of the present invention is to provide an improved structure for fabricating semiconductor components applicable in the microwave and radar fields, and semiconductor devices using the improved structure will exhibit lower gate leakage current and less DC. Power loss, less attenuation loss, and better isolation.

Accordingly, the present invention is directed to a structure fabricated on a Group III-V compound semiconductor wafer suitable for use on a semiconductor device, a semiconductor device including the structure, and a method of fabricating the structure.

In one aspect of the present invention, a GaAs metal oxide semiconductor pseudomorphic high electron mobility transistor (MOS-PHEMT) structure is provided. The structure comprises: a substrate; a III-V compound semiconductor; a gate dielectric deposited on the III-V compound semiconductor via atomic layer deposition (ALD) deposition a plurality of ohmic contacts coupled to the III-V compound semiconductor; and a gate electrode positioned on the gate dielectric. In one example, the gate dielectric is an aluminum oxide (Al ₂ O ₃ ) film having a thickness between 8 nm and 20 nm.

In a second aspect of the invention, a method of making the above structure is provided. The method comprises the steps of: forming a III-V compound semiconductor on a substrate; forming a gate dielectric on the III-V compound semiconductor by atomic layer deposition; and electron gun deposition (electron gun) Deposition, E-gun) forming a plurality of ohmic contacts coupled to the III-V compound semiconductor; and applying a layer of metal on the gate dielectric to form a gate electrode.

In a third aspect of the invention, a GaAs MOS-PHEMT single-pole-double-throw (SPDT) switch comprising a GaAs MOS-PHEMT structure fabricated in the foregoing manner is provided. Compared to conventional PHEMT switches, the GaAs MOS-PHEMT SPDT switches are characterized by lower gate leakage current, less DC power loss, less attenuation loss, and better isolation properties.

These and other features of the present disclosure will become more apparent from the following detailed description. The above summary and the following detailed description are merely illustrative, and are not intended to limit the scope of the disclosure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same element symbols represent the same or corresponding elements.

The present invention relates to a MOS-PHEMT structure fabricated on a Group III-V composite semiconductor wafer; and a method of fabricating the same, wherein the III-V compound semiconductor wafer can be used as a semiconductor component Use, for example, as a MOS-PHEMT SPDT switch.

In a preferred embodiment of the present invention, a GaAs metal oxide semiconductor pseudomorphic high electron mobility transistor (GaAs) fabricated on a III-V composite semiconductor wafer is used. A MOS-PHEMT) structure characterized by having a layer of an aluminum oxide gate dielectric deposited by atomic layer deposition (ALD). This high-k alumina dielectric provides lower gate leakage current and better thermal stability, thus allowing the fabricated semiconductor components (eg, MOS-PHEMT SPDT switches) to have less DC current Loss, less loss of insertion, and high-frequency switching elements have better insulation.

In one embodiment, a MOS-PHEMT device 10 fabricated on a Group III-V compound semiconductor wafer is provided. This component is fabricated using conventional lithography and lift-off techniques, including mesa etch, recess etch, dielectric deposition, ohmic contacts, and gates. . Table 1 details details of a specific example of the gallium arsenide oxy-semiconductor pseudo-high-reactive transistor (GaAs MOS-PHEMT) fabricated on the III-V composite semiconductor wafer. The functions and thicknesses of each layer in this particular example are listed in the respective columns of Table 1. And the molar ratio of each component.

Figure 1A depicts a cross-sectional view of a GaAs MOS-PHEMT structure that has not been fully completed. According to this embodiment, various epitaxial layers can be sequentially grown on the substrate 100. The substrate 100 can be fabricated from any of the Group III-V materials (eg, GaAs, InP, or the like, and preferably GaAs or any GaAs-based material), and any known technique can be used ( For example, metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) grows various epitaxial layers described above on the substrate 100. In one aspect of the invention, a buffer layer 101 is first created on the substrate 100. In the example of Figure 1A, this particular buffer layer 101 is a GaAs layer that does not contain dopants. Next, a non-doped InGaAs layer 102 having a thickness of 13 nm and an undoped AlGaAs layer 103 having a thickness of 40 nm and containing δ-doping 106 therein are epitaxially grown on the buffer layer 101. In Figure 1A, this δ-doping 106 is indicated by a dashed line. In a particular embodiment of FIG. 1A, the dopant-free InGaAs layer 102 is a non-doped In _0.2 Ga _0.8 As layer, and the δ-doped 106 has no dopant-doped AlGaAs layer 103 therein. It is a non-doped Al _0.25 Ga _0.75 As layer 103. Next, an AlAs layer 104 of about 1.5 nm may be grown on the specific structure of FIG. 1A, followed by an GaAs layer 105 containing an n+ type dopant of about 60 nm.

Next, the specific structure of FIG. 1A is etched by any suitable known etching technique to form a structure having a recess as shown in FIG. 1B. This etching step can be performed by any standard etching technique, including wet etching or dry etching. Next, a layer of gate dielectric 107 is deposited in the structure of FIG. 1B by atomic layer deposition (ALD). Suitable materials for the gate dielectric are Al ₂ O ₃ , HfO ₂ , La ₂ O ₃ , ZrO ₂ , Ga ₂ O ₃ , Y ₂ O ₃ , TiO ₂ , Ta ₂ O ₅ , HfAlO, TiAlO. And the group consisting of LaAlO. A material suitable as the gate dielectric is preferably selected from the group consisting of Al ₂ O ₃ , HfO ₂ , La ₂ O ₃ , or ZrO ₂ . In the structure of Fig. 1C, an Al ₂ O ₃ layer of about 8 nm to about 20 nm is deposited by atomic layer deposition at a temperature of about 300 °C. Preferably, an Al ₂ O ₃ layer of about 16 nm is deposited from a source gas containing trimethylalumium (TMA) and water vapor. In one embodiment, a gas cycle consisting of TMA, N ₂ , H ₂ O, and N _{2 is} performed, wherein times of TMA, N ₂ , H ₂ O, and N ₂ are set to 1, 10, 1, and 10, respectively. Seconds, and in this gas cycle, the deposition rate of alumina is about 1.3 /cycle. In one embodiment, the chamber used to perform the ALD process is provided by the Instrument Technology Research Center (Taiwan), but other suitable process chambers may be used to implement the ALD process. Compared with the conventional method for forming an Al ₂ O ₃ film, for example, sputtering, chemical vapor deposition, or oxidation of a pure aluminum film, an Al ₂ O ₃ film deposited by an ALD method, Better quality. ALD is a technique that utilizes sequential gas phase reactants for deposition, which deposits ultra-thin films. By repeatedly exposing the growth surface to the reaction gas, the amount of the film deposited in each cycle can be maintained constant (i.e., fixed), and therefore, the thickness of the deposited film layer can be controlled at the level of the atomic layer. In the illustrated embodiment, the deposited Al ₂ O ₃ dielectric film has a very low leakage current, and the density of the leakage current is about 10 ^-8 A/cm ^{2 for a} film having a thickness of about 16 nm.

Next, in the illustrated example, a composite structure (ie, the substrate 100 and the multilayer epitaxial layer thereon) is formed in the vicinity of the opposite sides of an active region 109 in the III-V compound semiconductor structure. Two ohmic contacts 108 are coupled as shown in FIG. 1D. These ohmic contacts 108 are deposited by means of an electron beam gun (E-gun) in a metal selected from the group consisting of Ni, Ge, Cu, Pd, Au, and combinations thereof. In the example shown, the ohmic contact 108 is formed with Ge-Au. In addition, the metal gate electrode 110 may be formed on the gate dielectric 107 by using an electron beam gun method, and it may include a metal selected from the group consisting of Ti, Pt, Cu, Al, TaN, Au, and combinations thereof (which is The electrodes used to form the ohmic contacts 108 are not identical. In the disclosed embodiment, the gate electrode 110 is made of Ti-Au.

The embodiments disclosed herein can be applied to a Group III-V compound semiconductor wafer. Composite semiconductor structures formed in accordance with the methods of embodiments of the present invention can be used to fabricate a variety of MMICs, including SPDT switches. Suitable high-reactive electro-optical crystals (HEMTs) can be fabricated in accordance with the disclosed method embodiments, including, but not limited to, pseudo-high-reactive electro-optical crystals (PHEMT), MOS field-effect transistors (metal- Oxide-semiconductor field effect transistor (MOSFET), metal-semiconductor field effect transistor (MESFET) and modified high electron mobility transistor (MHEMT).

In a preferred embodiment, a MOS-PHEMT structure having a gate length of 0.5 μm is fabricated by the above method. In this example, this MOS-PHEMT structure is characterized by having an Al ₂ O ₃ gate dielectric of about 16 nm. The resulting switch is then evaluated by measuring leakage current, control current, and microwave frequency characteristics. The results are shown in Figure 2.

Referring to Fig. 2, the switch including the MOS-PHEMT structure of the present invention has a high tolerance to various gate biases at various potentials compared to the PHEMT structure fabricated by the conventional method (Fig. 2). At V _G = -25 V, there is almost no leakage current; however, at the same voltage, the leakage current of the switch having the conventional PHEMT structure is as high as about -0.5 mA/mm.

Figure 3 depicts the relationship between the control current of the SPDT switch and the control voltage. The SPDT switch having the MOS-PHEMT structure of the present invention exhibits a lower control current over the entire 1.5V to 5.0V test range compared to a switch fabricated using the conventional PHEMT structure.

The insertion loss and isolation of the SPDT switching elements are shown in Figure 4. The SPDT switch having the MOS-PHEMT structure of the present invention has an attenuation loss of about 0.3 dB at 2.5 GHz (control voltage = +3/0 V) and an isolation of about 33.4 dB. In addition, the RF characteristics also show that the use of the MOS-PHEMT structure of the present invention can significantly improve the isolation of the switch, indicating that the MMOSs can be fabricated using the MOS-PHEMT structure of the present invention.

The present invention has been described in detail with reference to the preferred embodiments thereof. It is to be understood that those skilled in the art can change or modify the embodiment without departing from the scope and spirit of the invention.

100. . . Substrate

101. . . The buffer layer

102. . . Non-doped InGaAs layer

103. . . Non-doped AlGaAs layer

104. . . AlAs layer

105. . . GaAs layer containing n+ type dopant

106. . . Δ-doping

107. . . Gate dielectric

108. . . Ohmic contact

109. . . Active area

110. . . Metal gate electrode

The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood.

1A to 1E are schematic cross-sectional views showing the GaAs MOS-PHEMT structure fabricated in accordance with the method of the present invention in various stages of fabrication;

Figure 2 shows the gate leakage current measured with voltage difference between (a) a conventional PHEMT device and (b) a GaAs MOS-PHEMT device fabricated in accordance with a preferred embodiment of the present invention. Situation

Figure 3 shows the control current measured by the (a) conventional PHEMT element, and (b) the GaAs MOS-PHEMT element fabricated in accordance with a preferred embodiment of the present invention. Situation; and

Figure 4 shows the variation of the attenuation loss measured with frequency on (a) a conventional PHEMT device, and (b) a GaAs MOS-PHEMT device fabricated in accordance with a preferred embodiment of the present invention. .

Claims (18)

A structure of a MOS-pseudo-high-reactive transistor (MOS-PHEMT) comprising: a substrate; a composite semiconductor on the substrate, the composite semiconductor system InGaAs, AlGaAs, InP or a combination thereof; a gate dielectric deposited over the composite semiconductor by atomic layer deposition, wherein the gate dielectric is made of any of the following materials: Al ₂ O ₃ , HfO ₂ , La ₂ O ₃ or ZrO ₂ ; a plurality of ohmic contacts coupled to the composite semiconductor; and a gate electrode disposed on the gate dielectric. The structure of claim 1 wherein the gate dielectric is Al ₂ O ₃ . The structure of claim 1 wherein the gate dielectric has a thickness between about 8 nm and about 20 nm. The structure of claim 3, wherein the gate dielectric has a thickness of about 16 nm. The structure of claim 1, wherein the ohmic contacts are made of a material selected from the group consisting of Ni, Ge, Cu, Pd, Au, and combinations thereof; and the gate electrode is selected from the group consisting of Made of materials, including Ti, Pt, Cu, Al, TaN, Au, and combinations thereof. The structure of claim 1 wherein the substrate is GaAs. The structure of claim 1, wherein the composite semiconductor comprises InGaAs and AlGaAs. The structure of claim 7, wherein the InGaAs is undoped In _0.2 Ga _0.8 As; and the AlGaAs comprises Al _0.25 Ga _0.75 As having a δ-doping therein. The structure of claim 1 wherein the structure is operable to fabricate a single stone microwave integrated circuit (MMIC) single pole double throw (SPDT) switch. A method of fabricating a MOS-PHEMT structure useful for an MMIC SPDT switch, comprising: forming a composite semiconductor on a substrate, the composite semiconductor being InGaAs, AlGaAs, InP, or a combination thereof; and atomic layer deposition at the third Forming a gate dielectric on the -V group compound semiconductor, wherein the gate dielectric is made of any one of the following materials: Al ₂ O ₃ , HfO ₂ , La ₂ O ₃ , or ZrO ₂ ; An ohmic contact, and the ohmic contacts are coupled to the III-V compound semiconductor; and a metal is applied over the gate dielectric to form a gate electrode. The method of claim 10, wherein the substrate is GaAs. The method of claim 10, wherein the step of forming a composite semiconductor comprises forming InGaAs on the GaAs and forming AlGaAs on the InGaAs. The method of claim 12, wherein the step of forming a composite semiconductor comprises forming In _0.2 Ga _0.8 As on the GaAs, and forming Al _0.25 Ga _0.75 As on the In _0.2 Ga _0.8 As, wherein the Al _0.25 Ga _0.75 As contains a δ-doping therein. The method of claim 10, wherein the step of forming a gate dielectric comprises depositing an Al ₂ O ₃ layer having a thickness between about 8 nm and about 20 nm on the composite semiconductor. The method of claim 14, wherein the step of forming a gate dielectric comprises depositing an Al ₂ O ₃ layer having a thickness of about 16 nm on the composite semiconductor. The method of claim 10, wherein the step of forming a plurality of ohmic contacts comprises depositing Ge/Au by electron gun deposition to form the ohmic contacts; and the step of applying the metal comprises applying Ti/Au to The gate is dielectrically formed to form the gate electrode. The method of claim 10, wherein the ohmic contacts are made of a material selected from the group consisting of Ni, Ge, Cu, Pd, Au, and combinations thereof; and the gate electrode is Made of materials selected from the group consisting of Ti, Pt, Cu, Al, TaN, Au, and combinations thereof. A GaAs MOS-PHEMT switch comprising the structure of claim 1 wherein the structure comprises an Al ₂ O ₃ layer having a thickness of about 16 nm and the switch has a gate having a length of about 0.5 μm.