JP2011069943A - Display device and electronic equipment - Google Patents

Abstract

An image quality of a display device is improved.
When a threshold correction preparation period for a plurality of pixels 600 connected in units of rows starts at the same time, a control transistor 670 uses a first node (ND1) based on an initialization potential (Vss) in a power supply line 410. ) Connect between 650 and the power supply line 410. As a result, the potential of the first node (ND1) 650 decreases. Next, in the threshold correction preparation period, the scanning line (WSL) 210 supplies the ON potential (Von) to the writing transistor 610 at a different timing for each row. Accordingly, the write transistor 610 is turned on, so that the potential of the first node (ND1) 650 increases. When the driving transistor is turned on by the increase in the potential of the first node (ND1) 650, the potential of the input terminal of the light-emitting element is decreased at a different timing for each row.
[Selection] Figure 14

Description

  The present invention relates to a display device, and more particularly to a display device using a light-emitting element as a pixel and an electronic apparatus including the display device.

  In recent years, development of flat self-luminous display devices using organic EL (Electroluminescence) elements as light emitting elements has been actively conducted in recent years. In the display device using the organic EL element, the electric field applied to the organic thin film is controlled by the driving transistor constituting the pixel circuit. The threshold voltage and mobility of the driving transistor vary from individual to individual. . For this reason, a process for correcting these individual differences is required.

  As a display device having a function of correcting the threshold voltage of the driving transistor, a display device having a function of correcting the threshold voltage of the driving transistor by supplying a current to the driving transistor after initializing the pixel circuit has been proposed (for example, , See Patent Document 1). In this display device, after initializing the potentials at the gate terminal and the source terminal of the driving transistor, the threshold value of the driving transistor is corrected by passing a current until the potential difference between the gate and the source reflects the threshold voltage.

JP 2008-33193 A (FIG. 3B)

  In the above-described conventional technology, it is possible to correct the variation in the threshold voltage of the drive transistor that constitutes the pixel circuit. In this case, since the power supply signal is switched, a driver for switching the power supply signal is required for each row, which increases the cost of the display device. On the other hand, it is conceivable to reduce the number of drivers by adopting a configuration in which the power supply signal is switched every plural rows.

  In such a configuration, the cathode electrode of the organic EL element is shared by all pixel circuits. For this reason, fluctuations in the potential of the anode terminal of the organic EL elements in each row when the power supply signal is switched cause fluctuations in the potential of the cathode electrode shared by all the pixel circuits via the parasitic capacitance of the organic EL elements. Therefore, in such a configuration, the potential of the cathode electrodes of the organic EL elements shared by all the pixel circuits greatly fluctuates due to the potential fluctuation of the cathode electrodes in a plurality of rows occurring simultaneously when the power supply signal is switched. The image quality will be degraded.

  Therefore, the present invention has been made in view of such a situation, and an object thereof is to improve the image quality of a display device using an organic EL element.

The present invention has been made to solve the above problems, and a first aspect thereof includes a plurality of pixel circuits arranged in a row and a power supply potential for the plurality of pixel circuits to emit light. A power supply line for supplying a low power supply potential of a low potential to the plurality of pixel circuits, and a scanning signal for supplying a video signal including video information to be displayed to the plurality of pixel circuits to the plurality of pixel circuits. Each of the plurality of pixel circuits. The scanning circuit is provided for each row, and when the low power supply potential is supplied, the scanning circuit changes the potential of the scanning signal to the on potential at a timing different from that of the other rows. Is connected between a holding capacitor that holds a voltage corresponding to the video signal, a light emitting element that emits light based on the voltage held in the holding capacitor, and the power line and one end of the holding capacitor. Above the power line A connection element that becomes conductive when a low power supply potential is supplied and lowers the potential of one end of the storage capacitor; and the video signal is written to the storage capacitor when the light emitting element emits light; A writing transistor that raises the potential of one end of the storage capacitor by becoming conductive based on the on-potential when a low power supply potential is supplied; and a gate terminal connected to the one end of the storage capacitor; When the light emitting element emits light, a current is supplied to the light emitting element according to a gate-source voltage, and the writing transistor is turned on to increase the potential of the gate terminal, thereby causing the potential of the input terminal of the light emitting element. A display device and an electronic device including a driving transistor for reducing the resistance. Thus, after the potential at one end of the storage capacitor is lowered by the connecting element, the potential at one end of the storage capacitor is increased at different timings for each row, thereby lowering the potential of the input terminal of the light emitting element.

  In the first aspect, a power supply circuit that supplies the same low power supply potential to a plurality of pixel circuits for each of a plurality of rows may be further provided. As a result, in a row sharing the same power supply line, after the potential of one end of the storage capacitor is lowered by the connecting element, the potential of one end of the storage capacitor is increased at a different timing for each row to thereby increase the potential of the input terminal of the light emitting element. It brings about the effect of lowering.

  In the first aspect, the connection element may be configured by a transistor having a drain terminal connected to the power supply line and a source terminal connected to one end of the storage capacitor. This brings about the effect that the potential of one end of the storage capacitor is lowered by the transistor. In this case, the transistor constituting the connection element may be diode-connected to the gate terminal of the transistor to the source terminal of the transistor. As a result, the potential of one end of the storage capacitor is lowered by the diode-connected transistor. In this case, the semiconductor device further includes a control circuit that supplies a connection control signal for turning on the transistor constituting the connection element to the gate terminal of the transistor, and the transistor constituting the connection element includes the connection control signal. And the potential of one end of the storage capacitor may be lowered based on the low power supply potential. This brings about the effect that the potential of one end of the storage capacitor is lowered by the transistor controlled by the connection control signal supplied from the control circuit.

  In the first aspect, the scanning circuit has a potential higher than that of a signal that makes the writing transistor non-conductive when the low power supply potential is supplied during a period in which the light emitting element emits light. A signal may be supplied to the write transistor. As a result, during the period in which the light emitting element emits light, the write transistor is brought into a non-conductive state with a signal having a higher potential than the signal for making the write transistor non-conductive when a low power supply potential is supplied. .

  ADVANTAGE OF THE INVENTION According to this invention, the outstanding effect that the image quality of the display apparatus using an organic EL element can be improved can be show | played.

It is a conceptual diagram which shows the example of 1 structure of the display apparatus used as the foundation of this invention. It is a timing chart regarding an example of the basic operation of the display apparatus 100 which is the basis of the present invention. It is a circuit diagram which shows typically the structural example of the pixel 600 used as the foundation of this invention. 4 is a timing chart regarding an example of a basic operation of the pixel 600 in the configuration of FIG. 3. It is a circuit diagram showing typically the operation state of pixel 600 corresponding to each period of TP8, TP1, and TP2. FIG. 6 is a circuit diagram schematically showing an operation state of a pixel 600 corresponding to each period of TP3 to TP5. FIG. 6 is a circuit diagram schematically showing an operation state of a pixel 600 corresponding to a period from TP6 to TP8. 10 is a timing chart showing an example of the operation of the pixel 600 in which the potential of the cathode electrode 690 decreases as the potential of the second node 660 decreases rapidly in the threshold value correction preparation period TP3 in the display device that is the basis of the present invention. 10 is a timing chart showing an example of a potential decrease of the cathode electrode 690 when a decrease in potential of the cathode electrode 690 occurs simultaneously in a plurality of pixels 600. 4 is a timing chart regarding an operation example of the display device 100 in which a potential change of a cathode electrode 690 occurs in the pixel 600 having the configuration of FIG. 3. 4 is a timing chart showing an example of the operation of the pixel 600 when light emission of the pixel 600 becomes bright due to a decrease in the potential of the cathode electrode 690 in the pixel 600 having the configuration of FIG. 3. 4 is a timing chart showing an example of the operation of the pixel 600 when the light emission of the pixel 600 becomes dark due to the potential change of the cathode electrode 690 in the pixel 600 having the configuration of FIG. 3. 13 is a diagram related to a display image displayed on the display device 100 when the potential change of the cathode electrode 690 in the pixel 600 having the configuration of FIG. 3 affects the operation of the pixel 600 as illustrated in FIGS. FIG. 3 is a circuit diagram schematically illustrating a configuration example of a pixel 600 according to the first embodiment of the present invention. 5 is a timing chart relating to an example of a basic operation of the pixel 600 according to the first embodiment of the present invention. FIG. 5 is a circuit diagram schematically showing an operation state of a pixel 600 corresponding to each of threshold correction preparation periods TP3-1 to 3-3 in the first embodiment of the present invention. 6 is a timing chart relating to an example of a potential change of the cathode electrode 690 generated due to scanning signals of a plurality of scanning lines (WSL) 211 to 213 sharing a power supply line in the first embodiment of the present invention. It is a conceptual diagram which shows one structural example of the display apparatus 100 in the 2nd Embodiment of this invention. It is a timing chart regarding an example of basic operation of pixel 600 in a 2nd embodiment of the present invention. It is a circuit diagram which shows typically the operation state of the pixel 600 each corresponding to the period of threshold value correction preparation period TP3-1 to 3-3 in the 2nd Embodiment of this invention. It is a circuit diagram which shows typically the operation state of light emission period TP8 of the pixel 600 of the 1st and 2nd embodiment of this invention in an actual circuit. It is a timing chart regarding an example of basic operation of pixel 600 in a 3rd embodiment of the present invention. This is an application example of the embodiment of the present invention to a television set. This is an application example of the embodiment of the present invention to a digital still camera. This is an example of application of the embodiment of the present invention to a notebook personal computer. This is an application example of the embodiment of the present invention to a mobile terminal device. This is an application example of the embodiment of the present invention to a video camera.

Hereinafter, modes for carrying out the present invention (hereinafter referred to as embodiments) will be described. The description will be made in the following order.
1. Display device as a basis of the present invention (display control: example of basic operation of display device by sharing power line)
2. First embodiment (display control: an example in which a control transistor is provided in a pixel)
3. Second embodiment (display control: an example in which a control auxiliary scanner for controlling a control transistor is provided)
4). Third embodiment (display control: an example in which a scanning signal of a scanning line is ternarized)
5). Application example of the present invention (display control: example of electronic equipment)

<1. Display device that is the basis of the present invention>
[Configuration example of display device]
FIG. 1 is a conceptual diagram showing a configuration example of a display device that is the basis of the present invention.

  The display device 100 includes a write scanner (WSCN: Write SCaNner) 200, a horizontal selector (HSEL: Horizontal SELector) 300, and a power supply scanner (DSCN: Drive SCaNner) 400. The display device 100 includes a pixel array unit 500 and a timing generation unit 700. The pixel array unit 500 includes a plurality of pixels 600 arranged in an n × m two-dimensional matrix.

  The display device 100 is provided with a power supply line (DSL: Drive Scan Line) 410 that connects between the pixel 600 and a power supply scanner (DSCN) 400. In addition, the display device 100 is provided with a scan line (WSL: Write Scan Line) 210 that connects between the pixel 600 and a write scanner (WSCN) 200. Further, the display device 100 is provided with a data line (DTL: DaTa Line) 310 that connects between the pixel 600 and a horizontal selector (HSEL) 300.

  The display device 100 is provided with a start pulse line (SPL) 711 and a clock pulse line (CKL: ClocK pulse Line) 721 that connect between the power supply scanner (DSCN) 200 and the timing generator 700. ing. Further, the display device 100 is provided with a start pulse line (SPL) 712, a clock pulse line (CKL) 722, and a video signal line 730 that connect the horizontal selector (HSEL) 300 and the timing generator 700, respectively. It has been. Further, the display device 100 is provided with a start pulse line (SPL) 713 and a clock pulse line (CKL) 723 that connect the write scanner (WSCN) 400 and the timing generator 700.

  The timing generation unit 700 generates a start pulse for starting the light emission of the pixel 600 and a clock pulse for synchronizing each signal for causing the pixel 600 to emit light based on the video signal displayed on the pixel 600. To do. The timing generator 700 supplies a start pulse and a clock pulse for the operation of the power scanner (DSCN) 200 to the power scanner (DSCN) 200 via a start pulse line (SPL) 711 and a clock pulse line (CKL) 721.

  Further, the timing generation unit 700 sends a start pulse and a clock pulse for the operation of the horizontal selector (HSEL) 300 to the horizontal selector (HSEL) 300 via the start pulse line (SPL) 712 and the clock pulse line (CKL) 722. Supply. The timing generation unit 700 supplies a video signal to the horizontal selector (HSEL) 300 via the video signal line 730. In addition, the timing generation unit 700 sends a start pulse and a clock pulse for the operation of the write scanner (WSCN) 400 to the write scanner (WSCN) 400 via the start pulse line (SPL) 713 and the clock pulse line (CKL) 723. Supply.

  The write scanner (WSCN) 200 scans the pixels 600 line-sequentially. The write scanner (WSCN) 200 controls the timing of writing the data signal supplied from the data line (DTL) 310 to the pixel 600 in units of rows. The write scanner (WSCN) 200 generates an ON potential for writing a data signal and an OFF potential for stopping the writing of the data signal as scanning signals. The write scanner (WSCN) 200 generates a scanning signal based on a start pulse supplied via a start pulse line (SPL) 711. The write scanner (WSCN) 200 supplies the generated scanning signal to the scanning line (WSL) 210. The write scanner (WSCN) 200 is an example of a scanning circuit described in the claims.

  The write scanner (WSCN) 200 includes drivers 201 to 205 corresponding to the respective rows of the pixels 600. The drivers 201 to 205 generate scanning signals for writing data signals supplied from the data lines (DTL) 310 to the pixels 600 in the corresponding rows. The drivers 201 to 205 supply the generated scanning signals to the scanning lines (WSL) 211 to 215, respectively.

  The horizontal selector (HSEL) 300 includes a potential of a video signal, a potential of a reference signal for performing correction (threshold correction) on a threshold voltage of a driving transistor included in the pixel 600, and a quenching signal for quenching the pixel 600. One of potential (quenching potential) is selected. The horizontal selector (HSEL) 300 switches data signals in accordance with line sequential scanning by the write scanner (WSCN) 200. The horizontal selector (HSEL) 300 generates a data signal based on a start pulse supplied via a start pulse line (SPL) 712. The horizontal selector (HSEL) 300 supplies the generated data signal to the data line (DTL) 310.

  The power supply scanner (DSCN) 400 switches between a power supply potential and an initialization potential for initializing the pixels 600 in accordance with the line sequential scanning by the write scanner (WSCN) 200 and supplies the power supply signal to the power supply line (DSL) 210 as a power supply signal. To do. The power scanner (DSCN) 400 generates a power signal based on a start pulse supplied via a start pulse line (SPL) 713. The power scanner (DSCN) 400 is an example of a power supply circuit described in the claims.

  The power supply scanner (DSCN) 400 includes drivers 401 to 403 respectively corresponding to a plurality of rows (j rows). The drivers 401 to 403 generate power supply signals for pixels 600 in a certain number of rows corresponding to the drivers 401 to 403, respectively. The drivers 401 to 403 supply the generated power supply signals to power supply lines (DSL) 411 to 413, respectively. That is, the power supply lines (DSL) 411 to 413 supply the same power supply potential to the plurality of pixels 600 for each of a plurality of rows (j rows). Note that the power supply lines (DSL) 411 to 413 are examples of the power supply lines described in the claims.

  The pixel 600 holds the potential of the video signal from the data line (DTL) 310 based on the scanning signal from the scanning line (WSL) 210 and emits light for a predetermined period according to the held potential. The pixel 600 is an example of a pixel circuit described in the claims.

  As described above, the power supply scanner (DSCN) 400 can reduce the number of drivers of the power supply scanner (DSCN) 400 by supplying the same power supply signal to the pixels 600 in a plurality of rows. Thereby, the manufacturing cost of the display apparatus 100 can be reduced.

[Example of basic operation of display device]
FIG. 2 is a timing chart relating to an example of a basic operation of the display device 100 as the basis of the present invention. Here, potential changes of the power supply lines (DSL) 411 and 412, the data line (DTL) 310, and the scanning lines (WSL) 211 to 214 are shown with the horizontal axis as a common time axis.

  The potential change of the data line (DTL) 310 is a potential change of the data signal generated by the horizontal selector (HSEL) 300. A change in potential of the power supply lines (DSL) 411 and 412 is a change in potential of the power supply signal generated by the drivers 401 and 402 in the power supply scanner (DSCN) 400.

  Scanning lines (WSL) 211 to 214 are potential changes of scanning signals generated by the drivers 201 to 204 in the write scanner (WSCN) 200, respectively. The scanning lines (WSL) 211 to 214 are supplied with at least one of an on potential (Von) and an off potential (Voff) as a scanning signal. In FIG. 2, as an example, three pulses 221 to 223 are supplied to the scanning lines (WSL) 211 to 214, respectively.

  The first pulse 221 is a pulse for applying the extinction signal potential (Vers) to the pixel 600 in order to extinguish the light emission of the pixel 600. The second pulse 222 is a pulse for applying the potential (Vofs) of the reference signal to the pixel 600 for threshold correction. The third pulse 223 is a pulse for correcting the mobility of the driving transistor constituting the pixel 600 and writing the video signal (Vsig). Further, each pulse is supplied to the scanning line (WSL2) 212 after 1H (horizontal scanning period) with respect to the scanning line (WSL1) 211. Further, although not shown here, each pulse is supplied to the scanning line one row below the scanning line (WSL2) 212 after 1H with reference to the scanning line (WSL2) 212.

  In this case, the power supply signal of the power supply line (DSL) 411 is simultaneously applied to the pixels 600 connected to the scanning lines (WSL) 211 to 213, and the power supply line (DSL) is connected to the pixels 600 connected to the scanning lines (WSL) 214. DSLj + 1) 412 is applied.

[Pixel configuration example]
FIG. 3 is a circuit diagram schematically showing a configuration example of the pixel 600 that is the basis of the present invention. The pixel 600 includes a writing transistor 610, a driving transistor 620, a storage capacitor 630, and a light emitting element 640. Here, it is assumed that the write transistor 610 and the drive transistor 620 are n-channel transistors.

  A scanning line (WSL) 210 and a data line (DTL) 310 are connected to a gate terminal and a drain terminal of the writing transistor 610, respectively. One end of the writing transistor 610 is connected to one electrode of the storage capacitor 630 and the gate terminal (g) of the driving transistor 620. Here, this connection part is referred to as a first node (ND1) 650. The power supply line (DSL) 410 is connected to the drain terminal (d) of the driving transistor 620, and the other electrode of the storage capacitor 630 and the input terminal of the light emitting element 640 are connected to the source terminal (s) of the driving transistor 620. Is done. Here, this connection part is referred to as a second node (ND2) 660. A cathode electrode 690 is connected to the output terminal of the light emitting element 640.

  The write transistor 610 writes a data signal from the data line (DTL) 310 to the storage capacitor 630 in accordance with the scanning signal of the scanning line (WSL) 210. The writing transistor 610 applies a potential of a data signal to one electrode of the storage capacitor 630 in order to apply a voltage for causing the light emitting element 640 to emit light to the storage capacitor 630.

  The write transistor 610 holds the threshold voltage in the holding capacitor 630 by threshold correction based on the potential (Vofs) of the reference signal, and then writes a voltage corresponding to the video signal. In addition, the writing transistor 610 applies an extinction signal potential (Vers) to one electrode of the storage capacitor 630. That is, the writing transistor 610 applies a quenching signal potential (Vers) to the gate terminal of the driving transistor 620 in order to stop the supply of the driving current for causing the light emitting element 640 to emit light. Note that the write transistor 610 is an example of a write transistor described in the claims.

  The drive transistor 620 outputs a drive current based on the voltage held in the holding capacitor 630 to the light emitting element 640 in accordance with the potential of the video signal in a state where the power supply potential (Vcc) is applied from the power supply line (DSL) 410. To do. In addition, the driving transistor 620 stops the supply of the driving current to the light emitting element 640 according to the potential (Vers) of the extinction signal given to the gate terminal by the writing transistor 610. The drive transistor 620 is an example of a drive transistor described in the claims.

  The storage capacitor 630 holds a voltage corresponding to the data signal provided by the write transistor 610. For example, the storage capacitor 630 holds a voltage corresponding to the video signal written by the write transistor 610. The storage capacitor 630 is an example of a storage capacitor described in the claims.

  The light emitting element 640 emits light according to the magnitude of the drive current supplied from the drive transistor 620. The light emitting element 640 can be realized by, for example, an organic EL element. The light emitting element 640 has an output terminal connected to the cathode electrode 690. From the cathode electrode 690, a cathode potential (Vcat) is supplied as a reference potential of the light emitting element. The cathode electrode 690 is a common line for all the pixels in the display device 100, and is connected to the output terminal of the light emitting element 640 of all the pixels in the display device 100. Note that the light-emitting element 640 is an example of a light-emitting element described in the claims.

  In this example, it is assumed that the write transistor 610 and the drive transistor 620 are n-channel transistors, but the present invention is not limited to this combination. Further, these transistors may be enhancement type transistors, depletion type transistors, or dual gate transistors.

[Example of basic pixel operation]
FIG. 4 is a timing chart regarding an example of a basic operation of the pixel 600 in the configuration of FIG. In this timing chart, the horizontal axis is a common time axis, the scanning line (WSL) 210, the data line (DTL) 310, the power supply line (DSL) 410, the first node (ND1) 650, the second node (ND2). The potential change of 660 and cathode electrode 690 is shown. Here, the potential change of the second node (ND2) 660 is indicated by a dotted line, and other potential changes are indicated by a solid line. In addition, the length of the horizontal axis indicating each period is a schematic one and does not indicate the ratio of the time length of each period.

  In this timing chart, the operation transition of the pixel 600 is divided into periods TP1 to TP8 for convenience. In the light emission period TP8, the light emitting element 640 is in a light emitting state. Immediately before the end of the light emission period TP8, the scanning signal of the scanning line (WSL) 210 is set to the off potential (Voff), and the data line (DTL) 310 is set to the potential of the quenching signal (Vers). The power signal of the power line (DSL) 410 is set to the power supply potential (Vcc).

  Thereafter, a new field of line sequential scanning is entered, and in the extinction period TP1, the scanning signal of the scanning line (WSL) 210 is switched from the off potential (Voff) to the on potential (Von). Accordingly, the supply of the drive current to the light emitting element 640 is stopped as the potential of the first node (ND1) 650 decreases to the potential (Vers) of the extinction signal. Under the influence of coupling by the storage capacitor 630, the potential of the second node (ND2) 660 also starts to decrease to the sum of the threshold voltage of the light emitting element 640 and the cathode potential (Vthel + Vcat).

  Next, in the extinction period TP2, the scanning signal of the scanning line (WSL) 210 is switched to the off potential (Voff). Then, since the potential of the second node (ND2) 660 decreases to the threshold potential (Vthel + Vcat) of the light emitting element 640, the light emitting element 640 is extinguished. At this time, the potential of the first node (ND1) 650 also decreases due to the influence of the coupling from the storage capacitor 630. Vthel is a threshold voltage of the light emitting element 640, and Vcat is a potential supplied from the cathode electrode 690 shown in FIG.

  Further, in the threshold correction preparation period TP3, the potential of the first node (ND1) 650 decreases to near the initialization potential (Vss). In this case, when the scanning signal of the scanning line (WSL) 210 is set near the potential (Vofs) of the reference signal of the data line (DTL) 310, the first node (ND1) is connected from the data line (DTL) 310 via the write transistor 610. ) Current leaks in the direction of 650. Therefore, in consideration of the potential of the first node (ND1) 650 in the threshold correction preparation period TP3, the off-potential (Voff) of the scanning signal of the scanning line (WSL) 210 is the first node (in the threshold correction preparation period TP3). ND1) A potential lower than that of 650 is set.

  Subsequently, in the threshold correction preparation period TP3, the power supply signal of the power supply line (DSL) 410 is switched from the power supply potential (Vcc) to the initialization potential (Vss). Accordingly, a current flows from the source terminal side to the drain terminal side in the driving transistor 620, so that the potential of the second node (ND2) 660 decreases. At this time, the potential of the first node (ND1) 650 decreases to “Vss + Vthd”. At this time, the potential of the second node (ND2) 660 also decreases. That is, the pixel 600 is initialized. Note that Vthd is a threshold voltage between the drain terminal and the gate terminal of the driving transistor 620, and is herein referred to as a threshold voltage on the drain terminal side.

  Next, in the threshold correction standby period TP4, the power signal of the power line (DSL) 410 is switched from the initialization potential (Vss) to the power supply potential (Vcc). Accordingly, a current flows through the driving transistor 620 through the other electrode of the storage capacitor 630 on the source terminal side, and the potentials of the first node (ND1) 650 and the second node (ND2) 660 are increased. However, since the gate-source voltage of the driving transistor 620 is equal to or lower than the threshold voltage, the current flowing through the driving transistor 620 is very small. For this reason, the potential rise of the first node (ND1) 650 and the second node (ND2) 660 is very small.

  Next, in the threshold correction period TP5, a threshold correction operation is performed. When the data signal of the data line (DTL) 310 is the potential (Vofs) of the reference signal, the scanning signal of the scanning line (WSL) 210 is switched from the off potential (Voff) to the on potential (Von). Thus, a voltage corresponding to the threshold voltage (Vth) of the driving transistor 620 is applied between the first node (ND1) 650 and the second node (ND2) 660. After that, in TP6, the scanning signal of the scanning line (WSL) 210 is once dropped to the off potential (Voff), and the data signal of the data line (DTL) 310 is changed from the potential of the reference signal (Vofs) to the potential of the video signal (Vsig). ).

  Next, in the writing period / mobility correction period TP7, the scanning signal of the scanning line (WSL) 210 is raised to the ON potential (Von), whereby the potential of the first node (ND1) 650 is changed to the potential (Vsig) of the video signal. ). As a result, a current flows from the driving transistor 620 to the parasitic capacitance 641 of the light emitting element 640, and charging of the parasitic capacitance 641 is started. On the other hand, the potential of the second node (ND2) 660 increases from the potential (Vofs−Vth) applied at TP5 by an increase amount (ΔV) due to mobility correction. That is, when the scanning signal of the scanning line (WSL) 210 is turned on (Von), the potential (Vsig) of the video signal is written to one electrode of the storage capacitor 630. At the same time, a potential ((Vofs−Vth) + ΔV) that is increased by the amount of increase (ΔV) by mobility correction from the potential (Vofs−Vth) applied at TP5 is applied to the other electrode of the storage capacitor 630. As a result, the storage capacitor 630 holds a voltage of “Vsig − ((Vofs−Vth) + ΔV)” as a voltage corresponding to the video signal.

  Thereafter, in the light emission period TP8, the scanning signal of the scanning line (WSL) 210 is set to the off potential (Voff). Accordingly, the light emitting element 640 emits light with luminance according to the voltage (Vsig−Vofs + Vth−ΔV) held in the storage capacitor 630. In this case, the voltage (Vsig−Vofs + Vth−ΔV) held in the storage capacitor 630 is corrected by the threshold voltage (Vth) and the amount of increase (ΔV) due to mobility correction. Therefore, the luminance of the light-emitting element 640 is not affected by variations in threshold voltage (Vth) and mobility in the driving transistor 620. Note that the potentials of the first node (ND1) 650 and the second node (ND2) 660 rise during the period up to the middle of the light emission period TP8. At this time, the potential difference (Vsig−Vofs + Vth−ΔV) between the first node (ND1) 650 and the second node (ND2) 660 is maintained.

  Although an example in which the threshold correction operation is performed once for one light emission in the light emitting element 640 has been described here, the number of threshold correction operations is not limited to this, and may be two or more. .

[Details of pixel operation status]
Next, the operation of the above-described pixel 600 will be described in detail with reference to the drawings. In the following drawings, the operation state of the pixel 600 corresponding to the period from TP1 to TP8 in the timing chart shown in FIG. 4 is shown. For convenience, the parasitic capacitance 641 of the light emitting element 640 is illustrated. Further, the writing transistor 610 is illustrated as a switch, and the scanning line (WSL) 210 is omitted.

  FIGS. 5A to 5C are circuit diagrams schematically showing the operation state of the pixel 600 corresponding to the periods TP8, TP1, and TP2. In the light emission period TP8, as shown in FIG. 5A, the power supply signal of the power supply line (DSL) 410 is set to the power supply potential (Vcc), and the drive transistor 620 supplies the drive current (Ids) to the light emitting element 640. Supply.

  Next, in the extinction period TP1, as shown in FIG. 5B, when the data signal of the data line (DTL) 310 is the potential (Vers) of the extinction signal, the scanning signal of the scanning line (WSL) 210 is turned off. Transition from the potential (Voff) to the on potential (Von). As a result, the writing transistor 610 is turned on (conductive), so that the potential of the first node (ND1) 650 is lowered to the potential (Vers) of the extinction signal. At this time, the supply of the drive current to the light emitting element 640 is stopped. Then, the potential of the second node (ND2) 660 also decreases due to the influence of the coupling via the storage capacitor 630, and further starts to decrease to the sum (Vthel + Vcat) of the threshold voltage of the light emitting element 640 and the cathode potential.

  Subsequently, in the extinction period TP2, as shown in FIG. 5C, when the scanning signal of the scanning line (WSL) 210 transitions to an off potential (Voff), the writing transistor 610 is turned off (non-conducting). Become. Here, the light-emitting element 640 is extinguished when the potential of the second node (ND2) 660 decreases to the threshold potential (Vthel + Vcat) of the light-emitting element 640. Note that the potential of the first node (ND1) 650 also decreases to follow the potential decrease of the second node (ND2) 660.

  6A to 6C are circuit diagrams schematically showing the operation state of the pixel 600 corresponding to the periods TP3 to TP5, respectively.

  Subsequent to TP2, in the threshold correction preparation period TP3, as shown in FIG. 6A, the power supply signal of the power supply line (DSL) 410 is switched from the power supply potential (Vcc) to the initialization potential (Vss). As a result, a current flows through the driving transistor 620 in the direction of the power supply line (DSL) 410, so that the potential of the second node (ND2) 660 decreases. At the same time, since the first node (ND1) 650 is in a floating state, the potential of the first node (ND1) 650 is also lowered to follow the potential drop of the second node (ND2) 660. At this time, the potential difference between the potential of the first node (ND1) 650 and the initialization potential (Vss) of the power supply line (DSL) 410 is a voltage corresponding to the threshold voltage (Vthd) on the drain terminal side of the driving transistor 620. Until this occurs, the potential of the first node (ND1) 650 decreases. That is, the potential of the first node (ND1) 650 decreases to “Vss + Vthd”. In this way, the pixel 600 is initialized.

  Next, in the threshold correction standby period TP4, as shown in FIG. 6B, the power supply signal of the power supply line (DSL) 410 is switched from the initialization potential (Vss) to the initialization potential (Vcc). As a result, a small amount of current flows through the driving transistor 620 in the direction of the other electrode of the storage capacitor 630, so that the potentials of the first node (ND1) 650 and the second node (ND2) 660 slightly increase.

  In the threshold correction period TP5, as shown in FIG. 6C, when the data signal of the data line (DTL) 310 is the potential (Vofs) of the reference signal, the scanning signal of the scanning line (WSL) 210 is turned off. Transition from the potential (Voff) to the on potential (Von). Thereby, the potential of the first node (ND1) 650 is set to the potential (Vofs) of the reference signal. At this time, if the gate-source voltage of the driving transistor 620 is larger than the threshold voltage, a current flows from the driving transistor 620 to the other electrode of the storage capacitor 630, so that the potential of the second node (ND2) 660 increases.

  The potential difference between the first node (ND1) 650 and the second node (ND2) 660 is a potential difference corresponding to the threshold voltage (Vth) between the source terminal and the gate terminal of the driving transistor 620. At this time, the potential of the second node (ND2) reaches the threshold potential (Vofs−Vth) on the source terminal side of the driving transistor 620. As a result, a voltage corresponding to the threshold voltage (Vth) of the drive transistor 620 is held in the holding capacitor 630 with reference to the potential (Vofs) of the reference signal, whereby the threshold correction operation is completed. Here, the cathode potential (Vcat) of the cathode electrode 690 and the potential (Vofs) of the reference signal are set so that current from the driving transistor 620 does not flow to the light emitting element 640.

  FIGS. 7A to 7C are circuit diagrams schematically showing the operation states of the pixels 600 corresponding to the periods TP6 to TP8, respectively.

  Following TP5, at TP6, as shown in FIG. 7A, the scanning signal on the scanning line (WSL) 210 transitions from the ON potential (Von) to the OFF potential (Voff), whereby the writing transistor 610 is turned OFF. (Non-conducting) state. Thereafter, the data signal of the data line (DTL) 310 is switched from the potential (Vofs) of the reference signal to the potential (Vsig) of the video signal. In this case, in the data line (DTL) 310, the rise of the potential (Vsig) of the video signal is moderated by the write transistors 610 in the plurality of pixels 600 connected to the data line (DTL) 310. Therefore, in consideration of the transient characteristics of the data line (DTL) 310, the writing transistor 610 is turned off until the data signal reaches the potential (Vsig) of the video signal.

  In the writing period / mobility correction period TP7 subsequent to TP6, as shown in FIG. 7B, the writing transistor 610 is turned on when the scanning signal of the scanning line (WSL) 210 transitions to the ON potential (Von). It becomes a state. As a result, the potential of the first node (ND1) 650 is set to the potential (Vsig) of the video signal. At the same time, a current flows from the driving transistor 620 to the other electrode of the storage capacitor 630, whereby the potential of the second node (ND2) 660 rises by “ΔV” from the potential (Vofs−Vth) applied at TP5. The potential difference between the first node (ND1) 650 and the second node (ND2) 660 is “Vsig−Vofs + Vth−ΔV”. Thus, the writing of the potential (Vsig) of the video signal and the adjustment of the increase amount (ΔV) by the mobility correction are performed.

  In this operation, the larger the potential (Vsig) of the video signal, the larger the current output from the driving transistor, and the greater the amount of increase (ΔV) due to mobility correction. Therefore, mobility correction according to the luminance level (the potential of the video signal) can be performed. In addition, when the potential (Vsig) of the video signal for each pixel is made constant, the amount of increase (ΔV) due to the mobility correction increases as the mobility of the driving transistor increases. For example, in a pixel where the mobility of the driving transistor is large, the amount of current flowing through the other electrode of the storage capacitor is larger than in a pixel where the mobility is small, and thus the gate-source voltage of the driving transistor is lowered accordingly. Therefore, in a pixel having a high mobility of the driving transistor, the driving current supplied to the light emitting element in the light emission period is adjusted to the same level as that of the pixel having a low mobility. In this way, variation in mobility in the drive transistor for each pixel is removed.

  Next, in the light emission period TP8, as illustrated in FIG. 7C, the writing signal 610 is turned off by the transition of the scanning signal of the scanning line (WSL) 210 to the off potential (Voff). As a result, the potential of the second node (ND2) 660 rises according to the drive current (Ids) from the drive transistor 620, and the potential of the first node (ND1) 650 also rises in conjunction with it. At this time, the potential difference (Vsig−Vofs + Vth−ΔV) between the first node (ND1) 650 and the second node (ND2) 660 is maintained by the bootstrap operation.

  Thus, after the voltage corresponding to the threshold voltage (Vth) is held in the storage capacitor 630 by the threshold correction operation, the increase amount (ΔV) due to the mobility correction operation is applied to the other electrode of the storage capacitor 630. Accordingly, variations in threshold voltage and mobility in the drive transistor 620 for each pixel 600 are canceled, so that unevenness that appears in the display image can be prevented.

  In the examples so far, the description has been made assuming an operation in an ideal state in which the parasitic capacitance 641 of the light emitting element 640 is ignored. However, in the actual circuit, the potential of the second node (ND2) 660 in the pixel 600 rapidly decreases in the threshold correction preparation period TP3. Accordingly, the potential of the cathode electrode 690 is lowered due to the influence of capacitive coupling due to the parasitic capacitance 641 of the light emitting element 640. For this reason, in such a display device 100, it is assumed that the potential of the second node (ND2) 660 in the pixels 600 in a plurality of rows decreases at the same time, so that the variation in the cathode potential at the cathode electrode 690 increases. The Next, the operation of the display device 100 when the potential supplied from the cathode electrode 690 varies will be described below with reference to the drawings.

[Example of potential change of cathode electrode generated by one pixel in actual circuit]
FIG. 8 is a timing chart showing an example of the operation of the pixel 600 in which the potential of the cathode electrode 690 decreases as the potential of the second node 660 decreases rapidly in the threshold correction preparation period TP3. Note that, here, except for the potential change supplied from the cathode electrode 690 in the threshold correction preparation period TP3, it is the same as the potential change in the operation of the pixel 600 shown in FIG. Therefore, the description here is omitted. Here, the description will be made assuming that the potential change of the cathode electrode 690 is a potential change generated by one pixel.

  In the threshold correction preparation period TP3, the power supply signal of the power supply line (DSL) 410 is switched from the power supply potential (Vcc) to the initialization potential (Vss). As a result, a current flows through the driving transistor 620 toward the drain terminal, so that the potential of the first node (ND1) 650 decreases to “Vss + Vthd”. As a result, the potential of the second node (ND2) 660 also decreases.

  At this time, the potential of the cathode electrode 690 of the pixel 600 in an ideal state is a constant potential (Vcat) because the cathode potential (Vcat) is always supplied as shown in FIG. However, the potential of the cathode electrode 690 of the pixel 600 in the actual circuit slightly decreases as the potential of the second node (ND2) 660 decreases due to the influence of capacitive coupling caused by the parasitic capacitance 641 of the light emitting element 640. Thereafter, it immediately returns to the cathode potential (Vcat) due to the influence of the potential (Vcat) supplied to the cathode electrode.

  Thus, the potential of the cathode electrode 690 of the pixel 600 in the actual circuit slightly changes under the influence of the rapid change in the potential of the second node (ND2) 660. Since the potential drop of the cathode electrode 690 in the pixel 600 is very small, the other pixels 600 sharing the cathode electrode 690 are not affected. However, when the potential decrease of the second node (ND2) 660 causing the potential decrease occurs in the plurality of pixels 600 at the same time, it may be considered that the light emission of the predetermined pixel 600 is affected.

  Next, the decrease in the potential of the cathode electrode 690 when the decrease in the potential of the cathode electrode 690 occurs simultaneously in the plurality of pixels 600 will be described with reference to the drawings.

[Example of Potential Change of Cathode Electrode Generated due to One Scan Line in Actual Circuit and Pixels Supplyed with Multiple Scan Lines Supplying Same Power Supply Potential]
FIG. 9 is a timing chart illustrating an example of a decrease in the potential of the cathode electrode 690 when a decrease in the potential of the cathode electrode 690 occurs simultaneously in the plurality of pixels 600. FIG. 9A is a timing diagram illustrating an example of a potential change of the cathode electrode 690 caused by a potential drop of the second node (ND2) 660 in the plurality of pixels 600 to which the scanning line (WSL) 211 is connected. It is a chart.

  FIG. 9B shows a cathode generated due to the potential drop of the second node (ND2) 660 in the plurality of pixels 600 to which the scanning lines (WSL) 211 to 213 to which the same power supply potential is supplied are connected. 6 is a timing chart showing an example of potential change of an electrode 690. Here, the horizontal axis represents the time axis, and the potential change of the signals of the power supply line (DSL) 411, the scanning line (WSL) 211, and the cathode electrode 690 in the threshold correction preparation period TP3 is shown. Note that the operation of the pixel 600 when the potential decrease of the cathode electrode 690 occurs is the same as the operation of the pixel 600 shown in FIG. 8, and thus description thereof is omitted here. In addition, the length of the horizontal axis which shows each period is typical, and does not show the ratio of the time length of each period.

  FIG. 9A shows the potential of the cathode electrode 690 generated due to the potential drop of the second node (ND2) 660 in the plurality of pixels 600 to which the scanning line (WSL) 211 is connected in the threshold correction preparation period TP3. Changes are shown.

  In the threshold correction preparation period TP3, the potential of the cathode electrode 690 in the pixel 600 slightly decreases under the influence of the rapid change in the potential of the second node (ND2) 660 of the pixel 600 as shown in FIG. . The scanning line (WSL) 211 supplies the same scanning signal to the plurality of pixels 600 to which the scanning line (WSL) 211 is connected. For this reason, the potential drop of the cathode electrode 690 shown in FIG. 8 occurs simultaneously in the plurality of pixels 600 to which the scanning line (WSL) 211 is connected.

  That is, the potential change of the cathode electrode 690 caused by the scanning signal supplied from the scanning line (WSL) 211 is a potential obtained by accumulating the potential changes of all the pixels 600 to which the scanning line (WSL) 211 is connected. It becomes a change. Accordingly, the potential change of the cathode electrode 690 is not so large as to affect the light emission of the other pixels 600 sharing the cathode electrode, but is larger than the potential change generated by each pixel 600. Become.

  FIG. 9B shows potential changes of the cathode electrode 690 caused by the plurality of pixels 600 to which the scanning lines (WSL) 211 to 213 are connected.

  In this case, the potential change of the cathode electrode 690 is larger than the potential change generated by each pixel 600 shown in FIG. 9A and is generated for each of the scanning lines (WSL) 211 to 213.

  In the pixel 600 configured as shown in FIG. 3, the same power supply potential is supplied for each of a plurality of rows (j rows). For this reason, the potential drop of the cathode electrode 690 caused by the plurality of pixels 600 sharing the power supply line all occurs simultaneously. Thus, the potential drop of the cathode electrode 690 generated in the scanning lines (WSL) 211 to 213 to which the power supply signal of the power supply line (DSL) 411 is supplied is all reduced by the potential of the cathode electrode 690 generated for each row. The accumulated potential drops.

  That is, as the number of scanning lines (WSL) 211 to 213 sharing the power supply line (DSL) 411 increases, the potential of the cathode electrode 690 decreases more. That is, when the number of scanning lines (WSL) 211 to 213 to which the same power supply potential is supplied is increased to a certain degree, the potential change of the cathode electrode 690 affects the operation of the other pixels 600 sharing the cathode electrode. The bigger it gets.

  Next, in the pixel 600 having the configuration shown in FIG. 3, an actual operation of the display device 100 accompanying the occurrence of a potential change of the cathode electrode 690 will be described with reference to the drawings.

[Example of potential change of cathode electrode generated in display device of actual circuit]
FIG. 10 is a timing chart regarding an operation example of the display device 100 in which the potential change of the cathode electrode 690 occurs in the pixel 600 having the configuration of FIG. Here, it is assumed that the display apparatus 100 is supplied with the power supply potential by five power supply lines (DSL) 411 to 415 that supply the same power supply potential for each of a plurality of rows (j rows). Further, here, it is assumed that the number of scanning lines (WSL) sharing the power supply line is a number that causes a potential change of the cathode electrode 690 that affects the operation of the pixel 600.

  In the pixel 600 having the configuration shown in FIG. 3, as shown in FIG. 9B, when the potential of the power supply signal of the power supply lines (DSL) 411 to 413 becomes the initialization potential (Vss), the potential of the cathode electrode 690 is reduced. A decrease occurs. For this reason, the potential at the cathode electrode 690 greatly decreases each time the power supply signals of the power supply lines (DSL) 411 to 413 become the initialization potential (Vss) in the threshold correction preparation period TP3.

  Thus, in the display device 100 in an actual circuit, the potential of the cathode electrode 690 is not constant but varies. The potential of the cathode electrode 690 greatly decreases every time the power signal of the power supply lines (DSL) 411 to 413 reaches the initialization potential (Vss). In other words, after the potential of the cathode electrode 690 greatly decreases from the cathode potential (Vcat), it returns to the cathode potential (Vcat) at regular intervals. This decrease in the potential of the cathode electrode 690 may affect the light emission of the pixel 600. Next, the operation of the pixel 600 when the potential drop of the cathode electrode 690 affects the operation of the pixel 600 will be described with reference to the drawings.

[Example of light emission of pixel due to potential change of cathode electrode]
FIG. 11 is a timing chart showing an example of the operation of the pixel 600 when the light emission of the pixel 600 becomes bright due to a decrease in the potential of the cathode electrode 690 in the pixel 600 configured as shown in FIG. Here, using the horizontal axis as a common time axis, the power supply line (DSL) 410, the data line (DTL) 310, the scanning line (WSL) 210, the second node (ND2) 660, the first node (ND1) 650, the cathode A change in potential of the electrode 690 is shown. With respect to the second node (ND2) 660 and the first node (ND1) 650, the potential change when affected by the potential change of the cathode electrode 690 in an actual circuit is not affected by the broken line and the solid line. A potential change in a simple state is indicated by a chain line. In addition, the length of the horizontal axis indicating each period is a schematic one and does not indicate the ratio of the time length of each period. Here, the operations in the periods other than the periods TP5 to TP8 are the same as the operations of the pixel 600 shown in FIG. 4, and thus the same reference numerals as those in FIG. Further, here, the operation of the pixel 600 affected by the potential drop of the cathode electrode 690 at the latter half of the threshold correction period TP5 will be described.

  Incorrect threshold voltage correction operation is performed in the threshold correction period TP5 of the pixel 600 in which light emission is brightened by the potential change of the cathode electrode 690. In the threshold correction period TP5 of the pixel 600, the first transistor (ND1) 650 and the second node (ND2) 650 are turned on by turning on the writing transistor 610 as in FIG. 4 until the potential of the cathode electrode 690 decreases. The potential increases. However, when the potential of the cathode electrode 690 starts to decrease in the latter half of the threshold correction period TP5, the potential of the second node (ND2) 660 also decreases due to capacitive coupling via the parasitic capacitance 641 of the light emitting element 640. At this time, since the potential of the reference signal (Vofs) is supplied from the data line (DTL) 310, the potential of the first node (ND1) 650 remains the potential (Vofs) of the reference signal.

  That is, the reference signal potential (Vofs) is applied to the first node (ND1) 650, and the second node (ND2) 660 is lower than the threshold potential (Vofs−Vth) on the source terminal side of the driving transistor 620. A potential is applied. As a result, the voltage between the first node (ND1) 650 and the second node (ND2) 660 becomes a voltage (Vthp) larger than the threshold voltage (Vth) in an ideal state. The threshold correction period TP5 ends while the voltage between the first node (ND1) 650 and the second node (ND2) 660 is maintained at a voltage (Vthp) greater than the threshold voltage (Vth).

  After that, in the period TP6, the potential of the first node (ND1) 650 and the potential of the second node (ND2) 660 are increased. In this period TP6, the potential of the scanning signal supplied to the scanning line (WSL) 210 is once dropped to the off potential (Voff). As a result, the first node (ND1) 650 enters a floating state. In the pixel 600 in an ideal state, since the voltage between the first node (ND1) 650 and the second node (ND2) 660 is the threshold voltage (Vth), the first node (ND1) 650 and the second node The potential of (ND2) 660 does not rise.

  On the other hand, in the pixel 600 affected by the potential change, the potentials of the first node (ND1) 650 and the second node (ND2) 660 rise. This potential increase is caused by the potential of the cathode electrode 690 becoming the cathode potential (Vcat) in addition to the potential increase based on the potential difference (Vthp) between the first node (ND1) 650 and the second node (ND2) 660. This is due to the increase in potential when returning. The potential of the first node (ND1) 650 is the potential difference (Vthp) between the first node (ND1) 650 and the second node (ND2) 660 by coupling (bootstrap operation) via the storage capacitor 630. Ascending while maintaining. That is, the first node (ND1) 650 and the second node (ND2) 660 rise by “ΔVofs” from the potential applied at TP5. Accordingly, the potential of the first node (ND1) 650 becomes higher than the potential (Vofs) of the reference signal, and the potential of the second node (ND2) 660 is the threshold potential on the source terminal side in the driving transistor 620. The potential is lower than (Vofs−Vth).

  Subsequently, in the writing period / mobility correction period TP7, the scanning signal of the scanning line (WSL) 210 is raised to the ON potential (Von), so that the potential of the first node (ND1) 650 becomes the potential of the video signal (Vsig). ). Then, the potential of the second node (ND2) 660 rises from the potential applied in TP6, similarly to the writing period / mobility correction period TP7 shown in FIG. The mobility correction in this case is an inaccurate mobility because the potential of the second node (ND2) 660 applied at TP6 is lower than the threshold potential (Vofs−Vth) on the source terminal side of the driving transistor 620. It becomes correction.

  Due to this inaccurate mobility correction, the potential of the second node (ND2) 660 increases from the potential applied in the period TP6 by an increase amount (ΔVp) due to inaccurate mobility correction. That is, when the scanning signal of the scanning line (WSL) 210 is turned on (Von), the potential (Vsig) of the video signal is written to one electrode of the storage capacitor 630. At the same time, a potential that is increased by an increase amount (ΔVp) due to inaccurate mobility correction from the potential applied in the period TP6 is applied to the other electrode of the storage capacitor 630. As a result, the holding capacitor 630 holds a voltage (Vsig − ((Vofs + ΔVofs−Vthp) + ΔVp)) larger than the voltage (Vsig − ((Vofs−Vth) + ΔV)) held in an ideal state. .

  Thereafter, in the light emission period TP8, the scanning signal of the scanning line (WSL) 210 is set to the off potential (Voff). Accordingly, the light-emitting element 640 emits light with luminance corresponding to the voltage (Vsig − ((Vofs + ΔVofs−Vthp) + ΔVp)) held in the storage capacitor 630. The voltage (Vsig − ((Vofs + ΔVofs−Vthp) + ΔVp)) held in the holding capacitor 630 is larger than the voltage (Vsig − ((Vofs−Vth) + ΔV)) held in the pixel 600 in an ideal state. . For this reason, the potential of the second node (ND2) 660 is higher than the potential of the second node (ND2) 660 in the pixel 600 in an ideal state. For this reason, the luminance of the pixel 600 affected by the potential drop of the cathode electrode 690 in the latter half of the threshold correction period TP5 is higher than the luminance when the threshold voltage (Vth) and mobility variation are corrected correctly. It becomes brightness.

  As described above, when the potential of the cathode electrode 690 is affected by the latter half of the threshold correction period TP5, the luminance of the light emission of the pixel 600 is higher than that in the ideal state. It becomes brighter.

[Example of light emission of pixels darkened due to potential change of cathode electrode]
FIG. 12 is a timing chart showing an example of the operation of the pixel 600 when the light emission of the pixel 600 becomes dark due to the potential change of the cathode electrode 690 in the pixel 600 configured as shown in FIG. Here, since the second node (ND2) 660, the first node (ND1) 650, and the cathode electrode 690 are the same as those shown in FIG. 11 except for potential changes, detailed description thereof is omitted. Here, the operation of the pixel 600 affected by the potential drop of the cathode electrode 690 at the timing immediately before the threshold correction period TP5 starts will be described.

  In the case where the light emission of the pixel 600 becomes dark due to the potential change of the cathode electrode 690, unnecessary reduction of the potentials of the second node (ND2) 660 and the first node (ND1) 650 occurs in the threshold correction standby period TP4. Until the potential of the cathode electrode 690 decreases, the potential of the first node (ND1) 650 and the second node (ND2) 660 is the initialization potential of the power supply signal of the power supply line (DSL) 410 (see FIG. 4). Vss) is maintained at a potential in the vicinity.

  However, if the potential of the cathode electrode 690 starts to decrease immediately before the threshold correction period TP5 starts, the potential of the second node (ND2) 660 also decreases due to capacitive coupling via the parasitic capacitance 641 of the light emitting element 640. At this time, the potential of the first node (ND 1) 650 decreases according to the amount of decrease in the potential of the second node (ND 2) 660 due to coupling via the storage capacitor 630. Accordingly, the potential of the first node (ND1) 650 and the potential of the second node (ND2) 660 are lower than those near the initialization potential (Vss) of the power supply line (DSL) 410.

  Subsequently, in the threshold correction period TP5, as in FIG. 4, the potentials of the first node (ND1) 650 and the second node (ND2) 660 are increased by turning on the writing transistor 610. At this time, the increase in the potential of the second node (ND2) 660 also includes the influence of the potential change when the potential of the cathode electrode 690 returns to the cathode potential (Vcat). The potential of the second node (ND2) 660 increases due to the influence of the capacitive coupling, and thus becomes a voltage higher than the threshold potential (Vofs−Vth) on the source terminal side in the driving transistor 620. That is, the potential of the reference signal (Vofs) is applied to the potential of the first node (ND1) 650, and the threshold potential (Vofs−Vth) on the source terminal side of the driving transistor 620 is applied to the second node (ND2) 660. A higher potential is applied. Thereby, the voltage between the first node (ND1) 650 and the second node (ND2) 660 becomes a voltage (Vthp) smaller than the threshold voltage (Vth) in an ideal state.

  After that, in the period TP6, the potential of the first node (ND1) 650 and the potential of the second node (ND2) 660 are increased. In this period TP6, the voltage between the first node (ND1) 650 and the second node (ND2) 660 is a voltage (Vthp) smaller than the threshold voltage (Vth) in the pixel 600 in an ideal state. Little current flows through the drive transistor 620. At this time, the potential of the second node (ND2) 660 increases based on the increase in potential when the potential of the cathode electrode 690 returns to the cathode potential (Vcat).

  Further, the potential of the first node (ND1) 650 rises while holding the potential difference (Vthp) between the first node (ND1) 650 and the second node (ND2) 660 by coupling through the storage capacitor 630. To do. That is, the first node (ND1) 650 and the second node (ND2) 660 rise by “ΔVofs” from the potential applied in the threshold correction period TP5. Accordingly, the potential of the first node (ND1) 650 becomes higher than the potential (Vofs) of the reference signal, and the potential of the second node (ND2) 660 is the threshold potential (Vofs) on the source terminal side of the driving transistor 620. -Vth).

  Subsequently, in the writing period / mobility correction period TP7, the scanning signal of the scanning line (WSL) 210 is raised to the ON potential (Von), so that the potential of the first node (ND1) 650 becomes the potential of the video signal (Vsig). ). At the same time, the potential of the second node (ND2) 660 rises from the potential applied in TP6, similarly to the writing period / mobility correction period TP7 shown in FIG.

  The mobility correction in this case is inaccurate because the potential of the second node (ND2) 660 added in the period TP6 is higher than the threshold potential (Vofs−Vth) on the source terminal side of the driving transistor 620. Mobility correction. Due to this inaccurate mobility correction, the potential of the second node (ND2) 660 increases from the potential applied in the period TP6 by an increase amount (ΔVp) due to inaccurate mobility correction. Thus, the holding capacitor 630 holds a voltage (Vsig − ((Vofs + ΔVofs−Vthp) + ΔVp)) smaller than the voltage (Vsig − ((Vofs−Vth) + ΔV)) held in an ideal state. .

  Thereafter, in the light emission period TP8, the scanning signal of the scanning line (WSL) 210 is set to the off potential (Voff). Accordingly, the light-emitting element 640 emits light with luminance corresponding to the voltage (Vsig − ((Vofs + ΔVofs−Vthp) + ΔVp)) held in the storage capacitor 630. The voltage (Vsig − ((Vofs + ΔVofs−Vthp) + ΔVp)) held in the holding capacitor 630 is smaller than the voltage (Vsig − ((Vofs−Vth) + ΔV)) held in the ideal pixel 600. . Therefore, the potential of the second node (ND2) 660 is smaller than the potential of the second node (ND2) 660 in the pixel 600 in an ideal state. As a result, the luminance of the pixel 600 affected by the decrease in the potential of the cathode electrode 690 at the timing immediately before the threshold correction period TP5 starts is more than the luminance when the variations in threshold voltage (Vth) and mobility are corrected correctly. However, it becomes low brightness.

  As described above, the luminance of the light emission of the pixel 600 affected by the potential drop of the cathode electrode 690 at the timing immediately before the threshold correction period TP5 starts is lower than the luminance in the ideal state and becomes darker. End up.

  Next, a display example of the display device 100 when the potential change of the cathode electrode 690 affects the operation of the pixel 600 as illustrated in FIGS. 11 and 12 will be described with reference to the drawings.

[Example of display on display device affected by potential change of cathode electrode]
FIG. 13 relates to a display image displayed on the display device 100 when the potential change of the cathode electrode 690 in the pixel 600 having the configuration shown in FIG. 3 affects the operation of the pixel 600 as shown in FIGS. FIG. Here, the input image input to the display device 100 is assumed to be an image that is all gray.

  The power line common areas 451 to 455 indicate respective areas displayed by the pixels 600 to which the same power signal is supplied. In the power line common areas 451 to 455, the pixel 600 having a high luminance shown in FIG. 11 is shown by a lighter color than gray, and the pixel 600 having a low luminance shown in FIG. 12 is shown by a darker color than gray. .

  As described above, the display image displayed on the display device 100 is an image in which streaks enter predetermined rows of the power supply line shared regions 451 to 455 due to the influence of the potential change of the cathode electrode 690. For this reason, the first embodiment described below is improved to reduce the potential change of the cathode electrode 690.

<2. First Embodiment>
[Pixel configuration example]
FIG. 14 is a circuit diagram schematically illustrating a configuration example of the pixel 600 according to the first embodiment of the present invention. The pixel 600 includes a control transistor 670 in addition to the configuration of the pixel 600 shown in FIG. Here, since the configuration other than the control transistor 670 is the same as that in FIG. 3, the same reference numerals as those in FIG.

  In this configuration, the control transistor 670 has a gate terminal and a source terminal connected to the source terminal of the write transistor 610 and a drain terminal connected to the power supply line (DSL) 410.

  The control transistor 670 plays a role for delaying the timing of the potential drop at the cathode electrode 690 due to the switching of the power signal. The control transistor 670 connects the first node (ND1) 650 and the power supply line (DSL) 410. Further, the control transistor 670 has its gate terminal diode-connected to its source terminal. Therefore, for example, when the potential of the first node (ND1) 650 is higher than the potential of the power supply line (DSL) 410, the control transistor 670 connects the first node (ND1) 650 and the power supply line (DSL) 410. Conduct. As a result, the control transistor 670 lowers the potential of the source terminal of the drive transistor 620. The control transistor 670 is an example of a connection element described in the claims.

[Example of basic pixel operation]
FIG. 15 is a timing chart regarding an example of a basic operation of the pixel 600 according to the first embodiment of the present invention. In this timing chart, the horizontal axis is a common time axis, the scanning line (WSL) 210, the data line (DTL) 310, the power supply line (DSL) 410, the first node (ND1) 650, the second node (ND2). The potential change of 660 and cathode electrode 690 is shown. Here, regarding the scanning line (WSL) 210 and the cathode electrode 690, the potential change in the first embodiment is indicated by a solid line, and the potential change in the conventional configuration is indicated by a chain line. In addition, the length of the horizontal axis indicating each period is a schematic one and does not indicate the ratio of the time length of each period. Further, here, the operation of the pixel 600 in the period other than the threshold correction preparation periods TP3-1 to 3-3 is the same as the operation of the pixel 600 shown in FIG. In this example, the potential change of the cathode electrode 690 is described as a potential change caused by one pixel 600.

  In the threshold correction preparation period TP3-1, the power supply signal of the power supply line (DSL) 410 is switched from the power supply potential (Vcc) to the initialization potential (Vss). As a result, the potential of the first node (ND1) 650 decreases to “Vss + Vthc” due to a current flowing from the first node (ND1) 650 to the power supply line (DSL) 410 via the control transistor 670. Here, Vthc is a voltage corresponding to the threshold voltage on the drain side in the control transistor 670. At this time, since a current flows from the second node (ND2) 660 to the power supply line (DSL) 410 via the driving transistor 620, the potential of the second node (ND2) 660 decreases to “Vy”. Note that the initialization potential (Vss) of the power supply signal of the power supply line (DSL) 410 in the threshold correction preparation periods TP3-1 to 3-3 is an example of the low power supply potential described in the claims.

  Next, in the second node potential decrease period TP3-2 of the threshold correction preparation period, the scanning signal of the scanning line (WSL) 210 is switched from the off potential (Voff) to the on potential (Von). As a result, the write transistor 610 becomes conductive, and the potential of the first node (ND1) 650 rises to “Va”. At this time, if the gate-source voltage of the driving transistor 620 is larger than the threshold voltage (Vth), the potential of the first node (ND1) 650 increases, and the direction from the second node (ND2) 660 to the power supply line (DSL) 410 Current flows through the drive transistor 620. As a result, the potential of the second node (ND2) 660 decreases to “Vss”. That is, as the potential of the gate terminal of the driving transistor 620 increases, the potential of the input terminal of the light emitting element 640 decreases to “Vss”. The decrease in the potential of the second node (ND2) 660 slightly decreases the potential of the cathode electrode 690 from the cathode potential (Vcat) by capacitive coupling via the parasitic capacitance 641 of the light emitting element 640.

  On the other hand, the potential change of the cathode electrode 690 caused by one pixel 600 in the conventional configuration indicated by the chain line decreases immediately after the threshold correction preparation period starts. Note that the on potential (Von) of the scanning signal of the scanning line (WSL) 210 in the second node potential lowering period TP3-2 of the threshold correction preparation period is an example of an on potential described in the claims.

  Next, in the threshold correction preparation period TP3-3, the scanning signal of the scanning line (WSL) 210 is switched from the on potential (Von) to the off potential (Voff). As a result, the potential of the first node (ND1) 650 decreases to “Vss + Vthc” in the same manner as the threshold correction preparation period TP3-1. At this time, the potential of the second node (ND2) 660 is transmitted to the second node (ND2) 660 by coupling via the storage capacitor 630 accompanying the decrease in the potential of the first node (ND1) 650, whereby the potential of the second node (ND2) 660 becomes “ Slightly lower than “Vss”.

  Thus, by providing the pixel 600 including the control transistor 670 with the second node potential decrease period TP3-2 in the threshold correction preparation period, the timing at which the potential of the cathode electrode 690 decreases is set to the second node potential decrease period TP3-2. Can be.

[Details of pixel operation status]
Next, the operation of the above-described pixel 600 will be described below with reference to the drawings. In the following drawings, an operation state of the pixel 600 corresponding to the threshold correction preparation periods TP3-1 to 3-3 in the timing chart shown in FIG. 15 is shown. Here, the operation state in the period other than the threshold correction preparation periods TP3-1 to 3-3 is the same as the operation state shown in FIGS. For convenience, the parasitic capacitance 641 of the light emitting element 640 is illustrated. Further, the writing transistor 610 is illustrated as a switch, and the scanning line (WSL) 210 is omitted.

  FIGS. 16A to 16C are circuit diagrams schematically showing the operation states of the pixels 600 corresponding to the threshold correction preparation periods TP3-1 to 3-3 in the first embodiment of the present invention. It is.

  In the threshold correction preparation period TP3-1, as shown in FIG. 16A, the power supply signal of the power supply line (DSL) 410 is switched from the power supply potential (Vcc) to the initialization potential (Vss). Immediately after the start of this period, since the potential of the first node (ND1) 650 is higher than the potential (Vss) of the power supply line (DSL) 410, power is supplied from the first node (ND1) 650 via the control transistor 670. A current flows through the line (DSL) 410. As a result, the potential of the first node (ND1) 650 decreases. At this time, the potential difference between the potential of the first node (ND1) 650 and the initialization potential (Vss) of the power supply line (DSL) 410 becomes a voltage corresponding to the threshold voltage (Vthc) on the drain side of the control transistor 670. Until then, the potential of the first node (ND1) 650 decreases. That is, the potential of the first node (ND1) 650 decreases to “Vss + Vthc”.

  Further, the potential of the second node (ND2) 660 also causes a current to flow in the direction of the power supply line (DSL) 410 through the driving transistor 620 when the power supply signal of the power supply line (DSL) 410 becomes the initialization potential (Vss). It drops because it flows. The speed at which this current flows is higher as the capacity of the second node (ND2) 660 is smaller. Comparing the capacitance associated with the second node (ND2) 660 and the capacitance associated with the first node (ND1) 650, the second node (ND2) 660 is accompanied by a parasitic capacitance 641 of the light emitting element 640 larger than the storage capacitor 630. Therefore, the capacity of the second node (ND2) 660 is larger. Therefore, the speed at which the potential of the second node (ND2) 660 decreases is slower than the speed at which the potential of the first node (ND1) 650 decreases.

  When the potential of the first node (ND1) 650 decreases to “Vss + Vthc”, the voltage between the potential of the first node (ND1) 650 and the power supply line (DSL) 410 is the threshold value of the drain terminal of the driving transistor 620. It becomes a voltage near the voltage “Vthd”. As a result, the potential of the second node (ND2) 660 decreases to “Vy” by being gradually decreased after being rapidly decreased.

  Next, in the second node potential decrease period TP3-2 of the threshold correction preparation period, as shown in FIG. 16B, the scanning signal of the scanning line (WSL) 210 changes from the off potential (Voff) to the on potential (Von). Can be switched to. As a result, the reference signal (Vofs) of the data signal of the data line (DTL) 310 is supplied to the first node (ND1) 650. As a result, the potential of the first node (ND1) 650 increases, so that the voltage between the first node (ND1) 650 and the power supply line (DSL) 410 increases. Therefore, a current flows from the data line (DTL) 310 to the power supply line (DSL) 410 via the control transistor 670.

  In this case, the control transistor 670 functions as a resistor connected between the power supply line (DSL) 410 and the first node (ND1) 650. Since the voltage drop occurs due to the function of the resistance of the control transistor 670, the potential of the first node (ND1) 650 is lower than the potential of the reference signal (Vofs) of the data signal of the data line (DTL) 310. Become. In this manner, the potential of the first node (ND1) 650 rises to “Va”, which is a potential lower than the potential of the reference signal (Vofs) of the data signal of the data line (DTL) 310.

  Further, due to the rise in the potential of the first node (ND1) 650, the voltage between the power supply line (DSL) 410 and the first node (ND1) 650 becomes higher than the threshold voltage (Vthd) of the driving transistor 620. For this reason, the driving transistor 620 becomes conductive, and a current flows from the second node (ND2) 660 to the power supply line (DSL) 410. As a result, the potential of the second node (ND2) 660 decreases from “Vy” to the initialization potential (Vss) of the power supply signal of the power supply line (DSL) 410. In addition, the decrease in the potential of the second node (ND2) 660 slightly decreases the potential of the cathode electrode 690 from “Vcat” due to capacitive coupling via the parasitic capacitance 641 of the light emitting element 640.

  Following the second node potential drop period TP3-2, in the threshold correction preparation period 3-3, as shown in FIG. 16C, the scanning signal of the scanning line (WSL) 210 changes from the on potential (Von) to the off potential. (Voff). As a result, the potential (Vofs) of the first node (ND1) 650 decreases to “Vss + Vthc” in the same manner as the threshold correction preparation period TP3-1. At this time, the potential of the second node (ND2) 660 slightly decreases from “Vss” due to the coupling through the storage capacitor 630 accompanying the decrease of the potential of the first node (ND1) 650.

  Next, a potential change of the cathode electrode 690 caused by scanning signals of a plurality of scanning lines sharing the power supply line in the first embodiment of the present invention will be described with reference to the drawings.

[Example of potential change of cathode electrode caused by a plurality of scanning lines supplied with the same power supply potential in the first embodiment of the present invention]
FIG. 17 is a timing chart relating to an example of potential change of the cathode electrode 690 generated due to the scanning signals of the plurality of scanning lines (WSL) 211 to 213 sharing the power supply line in the first embodiment of the present invention. is there. Here, the horizontal axis indicates the time axis, and the potential changes in the signals of the power supply line (DSL) 411, the scanning line (WSL) 211, and the cathode electrode 690 in the threshold correction preparation periods TP3-1 to 3-3 are shown. Regarding the scanning lines (WSL) 211 to 213 and the cathode electrode 690, the potential change in the first embodiment is indicated by a solid line, and the potential change in the conventional configuration is indicated by a chain line. In addition, the length of the horizontal axis which shows each period is typical, and does not show the ratio of the time length of each period.

  In the first embodiment of the present invention, the same power supply potential is supplied by the power supply line (DSL) 411 to the pixels 600 to which the scanning lines (WSL) 211 to 213 are connected. The timing at which the second node potential decrease period 3-2 of the threshold correction preparation period in the pixel 600 starts is different for each of the scanning lines (WSL) 211 to 213. For this reason, the timing at which the potential of the cathode electrode 690 decreases differs for each of the scanning lines (WSL) 211 to 213. As a result, the potential change of the cathode electrode 690 is dispersed for each scanning signal of the scanning lines (WSL) 211 to 213, so that the potential change does not affect the light emission of the pixel 600.

  As described above, in the display device 100 according to the first embodiment of the present invention, the timing at which the potential of the cathode electrode 690 decreases can be set to the second node potential decrease period TP3-2 for each scanning line. Thereby, in the first embodiment of the present invention, since the amount of fluctuation in the potential of the cathode electrode 690 can be suppressed as compared with the conventional configuration, the influence on the operation of the pixel 600 can be reduced. . That is, the display device 100 according to the first embodiment of the present invention can improve the image quality of the display device.

  Next, a display device 100 according to a second embodiment of the present invention will be described with reference to the drawings.

<3. Second Embodiment>
[Configuration Example of Display Device in Second Embodiment of the Present Invention]
FIG. 18 is a conceptual diagram showing a configuration example of the display device 100 according to the second embodiment of the present invention. The display device 100 includes a control auxiliary scanner 800 in addition to the configuration of the display device 100 shown in FIG. Further, the display device 100 is provided with a control line 810 that connects between the auxiliary control scanner 800 and the gate terminal of the control transistor 670. In addition, the display device 100 is provided with a start pulse line (SPL) 714 and a clock pulse line (CKL) 724 that connect between the auxiliary control scanner 800 and the timing generator 700. Here, the configuration other than the auxiliary control scanner 800, the control line 810, and the timing generation unit 700 is the same as that shown in FIGS. Is omitted.

  In this configuration, the control line 810 is wired for each row of the pixels 600 and connected to the gate terminal of the control transistor 670.

  The timing generator 700 supplies a start pulse and a clock pulse for the operation of the control auxiliary scanner 800 to the control auxiliary scanner 800 via the start pulse line (SPL) 714 and the clock pulse line (CKL) 724. Note that the timing generation unit 700 is the same as the timing generation unit 700 shown in FIG. 1, and thus detailed description thereof is omitted here.

  The auxiliary control scanner 800 controls the control transistor 670 in the pixel 600 to be on or off. The control transistor 670 generates a control on potential for turning on the control transistor 670 and a control off potential for turning off the control transistor 670 as control auxiliary signals. The control auxiliary scanner 800 generates a control auxiliary signal based on a start pulse supplied via a start pulse line (SPL) 714. The auxiliary control scanner 800 supplies the generated auxiliary control signal to the control transistor 670 via the control line 810. The auxiliary control scanner 800 is an example of a control circuit described in the claims.

  The control transistor 670 performs a connection between the first node (ND1) 670 and the power supply line (DSL) 410 based on a control auxiliary signal supplied from the control auxiliary scanner 800 via the control line 810. . The control transistor 670 is turned on when a control-on potential is supplied as a control auxiliary signal, and connects the first node (ND1) 670 and the power supply line (DSL) 410. The control transistor 670 is an example of a connection element described in the claims.

[Example of Basic Operation of Pixel in Second Embodiment of the Present Invention]
FIG. 19 is a timing chart regarding an example of a basic operation of the pixel 600 according to the second embodiment of the present invention. Here, in addition to the potential change shown in FIG. 15, the potential change of the control line 810 is shown. Note that, except for potential changes of the first node (ND1) 650, the second node (ND2) 660, and the control line 810, they are the same as those shown in FIG. Further, the operation during the period other than the threshold correction preparation periods TP3-1 to 3-3 is the same as the operation in the conventional configuration of the pixel 600 shown in FIG. For these reasons, the description of the operation during periods other than the threshold correction preparation periods TP3-1 to 3-3 is omitted here. Here, the description will be made assuming that the potential change of the cathode electrode 690 is a potential change generated by one pixel.

  In the threshold correction preparation period TP3-1 in the second embodiment of the present invention, the power supply signal of the power supply line (DSL) 410 is switched from the power supply potential (Vcc) to the initialization potential (Vss). At this time, current flows from the second node (ND2) 660 to the power supply line (DSL) 410, and the potential of the second node (ND2) 660 starts to decrease. Here, if the parasitic capacitance 641 of the light emitting element 640 is large, the potential of the second node (ND2) 660 gradually decreases. Further, as the potential of the second node (ND2) 660 decreases, the first node (ND1) 650 also starts decreasing. Then, at a predetermined timing, the potential of the control auxiliary signal on the control line 810 is switched from the control off potential (Voffc) to the control on potential (Vonc). The potential of the first node (ND1) 650 is reduced to the potential (Vss) of the power supply signal of the power supply line (DSL) 410 because the writing transistor 610 is in an off state. At this time, when the gate-source voltage of the driving transistor 620 becomes smaller than the threshold voltage (Vthd) of the drain terminal of the driving transistor 620, current hardly flows from the second node (ND2) 660 to the power supply line (DSL) 410. For this reason, the potential of the second node (ND2) 660 is finally lowered to “Vyy”.

  Then, after the potential of the first node (ND1) 650 drops to “Vss”, the potential of the control auxiliary signal on the control line 810 is switched from the control on potential (Vonc) to the control off potential (Voffc) at a predetermined timing. It is done. The control-on potential (Vonc) is an example of a connection control signal described in the claims.

  Next, in the second node potential lowering period TP3-2 of the threshold correction preparation period in the second embodiment of the present invention, the scanning signal of the scanning line (WSL) 210 changes from the off potential (Voff) to the on potential (Von). Can be switched to. As a result, the reference signal (Vofs) of the data signal of the data line (DTL) 310 is supplied to the first node (ND1) 650. At this time, since the control auxiliary signal of the control line 810 is the control off potential (Voffc), the current of the first node (ND1) 650 does not flow to the control transistor 670. As a result, the potential of the first node (ND1) 650 rises to “Vofs”. Based on the potential of the first node (ND 1) 650, a current flows from the second node (ND 2) 660 to the power supply line (DSL) 410 via the drive transistor 620. For this reason, the potential of the second node (ND2) 660 decreases to “Vss”.

  In addition, the decrease in the potential of the second node (ND2) 660 slightly decreases the potential of the cathode electrode 690 from “Vcat” due to capacitive coupling via the parasitic capacitance 641 of the light emitting element 640. The scanning signal of the scanning line (WSL) 210 is switched from the off potential (Voff) to the on potential (Von) at a predetermined timing after the potential of the second node (ND2) 660 decreases to “Vss”.

  Next, in the threshold correction preparation period TP3-3 in the second embodiment of the present invention, the potential of the control auxiliary signal on the control line 810 is switched from the control off potential (Voffc) to the control on potential (Vonc). As a result, the potential (Vofs) of the first node (ND1) 650 decreases to “Vss” in the same manner as in the threshold correction preparation period TP3-1. At this time, the potential of the second node (ND2) 660 slightly decreases from “Vss” due to the coupling through the storage capacitor 630 accompanying the decrease of the potential of the first node (ND1) 650.

  As described above, the second node potential lowering period TP3-2 can be set at the timing when the potential of the cathode electrode 690 is lowered by further providing the auxiliary control scanner 800 in the second embodiment of the present invention.

[Details of Operation State of Pixel in Second Embodiment of Present Invention]
Next, the operation of the above-described pixel 600 will be described below with reference to the drawings. In the following drawings, an operation state of the pixel 600 corresponding to the threshold correction preparation periods TP3-1 to 3-3 in the timing chart shown in FIG. 19 is shown. Here, the operation state during the period other than the threshold correction preparation periods TP3-1 to 3-3 is the same as the operation state shown in FIGS. For convenience, the parasitic capacitance 641 of the light emitting element 640 is illustrated. Further, the writing transistor 610 and the control transistor 670 are illustrated as switches, and the scanning line (WSL) 210 and the control line 810 are omitted.

  FIGS. 20A to 20C are circuit diagrams schematically showing the operation state of the pixel 600 corresponding to the threshold correction preparation periods TP3-1 to 3-3 in the second embodiment of the present invention. It is.

  In the threshold correction preparation period TP3-1, as shown in FIG. 20A, the power supply signal of the power supply line (DSL) 410 is switched from the power supply potential (Vcc) to the initialization potential (Vss). At this time, current flows from the second node (ND2) 660 to the power supply line (DSL) 410, and the potential of the second node (ND2) 660 starts to decrease. The decrease in the potential of the second node (ND2) 660 is gradually decreased if the parasitic capacitance 641 of the light emitting element 640 is large. Therefore, the potential of the second node (ND2) 660 is gradually decreased. As the potential of the second node (ND2) 660 gradually decreases, the first node (ND1) 650 also starts decreasing. Then, the potential of the control auxiliary signal on the control line 810 is switched from the control off potential (Voffc) to the control on potential (Vonc) at a predetermined timing. As a result, the control transistor 670 becomes conductive, and a current flows from the first node (ND1) 650 to the power supply line (DSL) 410. At this time, since the potential of the scanning signal of the scanning line (WSL) 210 is the off potential (Voff), the data signal is not supplied to the first node (ND1) 650. As a result, the potential of the first node (ND1) 650 decreases to “Vss”. That is, the control transistor 670 according to the second embodiment of the present invention sets the potential of the source terminal of the write transistor 610 based on the control on potential (Vinc) of the control auxiliary signal and the initialization potential (Vss) of the power supply signal. Reduce to "Vss".

  Further, the potential of the second node (ND2) 660 also causes a current to flow in the direction of the power supply line (DSL) 410 through the driving transistor 620 when the power supply signal of the power supply line (DSL) 410 becomes the initialization potential (Vss). It drops because it flows. The speed at which this current flows is faster as the capacity of the second node (ND2) 660 is smaller. Comparing the capacitance of the second node (ND2) 660 with the capacitance of the first node (ND1) 650, the second node (ND2) 660 has a parasitic capacitance 641 of the light emitting element 640 larger than the storage capacitor 630. Therefore, the capacity of the second node (ND2) 660 is larger. Therefore, the speed at which the potential of the second node (ND2) 660 decreases is slower than the speed at which the potential of the first node (ND1) 650 decreases.

  When the potential of the first node (ND1) 650 decreases to “Vss”, the voltage between the potential of the first node (ND1) 650 and the power supply line (DSL) 410 is the threshold value of the drain terminal of the driving transistor 620. The voltage is smaller than the voltage “Vthd”. As a result, the potential of the second node (ND2) 660 decreases to “Vyy” by stopping the decrease after rapidly decreasing. Then, after the potential of the first node (ND1) 650 decreases to “Vss”, the potential of the control auxiliary signal of the control line 810 is switched from the control on potential (Vonc) to the control off potential (Voffc) at a predetermined timing. It is done.

  Next, in the second node potential decrease period TP3-2 of the threshold correction preparation period, as shown in FIG. 20B, the scanning signal of the scanning line (WSL) 210 changes from the off potential (Voff) to the on potential (Von). Can be switched to. As a result, the reference signal (Vofs) of the data signal of the data line (DTL) 310 is supplied to the first node (ND1) 650. At this time, since the control auxiliary signal of the control line 810 is the control off potential (Voffc), no current flows through the control transistor 670. As a result, the potential of the first node (ND1) 650 rises to “Vofs”.

  Further, due to the rise in the potential of the first node (ND1) 650, the voltage between the power supply line (DSL) 410 and the first node (ND1) 650 becomes higher than the threshold voltage (Vthd) of the driving transistor 620. For this reason, the driving transistor 620 becomes conductive, and a current flows from the second node (ND2) 660 to the power supply line (DSL) 410. As a result, the potential of the second node (ND2) 660 decreases from “Vyy” to the initialization potential (Vss) of the power supply signal of the power supply line (DSL) 410.

  In addition, the decrease in the potential of the second node (ND2) 660 slightly decreases the potential of the cathode electrode 690 from “Vcat” due to capacitive coupling via the parasitic capacitance 641 of the light emitting element 640. The scanning signal of the scanning line (WSL) 210 is switched from the off potential (Voff) to the on potential (Von) at a predetermined timing after the potential of the second node (ND2) 660 decreases to “Vss”.

  Following the second node potential decrease period TP3-2, in the threshold correction preparation period 3-3, as shown in FIG. 20C, the potential of the control auxiliary signal on the control line 810 is changed from the control off potential (Voffc). It is switched to the control ON potential (Vonc). As a result, the potential (Vofs) of the first node (ND1) 650 decreases to “Vss” in the same manner as in the threshold correction preparation period TP3-1. At this time, the potential of the second node (ND2) 660 slightly decreases from “Vss” due to the coupling through the storage capacitor 630 accompanying the decrease of the potential of the first node (ND1) 650.

  As described above, in the pixel 600 according to the second embodiment of the present invention and the pixel 600 according to the second embodiment of the present invention, the timing at which the potential of the cathode electrode 690 decreases is set to the second node potential decrease period TP3-2. Can do. Note that in these pixels 600 in an actual circuit, the off potential (Voff) of the scanning signal of the scanning line (WSL) 210 is much lower than the potential of the drain terminal and the source terminal of the writing transistor 610 in the light emission period TP8. For this reason, current leakage occurs between the drain terminal and the source terminal of the writing transistor 610 because the writing transistor 610 is not completely turned off in the light emission period TP8.

[Details of Operation State of Pixel in Light-Emitting Period in First and Second Embodiments of the Present Invention]
FIG. 21 is a circuit diagram schematically showing an operation state in the light emission period TP8 of the pixel 600 according to the first and second embodiments of the present invention in an actual circuit. Here, the operation states other than the writing transistor 610 in the light emission period TP8 are the same as the operation states in the light emission period TP8 shown in FIGS. Note that, here, the off potential (Voff) of the scanning signal of the scanning line (WSL) 210 turns off the writing transistor 610 in the threshold correction preparation periods TP3-1 and 3-3, so that the first node in this period (ND1) It is assumed that the potential is lower than 650. That is, the off potential (Voff) of the scanning signal of the scanning line (WSL) 210 is in the off state of the writing transistor 610 near the initialization potential (Vss) of the power supply signal in the threshold correction preparation periods TP3-1 and 3-3. Assume that it is a potential.

  In the light emission period TP8, the writing signal 610 is turned off by the scanning signal of the scanning line (WSL) 210 being changed to the off potential (Voff). In this case, since the off potential (Voff) of the scanning signal of the scanning line (WSL) 210 is a potential near the initialization potential (Vss) of the power supply signal, the potential of the reference signal of the data signal of the data line 310 ( Vofs), which is a very low potential.

  However, the writing transistor 610 leaks because the off potential (Voff) of the scanning signal is much lower than the potential (Vofs) of the reference signal of the data signal. Due to this leakage, a current flows from the first node (ND1) 650 to the data line (310), so that the potential of the first node (ND1) 650 gradually becomes lower.

  The decrease in the potential of the first node (ND1) 650 causes the storage capacitor 630 to decrease the potential of the second node (ND1) 660. That is, the leakage of the writing transistor 610 in the light emission period TP8 makes the light emission of the pixel 600 darker than the light emission based on the video signal by lowering the potential of the second node (ND1) 660.

  As described above, in the pixel 600 according to the first and second embodiments of the present invention, the light emission luminance of the pixel 600 becomes darker than the light emission luminance based on the video signal due to the leakage of the writing transistor 610 in the light emission period TP8. End up. In order to solve the problem of current leakage of the write transistor 610 in the light emission period TP8, a third embodiment of the present invention described below is improved.

<4. Third Embodiment>
[Example of Basic Operation of Pixel in Third Embodiment of the Present Invention]
FIG. 22 is a timing chart regarding an example of a basic operation of the pixel 600 according to the third embodiment of the present invention. Here, the second embodiment of the pixel 600 shown in FIG. 15 is performed except for the potential change of the scanning line (WSL) 210, the first node (ND1) 650, and the second node (ND2) 660 in the light emission periods TP8 and TP6. The operation is the same as that in the embodiment. For this reason, description of the operation in the periods other than the light emission periods TP8 and TP6 is omitted here. Regarding the scanning line (WSL) 210 and the first node (ND1) 650, the potential change in the third embodiment is indicated by a solid line, and the potential change in the second embodiment is indicated by a chain line. Regarding the second node (ND2) 660, the potential change in the third embodiment is indicated by a broken line, and the potential change in the second embodiment is indicated by a chain line.

  Note that here, the second off potential (Voff2) of the scanning signal of the scanning line (WSL) 210 in the third embodiment is the initialization of the power supply signal of the power supply line (DSL) 310 in the second embodiment. It is assumed that the potential is the same as the potential (Vss). Further, it is assumed that the second off potential (Voff2) is the same potential as the off potential (Voff) of the scanning signal in the second embodiment. Furthermore, here, the first off potential (Voff1) of the scanning signal of the scanning line (WSL) 210 in the third embodiment is the reference of the data signal of the data line (DTL) 310 in the second embodiment. It is assumed that the potential is the same as the signal potential (Vofs).

  In the light emission period TP8 in the third embodiment, the scanning signal of the scanning line (WSL) 210 is set to the first off potential (Voff1). Accordingly, the light emitting element 640 emits light with luminance according to the voltage (Vsig−Vofs + Vth−ΔV) held in the storage capacitor 630. In this case, since the potentials of the first node (ND1) 650 and the second node (ND2) 660 are constant, the light emission luminance of the light emitting element 640 does not change until the light emission period TP8 ends. Note that the first off-potential (Voff1) of the scanning signal of the scanning line (WSL) 210 is higher than the signal that makes the writing transistor non-conductive when the low power supply potential described in the claims is supplied. It is an example of a high potential signal.

  On the other hand, in the light emission period TP8 of the actual circuit in the second embodiment indicated by the chain line, the scanning signal of the scanning line (WSL) 210 is set to the off potential (Voff). Since this off potential (Voff) is a potential near the initialization potential (Vss) of the power supply signal of the power supply line (DSL) 310, the writing transistor 610 leaks. Due to this leakage, the potential of the first node (ND1) 650 in the light emission period TP8 gradually decreases.

  Then, the potential of the second node (ND2) 660 decreases due to the coupling through the storage capacitor 630 due to the decrease of the potential of the first node (ND1) 650. That is, in the light emission period TP8 of the actual circuit in the second embodiment, the light emission of the pixel 600 becomes darker than the light emission based on the video signal due to the leakage of the writing transistor 610 in the light emission period TP8. On the other hand, in the light emission period TP8 of the second example of the second embodiment of the present invention, the writing transistor 610 does not leak, so the pixel 600 emits light based on the video signal.

  Thus, in the third embodiment of the present invention, the image quality of the display device can be improved by reducing the potential change of the cathode electrode 690 and preventing the writing transistor 610 from leaking.

  Note that in the third embodiment, the scanning signal of the scanning line (WSL) 210 is also set to the first off potential (Voff1) in the period TP6. Thereby, it is possible to prevent the potential of the first node (ND1) 650 from decreasing during the transition from the threshold correction period TP5 to the writing period / mobility correction period TP7.

  As described above, according to the embodiment of the present invention, the timing at which the potential of the cathode electrode 690 connected to the pixel 600 decreases can be set to the second node potential decrease period TP3-2. Thereby, the timing at which the potential of the cathode electrode 690 based on the second node (ND2) 660 decreases can be set to the second node potential decrease period TP3-2 for each scanning line. This suppresses a decrease in the potential of the cathode electrode 690 that affects the light emission of the pixel 600 that is caused by the pixel 600 to which the plurality of scanning lines to which the same power supply potential is supplied is connected. Can do. That is, according to the embodiment of the present invention, the image quality of the display device can be improved.

  Here, an example of the pixel 600 including the control transistor 670 has been described. However, this control transistor 670 is anything that allows the current of the source terminal of the write transistor 610 to pass through the power supply line (DSL) 410 when the potential of the source terminal of the write transistor 610 is higher than the potential of the power supply line (DSL) 410. Good. For example, instead of the control transistor 670, a diode or the like can be considered as being connected between one end of the write transistor 610 and the power supply line (DSL) 410.

  Note that the display device according to the second embodiment of the present invention has a flat panel shape and is applied to various electronic devices such as digital cameras, notebook personal computers, mobile phones, and video cameras. Can do. Further, the present invention can be applied to a display of an electronic device in any field that displays a video signal input to the electronic device or a video signal generated in the electronic device as an image or a video. Examples of electronic devices to which such a display device is applied are shown below.

<5. Application example of the present invention>
[Application example to electronic equipment]
FIG. 23 shows an application example of the embodiment of the present invention to a television set. This television set is a television set to which the embodiment of the present invention is applied. This television set includes a video display screen 11 including a front panel 12, a filter glass 13, and the like, and is manufactured by using the display device according to the embodiment of the present invention for the video display screen 11.

  FIG. 24 shows an application example of the embodiment of the present invention to a digital still camera. This digital still camera is a digital still camera to which the embodiment of the present invention is applied. Here, a front view of the digital still camera is shown above, and a rear view of the digital still camera is shown below. This digital still camera includes an imaging lens 15, a display unit 16, a control switch, a menu switch, a shutter 19 and the like, and is manufactured by using the display device in the embodiment of the present invention for the display unit 16.

  FIG. 25 shows an application example of the embodiment of the present invention to a notebook personal computer. This notebook personal computer is a notebook personal computer to which the embodiment of the present invention is applied. The notebook personal computer includes a keyboard 21 that is operated when inputting characters and the like in the main body 20, and a display unit 22 that displays an image in the main body cover. The display device according to the embodiment of the present invention is the It is manufactured by using it for the display portion 22.

  FIG. 26 shows an application example of the embodiment of the present invention to a mobile terminal device. This portable terminal device is a portable terminal device to which the embodiment of the present invention is applied. Here, the opened state of the portable terminal device is shown on the left side, and the closed state of the portable terminal device is shown on the right side. The portable terminal device includes an upper housing 23, a lower housing 24, a connecting portion (here, a hinge portion) 25, a display 26, a sub display 27, a picture light 28, a camera 29, and the like. The portable terminal device is manufactured by using the display device according to the embodiment of the present invention for the display 26 or the sub display 27.

  FIG. 27 shows an application example of the embodiment of the present invention to a video camera. This video camera is a video camera to which the embodiment of the present invention is applied. This video camera includes a main body 30, a lens 34 for photographing an object on a side facing forward, a start / stop switch 35 at the time of photographing, a monitor 36, and the like. The display device according to the embodiment of the present invention is the monitor 36. It is produced by using.

  The embodiment of the present invention is an example for embodying the present invention, and has a corresponding relationship with the invention-specific matters in the claims as described above. However, the present invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 100 Display apparatus 200 Write scanner 201-205 Driver 210-215 Scan line 300 Horizontal selector 310 Data line 400 Power supply scanner 401-403 Driver 410-413 Power supply line 500 Pixel array part 600 Pixel 610 Write transistor 620 Drive transistor 630 Retention capacity 640 Light emission Element 641 Parasitic capacitance 670 Control transistor 690 Cathode electrode 700 Timing generator 711 to 714 Start pulse line 721 to 724 Clock pulse line 730 Video signal line 800 Control auxiliary scanner 810 Control line

Claims (7)

A plurality of pixel circuits arranged in rows;
A power supply line that supplies a low power supply potential lower than a power supply potential for light emission of the plurality of pixel circuits to the plurality of pixel circuits;
A scanning signal for supplying a video signal including video information to be displayed to the plurality of pixel circuits is supplied to the plurality of pixel circuits for each row, and the scanning is performed when the low power supply potential is supplied. A scanning circuit that changes the potential of the signal to the on potential at a timing different from that of the other rows,
Each of the plurality of pixel circuits is
A holding capacitor for holding a voltage corresponding to the video signal;
A light emitting element that emits light based on the voltage held in the holding capacitor;
A connection element connected between the power supply line and one end of the storage capacitor, and becomes conductive when the low power supply potential is supplied to the power supply line, and reduces the potential of one end of the storage capacitor;
One end of the storage capacitor is written by writing the video signal to the storage capacitor when the light emitting element emits light, and becomes conductive based on the ON potential when the low power supply potential is supplied to the power supply line. A write transistor that raises the potential of
A gate terminal is connected to the one end of the storage capacitor, and when the light emitting element emits light, current is supplied to the light emitting element in accordance with a gate-source voltage, and the writing transistor becomes the conductive state, whereby the gate terminal And a drive transistor that lowers the potential of the input terminal of the light-emitting element.   The display device according to claim 1, further comprising a power supply circuit that supplies the same low power supply potential to a plurality of pixel circuits for each of a plurality of rows.   The display device according to claim 1, wherein the connection element includes a transistor having a drain terminal connected to the power supply line and a source terminal connected to one end of the storage capacitor.   The display device according to claim 3, wherein the transistor constituting the connection element diode-connects the gate terminal of the transistor to the source terminal of the transistor. A control circuit for supplying a connection control signal for turning on the transistor constituting the connection element to the gate terminal of the transistor;
The display device according to claim 3, wherein the transistor constituting the connection element lowers the potential of one end of the storage capacitor based on the connection control signal and the low power supply potential.   The scanning circuit supplies a signal having a higher potential to the writing transistor than a signal for turning off the writing transistor when the low power supply potential is supplied during a period in which the light emitting element emits light. Item 4. The display device according to Item 1. A plurality of pixel circuits arranged in rows;
A power supply line that supplies a low power supply potential lower than a power supply potential for light emission of the plurality of pixel circuits to the plurality of pixel circuits;
A scanning signal for supplying a video signal including video information to be displayed to the plurality of pixel circuits is supplied to the plurality of pixel circuits for each row, and the scanning is performed when the low power supply potential is supplied. A scanning circuit that changes the potential of the signal to the on potential at a timing different from that of the other rows,
Each of the plurality of pixel circuits is
A holding capacitor for holding a voltage corresponding to the video signal;
A light emitting element that emits light based on the voltage held in the holding capacitor;
A connection element connected between the power supply line and one end of the storage capacitor, and becomes conductive when the low power supply potential is supplied to the power supply line, and reduces the potential of one end of the storage capacitor;
One end of the storage capacitor is written by writing the video signal to the storage capacitor when the light emitting element emits light, and becomes conductive based on the ON potential when the low power supply potential is supplied to the power supply line. A write transistor that raises the potential of
A gate terminal is connected to the one end of the storage capacitor, and when the light emitting element emits light, current is supplied to the light emitting element in accordance with a gate-source voltage, and the writing transistor becomes the conductive state, whereby the gate terminal An electronic device comprising: a drive transistor that raises the potential of the light emitting element to lower the potential of the input terminal of the light emitting element.