JP2011054701A - Semiconductor device - Google Patents

Abstract

In a semiconductor device having a metal wiring to be removed by laser trimming, generation of cracks is suppressed in an element isolation region under the metal wiring.
For example, a P-type semiconductor substrate is formed with a P + type element isolation region adjacent to an N− type semiconductor layer and a LOCOS insulating film covering the P + type element isolation region. These are covered with the first interlayer insulating film 21. On the first interlayer insulating film 21, metal wirings 23A, 23B, and 23C extending in parallel are formed as fuse wirings. In the through hole 21TH of the first interlayer insulating film 21, a refractory metal layer 22 made of tungsten or the like is formed. Since the refractory metal layer 22 absorbs excess heat generated during laser trimming, cracks are less likely to occur in the first interlayer insulating film 21.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having fuse wiring connected between a plurality of electronic devices.

  Conventionally, in order to adjust the specifications and performance of a completed semiconductor device, a fuse wiring that is partially removed by laser trimming or the like is connected between a plurality of electronic devices of the semiconductor device.

  For example, as shown in FIG. 9, each fuse wiring is constituted by a plurality of metal wirings 123A and 123B extending in parallel on a first interlayer insulating film 121 extending from a formation region of an electronic device (not shown). These metal wirings 123A and 123B are made of a metal material used for the multilayer wiring, for example, aluminum, and are covered with a second interlayer insulating film 124 extending from the formation region of the electronic device. The metal wirings 123A and 123B are formed to overlap with a LOCOS (Local Oxidation of Silicon) insulating film 113 on a P + type element isolation region 112 included in a P type semiconductor substrate 110, for example. The semiconductor substrate 110 includes, for example, an N− type semiconductor layer (not shown) adjacent to the P + type element isolation region 112.

  A part of a specific metal wiring, for example, the metal wiring 123A is vaporized by laser irradiation or the like, and the fuse wiring made of the metal wiring 123A is disconnected.

JP 2008-177270 A JP 2004-103960 A JP 2006-041257 A

  When laser trimming the metal wiring 123A formed as the fuse wiring, as shown in FIG. 10, a part of the metal wiring 123A irradiated with the laser is vaporized and removed. At this time, in the region where the metal wiring 123A was originally formed, that is, in the vicinity of the bottom of the opening 124A, the metal wiring 123A is released from the first interlayer insulating film 121 to a part of the element isolation region 112 when vaporized. Due to the heat generated, the crack 112C is generated. The crack 112 </ b> C generated in the element isolation region 112 may cause a leak current between the element isolation region 112 and an N− type semiconductor layer (not shown) adjacent thereto.

  The present invention has been made in view of the above problems, and its main features are as follows.

  A semiconductor device of the present invention includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a fuse wiring made of a metal wiring formed on the first insulating film, and a second covering the fuse wiring. An insulating film and a refractory metal layer that penetrates the first insulating film and that is spaced from both ends of the fuse wiring in the planar direction of the semiconductor substrate and extends along the fuse wiring.

  In the semiconductor device of the present invention having the above structure, the refractory metal layer is composed of a plurality of columnar bodies, and each columnar body is spaced apart from each other in the planar direction of the semiconductor substrate, with the first insulating film interposed therebetween. Insulated from each other.

  The semiconductor device according to the present invention is characterized in that, in the above structure, the metal wiring constituting the fuse wiring is made of a metal material containing aluminum.

  In the semiconductor device of the present invention having the above structure, the semiconductor substrate includes an element isolation region made of the same first conductivity type impurity diffusion layer as the semiconductor substrate, and a second conductivity type semiconductor layer adjacent to the element isolation region. The fuse wiring is formed so as to overlap with the element isolation region in the planar direction of the semiconductor substrate.

  Further, in the semiconductor device of the present invention having the above structure, a second conductivity type impurity diffusion layer surrounded by the first conductivity type impurity diffusion layer is formed on the surface in the element isolation region. It is characterized by being formed so as to overlap with the second conductivity type impurity diffusion layer in the planar direction of the semiconductor substrate.

  According to the present invention, when a metal wiring formed as a fuse wiring on a first insulating film (for example, an interlayer insulating film) is subjected to laser trimming, cracks extending from the first insulating film to a part of a semiconductor substrate are prevented. Occurrence can be suppressed.

1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view showing the vicinity of fuse wiring of the semiconductor device of FIG. 1. It is sectional drawing along the AA line of FIG. FIG. 2 is a plan view showing the vicinity of fuse wiring of the semiconductor device of FIG. 1. It is sectional drawing along the AA line of FIG. It is sectional drawing which shows the modification of FIG. It is a top view which shows the semiconductor device by the 2nd Embodiment of this invention. It is sectional drawing which shows the modification of the 1st and 2nd embodiment of this invention. It is sectional drawing which shows the fuse wiring by a prior art example. It is sectional drawing which shows the fuse wiring by a prior art example.

[First Embodiment]
A semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic circuit diagram showing a configuration example of this semiconductor device. In the semiconductor device 1, a circuit 2 including a plurality of electronic devices (not shown) is formed. In this circuit 2, in order to adjust the output voltage Vout output from the output terminal 3, for example, a plurality of resistance elements 5A, 5B, 5C are connected in parallel via fuse wirings 4A, 4B, 4C. Yes. Then, in the semiconductor device completed with such a configuration, if necessary, the output voltage Vout is adjusted by changing the resistance value by disconnecting any of the fuse wirings 4A, 4B, and 4C by laser trimming. can do.

  Note that the semiconductor device of the present invention is not limited to the configuration example of FIG. 1, and a fuse wiring is connected to an arbitrary electronic device or signal line, for example, a gate line of a transistor included in the circuit 2. (Not shown). An arbitrary number of fuse wirings 4A, 4B, and 4C may be arranged. In the present embodiment, a configuration example in which three fuse wirings 4A, 4B, and 4C are arranged is shown.

  Hereinafter, detailed configurations of the fuse wirings 4A, 4B, and 4C formed in the semiconductor device 1 will be described with reference to the drawings. FIG. 2 is a plan view partially showing the vicinity of the fuse wirings 4A, 4B, 4C in the semiconductor device 1 of FIG. FIG. 3 is a cross-sectional view taken along line AA in FIG. For convenience of explanation, in FIG. 2 and FIG. 3, illustrations are omitted except for the main components.

  As shown in FIGS. 2 and 3, for example, an N− type semiconductor layer 11 is formed on a P type semiconductor substrate 10 by an epitaxial growth method. Further, in the semiconductor substrate 10, a semiconductor layer made of an impurity diffusion layer of the same conductivity type as the semiconductor substrate 10, for example, a P + type, is formed as the element isolation region 12 that electrically isolates the semiconductor layer 11. The semiconductor layer 11 and the element isolation region 12 are both constituent elements included in the semiconductor substrate 10, but are referred to with individual reference numbers for the sake of clarity.

  On the element isolation region 12, for example, a LOCOS insulating film 13 is formed via an inversion prevention layer (not shown), and an insulating film 14 covering the semiconductor layer 11 extends on both sides thereof. The LOCOS insulating film 13 and the insulating film 14 are covered with a first interlayer insulating film 21. The first interlayer insulating film 21 is an interlayer insulating film used in a laminated structure such as a multilayer wiring of an electronic device (not shown) included in the circuit 2 and is made of a single layer or two or more layers of insulating films.

  A plurality of through holes 21TH are formed in the first interlayer insulating film 21. These through holes 21TH are formed so as to be separated from each other by a predetermined distance in the planar direction of the semiconductor substrate 10 and their longitudinal directions extend in parallel or substantially parallel to each other.

  A refractory metal layer 22 is formed in each through hole 21TH. The refractory metal layer 22 has a melting point higher than that of a metal material used for the multilayer wiring structure of the semiconductor device 1, for example, aluminum, and is preferably made of tungsten or a metal material containing tungsten. The width of the refractory metal layer 22 in the direction orthogonal to the longitudinal direction is, for example, about 0.2 μm to 0.4 μm.

  On the first interlayer insulating film 21, a plurality of metal wirings 23A, 23B, and 23C extend in parallel with each other as the plurality of fuse wirings 4A, 4B, and 4C in FIG. The longitudinal directions of these metal wirings 23A, 23B, and 23C are separated from the through hole 21TH in which the refractory metal layer 22 is formed and extend in parallel or substantially in parallel. For example, one end of each of the metal wirings 23A, 23B, and 23C is connected to an electronic device included in the circuit 2 of FIG. 1 through the contact (not shown), and the other end is connected to the output terminal 3. Connected to the resistance elements 5A, 5B, 5C (not shown). The metal wirings 23A, 23B, and 23C are made of a metal material used for the multilayer wiring structure of the semiconductor device 1, for example, aluminum or a metal material containing aluminum.

  In the planar direction of the semiconductor substrate 10, the width in the direction orthogonal to the longitudinal direction of the metal wirings 23A, 23B, and 23C is, for example, about 1 μm, and the pitch of each metal wiring 23A, 23B, 23C is, for example, about 5 μm to 10 μm. .

  In the description of FIG. 2 to FIG. 8, the fuse wirings 4A, 4B, and 4C of FIG. 1 are described as being unified with the metal wirings 23A, 23B, and 23C.

  The first interlayer insulating film 21 and the metal wirings 23A, 23B, and 23C are covered with the second interlayer insulating film 24. The second interlayer insulating film 24 is an interlayer insulating film used for a laminated structure such as a multilayer wiring of an electronic device (not shown) included in the circuit 2 and is formed of a single layer or two or more layers of insulating films. When the second interlayer insulating film 24 is composed of two insulating films, for example, an SOG (Spin on Glass) film and a TEOS (Tetra Ethyl Ortho Silicate) film are stacked in this order from the lower layer.

  Hereinafter, laser trimming in the semiconductor device having the above configuration will be described with reference to the drawings. FIG. 4 is a plan view when a specific metal wiring, for example, the metal wiring 23A, among the plurality of metal wirings 23A, 23B, and 23C formed as fuse wiring in this semiconductor device is laser-trimmed, and FIG. It is sectional drawing along the AA of 4. 4 and 5 show the same region as in FIGS. 2 and 3, and illustrations are omitted except for the main components.

  As shown in FIGS. 4 and 5, at the time of laser trimming, for example, spot irradiation with a diameter of about 4 μm from the surface side of the second interlayer insulating film 24 toward a part of the metal wiring 23A is 1 μJ. Laser irradiation is performed with an output of (joule) to about 1.6 μJ. A part of the metal wiring 23A is vaporized and removed by this laser irradiation. At this time, part of the heat released by the vaporization of the metal wiring 23 </ b> A is transmitted to the refractory metal layer 22 penetrating the first interlayer insulating film 21 as extra heat. And since the heat absorption rate of the refractory metal layer 22 is high, the excess heat is absorbed by the refractory metal layer 22.

  Therefore, the excess heat is less likely to be accumulated in the first interlayer insulating film 21 below the metal wiring 23A, that is, in the vicinity of the bottom of the opening 24A, and in the lower layers, that is, the LOCOS insulating film 13 and the element isolation region 12. It becomes difficult to be transmitted. Thereby, cracks from the first interlayer insulating film 21 to a part of the element isolation region 12 are less likely to occur. Therefore, as in the conventional example, it is possible to suppress the occurrence of a crack current in the P + type element isolation region 12 and a leak current between the element isolation region 12 and the N− type semiconductor layer 11 adjacent thereto as much as possible. In addition, the yield of the semiconductor device can be improved.

  Furthermore, since the metal wiring 23A has a lower melting point than that of a fuse wiring made of another material, for example, a polysilicon layer, it can be vaporized by weak output laser irradiation. Heat is absorbed by the refractory metal layer 22. For this reason, the heat and pressure of the gas generated when the metal wiring 23A is vaporized is suppressed to be small, and the second interlayer insulating film 24 on the metal wiring 23A and the other metal wirings 23B and 23C adjacent thereto is more than necessary. In other words, it is not deformed or removed in a wide range. That is, the opening 24A of the second interlayer insulating film 24 opened by laser trimming is formed as small as possible.

  Note that the shape of the opening 24A of the second interlayer insulating film 24 is not limited to the shape illustrated in the actual laser trimming, and may be various shapes. Here, the shape of the opening 24A is schematically illustrated in a simplified manner.

  In order to reduce the opening 24A of the second interlayer insulating film 24 more reliably during laser trimming, as a modification of FIG. 3, as shown in the sectional view of FIG. 6, the second interlayer insulating film 24 is used. A plurality of through holes 24TH may be formed, and another high melting point metal layer 25 similar to the high melting point metal layer 22 may be formed in each through hole 24TH. The through hole 24TH and the refractory metal layer 25 are separated from the metal wirings 23A, 23B, and 23C in the planar direction of the semiconductor substrate 10 and extend in parallel or substantially parallel to the longitudinal direction of the metal wirings 23A, 23B, and 23C. Formed. In the example of FIG. 6, the two refractory metal layers 22 and 25 overlap each other in the planar direction of the semiconductor substrate 10, but the two refractory metal layers 22 and 25 do not necessarily overlap each other, Each may be formed with a different pattern.

  With this configuration, part of the heat released by vaporizing the metal wiring 23 </ b> A by laser irradiation is transmitted as extra heat to the refractory metal layer 25 penetrating through the second interlayer insulating film 24. Since the heat absorption rate of the refractory metal layer 25 is high, the excess heat is absorbed by the refractory metal layer 25. Most of the heat absorbed by the refractory metal layer 25 is released from the exposed surface of the refractory metal layer 25, that is, the portion exposed at the opening of the through hole 24 TH of the second interlayer insulating film 24.

  For this reason, the heat and pressure of the gas generated when the metal wiring 23A is vaporized is suppressed to be small, and the second interlayer insulating film 24 on the metal wiring 23A and the other metal wirings 23B and 23C adjacent thereto is more than necessary. The possibility of deformation or removal in a wide range is reduced. Of course, the excess heat is absorbed by the two high-melting point metal layers 22 and 25, so that cracks from the first interlayer insulating film 21 to the element isolation region 12 are further less likely to occur.

  Further, although not shown, another insulating film may be formed on the second interlayer insulating film 24, but through holes similar to the through holes 21TH and 24TH are formed in the insulating film. A refractory metal layer similar to the refractory metal layers 22 and 25 may be formed in the hole. Even in this configuration, the same effect as described above can be obtained.

[Second Embodiment]
In the first embodiment, cracks in the element isolation region 12 can be suppressed at the time of laser trimming. However, the characteristics of the materials of the first interlayer insulating film 21 and the second interlayer insulating film 24, the laser Depending on the irradiation conditions, a crack is generated in the first interlayer insulating film 21 in the vicinity of the bottom of the opening 24A due to heat released when the metal wiring 23A is vaporized, and the metal wiring 23A vaporized in the crack. May flow in. The crack extends between each end 23T of the metal wiring 23A remaining after laser trimming (that is, the portion not irradiated with laser) and the refractory metal layer 22, and provides an electrical conduction path therebetween. May be configured. If a plurality of cracks are generated, the two ends 23T of the metal wiring 23A, which would normally be disconnected as the fuse wiring 4A, may be conducted through the crack and the refractory metal layer 22.

  In order to cope with this problem, as a second embodiment of the present invention, the refractory metal layer 22 in the first embodiment comprises a plurality of columnar bodies as shown in the plan view of FIG. They may be spaced apart from each other in the ten plane directions and insulated from each other through the first interlayer insulating film 21. FIG. 7 shows a state in which a part of the metal wiring 23A is removed by laser trimming in the configuration of FIGS. Note that the configuration of the refractory metal layer 22 formed of such a columnar body may be applied to the refractory metal layer 25 of the second interlayer insulating film 24 in FIG.

  According to this configuration, even if a plurality of cracks 21C are generated so as to connect with the refractory metal layer 22 through the first interlayer insulating film 21, the plurality of refractory metal layers 22 made of columnar bodies are respectively Since these are insulated from each other through the first interlayer insulating film 21, the cracks 21C are hardly electrically connected to each other. That is, the possibility that the two ends 23T of the disconnected metal wiring 23A are electrically connected via the plurality of cracks 21C and the refractory metal layer 22 can be extremely reduced.

  In the first embodiment, in addition to the problem of the crack 21C generated in the first interlayer insulating film 21, the second interlayer is caused by the heat and pressure of the gas vaporized by the metal wiring 23A during laser trimming. A part of the insulating film 24 may be removed in the vicinity of the bottom of the opening 24A, and the residue of the metal wiring 23A may scatter to the refractory metal layer 22 (not shown).

  The residue of the metal wiring 23A may extend to a plurality of locations so as to electrically connect the ends 23T of the metal wiring 23A remaining after the laser trimming and the refractory metal layer 22. In this case, there is a possibility that the two ends 23T of the metal wiring 23A that should be disconnected are electrically connected to the residue of the metal wiring 23A via the refractory metal layer 22. Also in this case, according to the present embodiment, the refractory metal layers 22 made of columnar bodies are arranged so as to be insulated from each other, so that the two ends of the metal wiring 23A are the same as in the case of the crack 21C. The possibility that 23T conducts is extremely low. The configuration and effects other than the refractory metal layer 22 are the same as those in the first embodiment.

  Needless to say, the present invention is not limited to the above-described embodiment, and modifications can be made without departing from the scope of the invention.

  For example, in the first embodiment, the provision of the refractory metal layer 22 makes it difficult for cracks to occur in the element isolation region 12, and leakage current between the P + type element isolation region and the N− type semiconductor layer 11. However, in order to further enhance the deterrent effect, it may be configured as shown in the sectional view of FIG. That is, on the surface of the P + type element isolation region 12 and overlapping with the plurality of metal wirings 23A, 23B, and 23C, as an impurity diffusion layer having a conductivity type opposite to the element isolation region 12, for example, N + type impurity diffusion Layer 19 is formed. The N + type impurity diffusion layer 19 is formed shallower than the entire element isolation region 12 in the thickness direction of the semiconductor substrate 10, and smaller than the entire width of the element isolation region 12 in the planar direction of the semiconductor substrate 10. That is, the periphery and the lower side of the N + type impurity diffusion layer 19 are surrounded by the P + type element isolation region 12.

  With this configuration, the heat released by the vaporization of the metal wiring 23A during laser trimming is mainly transmitted to the N + type impurity diffusion layer 19 in a region overlapping with the metal wiring 23A, but the element isolation surrounding the periphery and the lower part thereof. Since it hardly transmits to the region 12, cracks are hardly generated in the element isolation region 12. Further, cracks due to heat released by vaporization of the metal wiring 23A are less likely to occur in the N + type impurity diffusion layer 19 than in the P + type element isolation region 12, so that cracks are also generated in the N + type impurity diffusion layer 19. It becomes difficult to occur. Therefore, in the first embodiment, the leakage current between the element isolation region 12 and the N− type semiconductor layer 11 can be suppressed more reliably. This configuration can also be applied to the second embodiment.

  In the first and second embodiments, the metal wirings 23A, 23B, and 23C constituting the fuse wiring are all formed so as to overlap the element isolation region 12. However, the element isolation region is partially formed. 12 may be formed so as to overlap with 12 or may be formed in a region that does not overlap at all.

  In the first and second embodiments, the metal wirings 23A, 23B, and 23C functioning as the fuse wirings 4A, 4B, and 4C are formed separately from the electronic devices of the circuit 2 and the resistance elements 5A, 5B, and 5C. However, the present invention is not limited to this. That is, the present invention is also applicable to a case where the metal devices 23A, 23B, and 23C functioning as the fuse wires 4A, 4B, and 4C are included in some of the components of the electronic device and the resistive elements 5A, 5B, and 5C of the circuit 2. Is done. For example, when part of the resistance elements 5A, 5B, and 5C itself is composed of metal wirings 23A, 23B, and 23C, the metal wirings 23A, 23B, and 23C are used as fuse wirings 4A, 4B, and 4C for laser trimming. It should be the target.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Circuit 3 Output terminal 4A, 4B, 4C Fuse wiring 5A, 5B, 5C Resistance element 10,110 Semiconductor substrate 11 Semiconductor layer 12,112 Element isolation region 13,113 LOCOS insulating film 14 Insulating film 19 N + type impurity diffusion Layers 21, 121 First interlayer insulating film 21TH Through hole 22 Refractory metal layers 23A, 23B, 23C, 123A, 123B Metal wiring 24, 124 Second interlayer insulating film

Claims (5)

A semiconductor substrate;
A first insulating film formed on the semiconductor substrate;
Fuse wiring composed of metal wiring formed on the first insulating film;
A second insulating film covering the fuse wiring;
A semiconductor device comprising: a refractory metal layer that penetrates the first insulating film and extends along the fuse wiring so as to be separated from both ends of the fuse wiring in a planar direction of the semiconductor substrate.   The refractory metal layer is composed of a plurality of columnar bodies, and each columnar body is spaced apart from each other in the planar direction of the semiconductor substrate, and is insulated from each other through the first insulating film. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the metal wiring constituting the fuse wiring is made of a metal material containing aluminum. The semiconductor substrate includes an element isolation region composed of an impurity diffusion layer of the same first conductivity type as the semiconductor substrate, and a second conductivity type semiconductor layer adjacent to the element isolation region,
4. The semiconductor device according to claim 1, wherein the fuse wiring is formed so as to overlap with the element isolation region in a planar direction of the semiconductor substrate. A second conductivity type impurity diffusion layer surrounded by the first conductivity type impurity diffusion layer is formed on a surface in the element isolation region,
5. The semiconductor device according to claim 4, wherein the fuse wiring is formed so as to overlap the impurity diffusion layer of the second conductivity type in a planar direction of the semiconductor substrate.

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