JP2011044478A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

An object of the present invention is to reduce the warpage of a semiconductor device due to thermal expansion and the damage of an external electrode, thereby improving the reliability of the semiconductor device.
A semiconductor chip provided with an electrode pad on one side; a sub-wiring substrate on which a connection pad is provided on one side; a connection member for electrically connecting the electrode pad and the connection pad; A sub-wiring board 6 is mounted on one surface, and a main wiring board 7 provided with external terminals 11 that are electrically connected to connection pads 6a of the sub-wiring board 6 is provided, covering the entire outer periphery of the semiconductor chip 5, And a sealing resin material 9 for fixing the semiconductor chip 5 on one surface side of the main wiring board 7. The sub wiring board 6 is located between the main wiring board 7 and the semiconductor chip 5 in the thickness direction of the main wiring board 7.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a wiring board and a method for manufacturing the same.

  Conventionally, a BGA (Ball Grid Array) type semiconductor device has a wiring board having a plurality of connection pads on one surface and a plurality of lands electrically connected to the connection pads on the other surface, and one surface of the wiring substrate. A semiconductor chip mounted on the semiconductor chip, a wire for electrically connecting the electrode pad of the semiconductor chip and the connection pad of the wiring board, a sealing body made of an insulating resin covering at least the semiconductor chip and the wire, and a land of the wiring board And external terminals (solder balls) provided on the board. Such semiconductor devices related to the present invention are described in Patent Documents 1 and 2, for example.

  For example, Patent Document 3 discloses a semiconductor device including a multichip module substrate on which a semiconductor chip is mounted, and a sub-substrate that is electrically connected to the semiconductor chip via a wire. In this semiconductor device, a sub substrate to which a semiconductor chip is electrically connected is mounted on a multichip module substrate.

Japanese Patent Laid-Open No. 2001-44229 (FIG. 7) Japanese Patent Laying-Open No. 2001-44324 (FIG. 7) JP-A-11-297927 (FIG. 1)

  By the way, in the structure of patent document 1 and 2 mentioned above, since the semiconductor chip is being fixed on the wiring board with an adhesive or the like, stress caused by the difference in thermal expansion coefficient between the semiconductor chip and the wiring board occurs. There is a risk of reducing the reliability of the semiconductor device.

  Further, in the configurations of Patent Documents 1 and 2, since the semiconductor chip is bonded and fixed on the wiring board, there are an area where the semiconductor chip is mounted on the wiring board and an area where the semiconductor chip is not present on the wiring board. There is a problem that stress concentrates at the four corners of the boundary, particularly the outer periphery of the semiconductor chip. Due to such stress concentration, external terminals (solder balls) arranged below the four corners of the semiconductor chip are damaged, and the semiconductor device is mounted on the mounting board at the time of secondary mounting. Reliability may be reduced.

  Further, in Patent Documents 1 and 2, since the semiconductor chip is bonded and fixed on the wiring board, there is a problem in that the semiconductor device is warped due to a difference in thermal expansion coefficient between the semiconductor chip and the wiring board. Furthermore, depending on the state of the warp generated in the semiconductor device, the mounting accuracy of the semiconductor device may be deteriorated, or a connection failure between the mounting substrate and the external terminal may occur.

  Further, in Patent Document 3, a part of a semiconductor chip mounted on a wiring board, and a gap between the semiconductor chip and the wiring board are exposed without being covered with a sealing resin. For this reason, when a DRAM (Dynamic Random Access Memory) is used as a semiconductor chip, the refresh characteristics may be deteriorated due to the difference in stress due to the difference in thermal expansion of the sealing resin around the semiconductor chip. It was.

  Further, in Patent Document 3, since a part of the semiconductor chip is not covered with the sealing resin, there is a possibility that the moisture resistance of the semiconductor device is lowered and the mechanical strength of the semiconductor device is lowered.

  The present invention solves the above-described problems.

  According to one aspect of the semiconductor device of the present invention, a semiconductor chip provided with an electrode pad on one surface, a sub-wiring substrate provided with a connection pad on one surface, and a connection for electrically connecting the electrode pad and the connection pad. A main wiring board on which a sub wiring board is mounted on one side and provided with external terminals that are electrically connected to connection pads of the sub wiring board; and a main wiring board that covers the entire outer periphery of the semiconductor chip. And a fixing material for fixing the semiconductor chip to the one surface side. The sub wiring board is located between the main wiring board and the semiconductor chip in the thickness direction of the main wiring board.

  The semiconductor device according to the present invention configured as described above is configured such that a fixing material is disposed between one surface of the main wiring substrate and the semiconductor chip, and the semiconductor chip is not directly fixed on one surface of the main wiring substrate. Yes. With this configuration, the stress caused by the difference in thermal expansion coefficient between the semiconductor chip and the main wiring board is reduced, and the warpage of the semiconductor device is reduced. Further, with this configuration, the stress acting on the external terminals arranged in the vicinity of the outer periphery of the semiconductor chip is reduced, so that damage to the external terminals is reduced.

  In the semiconductor device according to the present invention, the entire outer periphery of the semiconductor chip, that is, the entire outer peripheral surface of the semiconductor chip is covered with the fixing material, so that the moisture resistance and mechanical strength of the semiconductor device are improved. Further, since the entire outer peripheral surface of the semiconductor chip is covered with the fixing material, the stress applied to the semiconductor chip due to the thermal expansion of the fixing material can be applied uniformly around the semiconductor chip. Therefore, the reliability of the semiconductor device is improved.

  As described above, according to the present invention, it is possible to reduce the occurrence of warpage in the semiconductor device due to thermal expansion and the breakage of the external electrode, and improve the reliability of the semiconductor device.

It is a top view which notches and shows a part of semiconductor device of a 1st Example. It is sectional drawing which shows the semiconductor device of a 1st Example. In the manufacturing method of the semiconductor device of the 1st example, it is a sectional view for explaining the process of electrically connecting a semiconductor chip and a sub wiring board using a mounting base. It is a perspective view which shows the structure by which the semiconductor chip and the subwiring board were connected via the wire. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device of a 1st Example. It is sectional drawing which shows the semiconductor device of a 2nd Example. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device of a 2nd Example.

  Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view showing a BGA type semiconductor device according to the first embodiment with a part thereof cut away. FIG. 2 is a cross-sectional view showing the semiconductor device of the first embodiment.

  As shown in FIGS. 1 and 2, the semiconductor device 1 of the first embodiment includes a semiconductor chip 5, a sub-wiring board 6 electrically connected to the semiconductor chip 5 through wires 8, and a sub-wiring board. 6 is mounted, and a sealing resin material 9 for fixing the semiconductor chip 5 to the main wiring board 7 is provided.

  On one surface (front surface) of the semiconductor chip 5, a predetermined circuit such as a logic circuit or a storage circuit is formed. In addition, a plurality of electrode pads 5a are formed at positions near the outer periphery of the surface of the semiconductor chip 5, and a passivation film (not shown) is formed on the surface of the semiconductor chip 5 excluding the electrode pads 5a. The surface that is is protected.

  The main wiring board 7 is a glass epoxy board that is formed in a substantially square shape with predetermined wirings and has a thickness of, for example, about 0.2 mm. The main wiring board 7 has predetermined wirings formed on both surfaces of a base material, and the wirings are partially covered with an insulating film (not shown) such as a solder resist. A plurality of connection pads 7 a are formed on a portion of one surface (front surface) of the main wiring substrate 7 exposed from the solder resist. Also, on the other surface (back surface) opposite to the front surface of the main wiring board 7, a plurality of lands 7b are formed in a portion exposed from the solder resist of the wiring. The connection pad 7a and the land 7b corresponding to the connection pad 7a are electrically connected to each other by the wiring 7c of the main wiring board 7, as shown in FIG. The plurality of lands 7b are respectively mounted with solder balls constituting the external terminals 11, and the external terminals 11 are arranged in a grid at predetermined intervals.

  A sub wiring board 6 is mounted on the surface of the main wiring board 7. The sub wiring board 6 is a glass epoxy board formed with a thickness of about 0.2 mm, for example. The sub wiring board 6 is formed in a substantially rectangular frame shape having an opening 13 that is slightly larger than the outer shape of the semiconductor chip 5, and predetermined wiring is formed. Further, similarly to the main wiring board 7, the sub wiring board 6 is formed with a plurality of connection pads 6a and lands 6b electrically connected to the connection pads 6a. The lands 6b of the sub wiring board 6 and the connection pads 7a of the main wiring board 7 are electrically connected through the bump electrodes 12, respectively.

  The semiconductor chip 5 is disposed at a position above the opening 13 of the sub wiring substrate 6. The semiconductor chip 5 is disposed in the opening 13 on a plane parallel to one surface (front surface) of the sub wiring substrate 6. In the thickness direction of the main wiring board 7, a gap is provided between the surface of the sub wiring board 6 and the other surface (back surface) opposite to the surface of the semiconductor chip 5. As described above, the semiconductor chip 5 is arranged above the opening 13 and the above-described gap is provided, so that the sealing resin material 9 can be smoothly distributed around the semiconductor chip 5 during manufacturing.

  Further, the electrode pads 5a of the semiconductor chip 5 are electrically connected by being connected to the connection pads 6a of the sub-wiring substrate 6 corresponding to the electrode pads 5a by the conductive wires 8 as connection members. ing. The wire 8 is made of, for example, Au or Cu.

  A sealing resin material 9 is provided on the surface of the main wiring board 7 so as to cover the entire outer periphery of each of the semiconductor chip 5, the sub wiring board 6, and the wires 8. The sealing resin material 9 is made of, for example, a thermosetting resin such as an epoxy resin, and the sealing resin material 9 is also filled and arranged between the front surface of the main wiring board 7 and the back surface of the semiconductor chip 5. The semiconductor chip 5 is held at a position above the main wiring board 7.

  As described above, the semiconductor device 1 according to the present embodiment includes the semiconductor chip 5 provided with the electrode pad 5a on the surface (one surface), the sub wiring substrate 6 provided with the connection pad 6a on the surface (one surface), the electrode A wire 8 (connection member) that electrically connects the pad 5a and the connection pad 6a, and a sub-wiring board 6 mounted on the surface (one surface) and electrically connected to the connection pad 6a of the sub-wiring board 6 A sealing resin material 9 (fixing material) that covers the entire outer periphery of the main wiring board 7 provided with the terminals 11 and the semiconductor chip 5 and fixes the semiconductor chip 5 to the surface (one surface) side of the main wiring board 7. And comprising. The sub wiring board 6 is located between the main wiring board 7 and the semiconductor chip 5 in the thickness direction of the main wiring board 7. In other words, the wire 8 (connection member) extends from the electrode pad 6 a of the semiconductor chip 5 across the thickness direction of the semiconductor chip 5 and is coupled to the connection pad 6 a of the sub wiring substrate 6.

  As in this configuration, the sealing resin material 9 is disposed between the front surface of the main wiring board 7 and the back surface of the semiconductor chip 5 so that the semiconductor chip 5 is not directly bonded and fixed on the front surface of the main wiring board 7. With this configuration, for example, in a reflow process for forming the external electrode 11, stress caused by a difference in thermal expansion coefficient between the semiconductor chip 5 and the main wiring board 7 is reduced, and the reliability of the semiconductor device 1 is improved. be able to. Furthermore, in the present embodiment, the semiconductor chip 5 is configured not to be directly bonded and fixed on the surface of the main wiring board 7, so that the semiconductor chip 5 is positioned near the lower four corners of the outer periphery of the semiconductor chip 5. Since the stress acting on each arranged external terminal 11 is reduced, damage to the external terminal 11 is reduced, and the reliability when the semiconductor device 1 is secondarily mounted on a mounting board or the like can be improved.

  Further, in the present embodiment, the semiconductor chip 5 is configured not to be directly bonded and fixed on the surface of the main wiring board 7, so that the thermal expansion coefficient difference between the semiconductor chip 5 and the main wiring board 7 occurs. Warpage of the semiconductor device 1 can be reduced.

  Further, in this embodiment, by using the sub wiring substrate 6, the space between the main wiring substrate 7 and the semiconductor chip 5 becomes hollow (non-contact), and the sealing resin material 9 is disposed on the entire periphery of the semiconductor chip 5. In addition, it is possible to adopt a FAN-IN structure in which the external terminal 11 is arranged at a position directly below the semiconductor chip 5 in the main wiring board 7.

  In addition, since the entire outer peripheral surface of the semiconductor chip 5 is configured to be covered with the sealing resin material 9, the moisture resistance and mechanical strength of the semiconductor device 1 can be improved. Further, when the semiconductor chip 5 is a DRAM (Dynamic Random Access Memory), the entire outer peripheral surface of the semiconductor chip 5 is covered with the sealing resin material 9, which is caused by thermal expansion of the sealing resin material 9. The stress applied to the semiconductor chip 5 is equalized. For this reason, deterioration of the refresh characteristic of the semiconductor device 1 can be reduced, and the refresh characteristic can be improved.

  Next, a method for manufacturing the semiconductor device of the first embodiment will be described.

  FIG. 3 is a cross-sectional view showing a wire bonding step between the semiconductor chip 5 and the sub wiring substrate 6.

  First, in the manufacturing method of the present embodiment, a wire bonding step is performed in which the semiconductor chip 5 is electrically connected to the sub wiring substrate 6 via the wires 8. In this wire bonding step, as shown in FIG. 3A, a wire bonding stage 21 is used as a mounting table on which the semiconductor chip 5 and the sub wiring substrate 6 are respectively mounted.

  As shown in FIGS. 3A and 3B1, the wire bonding stage 21 includes a chip mounting surface 22 on which the semiconductor chip 5 is mounted, a substrate mounting surface 23 on which the sub wiring substrate 6 is mounted, have. In the wire bonding stage 21, in the thickness direction of the semiconductor chip 5, the back surface of the semiconductor chip 5 placed on the chip placement surface 22 is higher than the surface of the sub-wiring substrate 6 placed on the substrate placement surface 23. The chip mounting surface 22 and the substrate mounting surface 23 are formed so as to be positioned.

  Further, the chip mounting surface 22 of the bonding stage 21 is provided with suction holes 25 so that the semiconductor chip 5 mounted on the chip mounting surface 22 is sucked and held. Although not shown, the substrate mounting surface 23 may be provided with suction holes similar to those of the chip mounting surface 22, and the sub-wiring substrate 6 may be held by suction. Further, the substrate mounting surface 23 is formed with a recess for avoiding contact with the bump electrode provided on the land 6 b of the sub wiring substrate 6.

  Further, as shown in FIG. 3B 2, the wire bonding stage 21 is provided with a support wall 24 as a support portion for supporting the wire 8 between the chip mounting surface 22 and the substrate mounting surface 23. Also good. The support wall 24 is formed in an annular shape along the outer periphery of the semiconductor chip 5, and the upper end surface of the support wall 24 protrudes above the position of the surface of the semiconductor chip 5. By using the wire bonding stage 21 having such a support wall 24, the support wall 24 supports the middle of the wire 8 in the length direction, so that the wire 8 is good without contacting the outer peripheral portion of the semiconductor chip 5. Therefore, the sealing resin material 9 can be smoothly distributed over the entire outer periphery of the semiconductor chip 5 and the entire outer periphery of the wire 8. Of course, a jig similarly configured may be used instead of the wire bonding stage 21.

  Using the thus configured bonding stage 21, as shown in FIG. 3A, the protruding portion on which the chip mounting surface 22 is formed is arranged in the opening 13 of the sub wiring board 6. The rear surface side of the frame-shaped sub wiring substrate 6 is mounted and held on the chip mounting surface of the bonding stage 21. Subsequently, the semiconductor chip 5 is mounted and held on the chip mounting surface 22 of the bonding stage.

  Next, as shown in FIGS. 3B1 and 3B2, the electrode pads 5a of the semiconductor chip 5 held on the bonding stage 21 and the connection pads 6a of the sub-wiring substrate 6 are electrically conductive. The wires 8 are connected and electrically connected.

  After all the wire connections corresponding to the electrode pads 5a of the semiconductor chip 5 are completed, the sub-wiring in which the semiconductor chip 5 is wire-connected as shown in FIGS. 3C and 4 is removed from the bonding stage 21. A substrate 6 is obtained. At this time, the semiconductor chip 5 is held above the sub-wiring substrate 6 by tensions of the plurality of wires 8.

  FIG. 5 is a cross-sectional view for explaining a manufacturing process of the semiconductor device 1 of the first embodiment.

  First, the wiring mother board used in this embodiment is processed by a MAP (Mold Array Process) method, and a plurality of product forming portions are arranged in a matrix. The product forming portion has the same configuration as that of the main wiring board 7 at the portion that becomes the above-described main wiring board 7 after the wiring mother board is cut and separated. A frame portion is provided around the product forming portions arranged in a matrix. Positioning holes (not shown) are provided in the frame portion at a predetermined interval so that the wiring mother board can be conveyed and positioned. Further, a dicing line DL is included in the region between the product forming portions. First, as shown in FIG. 5A, a wiring mother board constituting a plurality of main wiring boards 7 is prepared.

  Next, the wiring mother board is transferred to a sub-board mounting process. As shown in FIG. 5B, the sub-wiring board 6 to which the semiconductor chip 5 is wire-connected is flip-chip mounted on the main surface of the wiring mother board, so that each sub-wiring board 6 becomes each product. It is mounted on each forming part.

  In flip chip mounting, for example, a bonding tool of a flip chip bonder (not shown) is used to hold the outer peripheral portion of the front surface of the sub wiring board 6, and the bump electrode 12 formed on the land 6 b on the back surface of the sub wiring board 6 is used. It is mounted by ultrasonic thermocompression bonding on the connection pad 6a of the product forming part. For example, a stud bump made of Au or the like is used as the bump electrode 12. Although not shown, a recess for avoiding contact with the semiconductor chip 5 and the wire 8 is formed at the tip of the bonding tool, and the sub-wiring substrate 6 can be held so as not to deform the wire 8. Has been. Subsequently, the wiring mother board on which the sub wiring board 6 is mounted is transferred to a sealing process.

  In the sealing step, as shown in FIG. 5C, an integrated sealing body is formed on the surface of the wiring mother board by the sealing resin material 9 across the plurality of product forming portions. In this sealing step, for example, a compression mold apparatus (not shown) is used. The wiring mother board is set by attracting and holding the back surface of the wiring mother board to the upper mold of the molding die included in the compression molding apparatus.

  Then, a predetermined amount of a thermosetting resin such as an epoxy resin or the like is supplied to the lower mold of the molding mold included in the compression mold apparatus via the film, and the lower mold is predetermined. Heated to temperature, the granular sealing resin material 9 is melted. Thereafter, the upper die holding the other surface of the wiring mother board is lowered toward the lower die, and the surface side of the wiring mother board is immersed in the molten sealing resin material 9. Then, the sealing resin material 9 is compressed by the upper mold and the lower mold of the compression mold apparatus, thereby filling the predetermined portion on the wiring mother board with the sealing resin material 9.

  In this embodiment, since the sealing resin material 9 is not poured from the side surface of the semiconductor chip 5 by using a method of pressurizing and filling the sealing resin material 9 using a compression mold apparatus, the sealing resin material All the outer peripheral surfaces of the semiconductor chip 5 suspended from the wiring mother board by the plurality of wires 8 and the electrical connection between the main wiring board 7 and the sub wiring board 6 without generating a wire flow at the time of pouring 9 The sealing resin material 9 can be smoothly filled in the portion.

  Then, by sealing the sealing resin material 9 at a predetermined temperature of about 180 ° C., for example, a sealing body is formed by the sealing resin material 9 on the wiring motherboard as shown in FIG. Is done. By sealing so as to cover a plurality of product forming portions at once, a sealing body with good dimensional accuracy of the outer shape can be efficiently formed on the wiring mother board.

  Next, the wiring mother board on which the sealing body is formed is transferred to a ball mounting process. As shown in FIG. 5D, external terminals 11 are formed by mounting conductive solder balls on a plurality of lands arranged in a grid pattern on the back surface of the wiring mother board.

  In the ball mounting process, using a mounting tool (not shown) in which a plurality of suction holes are formed in accordance with the arrangement of lands on the wiring mother board, for example, a solder ball made of solder or the like is held by the mounting tool. Flux is transferred to the solder balls and mounted on the lands in the product formation area. After mounting the solder balls on all the product forming portions, the external terminals 11 are formed by heating the wiring mother board in a reflow process.

  Next, the wiring mother board on which the external terminals 11 are formed is transferred to a substrate dicing process, and as shown in FIG. 5E, the wiring mother board is cut along dicing lines, and each product mounting portion is cut. To separate. In this substrate dicing step, the sealing body side of the wiring mother board is placed on and bonded to the dicing tape 29, and the wiring mother board is fixed by the dicing tape 29. Thereafter, using a dicing blade of a dicing apparatus (not shown), the wiring mother board is cut in the vertical and horizontal directions along the dicing line, and is cut into individual product forming portions and separated. After cutting and separating, the semiconductor device 1 as a product forming portion is taken up from the dicing tape 29, whereby the semiconductor device 1 as shown in FIGS. 1 and 2 is obtained.

  As described above, the manufacturing method of the semiconductor device of this embodiment has the chip mounting surface 22 on which the semiconductor chip 5 is mounted and the substrate mounting surface 23 on which the sub wiring substrate 6 is mounted. 5 in the thickness direction, the semiconductor chip 5 placed on the chip placement surface 22 is positioned above the surface (one surface) of the sub-wiring substrate 6 placed on the substrate placement surface 23. This is performed using a bonding stage 21 (mounting table) on which the surface 22 and the substrate mounting surface 23 are formed. In this manufacturing method, the semiconductor chip 5 provided with the electrode pad 5a on the front surface (one surface) is placed on the chip mounting surface 22, and the sub-wiring substrate 6 provided with the connection pad 6a on the front surface (one surface) is provided as a substrate. A step of placing on the mounting surface 23, a step of electrically connecting the electrode pads 5a of the semiconductor chip 5 and the connection pads 6a of the sub-wiring substrate 6 via the wires 8 (connection members), and the semiconductor chip 5 and the wires The sub wiring board 6 electrically connected via 8 (connection member) is mounted on the surface (one surface) of the main wiring board 7, and the sub wiring board 6 and the connection pads 7a of the main wiring board 7 are electrically connected. And a step of covering the entire outer periphery of the semiconductor chip 5 with a sealing resin material 9 (fixing material) and fixing the semiconductor chip 5 on the surface (one surface) side of the main wiring board 7. Yes. According to this manufacturing method, for example, in a reflow process for forming the external electrode 11, warpage generated in the semiconductor device 1 due to thermal expansion and damage to the external electrode 11 are reduced, and the semiconductor device 1 with improved reliability is provided. can do.

(Second embodiment)
FIG. 6 is a cross-sectional view showing the semiconductor device of the second embodiment. FIG. 7 is a cross-sectional view for explaining a manufacturing process of the semiconductor device of the second embodiment.

  The semiconductor device 2 of the second embodiment has the same basic configuration as that of the first embodiment, and a concave portion in which the sub wiring board 6 is disposed is formed on the surface of the main wiring board 7. Only is different. For this reason, in the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted.

  As shown in FIG. 6, a recess 27 is formed in an annular shape along the outer periphery of the main wiring board 7 on the surface of the main wiring board 7 included in the semiconductor device 2 of the second embodiment. A connection pad 7 a is formed on the bottom surface of the recess 27, and the sub wiring substrate 6 disposed in the recess 27 is electrically connected to the connection pad 7 a via the bump electrode 12.

  As shown in FIG. 7, the semiconductor device 2 of the second embodiment is the same as that of the first embodiment described above except that the sub-wiring board 6 is disposed and mounted in the recess 27 of the wiring mother board. Since it is performed in the same manner as the manufacturing process in the example, the description is omitted.

  According to the semiconductor device 2 of the second embodiment, the same effect as that of the semiconductor device 1 of the first embodiment can be obtained, and the sub-wiring board 6 is placed in the recess 27 provided on the surface of the main wiring board 7. By being arranged, the semiconductor device 2 can be thinned.

  The sub circuit board 6 included in the semiconductor devices 1 and 2 according to the above-described embodiments is formed in a rectangular frame shape. However, the sub circuit board 6 may be divided into a plurality of parts as necessary. .

DESCRIPTION OF SYMBOLS 1 Semiconductor device 5 Semiconductor chip 5a Electrode pad 6 Sub wiring board 6a Connection pad 7 Main wiring board 8 Wire 9 Sealing resin material 11 External terminal 13 Opening part

Claims (11)

A semiconductor chip provided with electrode pads on one surface;
A sub-wiring board provided with connection pads on one side;
A connection member for electrically connecting the electrode pad and the connection pad;
The sub wiring board is mounted on one surface, and a main wiring board provided with external terminals that are electrically connected to the connection pads of the sub wiring board;
A fixing material provided to cover the entire outer periphery of the semiconductor chip, and fixing the semiconductor chip to the one surface side of the main wiring board,
The sub wiring board is a semiconductor device positioned between the main wiring board and the semiconductor chip in a thickness direction of the main wiring board. A semiconductor chip provided with electrode pads on one surface;
A sub-wiring board provided with connection pads on one side;
A connection member for electrically connecting the electrode pad and the connection pad;
The sub wiring board is mounted on one surface, and a main wiring board provided with external terminals that are electrically connected to the connection pads of the sub wiring board;
A fixing material provided to cover the entire outer periphery of the semiconductor chip, and fixing the semiconductor chip to the one surface side of the main wiring board,
The semiconductor device, wherein the connection member extends from the electrode pad of the semiconductor chip in a thickness direction of the semiconductor chip and is connected to the connection pad of the sub wiring board.   3. The semiconductor device according to claim 1, wherein the fixing material is a sealing material that covers the entire outer periphery of each of the connection member and the sub wiring board and is provided on the one surface of the main wiring board. . The sub wiring board is formed in a frame shape having an opening larger than the outer shape of the semiconductor chip,
4. The semiconductor device according to claim 1, wherein the semiconductor chip is disposed in the opening in a plane parallel to the one surface of the sub-wiring substrate. 5.   5. The gap according to claim 1, wherein a gap is provided between the one surface of the sub-wiring substrate and the other surface opposite to the one surface of the semiconductor chip in the thickness direction of the main wiring substrate. A semiconductor device according to 1.   6. The semiconductor device according to claim 1, wherein a concave portion in which the sub wiring board is disposed is formed on the one surface of the main wiring board. A semiconductor chip provided with electrode pads only on one surface;
A frame-shaped sub-wiring substrate having a connection pad on one surface and having an opening;
A connection member for electrically connecting the electrode pad and the connection pad of the sub-board;
The sub-wiring board is mounted on one surface, and another connection pad electrically connected to the connection pad of the sub-wiring board is provided on the one surface, and the other connection on the other surface opposite to the one surface. A main wiring board provided with external terminals electrically connected to the pads;
Covering the entire outer periphery of each of the semiconductor chip, the connection member and the sub wiring board, and a sealing material provided on the one surface of the main wiring board,
The semiconductor chip is disposed in the opening in a plane parallel to the one surface of the sub-wiring board,
A semiconductor device, wherein a gap is provided between the one surface of the sub-wiring substrate and another surface opposite to the one surface of the semiconductor chip in the thickness direction of the main wiring substrate. A chip mounting surface on which a semiconductor chip is mounted; and a substrate mounting surface on which a sub-wiring substrate is mounted. In the thickness direction of the semiconductor chip, the semiconductor chip mounted on the chip mounting surface is Using the mounting table on which the chip mounting surface and the substrate mounting surface are formed so as to be located above one surface of the sub wiring substrate mounted on the substrate mounting surface,
Placing the semiconductor chip provided with electrode pads on one surface on the chip mounting surface, and placing the sub-wiring substrate provided with the connection pads on one surface on the substrate mounting surface;
Electrically connecting the electrode pads of the semiconductor chip and the connection pads of the sub-wiring board via a connection member;
The sub-wiring board electrically connected to the semiconductor chip via the connecting member is mounted on one surface of the main wiring board, and the sub-wiring board and the connection pads of the main wiring board are electrically connected. Process,
Covering the entire outer periphery of the semiconductor chip with a fixing material, and fixing the semiconductor chip to the one surface side of the main wiring board;
A method for manufacturing a semiconductor device comprising:   In the step of fixing the semiconductor chip, the fixing material covers the entire outer periphery of each of the connection member and the sub wiring board, and the fixing material is provided on the one surface of the main wiring board and sealed. A method for manufacturing a semiconductor device according to claim 8.   10. The step of fixing the semiconductor chip, wherein the fixing material is pressurized in a mold to fill the entire outer periphery of each of the semiconductor chip, the connection member, and the sub wiring board. A method for manufacturing a semiconductor device.   11. The semiconductor device according to claim 8, wherein the support portion that supports the connection member uses the mounting table provided between the chip mounting surface and the substrate mounting surface. Production method.

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