JP2010511208A - Information processing apparatus and nonvolatile semiconductor memory drive - Google Patents

Abstract

  The information processing apparatus includes an information processing apparatus main body and a nonvolatile semiconductor memory drive accommodated in the information processing apparatus main body. The non-volatile semiconductor memory drive includes a non-volatile semiconductor memory, an address management table indicating a correspondence relationship between each logical block address and each physical address of the non-volatile semiconductor memory, and a control unit. The control unit refers to the address management table in response to reception of the read request from the information processing apparatus main body, and a physical address corresponding to the logical block address included in the read request is stored in the address management table. If not, data of a predetermined value is output to the information processing apparatus main body.

Description

  The present invention relates to an information processing apparatus and a nonvolatile semiconductor memory drive.

  As an apparatus for managing a nonvolatile semiconductor memory, for example, a memory management apparatus disclosed in Patent Document 1 is known.

  This memory management device returns an initial value to the host when there is a read request from the host for a storage unit for which an erase request has been made by the host.

  That is, the nonvolatile semiconductor memory management device refers to a nonvolatile semiconductor memory having a logical-physical address conversion table and a logical address designated by the erase request by referring to the logical-physical address conversion table in response to a data erase request from the host. And a controller that stores a physical block address associated with the block as a virtual erase area. When there is a read request for data included in the virtual erase area from the host, the control unit responds to the host with an initial value. For this reason, it is possible to recognize the data as if it was erased by the host without actually erasing the data on the nonvolatile semiconductor memory, so that the processing time required for erasing the data can be shortened.

JP 2006-79543 A

  However, in this memory management device, in order to initialize a nonvolatile semiconductor memory in which initial value data is not written in each storage unit at the time of shipment, all data is erased (all physical block addresses are virtualized). It is necessary to perform a process of storing as an erasing area, resulting in an increase in manufacturing process.

  An object of the present invention is to provide an information processing apparatus and a nonvolatile semiconductor memory drive that can omit the initialization process at the time of manufacture.

  According to one aspect of the present invention, an information processing apparatus main body and a non-volatile semiconductor memory drive housed in the information processing apparatus main body, the non-volatile semiconductor memory, each of logical block addresses, and the non-volatile semiconductor memory An address management table indicating a correspondence relationship with each physical address and a reference to the address management table in response to reception of a read request from the information processing apparatus main body, and corresponding to a logical block address included in the read request When a physical address is not stored in the address management table, an information processing apparatus is provided that includes a non-volatile semiconductor memory drive including control means for outputting data of a predetermined value to the information processing apparatus body.

  According to this information processing apparatus, when there is a read request for designating a logical block address in which the corresponding physical address is not stored, data of a predetermined value is output to the information processing apparatus body. The initialization process can be omitted.

FIG. 1 is a perspective view showing an appearance of an information processing apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the embodiment. FIG. 3 is a block diagram showing a schematic configuration of the SSD used in the information processing apparatus according to the embodiment. FIG. 4 is a schematic diagram showing the storage capacity and storage area of the SSD used in the information processing apparatus according to the embodiment. FIG. 5 is a diagram illustrating a configuration example of a flash address conversion table used in the information processing apparatus according to the embodiment. FIG. 6 is a flowchart showing the operation of the SSD used in the information processing apparatus according to the embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Configuration of information processing apparatus>
FIG. 1 is a perspective view showing an appearance of an information processing apparatus according to an embodiment of the present invention.

  The information processing apparatus 1 includes an information processing apparatus main body 2 and a display unit 3 attached to the information processing apparatus main body 2.

  The main body 2 has a box-shaped housing 4, and the housing 4 includes an upper wall 4 a, a peripheral wall 4 b, and a lower wall (not shown). The upper wall 4a of the housing 4 includes a front part 40, a central part 41, and a back part 42 in order from the side closer to the user who operates the information processing apparatus 1. The lower wall faces the installation surface on which the information processing apparatus 1 is placed. The peripheral wall 4b has a front wall 4ba, a rear wall 4bb, and left and right side walls 4bc, 4bd.

  The front unit 40 includes a touch pad 20 that is a pointing device, a palm rest 21, and an LED 22 that lights up in conjunction with the operation of each unit of the information processing apparatus 1.

  The central portion 41 includes a keyboard placement portion 23 to which a keyboard 23a capable of inputting character information and the like is attached.

  The back part 42 includes a battery pack 24 that is detachably attached. On the right side of the battery pack 24, a power switch 25 for turning on the information processing apparatus 1 is provided. A pair of hinge portions 26 a and 26 b that rotatably support the display unit 3 are provided on the left and right sides of the battery pack 24.

  A discharge port 29 for discharging the wind W from the inside of the housing 4 to the outside is provided in the left side wall 4bc of the housing 4. In addition, on the right side wall 4bd, for example, an ODD (optical disk drive) 27 that can read and write data from and on an optical storage medium such as a DVD, and a card slot 28 in which various cards are inserted and removed are arranged.

  The casing 4 is formed by a casing cover including a part of the peripheral wall 4b and the upper wall 4a, and a casing base including a part of the peripheral wall 4b and the lower wall. The housing cover is detachably combined with the housing base to form an accommodation space with the housing base. In this accommodation space, an SSD (solid state drive) 10 that functions as a nonvolatile semiconductor memory drive is accommodated. Details of the SSD 10 will be described later.

  The display unit 3 includes a display housing 30 having an opening 30a and a display device 31 including an LCD or the like that can display an image on a display screen 31a. The display device 31 is accommodated in the display housing 30, and the display screen 31a is exposed to the outside of the display housing 30 through the opening 30a.

  In the housing 4, in addition to the SSD 10, the battery pack 24, the ODD 27, and the card slot 28, a main circuit board, an expansion module, a fan, and the like (not shown) are accommodated.

  FIG. 2 is a block diagram showing a schematic configuration of the information processing apparatus according to the embodiment of the present invention.

  As shown in FIG. 2, the information processing apparatus 1 includes the SSD 10, the expansion module 12, the fan 13, the touch pad 20, the LED 22, the keyboard 23a, the power switch 25, the ODD 27, the card slot 28, and the display device 31. , EC (Embedded Controller) 111, Flash Memory 112 for storing BIOS (Basic Input Output System) 112a, South Bridge 113, North Bridge 114, CPU (Central Processing Unit) 115, GPU (Graphic Processing Unit) 116 and a main memory 117.

  An EC (embedded controller) 111 is an embedded system that controls each unit. The north bridge 114 is an LSI that controls connections among the CPU 115, the GPU 116, the main memory 117, and various buses. The CPU 115 is a processor that performs arithmetic processing on various signals, and executes an operating system and various application programs loaded from the SSD 10 to the main memory 117. The GPU 116 is a display controller that performs display control by processing video signals.

  The extension module 12 includes an extension circuit board, a card socket provided on the extension circuit board, and an extension module board inserted into the card socket. The card socket corresponds to a standard such as Mini-PCI, for example. Examples of the extension module substrate include a 3G (third generation) module, a television tuner, a GPS module, and a Wimax (registered trademark) module.

  The fan 13 is a cooling unit that cools the inside of the housing 4 based on the blown air, and discharges the air in the housing 4 to the outside as the wind W through the discharge port 29.

  The EC 111, the flash memory 112, the south bridge 113, the north bridge 114, the CPU 115, the GPU 116, and the main memory 117 are electronic components mounted on the main circuit board.

  Unlike the hard disk drive, the SSD 10 does not have a drive mechanism such as a magnetic disk or a head. However, the SSD 10 has a storage area of a NAND memory which is a nonvolatile semiconductor memory, a program such as an OS (operating system), and a user and software. It is a drive that can store data created based on it in a readable and writable manner for a long time and can operate as a startup drive of the information processing apparatus 1.

  FIG. 3 is a block diagram showing a schematic configuration of the SSD used in the present embodiment.

  The control unit 103 that functions as a memory controller is connected to the temperature sensor 101, the connector 102, the eight NAND memories 104A to 104H, the DRAM 105, and the power supply circuit 106, respectively. The control unit 103 is connected to the host device 8 through the connector 102, and is connected to the external device 9 as necessary.

  The power source 7 is a battery pack 24 or an AC adapter (not shown). For example, power of DC 3.3V is supplied to the power circuit 106 via the connector 102. The power source 7 supplies power to the entire information processing apparatus 1.

  The host apparatus 8 is the information processing apparatus 1 in the present embodiment, and the south bridge 113 mounted on the main circuit board and the control unit 103 are connected. Data transmission / reception is performed between the south bridge 113 and the control unit 103 based on a standard such as serial ATA. The host device 8 is a device that is connected when the SSD 10 is manufactured in FIG.

  The external device 9 is another information processing device different from the information processing device 1. The external device 9 is connected to the control unit 103 based on a standard such as RS-232C, for example, with respect to the SSD 10 removed from the information processing device 1, and has a function of reading data stored in the NAND memories 104A to 104H. Have.

  The board on which the SSD is mounted has an outer size equivalent to, for example, a 1.8 inch type or 2.5 inch type HDD (hard disk drive). In this embodiment, it is equivalent to the 1.8 inch type.

  On the substrate, the temperature sensor 101 is provided between the control unit 103 serving as a heat source and the NAND memories 104A to 104H. In the present embodiment, temperature sensor 101 is provided near the center of the substrate so as to be surrounded by control unit 103 and NAND memories 104A to 104H, and measures the temperature at that position. The measured temperature measured by the temperature sensor 101 is sent to the control unit 103 as temperature information. In this embodiment, the semiconductor temperature sensor using the characteristic that the voltage at the PN junction of the semiconductor changes with temperature is used. However, for example, a temperature sensor using another method such as a thermistor may be used.

  When the SSD 10 is operating, the temperature measured by the temperature sensor 101 provided at the above position is, for example, 50 ° C. to 60 ° C., which is about 10 ° C. higher than other regions of the substrate.

  The control unit 103 controls operations on the NAND memories 104A to 104H. Specifically, the control unit 103 controls reading / writing of data from / to the NAND memories 104 </ b> A to 104 </ b> H in response to a request (read request, write request, etc.) from the host device 8. The data transfer rate is, for example, 100 MB / Sec when reading data, and 40 MB / Sec when writing.

  The control unit 103 acquires temperature information from the temperature sensor 101 at a constant cycle, and reduces the response to the host device 8 when the measured temperature indicated by the temperature information exceeds a preset specified value. The operation for reducing the response is an operation for limiting a part of the processing capability of the SSD 10. As an operation for reducing the response, for example, a decrease in transfer speed when data read from the NAND memories 104A to 104H is transferred to the host device 8, or a transfer speed between the control unit 103 and the NAND memory memories 104A to 104H. Decrease, etc.

  Further, when the measured temperature exceeds the specified value, the control unit 103 outputs a warning signal to the host device 8 as information indicating that. The control unit 103 may output the temperature information itself to the host device 8 instead of the warning signal.

  In addition, the control unit 103 writes the acquired temperature information together with the acquired acquisition date and time at predetermined addresses in the NAND memories 104A to 104H.

  Each of the NAND memories 104A to 104H is, for example, a nonvolatile semiconductor memory having a storage capacity of 16 GB. Each of the NAND memories 104A to 104H is composed of, for example, an MLC (multilevel cell) -NAND memory (multilevel NAND memory) capable of recording 2 bits in one memory cell. The MLC-NAND memory has a smaller number of rewritable times than an SLC (single level cell) -NAND memory, but has a feature that it is easier to increase the storage capacity than an SLC (single level cell) -NAND memory. Have.

  Further, the NAND memories 104A to 104H have a characteristic that a period in which data can be held varies depending on an environmental temperature in which the NAND memories 104A to 104H are installed.

  The NAND memories 104 </ b> A to 104 </ b> H store data written under the control of the control unit 103, and store temperature information and acquisition date / time as a temperature history.

  The DRAM 105 is a buffer in which data is temporarily stored when data is read from and written to the NAND memories 104A to 104H under the control of the control unit 103. The DRAM 105 functions as a write cache that temporarily stores write data from the information processing apparatus main body 2 that functions as the host device 8.

  The connector 102 has a shape based on a standard such as serial ATA. Note that the control unit 103 and the power supply circuit 106 may be connected to the host device 8 and the power supply 7 by separate connectors, respectively.

  The power supply circuit 106 converts DC 3.3V supplied from the power supply 7 into, for example, DC 1.8V, 1.2V, and the like, and supplies these three types of voltages to each unit according to the drive voltage of each unit of the SSD 10. .

  FIG. 4 is a schematic diagram showing the storage capacity and storage area of the SSD 10 used in this embodiment.

  The control unit 103 of the SSD 10 manages seven types of storage capacities 104a to 104g shown in FIG.

  In the storage area between the storage capacities 104a and 104b, the management data 107a for operating the SSD 10 and the logical block address LBA are physical addresses (flash addresses) corresponding to sectors which are storage units of the NAND memories 104A to 104H. A flash address conversion table 108a for conversion into the above is stored. The flash address conversion table 108a is an address management table showing the correspondence between each logical block address LBA and each physical address of the NAND memories 104A to 104H. The control unit 103 controls writing and reading of data with respect to the NAND memories 104A to 104H using the flash address conversion table 108a. The control unit 103 refers to the flash address conversion table 108a in response to receiving a read request (read command) from the host device 8. When the physical address corresponding to the logical block address LBA included in the read request is stored in the flash address conversion table 108a, the control unit 103 executes read access to the NAND memories 104A to 104H using the physical address, Data is read from a predetermined storage location (sector) in the NAND memories 104A to 104H designated by the physical address. On the other hand, when the physical address corresponding to the logical block address LBA is not stored in the flash address conversion table 108a, that is, the logical / physical address conversion information corresponding to the logical block address LBA included in the read request is stored in the flash address conversion table 108a. If not stored, the control unit 103 outputs data of a predetermined value to the host device 8 as read data corresponding to the logical block address LBA.

  Normally, when the SSD 10 is shipped, it is necessary to write zero data (00h) in all or some of the storage areas of the SSD 10. This is because an initial value (for example, 00h) can be returned from the SSD 10 to the host in response to a read request from the host. In the NAND memory, all “1” data (FFh) is read from the erased storage location. Therefore, when the SSD 10 is shipped, it is necessary to write zero data (00h) in all or a part of the storage areas.

  In the present embodiment, when the host requests read access to an LBA for which the logical / physical address conversion information is not stored in the flash address conversion table 108a, the control unit 103 sets the initial value of the predetermined value as described above. Data, for example, zero data (00h) can be returned to the host device 8 as read data. Therefore, when the SSD 10 is shipped, for example, by simply executing the process of initializing the flash address conversion table 108a and setting the physical address corresponding to each LBA not stored in the flash address conversion table 108a. Initial data, for example, zero data (00h) can be returned to the host device 8 as read data. Therefore, for example, by clearing the physical address corresponding to each LBA belonging to the predetermined logical address range or the physical address corresponding to each LBA belonging to the entire logical address range from the flash address conversion table 108a, The step of writing initial data, that is, zero data (00h) to the storage area or a part of the storage area can be omitted. As a result, the manufacturing process can be simplified. Further, since the initial data (for example, zero data (00h)) of a predetermined value can be immediately returned to the host device 8 without actually performing read access to the NAND memory, the read operation performance can be improved. .

  If an LBA and a physical address are stored in each entry of the flash address conversion table 108a, both the LBA and the physical address may be cleared in the initialization process of the flash address conversion table 108a. Further, the flash address conversion table 108a can hold flag information indicating whether data is written to a physical address corresponding to the logical block address for each LBA. In this case, in the initialization process of the flash address conversion table 108a, the control unit 103 may set flag information corresponding to each LBA to a value indicating no writing. When the flag information corresponding to the LBA included in the read command from the host device 8 indicates no writing, the control unit 103 stores the physical address corresponding to the LBA included in the read request in the flash address conversion table 108a. It is determined that there is not, and initial data of a predetermined value is output to the host device 8.

  In the storage area between the storage capacities 104b and 104c, S.P. as memory inspection history information, which is statistical information such as the temperature information described above, is stored. M.M. A. R. T.A. (Self-Monitoring Analysis and Reporting Technology) Log data 107b is stored.

  For example, an unused storage area having a storage capacity of 2 MB is set in the storage area between the storage capacities 104c and 104d. This is because the minimum storage unit of LBA is 8 sectors and is a storage unit corresponding to 4 kB (a large storage unit is 1 MB), but the actual minimum recording unit of data is naturally 1 sector, so 1 MB By providing an empty storage area with the above storage capacity, S.I. M.M. A. R. This is because the T log data 107b and the data recorded below the storage capacity 104d are handled independently.

  The storage areas between the storage capacities 104d and 104e are unused and the storage capacities 104d and 104e have the same value except in special cases.

  The storage area between the storage capacities 104e and 104f is a storage area used for the OEM, and the unique information determined by the OEM request is written as described above.

  A storage area between the storage capacities 104f and 104g is a storage area used by the OEM or the user, and information is written according to settings of the OEM or the user.

  The storage area of the storage capacity 104g is a storage area used by the user, and information is written according to user settings.

  FIG. 5 shows a configuration example of a flash address conversion table used in this embodiment.

  The flash address conversion table 108a is a table that associates LBAs with flash addresses as described above. In this flash address conversion table 108a, for example, a “write” indicating whether or not data (for example, valid data such as initial data having a predetermined value described above) has been written to the flash address associated with each LBA. The “write” flag field is described by the control unit 103 as “present” or “not present”. Here, “present” indicates that writing has been performed on the flash address corresponding to the corresponding LBA, and “none” indicates no writing. The value of the “write” flag field is changed from “none” to “present” when the write operation is executed. Further, by initializing the SSD 10, for example, the values of all “write” flag fields are changed to “none”.

<Operation>
Below, operation | movement of the information processing apparatus 1 of this embodiment is demonstrated, referring each figure.

  FIG. 6 is a flowchart showing the operation of the SSD 10 used in this embodiment.

  When receiving a read request (read command) from the host device 8 (Yes in step S1), the control unit 103 refers to the flash address conversion table 108a (step S11).

  When the “write” flag field corresponding to the LBA included in the read request indicates “present” (YES in step S12), the control unit 103 sets the flash address corresponding to the LBA included in the read request to the flash address conversion table. 108a and read access to the NAND memories 104A to 104H is executed using the acquired flash address (step S13). In step S13, data stored in a certain storage location (sector) in the NAND memories 104A to 104H designated by the flash address is read. Then, the control unit 103 sends the data read from the NAND memories 104A to 104 to the host device 8 (step S14).

  On the other hand, when the “write” flag field corresponding to the LBA included in the read request indicates “none”, or the flash address corresponding to the LBA included in the read request is not stored in the flash address conversion table 108a. (NO in step S12), the control unit 103 creates zero data as an initial value (step S15). Next, the control unit 103 sends zero data as read data to the host device 8 (step S14).

  As described above, according to the present embodiment, when there is a read request from the host device 8 to an LBA corresponding to a flash address without writing, zero data that is an initial value is transferred to the host device 8. Therefore, there is no need for an initialization process at the time of manufacturing.

  Further, since reading is not executed for a flash address without writing, the reading performance of the SSD 10 is improved as compared with the case where reading is executed for all flash addresses regardless of whether or not writing is performed.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

Claims (7)

An information processing apparatus main body;
A non-volatile semiconductor memory drive housed in the information processing apparatus body, the non-volatile semiconductor memory, an address management table indicating a correspondence relationship between each logical block address and each physical address of the non-volatile semiconductor memory, In response to reception of a read request from the information processing apparatus body, the address management table is referenced, and a physical address corresponding to a logical block address included in the read request is not stored in the address management table. An information processing apparatus comprising: a nonvolatile semiconductor memory drive including control means for outputting value data to the information processing apparatus main body.   2. The control unit according to claim 1, wherein, when a physical address corresponding to a logical block address included in the read request is stored in the address management table, the control unit performs read access to the nonvolatile semiconductor memory using the physical address. The information processing apparatus described.   The address management table holds flag information indicating whether or not data is written to a physical address corresponding to the logical block address for each logical block address, and the control unit corresponds to the logical block address included in the read request. When the flag information indicates no writing, it is determined that the physical address corresponding to the logical block address included in the read request is not stored in the address management table, and the predetermined value data is output to the information processing apparatus main body The information processing apparatus according to claim 1.   The information processing apparatus according to claim 1, wherein the predetermined value data is zero data. A non-volatile semiconductor memory drive used as an external storage device of an information processing device,
Non-volatile semiconductor memory;
An address management table showing a correspondence relationship between each logical block address and each physical address of the nonvolatile semiconductor memory;
Reference is made to the address management table in response to reception of a read request from the information processing apparatus, and a predetermined value is set when a physical address corresponding to a logical block address included in the read request is not stored in the address management table A non-volatile semiconductor memory drive comprising control means for outputting the data of the data to the information processing apparatus main body.   6. The control unit according to claim 5, wherein when the physical address corresponding to the logical block address included in the read request is stored in the address management table, the control unit performs read access to the nonvolatile semiconductor memory using the physical address. The nonvolatile semiconductor memory drive described.   The address management table holds flag information indicating whether or not data is written to a physical address corresponding to the logical block address for each logical block address, and the control unit corresponds to the logical block address included in the read request. When the flag information indicates no writing, it is determined that the physical address corresponding to the logical block address included in the read request is not stored in the address management table, and the predetermined value data is output to the information processing apparatus. The non-volatile semiconductor memory drive according to claim 5.

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