JP2010231490A - Circuit board for control of failure transfer signal output due to cpu reset - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control the number of times of failure transfer signal output due to CPU reset which frequently occurs due to such an effect as an installation environment noise. <P>SOLUTION: A failure transfer signal output control circuit board 1 includes: a transistor DTA1 to be driven according to the rising of the CPU reset pulse input of a CPU substrate 20 of a monitoring control device 10; a capacitor C1 and a resistance R for charging and discharging the amplification currents of the transistor DTA1 in a prescribed time; an IC 3 having a comparator for determining whether both edge voltages of the capacitor exceed a specific reference voltage; and a relay RL1 to be driven by the output of the comparator. According to the CPU reset input by the prescribed number of times, failure transfer signal output is performed to the outside of the monitoring device. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to failure output control when a monitoring control device transfers information to other equipment.

There is a monitoring control device having a circuit that interrupts the CPU (performs CPU reset) when the microcomputer checks whether the microcomputer is operating normally by a watchdog timer and detects abnormal operation (for example, Patent Document 1).

JP-A-4-65731

By the way, since the transmission form and the like are different between the monitoring control devices of different systems, the other monitoring control device set as the lower device performs the transfer output with respect to the monitoring control device set as the higher device. May be used. For example, this is a case where the fire receiving device performs a fire transfer output, a failure transfer output, or the like to the security monitoring device.

  Here, the fire receiving device is provided with a watch dog timer, and the CPU is monitored by the function of the fire receiving device and the watch dog timer suitable for the CPU specifications of the fire receiving device. That is, when the CPU has a malfunction such as runaway, the CPU is reset by the watchdog timer, and the fire receiving device outputs a CPU reset output signal to the crime prevention monitoring device by means of relay driving or the like.

In addition, depending on the installation environment of the fire receiving device, a CPU reset may occur due to the influence of noise or the like and frequent failure transfer output may occur. In this case, the CPU reset is instantaneous, and even if the failure transfer is output, it is recovered instantaneously. Therefore, other monitoring control devices (security monitoring devices) on the transfer input side determine that the noise is The cause of the failure transfer output had to be confirmed every time, which was cumbersome and troublesome.

  In addition, as a method of solving failure transfer output due to CPU reset, which is not recognized as a cause of failure on such a supervisory control system, countermeasures by software change such as rewriting a program related to failure transfer output control of the fire receiving device are possible. Although it is conceivable, there is a problem that the program cannot be rewritten in an existing monitoring and control apparatus that cannot change software. Even when the software can be changed, a lot of time has to be spent on debugging work and verification work when the system is restarted, which is troublesome and expensive.

  Therefore, an object of the present invention is to provide a circuit board capable of easily and inexpensively performing failure transfer output control of a monitoring control device.

  In order to achieve the above object, the invention according to claim 1 is a failure transfer output control for detecting a rising edge or a falling edge of a CPU reset pulse input output from a CPU board of a supervisory controller and performing a failure transfer output. A circuit board that is driven by the CPU reset pulse input and outputs a current; a charging circuit section that charges the output current of the current output circuit section within a predetermined time; and A comparison circuit unit that outputs a HIGH voltage when a charging voltage exceeds a predetermined reference voltage, and a transfer output circuit unit that receives an output from the comparison circuit unit and outputs a failure transfer, are provided. .

  By providing the failure transfer output circuit board of the present invention in the monitoring control device, it is possible to perform reliable failure transfer output without changing software.

It is a circuit diagram which shows the failure transfer output control circuit board by CPU reset of this invention. It is a wave form diagram showing each operation state of a circuit element of a failure transfer output control circuit.

  FIG. 1 is a configuration diagram of the monitoring control device 10 and is a circuit diagram of a CPU board 20 and a fault transfer output control circuit board 1 (hereinafter referred to as “fault output countermeasure board 1”) by CPU reset. FIG. 2 is a waveform diagram showing each operation state of a circuit element of a failure countermeasure board 1 described later.

First, the system configuration of the monitoring control device 10 (fire receiving device 10) will be described.
A fire detector (not shown) is connected to the monitoring control device 10 (fire receiving device 10) via a line. When a fire detection signal is received from the fire detector, the monitoring control device 10 (fire receiving device 10) , Fire alarm control and other control necessary for fire alarm.

  Further, the monitoring control device 10 (fire receiving device 10) is connected to a crime prevention monitoring device (not shown) which is another facility through a transfer line, and at the time of a fire alarm or the monitoring control device 10 (fire receiving device) 10) When a failure occurs due to a CPU runaway or the like, a fire transfer output or a failure transfer output is performed to a crime prevention monitoring device (monitoring control device of another facility).

Next, the internal configuration and operation of the monitoring control device 10 (fire receiving device 10) will be described.
The monitoring control device 10 (fire receiving device 10) includes a CPU board 20 and performs various control processes such as the fire alarm described above.

  The CPU board 20 includes a CPU 40 and a watchdog timer 50 (hereinafter referred to as WDT 50), and the WDT 50 monitors the normality / abnormality of the CPU 40. When the CPU 40 becomes in a failure state such as runaway or abnormal operation, the WDT 50 detects this and sends an interrupt signal to the CPU 40 in the failure state to reset the CPU 40.

  Also, one of the pins of the CPU 40 is electrically connected to the input terminal of the terminal portion 2 provided on the failure output countermeasure board 1 of the present invention via a wiring (hereinafter referred to as “pin”). When the CPU 40 is normal, a HIGH signal is output to the input terminal, and when the CPU 40 is abnormal, a LOW signal is output to the input terminal. Hereinafter, the signal input of the falling edge of the HIGH to LOW signal from the pin to the failure output countermeasure board 1 is referred to as CPU reset input.

Next, the operation state of the circuit elements of the failure countermeasure board 1 will be described mainly with reference to FIG.
2A shows the CPU reset input and the charging voltage of the charging capacitors C1 and C2 and the failure transfer output (the base voltage of the transistor DTC-1) when the power of the monitoring control device 10 (fire receiving device 10) is turned on. FIG. 2C is a waveform diagram when the CPU recovers from a failure state to a normal state.

  When the WDT 50 detects a failure such as a runaway of the CPU 40, the CPU 40 is reset by a CPU interrupt, and a CPU reset input is present from the pin of the CPU 40 to the input terminal (terminal portion 2) of the failure output countermeasure board 1 (FIGS. 1 and 2). b)).

By the CPU reset input, the transistor DTA1 (current output circuit unit of the present invention) of the failure output countermeasure board 1 is turned on (driven to output an amplified current), and charged to the integrating circuit composed of R2 and C1 (the present invention). Charging circuit section).
As shown in FIG. 2B, the CPU reset input is a pulse having a pulse width of 100 ms, and is input every 3 seconds depending on the setting of the WDT 50. Further, the constants of R2 and C1 of the integration circuit are obtained when the CPU reset input (CPU reset pulse input) is made four times in total from the first CPU reset input, and C1 is charged in about 11.6 seconds. Is set (saturated).

  When C1 is charged, the reference voltage of the comparator CMP1 (comparison circuit unit of the present invention) exceeds the reference voltage, and the CMP1 built in the IC3 outputs (ON), and DTA2, CMP2, DTA3 and DTC1 are continuously output by the output of CMP1. (Transfer output circuit section of the present invention) outputs (ON) (FIGS. 1 and 2).

  When DTC1 outputs (ON) (DTC1-B in FIG. 2B), relay RL1 is driven and contact RL'1 is closed (transfer output circuit section of the present invention).

  Therefore, by providing the failure control board 1 of the present invention in the monitoring control device 10, the CPU reset input generated due to instantaneous noise or the like is excluded, and only when there is a continuous CPU reset input, an external crime prevention monitoring is performed. Since the failure transfer output is made to the apparatus, it is possible to reliably detect the failure of the CPU.

  The present invention is also effective by installing the failure output countermeasure board 1 of the present invention when a failure of CPU failure output occurs in an existing monitoring control device or a monitoring control device of a system where software change is not easy. It is remarkable.

  In the present embodiment, the circuit structure for detecting the falling edge of the CPU reset pulse is used. However, the circuit structure for detecting the rising edge of the CPU reset pulse may be used.

1 Fault transfer output control circuit board (fault output countermeasure board)
2 terminals 3 IC3
10 Monitoring and Control Device 20 CPU Board 40 IC2

Claims (1)

A failure transfer output control circuit board that detects a rising or falling edge of a CPU reset pulse input that is output from the CPU board of the monitoring control device and performs a failure transfer output,
A current output circuit unit that outputs current by driving with the CPU reset pulse input, a charging circuit unit that charges the output current of the current output circuit unit within a predetermined time, and a charging voltage of the charging circuit unit is a predetermined reference A failure transfer output control circuit comprising: a comparison circuit unit that outputs a HIGH voltage when exceeding a voltage; and a transfer output circuit unit that receives an output from the comparison circuit unit and outputs a failure transfer output. substrate.

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