JP2010272691A - Thin film transistor substrate manufacturing method, thin film transistor substrate, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a TFT substrate with contact holes that are accurately formed by enhancing the accuracy of processing a contact etching, and to provide a method of manufacturing the TFT substrate which can reduce manufacturing costs without causing complication in manufacturing process of the TFT substrate. <P>SOLUTION: A resist layer 20 consisting of a thick resist part 21, a thin resist part 22 having a thinner thickness than the thick resist part and an opening 23, and having a pattern with a film thickness difference is provided, and an etching of an insulating film of the opening in the resist layer 20, a removal of the thin resist part 22 in the resist layer 20, and an etching of an insulating film of a lower layer of the thin resist part 22 are performed in a single etching process, thereby a gate contact hole 8 and a silicon contact hole 9 are formed to manufacture the TFT substrate 1. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a thin film transistor substrate, a thin film transistor substrate, and a display device using the thin film transistor substrate.

  A thin film transistor substrate (hereinafter also referred to as a TFT substrate) in which a thin film transistor (Thin Film Transistor) is provided on the surface of the substrate is known. The TFT substrate is used as a switching element of a display device such as an active matrix liquid crystal display device. The TFT substrate is configured, for example, by connecting a source electrode and a drain electrode to a polysilicon thin film as a semiconductor layer, and laminating a gate electrode on the upper or lower layer of the silicon thin film with a gate insulating film interposed therebetween.

  As shown in FIG. 12, the TFT substrate has a gate contact hole 102 for connecting to a gate electrode (gate wiring) 101 and a silicon for connecting a polysilicon thin film 103 to a source wiring (not shown). It is necessary to process the contact hole 104 at the same time. These contact holes 102 and 104 are usually formed after the polysilicon thin film 103, the gate insulating film 111, the gate electrode 101, and the interlayer insulating film 112 are provided on the surface of the substrate 110 as shown in FIG. Then, a resist pattern 113 is formed on the surface of the interlayer insulating film 112, and the interlayer insulating film 112 and the gate insulating film 111 are etched using the resist pattern 113 as a mask to perform hole processing.

  During the hole processing, if dry etching is performed in the state shown in FIG. 13A, the etching proceeds as shown in FIG. In the portion of the gate electrode 101, when the depth of the hole 102 a reaches the gate electrode 101, the hole 104 a on the polysilicon thin film 103 positioned below the gate electrode 101 does not reach the polysilicon thin film 103. . When etching is further performed from this state, a hole 104b reaching the polysilicon thin film 103 is formed as shown in FIG. On the other hand, the hole 102b on the gate electrode 101 is etched beyond the interlayer insulating film 112 to the portion of the gate electrode 101, and the film thickness of the gate electrode 101 is reduced. When the film reduction of the gate electrode proceeds, in the worst case, the gate electrode 101 is penetrated.

  In other words, as shown in FIG. 3C, the upper layer to be etched of the gate electrode 101 is only the interlayer insulating film 112. In order to form the gate contact hole 102, only the interlayer insulating film 112 needs to be etched. On the other hand, the layer to be etched above the polysilicon film 103 includes the gate insulating film 111 in addition to the interlayer insulating film 112. In order to form the silicon contact hole 104, it is necessary to etch both the interlayer insulating film 112 and the gate insulating film 111. When the gate contact hole 102 and the silicon contact hole 104 are simultaneously etched, the gate contact hole is excessively etched for the etching time of the gate insulating film 111. As a result, the film loss of the gate electrode 101 occurs.

  Therefore, if the gate contact hole 102 and the silicon contact hole 104 are etched at the same time, it is difficult to form the gate contact hole 102 and the silicon contact hole 104 together without reducing the thickness of the gate insulating film 101. It was.

  Patent Document 1 below describes means for improving the processing accuracy of a contact hole for a gate electrode and a polysilicon film when contact etching is performed in the manufacture of a TFT substrate. In this method, a silicon oxide film is formed as an etching stopper film on the gate electrode, dry etching is performed, the first stage etching is performed, and then the insulating film located below the etching stopper film is BHF wet etched. In this way, excessive etching of the gate insulating film and the polysilicon film itself is prevented by drilling.

Japanese Patent Laid-Open No. 2004-273797

  In order to increase the processing accuracy of contact etching, the contact hole forming method described in Patent Document 1 is effective. However, the method described in Patent Document 1 has a problem that it is necessary to provide a dry etching prevention film in the processing step. When the dry etching prevention film is formed, the number of processing steps is increased by one, which makes the operation complicated and increases the manufacturing cost.

  The present invention is intended to solve the above-mentioned problems of the prior art, and provides a TFT substrate on which contact holes are formed with high precision by increasing the processing accuracy of contact etching, and in manufacturing the TFT substrate. It is an object of the present invention to provide a method for manufacturing a TFT substrate capable of suppressing the manufacturing cost without complicating the process.

In order to solve such a problem, the manufacturing method of the TFT substrate of the present invention includes a semiconductor thin film formed via a gate insulating film and a laminate in which an insulating film is formed on the gate electrode. A method of manufacturing a thin film transistor substrate, wherein a gate contact hole formed on the gate electrode and a semiconductor contact hole formed on the semiconductor thin film are formed in the same lithography process,
The lithography step includes a resist forming step of forming a resist layer having a predetermined pattern on the surface of the insulating film, and an etching step of forming a contact hole by etching in the stacked body on which the resist layer is formed.
The resist layer in the etching step is a thick film resist portion formed in a hole non-formation region of the insulating film;
A thin film resist portion having a thickness smaller than that of the thick film resist portion formed in one of the contact regions of the gate contact region or the semiconductor contact region;
An opening formed in the other contact region of the gate contact region or the semiconductor contact region;
Formed as a pattern having a difference in film thickness,
The etching step includes etching the insulating film in the opening of the resist layer, removing the thin film resist portion of the resist layer, and etching the insulating film under the resist layer, thereby forming the gate contact hole and The gist is that the semiconductor contact holes are formed together.

The TFT substrate of the present invention is
A gate contact hole in the upper part of the gate electrode and a semiconductor contact hole in the upper part of the semiconductor thin film are formed in the same process on the semiconductor thin film and the gate electrode formed through the gate insulating film, In a thin film transistor substrate in which a source electrode is connected to the semiconductor thin film and a gate electrode through a contact hole,
The contact hole is
A thick film resist portion formed in a contact hole non-formation region of the insulating film;
A thin film resist portion having a thickness smaller than that of the thick film resist portion formed in one of the contact regions of the gate contact region or the semiconductor contact region;
Etching of the insulating film in the opening of the resist layer is provided with a patterned resist layer having a film thickness difference comprising an opening formed in the other contact region of the gate contact region or the semiconductor contact region And the removal of the thin film resist portion of the resist layer and the etching of the insulating film under the resist layer are performed, and the gate contact hole and the semiconductor contact hole are formed together. is there

  The gist of the display device of the present invention is that the above thin film transistor substrate is used as a switching element.

  The present invention provides a resist layer having a pattern having a film thickness difference consisting of a thick film resist portion, a thin film resist portion having a thickness smaller than that of the thick film resist portion, and an opening portion. Since the gate contact hole and the semiconductor contact hole are formed together by performing etching, removing the thin film resist portion of the resist layer, and etching the insulating film under the resist layer, contact Excessive etching can be prevented at the time of hole formation, and the processing accuracy of contact etching can be improved, and a TFT substrate on which contact holes are formed with high accuracy can be obtained. Furthermore, when manufacturing a TFT substrate having a contact hole with good accuracy, the manufacturing cost can be suppressed without complicating the manufacturing process.

FIGS. 1A and 1B are cross-sectional views showing the main part of a top gate type TFT substrate according to a first embodiment of the present invention. FIG. 2 is a plan view showing the main part of the TFT substrate of the embodiment of FIG. 1, showing a polysilicon thin film, a gate electrode, a source wiring, and a contact hole. 3A to 3D are cross-sectional views showing respective steps for explaining a manufacturing method of the TFT substrate shown in FIG. 4E to 4G are cross-sectional views showing respective steps for explaining the manufacturing method of the TFT substrate shown in FIG. FIGS. 5A and 5B are cross-sectional views of the main part of the resist forming process for forming the gate contact hole and the silicon contact hole. FIG. 5A shows a mask exposure state, and FIG. 5B shows a predetermined pattern. The resist layer is formed. FIG. 6 is a plan view of the multi-tone photomask used in FIG. FIG. 7 shows an embodiment of a multi-tone photomask, where (a) is a cross-sectional view of a halftone mask, and (b) is a cross-sectional view of a graytone mask. FIG. 8 is a cross-sectional view showing two binary masks. FIGS. 9A to 9D are cross-sectional views of the main part showing the etching process of the gate contact hole and the silicon contact hole. 10A to 10C are process diagrams showing the etching process of the second embodiment of the present invention. FIG. 11 is an explanatory view showing a cross section of the main part in a state in which the resist layer of the third embodiment of the present invention is formed. FIG. 12 is an explanatory diagram for explaining a conventional contact hole forming method. FIGS. 13A to 13C are explanatory diagrams when excessive etching occurs in the conventional contact hole forming method.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIGS. 1A and 1B are cross-sectional views showing a main part of a top gate type TFT substrate according to a first embodiment of the present invention. FIG. 1 (a), as shown in (b), TFT substrate 1, the thickness 0.5~0.7mm about the transparent non-alkali glass or the like _SiO 2 / SiNO the entire surface of the glass substrate 2 made of, SiO A base insulating film 3 as a contamination prevention film made of ₂ or the like is formed in a thickness of about 50 to 200 nm, and a semiconductor silicon thin film 4 is formed in a predetermined pattern as a semiconductor layer on the surface of the base insulating film 3. It is formed to a thickness of about. The semiconductor silicon thin film 4 includes an amorphous silicon (a-Si) thin film, a low-temperature polysilicon (LTPS) thin film, a high-temperature polysilicon (HTPS) thin film, a microcrystalline silicon (μc-Si) thin film, and a continuous grain boundary crystalline silicon (CGS) thin film. Etc. can be used.

Further, a gate insulating film 5 made of SiO ₂ , SiN, SiN / SiO ₂ or the like is provided on the entire surface of the semiconductor silicon thin film 4 to a thickness of about 200 to 500 nm, and W / TaN is formed on the surface of the gate insulating film 5. , Mo, MoW, Ti / Al and the like gate electrodes / wirings 6 and 16 (hereinafter, unless otherwise specified, the gate electrodes / wirings including the gate wiring may be referred to as gate electrodes) in a predetermined pattern. An interlayer insulating film 7 made of SiO ₂ / SIN, SiO ₂ / SiN / SiO ₂ , SiO ₂ , SiN or the like is formed on the entire surface of the gate electrode 6 with a thickness of about 100 to 300 nm. It is provided in a film thickness of about ~ 500 nm.

  Furthermore, on the interlayer insulating film 7, a source electrode 10 (source wiring) made of Ti / Al / Ti, Ti / Al, TiN / Al / TiN, Mo / Al-Nd / Mo, Mo / Al / Mo, etc. It is provided in a predetermined pattern with a film thickness of about 100 to 300 nm. The source electrode 10 includes a gate contact hole 8 and a silicon contact hole 9 on the gate electrode 16 of the insulating film (gate insulating film 5, interlayer insulating film 7) and on the polysilicon thin film 4. The source electrode 10 is connected to the gate electrode 16 and the polysilicon thin film 4 respectively, and the gate electrode 16 and the source electrode 10 and the polysilicon thin film 4 and the source electrode 10 are electrically connected.

  Furthermore, a protective film 11 made of an acrylic resin material or the like is provided on the entire surface of the source electrode 10 to a thickness of about 1000 to 3000 nm. Further, a transparent electrode 12 made of ITO (Indium tin Oxide), ZnO (zinc oxide), IZO (Indium zinc Oxide) or the like is formed on the protective film 11 in a predetermined pixel electrode pattern with a thickness of about 30 to 100 nm. Thickness is provided. The transparent electrode 12 is electrically connected to the underlying source electrode 10 using a contact hole 13 provided in the protective film 11.

  FIG. 2 is a plan view showing the main part of the TFT substrate of the embodiment of FIG. 1, showing a polysilicon thin film, a gate electrode, a source wiring, and a contact hole. 1A shows the AA cross section of FIG. 2, and FIG. 1B shows the BB cross section of FIG. FIG. 2 shows only a part of the TFT of the TFT substrate. Although not particularly illustrated, the TFT substrate 1 has a plurality of pixel electrodes (transparent electrodes) arranged in a matrix in a plan view. The TFT substrate has scanning signal lines (gate bus lines) 15 for supplying scanning signals to the pixel electrodes and data signal lines (data bus lines, power supply lines) 16 for supplying data signals. Are provided so as to cross each other. The TFT substrate 1 is provided with a TFT as a switching element at the intersection of the scanning signal line 15 and the data signal line 16. As shown in FIGS. 1A, 1B, and 2, each TFT includes a gate electrode 6 that is a part of a scanning wiring on a semiconductor silicon thin film 4 with a gate insulating film interposed therebetween. Source / drain electrodes 10 and 10 connected to a data signal line (power supply line) 15 are connected to positions on both sides of the gate electrode 6 of the silicon thin film 4.

  The source / drain electrodes 10 and 10 are connected to the data signal line 15 by the silicon contact hole 9. The gate wiring 16 and the data signal line 15 are connected by a gate contact hole 8.

  In the present invention, when forming a gate contact hole and a silicon contact hole of a TFT substrate, a thin film resist portion is provided in a thin portion of the insulating film forming the hole, and a portion having a thick insulating film forming the hole is opened. The gate contact hole and the semiconductor contact hole are formed by etching the insulating film at the opening of the resist layer, removing the thin film portion of the resist layer, and etching the insulating film below the resist layer. Are formed together. Hereinafter, a manufacturing method of the TFT substrate will be described.

FIGS. 3A to 3D and FIGS. 4E to 4G are cross-sectional views showing respective steps for explaining a method of manufacturing the TFT substrate shown in FIG. Here, an example of a method for manufacturing a TFT substrate using a low-temperature polysilicon thin film will be described. 3A to 3D and FIGS. 4E to 4G, the right side shows the silicon contact hole portion, and the left side shows the gate contact hole portion. Hereinafter, the whole manufacturing method of the TFT substrate will be described. First, as shown in FIG. 3A, after the glass substrate 2 is cleaned, a SiO ₂ / SiNO film is formed on the surface of the glass substrate 2 using a plasma CVD method or the like to form a base insulating film 3 on the entire surface.

  Next, an a-Si thin film is formed as a precursor on the entire surface by plasma CVD, dehydrogenation is performed by thermal annealing, and a laser beam is irradiated by excimer laser annealing to form an entire polysilicon film. Next, a polysilicon thin film 4 having a predetermined pattern is formed by lithography using resist pattern formation and dry etching.

  Next, as shown in FIG. 3B, a gate insulating film 5 is formed on the entire surface of the polysilicon thin film 4 by plasma CVD. Next, a metal film for forming the gate electrodes 6 and 16 is formed on the gate insulating film 5 by a sputtering method, and gate electrodes 6 and 16 having a predetermined pattern are formed by a lithography method by forming a resist pattern and etching ( (Refer FIG.3 (c)).

  Next, although not particularly illustrated, a resist pattern is formed in the n-type TFT region by mask exposure, and boron is applied to the source / drain regions of the polysilicon thin film in the p-type TFT region with the n-type TFT region masked. Implant by ion doping. Similarly, a resist pattern is formed in the p-type TFT region by mask exposure, and phosphorus is ion-doped and implanted into the source / drain regions of the polysilicon thin film in the n-type TFT region. Thereafter, an activation process of implanted ions is performed to reduce the resistance of the source / drain regions of the polysilicon thin film.

  Next, as shown in FIG. 3D, an interlayer insulating film 7 is formed on the entire surface of the gate electrodes 6 and 16 by plasma CVD.

  Next, as shown in FIG. 4E, the gate contact hole 8 and the semiconductor silicon thin film 4 above the gate electrode 16 are formed by a lithography process including a resist formation process for forming a resist pattern and an etching process for forming holes. The upper silicon contact hole 9 is formed. In the present invention, the gate contact hole 8 and the silicon contact hole 9 are formed by the same lithography process. The contact hole forming method is characterized in that a specific method is used (details of the contact hole forming method will be described later).

  Next, as shown in FIG. 4 (f), a Ti / Al / Ti film is formed on the entire surface of the interlayer insulating film in which the contact holes are formed by a sputtering method, and then predetermined by a lithography method using mask exposure and etching. Source / drain electrodes, source wirings, data signal lines and the like are formed in a pattern.

  Next, as shown in FIG. 4G, the protective film 11 on the source electrode and the contact hole 13 for joining the source electrode and the transparent conductive film at a predetermined position are formed by coating the entire surface of the photosensitive acrylic resin film. It is formed by mask exposure. And after forming an ITO film | membrane on the whole surface using sputtering method from the top, the transparent electrode 12 which consists of a transparent conductive film in a predetermined pattern shape is formed by the lithography method by mask exposure and etching, and it shows in FIG. A TFT substrate 1 is obtained.

  Hereinafter, a lithography process for forming the gate contact hole and the silicon contact hole will be described. The lithography process includes a resist forming process in which a resist layer 20 having a predetermined pattern is formed on the laminate in which the interlayer insulating film 7 is formed on the surface shown in FIG. 4D, and a laminate in which the resist layer 20 is formed. And an etching process in which drilling is performed by etching.

  FIGS. 5A and 5B are cross-sectional views of the main part of the resist forming process for forming the gate contact hole and the silicon contact hole. FIG. 5A shows a mask exposure state, and FIG. 5B shows a predetermined pattern. The resist layer is formed. In the resist forming step, as shown in FIG. 5A, first, a resist material is applied on the surface of the laminate on which the interlayer insulating film 7 is formed, and a photosensitive resist layer 18 is provided on the entire surface. Then, after performing exposure using a multi-tone photomask 30 made of a gray tone mask, development processing is performed. The multi-tone photomask 30 includes a light shielding portion 33, a transmitted light portion 31 that transmits light, and a semi-transmitted light portion 32.

  When the photosensitive resist layer 18 made of a negative resist material is exposed and developed using the multi-tone photomask 30, as shown in FIG. 5B, the pattern corresponding to the pattern of the multi-tone photomask 30 is obtained. A patterned resist layer 20 is formed. That is, the photosensitive resist layer 18 is formed as the thick film resist portion 21 by completely curing the portion corresponding to the transmitted light portion 31 of the multi-tone photomask 30. Further, the portion corresponding to the light shielding portion 33 of the multi-tone photomask 30 is an opening 23. Further, the portion corresponding to the semi-transmissive light portion 32 of the multi-tone photomask 30 is formed as a thin film resist portion 22 having a thickness smaller than that of the transmitted light portion 31 because the photosensitive resist layer 18 is not completely cured. Is done. In the resist layer 20, the portion corresponding to the transmitted light portion 31 becomes the thick film resist portion 21, the portion corresponding to the semi-transmitted light portion 32 becomes the thin film resist portion 32, and the portion corresponding to the light shielding portion 33 becomes the opening 23. Thus, it is formed as a pattern having a difference in film thickness.

  As shown in FIG. 5B, in the resist layer 20, the hole non-formation region on the surface of the interlayer insulating film 7 is formed as the thick film resist portion 21. A gate contact region on the gate electrode 16 is formed as a thin film resist portion 22 having a thickness smaller than that of the thick film resist portion 21. A silicon contact region on the semiconductor silicon thin film 4 which is a lower layer than the gate electrode 6 is formed as the opening 23.

  The hole non-formation region is an etching other than the gate contact region where the gate contact hole 8 of the gate electrode (gate wiring) 16 is formed and the silicon contact region where the silicon contact hole 9 of the semiconductor silicon thin film 4 is formed. It is the part that does not.

  FIG. 6 is a plan view of the multi-tone photomask used in FIG. The multi-tone photomask 30 in FIG. 6 corresponds to the pattern of the plan view of the TFT substrate in FIG. As shown in FIG. 6, in the multi-tone photomask 30, a portion where the silicon contact hole 9 reaching the lower layer side than the gate insulating film 5 is formed as a light shielding portion 33, and the gate contact above the gate insulating film 5 is formed. A portion where the hole 8 is formed is a semi-transmissive light portion 32, and the other portion is formed as a transmitted light portion 31. The semi-transmissive light portion 32 of the multi-tone photomask mask 30 corresponds to the thin-film resist portion 22 that is etched deep in the resist layer 20, and the light-shielding portion 33 of the multi-tone photomask 30 corresponds to the resist layer 20. Then, it corresponds to the opening 23 having a deep etching depth.

  As the resist material, a positive photosensitive resist material may be used in addition to the negative type material. When a positive photosensitive resist is used, a multi-tone photomask formed with the light shielding portion and the transmitted light portion reversed may be used.

  FIG. 7 shows an embodiment of a multi-tone photomask, where (a) is a cross-sectional view of a halftone mask, and (b) is a cross-sectional view of a graytone mask. A multi-tone photomask is a light-shielding part (black) and a light-transmitting part (white), and a binary mask whose pattern is composed of two gradations, a light-shielding part (black) and a light-transmitting part (white) that transmits light. It is configured as a photomask of three or more gradations composed of a semi-transmissive light portion (gray) that semi-transmits light in addition to the light portion (white). The multi-tone photomask includes a gray tone mask and a halftone mask. As a multi-tone photomask used for exposure, either a halftone mask 30A shown in FIG. 7A or a graytone mask 30B shown in FIG. 7B may be used.

  As shown in FIG. 7A, the halftone mask 30A reduces the amount of transmitted light by forming the light shielding film of the semi-transmissive light portion 32 thinner than the thickness of the light shielding portion 33 by means such as etching. Thus, the semi-transmissive light portion 32 is configured. As shown in FIG. 7B, the gray tone mask 30B has a semi-transmission light portion 32 formed by a light diffraction effect by providing a fine pattern below the exposure machine resolution limit as the semi-transmission light portion 32. It is. When a multi-tone photomask is used, a resist pattern with a film thickness difference can be formed by a single exposure and development when a resist layer with a film thickness difference is formed compared to when a binary mask is used. Therefore, the process can be shortened.

  As described above, any method can be used for forming the resist layer as long as it can form a difference in thickness of the resist layer depending on the location where the hole processing is desired. For example, instead of using a multi-tone photomask, a resist pattern having a film thickness difference may be formed using a binary mask.

  Photomasks such as multi-tone photomasks and binary masks are formed by forming a light-shielding film made of a metal thin film such as Cr on the surface of a transparent substrate such as a glass substrate. It can be manufactured by forming the part in a predetermined pattern.

  In order to form a resist pattern with a difference in film thickness using a binary mask, for example, a method using a plurality of binary masks with different transmitted light amounts or a plurality of binary masks can be used to partially change the exposure amount. And the like.

  FIG. 8 is a cross-sectional view showing two binary masks. For example, when a plurality of binary masks are used, as shown in FIG. 8, the first binary mask 41 provided with the light shielding portions 42 and 43 in the portions corresponding to the thin film resist portion 22 and the opening 23, and the opening 23. The second binary mask 45 provided with the light shielding portion 43 only in the portion to be used. First, when exposure and development are performed on the negative photosensitive resist layer using the first binary mask 41, the light shielding portions 42 and 43 become openings, and the transmitted light portion 44 becomes a thick film resist layer. It is formed. Further, when a photosensitive resist layer is applied and exposure and development are performed again using the second binary mask 45, the light shielding portion 43 is continuously formed as an opening. However, in the previous exposure and development, the portion of the light shielding portion 42 formed as the opening portion is not formed with the light shielding portion in the second binary mask, so the resist layer is cured and formed as a thin film resist layer. . Further, the portion corresponding to the transmitted light portion 44 is formed as the thick film resist portion 21 because the resist layer is formed by the previous exposure and development. As described above, the resist layer can be formed into a resist pattern having a film thickness difference.

  In order to form a resist pattern with a difference in film thickness using a plurality of binary masks, for example, when exposing a negative resist layer, the amount of light on the resist layer in the thin film resist portion is smaller than that in the thick film resist portion. As described above, the resist film thickness may be reduced by changing the exposure amount.

  FIGS. 9A to 9D are cross-sectional views of the main part showing the etching process of the gate contact hole and the silicon contact hole. In the etching process of the first embodiment, after the insulating film of the opening 23 is etched by a predetermined thickness, the thin film resist portion 22 of the resist layer 20 is removed, and the opening 23 and the removed thin film resist portion 22 are removed. The lower insulating film 7 is etched.

In the etching process, first, a contact first etching process is performed as shown in FIG. In the contact first etching step, an appropriate etching gas (C ₄ F ₈ , SF ₆ , CF ₄ , O ₂ , Ar, H _2, etc.) is used for the laminate provided with resist patterns having different film thicknesses. Dry etching is performed to etch the interlayer insulating film 7. The etching at this time is performed under the condition that the interlayer insulating film 7 can be etched but the thin film resist portion 22 of the resist layer is not etched. The interlayer insulating film 7 in the opening 23 is etched to form a part 9a of the silicon contact hole. On the other hand, the interlayer insulating film 7 on the gate electrode 16 is not etched because the thin film resist portion 22 is formed.

  In the contact first etching step, the film thickness D1 of the interlayer insulating film 7 on the gate electrode 16 after etching and the film thickness D2 of the insulating film (interlayer insulating film 7 + gate insulating film 5) on the semiconductor silicon thin film 4 are: In the next contact second etching step, it is preferable to perform etching so that the time required to etch all of the insulating film on the gate electrode and the insulating film on the semiconductor silicon thin film is the same time.

  Next, as shown in FIGS. 9B and 9C, a resist ashing process is performed. The resist ashing process is performed by ashing using a plasma ashing method in which the resist layer is decomposed with oxygen radicals, reduced in molecular weight, volatilized and removed from the laminated body in which the silicon contact hole 9 shown in FIG. Process. In the ashing process, the thin film resist portion 22 is removed. When the ashing process is performed, the resist layer 20 on the entire surface of the stacked body is processed as shown in FIG. 9B, and the film thicknesses of the thick film resist portion 21 and the thin film resist layer 22 decrease at the same speed. Then, ashing is stopped when the resist film in the thin film resist portion on the gate electrode disappears and becomes the opening 22b. At this time, as shown in FIG. 9C, the thick film resist portion 21 is thin, but the resist layer 20 itself remains.

  Next, as shown in FIG. 9D, a contact second etching step is performed. In the second contact etching process, as in the first contact etching process, dry etching using an appropriate etching gas is performed, and the remaining insulating film is etched. As shown in the figure, a gate contact hole 8 and a silicon contact hole 9 are formed. Thus, the gate contact hole 8 and the silicon contact hole 9 are formed together in the same etching process.

  In the contact first etching step, the etching is performed so that the time required to etch all of the interlayer insulating film 7 on the gate electrode 16 and the insulating films 5 and 7 on the semiconductor silicon thin film is the same time. Thus, the gate contact hole 8 can be prevented from being etched to the gate electrode 16 beyond the interlayer insulating film, or the silicon contact hole 9 can be prevented from being etched to the semiconductor silicon thin film 4. As a result, it is possible to prevent the film loss of the gate electrode 16, the increase in wiring resistance, the disconnection, and the like, and the film reduction and penetration of the semiconductor silicon thin film 4.

  A resist stripping step is performed after the second etching step. In the resist stripping step, the remaining resist layer 20 is removed. The resist layer 20 is removed by wet stripping in which the resist is removed with an organic alkali solution, dry stripping by ashing in which the resist is decomposed, reduced in molecular weight, volatilized and removed by oxygen radicals, or a combination of wet stripping and dry stripping. Any means may be used. The resist stripping means can be appropriately selected according to the material of the resist layer 20 and the like.

  10A to 10C are process diagrams showing the etching process of the second embodiment of the present invention. In the second embodiment, the etching process etches the insulating film in the opening 23 and simultaneously removes the thin film resist portion 22 of the resist layer and etches the insulating film under the thin film resist portion 22. .

In the etching process of the second embodiment, as shown in FIG. 10A, the resist layer 20 including the thick film resist portion 21, the thin film resist portion 22, and the opening 23 is formed in the resist forming step in the same manner as the first embodiment. The laminated body formed with is used. First, dry etching is performed using an appropriate etching gas (C ₄ F ₈ , SF ₆ , CF ₄ , O ₂ , Ar, H _2, etc.), and the interlayer insulating film 7 is etched. For the etching at this time, an etching condition having an etching rate for both the interlayer insulating film 7 and the resist layer 20 is selected. As a result, as shown in FIG. 10 a), the interlayer insulating film 7 is etched in the opening 23 of the resist layer 20, and the resist layer 20 is etched in the thick film resist portion 21 and the thin film resist portion 22.

  As shown in FIG. 10B, when the thin film resist portion 22 on the gate electrode 16 is completely removed, the etching of the insulating film (interlayer insulating film 7) on the semiconductor silicon thin film 4 proceeds halfway. Yes. At this time, the film thickness of the interlayer insulating film 7 on the gate electrode 16 and the film thickness of the insulating film on the semiconductor silicon thin film 4 are set to be the same as the time for removing these insulating films in the remaining etching. Is preferred. Specifically, the thickness of the thin film resist portion 22 and the thick film resist portion 21, the etching conditions for dry etching, and the like may be selected to satisfy the above conditions. Examples of the etching conditions include gas type, partial pressure, and discharge power.

  As shown in FIG. 10C, etching is further performed to remove the insulating film 7 on the gate electrode 16 and the insulating films 5 and 7 on the semiconductor silicon thin film 4, thereby forming the gate contact hole 8 and the silicon contact hole. 9 is formed. Thus, the gate contact hole 8 and the silicon contact hole 9 can be formed together in the same etching process.

  When performing this etching, if the removal of the thin film resist portion 22 and the etching of the interlayer insulating film 7 are performed so that the time for removing these remaining insulating films is the same, the gate electrode 16 and the semiconductor silicon thin film The time to reach 4 becomes the same time, and it is possible to reduce excessive etching.

  According to the second embodiment, compared with the first embodiment, there is an advantage that the resist film removal process by ashing can be reduced and the processing time can be shortened.

  FIG. 11 is an explanatory view showing a cross section of the main part in a state where the resist layer of the third embodiment of the present invention is formed. The third embodiment is an example in the case of manufacturing a TFT having a bottom gate structure as shown in FIG. The first and second embodiments are TFTs having a top gate structure, but the present invention can also be used for a TFT having a bottom gate structure as shown in the third embodiment.

  In a TFT having a bottom gate structure, for example, as shown in FIG. 11, a base insulating film 3 and gate electrodes 6 and 16 are provided on a glass substrate 2, and a semiconductor silicon thin film 4 is provided via a gate insulating film 5. A laminated body is configured. In this case, the resist layer 20 is provided with a thin film resist portion 22 above the semiconductor silicon thin film 4 (silicon contact region), an opening 23 above the gate electrode 16 (gate contact region), and other portions (holes). The non-formation region) is configured as a pattern having a film thickness difference including the thick film resist portion 21.

  The laminated body provided with the resist layer 20 having a pattern having a difference in film thickness shown in FIG. 11 is subjected to an etching process using the same etching method as in the first embodiment or the second embodiment, and the gate contact. Hole 8 and silicon contact hole 9 can be formed in the same processing step. That is, the TFT substrate of the third embodiment is also subjected to the etching of the insulating film in the opening 23 of the resist layer 20, the removal of the thin film resist portion 22 of the resist layer 20, and the etching of the insulating film underneath, 9 and the silicon contact hole 8 are formed together.

  The TFT substrate of the present invention can be used as an array substrate for an active matrix liquid crystal display element or the like. The TFT substrate of the present invention can be used as a switching device for various display elements other than liquid crystal display elements.

DESCRIPTION OF SYMBOLS 1 TFT substrate 2 Glass substrate 4 Semiconductor silicon thin film 5 Gate insulating films 6 and 16 Gate electrode 7 Interlayer insulating film 8 Gate contact hole 9 Silicon contact hole 10 Source electrode 20 Resist layer 21 Thick film resist part 22 Thin film resist part 23 Opening part 30 Multi-tone photomask 31 Transmitted light portion 32 Semi-transmitted light portion 33 Light shielding portion

Claims (17)

Formed in a stacked body in which an insulating film is formed on a semiconductor thin film and a gate electrode formed via a gate insulating film, and on a gate contact hole formed on the gate electrode and on the semiconductor thin film A method for manufacturing a thin film transistor substrate, wherein the semiconductor contact hole is formed in the same lithography process,
The lithography step includes a resist forming step of forming a resist layer having a predetermined pattern on the surface of the insulating film, and an etching step of forming a contact hole by etching in the stacked body on which the resist layer is formed.
The resist layer in the etching step is a thick film resist portion formed in a hole non-formation region of the insulating film;
A thin film resist portion having a thickness smaller than that of the thick film resist portion formed in one of the contact regions of the gate contact region or the semiconductor contact region;
An opening formed in the other contact region of the gate contact region or the semiconductor contact region;
Formed as a pattern having a difference in film thickness,
The etching step includes etching the insulating film in the opening of the resist layer, removing the thin film resist portion of the resist layer, and etching the insulating film under the resist layer, thereby forming the gate contact hole and A method of manufacturing a thin film transistor substrate, wherein the semiconductor contact holes are formed together.   After the etching step has etched the insulating film in the opening by a predetermined thickness, the thin film resist portion of the resist layer is removed, and the insulating film under the opening and the removed thin film resist portion is removed. The method of manufacturing a thin film transistor substrate according to claim 1, wherein:   3. The method of manufacturing a thin film transistor substrate according to claim 2, wherein a plasma ashing method is used to remove the thin film resist portion of the resist layer.   2. The thin film transistor according to claim 1, wherein the etching step etches the insulating film in the opening and simultaneously removes the thin film resist portion of the resist layer and etches a lower layer of the thin film resist portion. A method for manufacturing a substrate.   The method for manufacturing a thin film transistor substrate according to claim 1, wherein the etching in the etching step is dry etching.   The said resist formation process forms the said resist layer which has a film thickness difference by performing exposure using a multi-tone photomask, The any one of Claims 1-5 characterized by the above-mentioned. A method for manufacturing a thin film transistor substrate.   7. The method of manufacturing a thin film transistor substrate according to claim 6, wherein the multi-tone photomask is a gray tone mask.   7. The method of manufacturing a thin film transistor substrate according to claim 6, wherein the multi-tone photomask is a halftone mask.   The said resist formation process forms the said resist layer which has a film thickness difference by performing exposure using two types of masks from which transmitted light amount differs. A method for producing a thin film transistor substrate according to claim 1.   The said resist formation process forms the said resist layer which has a film thickness difference by changing each exposure amount using two types of masks, The any one of Claims 1-5 characterized by the above-mentioned. Manufacturing method of the thin film transistor substrate.   11. The thin film transistor according to claim 1, wherein the thin film transistor substrate has a top gate structure in which the gate electrode is provided on the semiconductor thin film via the gate insulating film. A method for manufacturing a substrate.   11. The thin film transistor substrate according to claim 1, wherein the thin film transistor substrate has a bottom gate structure in which the semiconductor thin film is provided on the gate electrode via a gate insulating film. Manufacturing method.   The method of manufacturing a thin film transistor substrate according to claim 1, wherein the semiconductor thin film is an amorphous silicon thin film.   The method of manufacturing a thin film transistor substrate according to claim 1, wherein the semiconductor thin film is a polysilicon thin film. A gate contact hole in the upper part of the gate electrode and a semiconductor contact hole in the upper part of the semiconductor thin film are formed in the same process on the semiconductor thin film and the gate electrode formed through the gate insulating film, In a thin film transistor substrate in which a source electrode is connected to the semiconductor thin film and a gate electrode through a contact hole,
The contact hole is
A thick film resist portion formed in a contact hole non-formation region of the insulating film;
A thin film resist portion having a thickness smaller than that of the thick film resist portion formed in one of the contact regions of the gate contact region or the semiconductor contact region;
Etching of the insulating film in the opening of the resist layer is provided with a patterned resist layer having a film thickness difference comprising an opening formed in the other contact region of the gate contact region or the semiconductor contact region A thin film transistor substrate, wherein the gate contact hole and the semiconductor contact hole are both formed by removing the thin film resist portion of the resist layer and etching the insulating film under the resist layer. .   16. A display device using the thin film transistor substrate according to claim 15 as a switching element.   The display device according to claim 16, wherein the thin film transistor substrate is used as an array substrate of a liquid crystal display device.

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