JP2010263149A - Semiconductor device - Google Patents

Abstract

【Task】
Provided is a semiconductor device that achieves both reduction in on-resistance of an IGBT and recovery characteristics of an FWD.
[Solution]
A first trench region, a first gate formed in the first trench region, and an emitter and a collector disposed in the thickness direction of the semiconductor layer are formed in a first region in the semiconductor layer. An IGBT for controlling a current flowing in the thickness direction of the semiconductor layer by controlling the potential of the first gate; and a second trench formed in a second region adjacent to the first region in the semiconductor layer. Region, a second gate formed in the second trench region, a base and a collector that are spaced apart in the thickness direction of the semiconductor layer, and a bottom formed in the second trench. FWD having a crystal defect region or lifetime control region in which the semiconductor layer is controlled, and by controlling the potential of the second gate when the FWD is turned off, the residual carriers in the semiconductor layer are converted into the crystal defect region or lifetime. To collect in your area.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device including an insulated gate bipolar transistor (IGBT) and a free wheeling diode (FWD).

  Conventionally, there has been a semiconductor device in which an insulated gate bipolar transistor (IGBT) and a free wheel diode (FWD) are formed in the same semiconductor layer. As such a semiconductor device, there is a semiconductor device in which a low lifetime layer extending in the width direction is formed in the drift layer of both the IGBT region and the FWD region (for example, see Patent Document 1).

  In addition, by irradiating electrons or the like from the lower side in the stacking direction of the semiconductor layer and forming a recombination region in the drift layer of the FWD region, traps carriers in the drift layer during FWD recovery and recovers the FWD. Some semiconductor devices have improved characteristics (see, for example, Patent Document 2).

JP 2005-317751 A JP 2007-103770 A

  However, in the semiconductor device in which the low lifetime layer extending in the width direction is formed in the drift layer of both the IGBT region and the FWD region, the on-resistance of the IGBT is increased due to the existence of the low lifetime layer in the drift layer of the IGBT region. However, there is a problem that the loss increases.

  Further, in a semiconductor device in which a recombination region is formed in the drift layer of the FWD region, only the FWD region is selected from the adjacent IGBT region and FWD region to form the recombination region, so that mask patterning is required. Therefore, there is a problem that the number of processes increases and the cost increases. In addition, since the recombination regions are scattered in the width direction in the entire drift layer, there is a problem that the recovery characteristics of the FWD cannot be sufficiently improved.

  Therefore, an object of the present invention is to provide a semiconductor device that achieves both reduction of the on-resistance of the IGBT and securing of sufficient FWD recovery characteristics.

  A semiconductor device according to one aspect of the present invention is formed in a first region in a semiconductor layer, and includes a first trench region, a first gate formed in the first trench region, and a thickness direction of the semiconductor layer. An IGBT having an emitter and a collector disposed apart from each other, and controlling an electric current flowing in a thickness direction of the semiconductor layer by controlling a potential of the first gate, and the first in the semiconductor layer A base formed in a second region adjacent to one region, a second trench region, a second gate formed in the second trench region, and a base spaced apart in the thickness direction of the semiconductor layer And a collector and a FWD formed at the bottom of the second trench and having a crystal defect region or a lifetime control region whose potential is controlled by the second gate, and the second gate is turned off when the FWD is off. Power of By controlling the collects residual carriers in the semiconductor layer by the crystalline defect region or the lifetime control region.

  According to the present invention, it is possible to provide a specific effect that it is possible to provide a semiconductor device that achieves both reduction of the on-resistance of the IGBT and ensuring of sufficient FWD recovery characteristics.

1 is a diagram illustrating a cross-sectional structure of a semiconductor device according to a first embodiment. FIG. 3 is a diagram showing steps for manufacturing the semiconductor device 100 according to the first embodiment; FIG. 10 is a diagram showing a method for manufacturing the semiconductor device of the second embodiment. FIG. 10 is a diagram illustrating a method of manufacturing a semiconductor device according to a modification example of the second embodiment. FIG. 10 is a diagram showing a method for manufacturing the semiconductor device of the third embodiment. FIG. 10 is a diagram showing a method for manufacturing the semiconductor device of the fourth embodiment. FIG. 10 is a diagram showing a method for manufacturing the semiconductor device of the fifth embodiment. FIG. 10 is a diagram showing a method for manufacturing the semiconductor device of the sixth embodiment. It is a figure which shows the semiconductor device and manufacturing method of Embodiment 7. FIG.

  Hereinafter, embodiments to which the semiconductor device of the present invention is applied will be described.

[Embodiment 1]
FIG. 1 is a diagram showing a cross-sectional structure of the semiconductor device of the first embodiment.

  Semiconductor device 100 of the first embodiment includes IGBT 10 and FWD 20 formed inside a semiconductor layer. The IGBT 10 and the FWD 20 are each formed in adjacent regions in the semiconductor layer. Here, FIG. 1 shows a set of IGBTs 10 and FWDs 20, but actually, the semiconductor device 100 includes a plurality of sets of IGBTs 10 and FWDs 20 to drive an electrical load represented by a motor. Used. Hereinafter, the structure and manufacturing method of the IGBT 10 and the FWD 20 will be described.

  The semiconductor layer in which the IGBT 10 and the FWD 20 are formed includes an n drift layer 101 manufactured by implanting impurities (typically phosphorus (P)) into a silicon wafer (semiconductor substrate), and an upper layer of the n drift layer 101. And a p base layer 102 formed by implanting impurities (typically boron (B)).

  That is, the IGBT 10 and the FWD 20 are formed in adjacent regions (first region and second region) inside the n drift layer 101 and the p base layer 102.

  IGBT 10 includes a gate electrode 110 formed in a trench 103 </ b> A that reaches the upper layer portion of n drift layer 101 from the upper surface of p base layer 102.

  The gate electrode 110 is formed via a gate oxide layer 104A formed in the trench 103A.

  FWD 20 also includes a gate electrode 120 formed in trench 103B that reaches the upper layer portion of n drift layer 101 from the upper surface of p base layer 102.

  The gate electrode 120 is formed via a gate oxide layer 104B formed in the trench 103B.

  The gate oxide films 104A and 104B are formed by, for example, performing oxidation by thermal oxidation treatment on the inner surfaces of the trenches 103A and 103B. The gate electrodes 110 and 120 are made of polysilicon, for example.

  A crystal defect layer 130 is formed in the n drift layer 101 below the trench 103B in the FWD 20. The crystal defect layer 130 is formed only in the n drift layer 101 below the trench 103B and is not formed in the IGBT 10. A method for manufacturing the crystal defect layer 130 will be described later.

  Further, an external power source 132 is connected to the gate electrode 120 via a switch 131, and a negative voltage is applied to the gate electrode 120 when the switch 131 is closed. The operation and effect of opening / closing the switch 131 and applying a negative voltage will be described later.

  A p + contact layer 105 and an n + diffusion layer 106 are formed in the upper layer portion of the p base layer 102. The p + contact layer 105 is a semiconductor region whose impurity concentration is set higher than that of the p base layer 102 by injecting an impurity (typically boron (B)) from the surface of the p base layer 102. The n + diffusion layer 106 is a semiconductor region whose conductivity type is changed to n-type by implanting impurities (typically arsenic (As)) after forming the p + contact layer 105, for example. Here, since the impurity concentration of the n + diffusion layer 106 is higher than that of the n drift layer 101, the conductivity type is shown as n + type.

  The p + contact layer 105 and the n + diffusion layer 106 are arranged in the IGBT 10 such that the n + diffusion layer 106 is disposed on both sides of the trench 103A where the gate electrode 110 is formed, and the p + contact layer is adjacent to the n + diffusion layer 106. 105 is disposed. In the FWD 20, the p + contact layer 105 is disposed on both sides of the trench 103B where the gate electrode 120 is formed.

  The p + contact layer 105 in the IGBT 10 functions as a contact layer for preventing latch-up, and the n + diffusion layer 106 functions as a diffusion layer for injecting electrons. Further, the p + contact layer 105 in the FWD 20 functions as the base of the FWD 20.

  Further, a p collector layer 107 and an n collector layer 108 are formed in the lower layer portion of the n drift layer 101. The p collector layer 107 is formed by pouring impurities (typically boron (B)) from the back surface (the lower surface in FIG. 1) of the n drift layer 101. The n collector layer 108 is fabricated by implanting impurities (typically phosphorus (P)) from the back surface (the lower surface in FIG. 1) of the n drift layer 101.

  The p collector layer 107 is a semiconductor layer that is formed in a region included in the IGBT 10 in the n drift layer 101 and serves as a collector of the IGBT 10.

  The n collector layer 108 is a semiconductor layer that is formed in a region included in the FWD 20 in the n drift layer 101 and serves as a collector of the FWD 20.

  Here, in order to explain the operation of the IGBT 10 and the FWD 20, as an example, the semiconductor device 100 includes four sets of the IGBT 10 and the FWD 20 and constitutes a bridge circuit that drives the motor. That is, a motor is connected between a pair of midpoints of a bridge circuit including four sets of IGBTs 10 and FWDs 20, and the bridge circuit converts a DC voltage supplied from a DC power source into an AC voltage to drive the motor AC. It shall be configured.

  In such a semiconductor device 100, when a gate voltage is applied to the gate electrode 110 in a state where a bias is applied between the emitter and collector of the IGBT 10 existing on the diagonal of the bridge circuit so as to increase the collector potential, A channel is formed in the vicinity of 110, and a current flows in a direction from the n drift layer 101 to the p base layer 102 in the IGBT 10. As a result, current is supplied to the motor through the two IGBTs 10 positioned diagonally.

  Further, when one of the IGBTs 10 is turned off by cutting off the application of the gate voltage to the gate electrode 110 of one of the two IGBTs 10 located diagonally, the n drift layer in the IGBT 10 The current flowing from 101 to the p base layer 102 becomes zero.

  At this time, an induced electromotive force is generated in the motor connected to the bridge circuit, and this induced electromotive force is generated in the n drift layer 101 and the p base layer 102 of the IGBT 10 that is turned on and the FWD 20 that forms a closed circuit with the motor. Applied. Thereby, the FWD 20 is turned on, and a current flows in a direction from the p base layer 102 in the FWD 20 toward the n drift layer 101.

  By repeating such an operation, the FWD 20 included in the bridge circuit is turned on when any of the IGBTs 10 is turned off, and an AC voltage is supplied to the motor from the bridge circuit.

  By the way, in the semiconductor device 100 of the first embodiment, the switch 131 is closed and the negative voltage is applied to the gate electrode 120 at the timing when the FWD 20 is turned off as described above. Further, at the timing when the FWD 20 is turned on, the switch 131 is opened, and application of a negative voltage to the gate electrode 120 is cut off. The opening / closing control of the switch 131 may be performed by the driving device for driving the semiconductor device 100 of the first embodiment together with the on / off control of the IGBT 10, or the driving for performing the control separately from the on / off control of the IGBT 10. You may carry out by a circuit.

  Since the negative voltage applied when the FWD 20 is turned off is applied to the crystal defect layer 130, when the FWD 20 is turned off, holes remaining as residual carriers in the n drift layer 101 in the FWD 20 are removed from the crystal defect layer. It can be collected in 130 and quickly disappear.

  For this reason, since the FWD 20 is quickly turned off, the recovery characteristics of the FWD 20 can be improved.

  Further, as described above, the crystal defect layer 130 is formed only under the gate electrode 120 in the FWD 20 and is not formed in the IGBT 10. Therefore, unlike the conventional semiconductor device, the on-resistance of the IGBT 10 does not increase. In addition, the on-resistance of the FWD 20 can be reduced as compared with the conventional case.

  Therefore, according to the first embodiment, it is possible to provide the semiconductor device 100 in which the recovery characteristics of the FWD 20 are improved without increasing the on-resistance of the IGBT 10.

  In addition, the semiconductor device 100 of the first embodiment can be manufactured without adding a step of performing patterning for the back surface process as in the conventional semiconductor device. Hereinafter, the manufacturing method will be described.

  FIG. 2 is a diagram showing a step-by-step method of manufacturing semiconductor device 100 of the first embodiment.

  First, as shown in FIG. 2A, trenches 103A and 103B are formed by performing anisotropic etching in a state where a silicon oxide film 151 is formed on the n drift layer 101 as a mask. Note that a silicon nitride film or a resist may be formed instead of the silicon oxide film 151 as a mask.

  Next, a thermal oxidation process is performed on the inner surfaces of the trenches 103A and 103B to form the gate oxide layers 104A and 104B, and then a resist 152 such as an organic film is applied to a region where the IGBT 10 is to be formed. ).

  The resist 152 is formed only in a region where the IGBT 10 is formed, and is patterned so as not to be formed in a region where the FWD 20 is formed.

  In addition, the resist 152 prevents inert ions from reaching the bottom of the trench 103A in the region where the IGBT 10 is formed when implanting inert ions or the like into the bottom of the trench 103B in the region where the FWD 20 is formed in a later step. It is necessary to have a thickness capable of protecting the bottom of the trench 103A.

  Note that a silicon oxide film, a silicon nitride film, or the like may be formed instead of the resist 152.

  Next, by using the silicon oxide film 151 and the resist 152 as a shielding film and irradiating inert ions into the trench 103B, as shown in FIG. 2C, the n drift layer 101 at the bottom of the trench 103 is formed. Then, the crystal defect layer 130 is formed.

  At this time, if the crystal defect layer 130 is formed deeper in the n drift layer 101 than the bottom of the trench 103B because the range of the inert ions is too long, as shown in FIG. The depth at which the crystal defect layer 130 is formed may be adjusted by forming a buffer layer 153 made of a resist such as an organic film or a silicon oxide film at the bottom of the trench 103B.

  Next, the silicon oxide film 151 and the resist 152 are removed from the state shown in FIG. 2C (or the silicon oxide film 151, the resist 152, and the buffer layer 153 are removed from the state shown in FIG. 2D). As a result, the trenches 103A and 103B and the upper surface of the n drift layer 101 are exposed as shown in FIG.

  Thereafter, the p base layer 102, the gate oxide layer 104A, the gate oxide layer 104B, the p + contact layer 105, the n + diffusion layer 106, the p collector layer 107, the n collector layer 108, the gate electrode 110, and the gate electrode 120 are formed. As a result, the semiconductor device 100 shown in FIG. 2F is obtained.

  Since the semiconductor device 100 shown in FIG. 2F is the same as the semiconductor device 100 shown in FIG. 1, the switch 131 (see FIG. 1) is turned on when the IGBT 10 is turned on (that is, when the FWD 20 is turned off). The gate electrode 120 is closed and a negative voltage is applied to the gate electrode 120. When the IGBT 10 is turned off, the switch 131 (see FIG. 1) is opened, and application of a negative voltage to the gate electrode 120 is cut off.

  Since the negative voltage applied when the FWD 20 is turned off is applied to the crystal defect layer 130, when the FWD 20 is turned off, holes remaining as residual carriers in the n drift layer 101 in the FWD 20 are removed from the crystal defect layer. It can be collected in 130 and quickly disappear. As a result, the FWD 20 is quickly turned off.

  Therefore, the recovery characteristics of the FWD 20 can be improved without increasing the on-resistance of the IGBT 10.

  As described above, according to the first embodiment, it is possible to provide the semiconductor device 100 in which the recovery characteristics of the FWD 20 are improved without increasing the on-resistance of the IGBT 10.

Examples of the inert ions implanted to form the crystal defect layer 130 include neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe). Further, protons, electrons, helium (He), or oxygen (O ₂ ) may be used instead of the inert ions.

[Embodiment 2]
FIG. 3 shows a method for manufacturing the semiconductor device of the second embodiment.

  The semiconductor device of the second embodiment is different from the method of manufacturing the semiconductor device of the first embodiment in the method for manufacturing the crystal defect layer 130. Since the other components are the same as those of the semiconductor device 100 of the first embodiment, the same components are denoted by the same reference numerals, and the description thereof is omitted.

  The state shown in FIG. 3A is the same as the state shown in FIG. 2A. After the silicon oxide film 151 is formed on the n drift layer 101 as a mask, anisotropic etching is performed. In this state, trenches 103A and 103B are formed.

  Next, after removing the silicon oxide film 151, as shown in FIG. 3B, the trenches 103A and 103B are all buried and the upper surface of the n drift layer 101 has a predetermined thickness (SiN film). ) 154 is formed. Instead of forming the silicon nitride film 154, a silicon germanium (SiGe) film or a silicon carbide (SiC) film may be formed.

  Here, before forming the silicon nitride film 154, for example, a silicon oxide film may be formed as a protective film on the inner surface of the trench 130A. This is an effective treatment for further improving the electrical characteristics of the IGBT 10 to be formed later.

  Next, the silicon nitride film 154 is etched back by anisotropic etching to leave the silicon nitride films 154A and 154B partially only at the bottoms of the trenches 130A and 130B. This state is the state shown in FIG.

  Further, when the silicon nitride film 154A in the trench 103A is removed by covering the region where the FWD 20 is formed with a mask, the silicon nitride film 154B is left only at the bottom of the trench 103B as shown in FIG. become.

  Subsequently, when the silicon nitride film 154B in the trench 103B is crystallized by performing heat treatment, stress is generated at the interface between the silicon nitride film 154B and the n drift layer 101 when crystallization occurs. Then, a defect occurs in the coupling in the n drift layer 101 at the bottom of the trench 103B, and a crystal defect layer 130 is formed as shown in FIG.

  After the formation of the crystal defect layer, the silicon nitride film 154B crystallized at the bottom of the trench 103B is removed, thereby removing the upper surfaces of the trenches 103A and 103B and the n drift layer 101 as shown in FIG. Get a bare state.

  Thereafter, the p base layer 102, the gate oxide layer 104A, the gate oxide layer 104B, the p + contact layer 105, the n + diffusion layer 106, the p collector layer 107, the n collector layer 108, the gate electrode 110, and the gate electrode 120 are formed. As a result, the semiconductor device 100 shown in FIG. 3E, the p base layer 102, the gate oxide layer 104A, the gate oxide layer 104B, the p + contact layer 105, the n + diffusion layer 106, the p collector layer 107, the n collector layer 108, the gate electrode 110, and When heat treatment is performed when forming the gate electrode 120 or the like, the heat treatment may be performed under a temperature condition that does not cause the crystal defect layer 130 to disappear.

  Since the semiconductor device 100 shown in FIG. 3G is the same as the semiconductor device 100 shown in FIG. 1, the switch 131 (see FIG. 1) is turned on when the IGBT 10 is turned on (that is, when the FWD 20 is turned off). The gate electrode 120 is closed and a negative voltage is applied to the gate electrode 120. When the IGBT 10 is turned off, the switch 131 (see FIG. 1) is opened, and application of a negative voltage to the gate electrode 120 is cut off.

  Since the negative voltage applied when the FWD 20 is turned off is applied to the crystal defect layer 130, when the FWD 20 is turned off, holes remaining as residual carriers in the n drift layer 101 in the FWD 20 are removed from the crystal defect layer. It can be collected in 130 and quickly disappear. As a result, the FWD 20 is quickly turned off.

  Therefore, it is possible to provide the semiconductor device 100 with improved recovery characteristics of the FWD 20 without increasing the on-resistance of the IGBT 10.

  Incidentally, after the step shown in FIG. 3E, the gate oxide film 104B and the gate electrode 120 may be formed in a state where the silicon nitride film 154B is left without being removed.

  In this case, the structure of the semiconductor device 100 is as shown in FIG. 4, but even when the silicon nitride film 154B is left at the bottom of the trench 103B as described above, the silicon nitride film 154B at the bottom of the trench 103B is removed. Similar to the formed semiconductor device, it is possible to provide the semiconductor device 100 in which the recovery characteristics of the FWD 20 are improved without increasing the on-resistance of the IGBT 10.

[Embodiment 3]
FIG. 5 shows a method for manufacturing the semiconductor device of the third embodiment.

  The semiconductor device of the third embodiment is different from the method of manufacturing the semiconductor device of the first and second embodiments in the method for producing the crystal defect layer 130. The other components are the same as those of the semiconductor device of the first to third embodiments, and thus the same components are denoted by the same reference numerals and the description thereof is omitted.

  As shown in FIG. 5A, trenches 103A and 103B are formed by performing anisotropic etching in a state where a silicon oxide film 151 is formed on the n drift layer 101 as a mask.

  At this time, the width of the trench 103B is set to be narrower than the width of the trench 103A by a predetermined width.

  Since anisotropic etching generally has a higher etching rate when the width is narrower, in Embodiment 3, the trench 103B is formed to be narrower and deeper than the trench 103A using this.

  Next, a silicon nitride film 154 is formed in the trenches 103A and 103B and on the upper surface of the n drift layer 101, and further, an anisotropic etching process is performed until the silicon nitride film 154 in the trench 103A is completely removed. Etch back.

  As a result, the upper surface of the n drift layer 101 and the silicon nitride film 154 in the trench 103A are all removed, and the silicon nitride film 154B remains only at the bottom of the trench 103B.

  The etching rate for etching back the silicon nitride film 154 may be adjusted so that the silicon nitride film 154B remains only at the bottom of the trench 103B.

  Thereafter, similarly to FIG. 3D and subsequent drawings of the second embodiment, the silicon nitride film 154B is crystallized by heat treatment to form the crystal defect layer 130 in the n drift layer 101 at the bottom of the trench 103B. can do.

  Further, by forming the p base layer 102, the gate oxide layer 104A, the gate oxide layer 104B, the p + contact layer 105, the n + diffusion layer 106, the p collector layer 107, the n collector layer 108, the gate electrode 110, and the gate electrode 120. A semiconductor device is obtained.

  The semiconductor device of the third embodiment is the same as the semiconductor device shown in FIGS. 1, 2 (f), and 3 (g) except that the trench 103B is narrower and deeper than the trench 103A. is there.

  Therefore, when the IGBT 10 is turned on (that is, when the FWD 20 is turned off), the switch 131 (see FIG. 1) is closed and a negative voltage is applied to the gate electrode 120. When the IGBT 10 is turned off, the switch 131 (see FIG. 1) is opened, and application of a negative voltage to the gate electrode 120 is cut off.

  Since the negative voltage applied when the FWD 20 is turned off is applied to the crystal defect layer 130, when the FWD 20 is turned off, holes remaining as residual carriers in the n drift layer 101 in the FWD 20 are removed from the crystal defect layer. It can be collected in 130 and quickly disappear. As a result, the FWD 20 is quickly turned off.

  Therefore, it is possible to provide the semiconductor device 100 with improved recovery characteristics of the FWD 20 without increasing the on-resistance of the IGBT 10.

  Further, in the semiconductor device of Embodiment 3, since the trench 103B is narrower and deeper than the trench 103A, as shown in FIG. 3D in Embodiment 2, the region where the FWD 20 is formed is covered with a mask. Thus, the step of removing the silicon nitride film 154A in the trench 103A can be omitted, and the manufacturing process can be simplified.

  Note that the silicon nitride film 154B at the bottom of the trench 103B may be left without being removed. In this case, the semiconductor device has a structure in which the trench 103B of the semiconductor device shown in FIG.

[Embodiment 4]
FIG. 6 shows a method for manufacturing the semiconductor device of the fourth embodiment.

  The semiconductor device of the fourth embodiment is different from the method of manufacturing the semiconductor device of the first to third embodiments in the method for manufacturing the crystal defect layer 130.

  In the third embodiment, trench 103B is formed to be narrower and deeper than trench 103A, and the silicon nitride film 154A in trench 103A is removed by covering with a mask using the difference in the etching rate of anisotropic etching. The form which can omit a process was demonstrated.

  In contrast, in the semiconductor device of the fourth embodiment, the trenches 103A and 103B have the same depth, but the trench 103B is made wider so that the difference in the etching rate of the silicon nitride film 154 is utilized. The difference from Embodiment 3 is that the silicon nitride film 154B is left only at the bottom of the trench 103B.

  Since other configurations are basically the same as those of the semiconductor device of the first to third embodiments, the same components are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 6A, trenches 103 </ b> A and 103 </ b> B are formed by performing anisotropic etching with the silicon oxide film 151 formed as a mask on the n drift layer 101.

  At this time, the width of the trench 103B is set wider by a predetermined width than the width of the trench 103A.

  In the fourth embodiment, the anisotropic etching conditions are adjusted so that the trenches 103A and 103B have the same depth and the trench 103B is wider than the trench 103A, and the trench 103A is etched back. And 103B are formed.

  Next, the silicon nitride film 154 is formed inside the trenches 103A and 103B and on the upper surface of the n drift layer 101, and further etched by anisotropic etching until the nitride film 154 in the trench 103A is completely removed. Back.

  Then, by further adjusting the anisotropic etching conditions, as shown in FIG. 6B, the upper surface of the n drift layer 101 and the silicon nitride film 154 in the trench 103A are all removed, and the bottom of the trench 103B is formed. Only the silicon nitride film 154B is left.

  Thereafter, similarly to FIG. 3D and subsequent drawings of the second embodiment, the silicon nitride film 154B is crystallized by heat treatment to form the crystal defect layer 130 in the n drift layer 101 at the bottom of the trench 103B. can do.

  Further, by forming the p base layer 102, the gate oxide layer 104A, the gate oxide layer 104B, the p + contact layer 105, the n + diffusion layer 106, the p collector layer 107, the n collector layer 108, the gate electrode 110, and the gate electrode 120. A semiconductor device is obtained.

  The semiconductor device of the fourth embodiment is the same as the semiconductor device shown in FIGS. 1, 2 (f), and 3 (g) except that the trench 103B is formed wider than the trench 103A.

  Therefore, when the IGBT 10 is turned on (that is, when the FWD 20 is turned off), the switch 131 (see FIG. 1) is closed and a negative voltage is applied to the gate electrode 120. When the IGBT 10 is turned off, the switch 131 (see FIG. 1) is opened, and application of a negative voltage to the gate electrode 120 is cut off.

  Since the negative voltage applied when the FWD 20 is turned off is applied to the crystal defect layer 130, when the FWD 20 is turned off, holes remaining as residual carriers in the n drift layer 101 in the FWD 20 are removed from the crystal defect layer. It can be collected in 130 and quickly disappear. As a result, the FWD 20 is quickly turned off.

  Therefore, it is possible to provide the semiconductor device 100 with improved recovery characteristics of the FWD 20 without increasing the on-resistance of the IGBT 10.

  Further, in the semiconductor device of the fourth embodiment, since the trench 103B is wider than the trench 103A, the region where the FWD 20 is formed is covered with a mask as shown in FIG. The step of removing the inner silicon nitride film 154A can be omitted, and the manufacturing process can be simplified.

  Note that the silicon nitride film 154B at the bottom of the trench 103B may be left without being removed. The structure of the semiconductor device in this case is such that the trench 103B of the semiconductor device shown in FIG.

[Embodiment 5]
FIG. 7 shows a method for manufacturing the semiconductor device of the fifth embodiment.

  The semiconductor device of the fourth embodiment differs from the method of manufacturing the semiconductor device of the first to fourth embodiments in the method for manufacturing the crystal defect layer 130.

  In the fourth embodiment, in the semiconductor device of the fourth embodiment, by making the width of the trench 103B wider than the trenches 103A and 103B, the difference in the etching rate of the silicon nitride film 154 is utilized to make only the bottom of the trench 103B. The silicon nitride film 154B was left.

  In contrast, the semiconductor device of the fifth embodiment has a wider trench 103B than that of the fourth embodiment, so that the method for manufacturing the crystal defect layer 130 is different from that of the fourth embodiment.

  Since other configurations are basically the same as those of the semiconductor device of the first to fourth embodiments, the same components are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 7A, the trench 103B is formed wider than the trench 103A by a predetermined width, and then a silicon nitride film 154 is formed. Since the width of the trench 103B is set to a sufficiently wide width, the trench 103B is not completely filled with the silicon nitride film 154.

  Next, as shown in FIG. 7B, a resist 152 is applied only on the silicon nitride film 154 in the trench 103B.

  Etching back the silicon oxide film 151 by anisotropic etching leaves the silicon nitride film 154B and the resist 152 only at the bottom of the trench 103B, as shown in FIG. 7C.

  Further, when the heat treatment is performed after removing the resist 152, the silicon nitride film 154B is crystallized, and the crystal defect layer 130 is formed at the interface with the n drift layer 101.

  Thereafter, the p base layer 102, the gate oxide layer 104A, the gate oxide layer 104B, the p + contact layer 105, the n + diffusion layer 106, the p collector layer 107, the n collector layer 108, the gate electrode 110, and the gate electrode 120 are formed. As a result, the semiconductor device of the fifth embodiment is obtained.

  The semiconductor device of the fifth embodiment is the same as the semiconductor device shown in FIGS. 1, 2 (f), and 3 (g) except that the trench 103B is formed wider than the trench 103A.

  Therefore, when the IGBT 10 is turned on (that is, when the FWD 20 is turned off), the switch 131 (see FIG. 1) is closed and a negative voltage is applied to the gate electrode 120. When the IGBT 10 is turned off, the switch 131 (see FIG. 1) is opened, and application of a negative voltage to the gate electrode 120 is cut off.

  Since the negative voltage applied when the FWD 20 is turned off is applied to the crystal defect layer 130, when the FWD 20 is turned off, holes that are residual carriers remaining in the n drift layer 101 in the FWD 20 are removed from the crystal defect layer. It can be collected in 130 and quickly disappear. As a result, the FWD 20 is quickly turned off.

  Therefore, it is possible to provide the semiconductor device 100 with improved recovery characteristics of the FWD 20 without increasing the on-resistance of the IGBT 10.

  In the semiconductor device of the fifth embodiment, since the trench 103B is wider than the trench 103A, the region where the FWD 20 is formed is covered with a mask as shown in FIG. The step of removing the inner silicon nitride film 154A can be omitted, and the manufacturing process can be simplified.

  Note that the silicon nitride film 154B at the bottom of the trench 103B may be left without being removed. The structure of the semiconductor device in this case is such that the trench 103B of the semiconductor device shown in FIG.

[Embodiment 6]
FIG. 8 shows a method for manufacturing the semiconductor device of the sixth embodiment.

  The semiconductor device of the sixth embodiment is different from the manufacturing method of the semiconductor device of the first to fifth embodiments in the method for manufacturing the crystal defect layer 130.

As shown in FIG. 8A, in the sixth embodiment, oxygen ions are implanted into the n drift layer 101. This ion implantation may be performed with an implantation amount of, for example, about 1e ¹⁸ / cm ² so that the oxygen ion implantation layer 155 is formed in a region where the bottom of the trench 103B formed in a later step is located.

  Next, heat treatment is performed to change the oxygen ion implanted layer 155 to the silicon oxide layer 155A. This heat treatment may be performed, for example, at 1100 ° C. to 1300 ° C. for several hours.

  By this heat treatment, as shown in FIG. 8B, defects are generated in the n drift layer 101 around the silicon oxide layer 155A, and a crystal defect layer 130 is formed.

  Next, as shown in FIG. 8C, trenches 103A and 103B are formed by anisotropic etching.

  At this time, if the silicon oxide layer 155A remains at the bottom of the trench 103B, the state shown in FIG.

  Thereafter, the p base layer 102, the gate oxide layer 104A, the gate oxide layer 104B, the p + contact layer 105, the n + diffusion layer 106, the p collector layer 107, the n collector layer 108, the gate electrode 110, and the gate electrode 120 are formed. As a result, the semiconductor device shown in FIG.

  The semiconductor device of the sixth embodiment is the same as the semiconductor device shown in FIGS. 1, 2 (f), and 3 (g) except that the method for forming the crystal defect layer 130 is different.

  Therefore, when the IGBT 10 is turned on (that is, when the FWD 20 is turned off), the switch 131 (see FIG. 1) is closed and a negative voltage is applied to the gate electrode 120. When the IGBT 10 is turned off, the switch 131 (see FIG. 1) is opened, and application of a negative voltage to the gate electrode 120 is cut off.

  Since the negative voltage applied when the FWD 20 is turned off is applied to the crystal defect layer 130, when the FWD 20 is turned off, holes remaining as residual carriers in the n drift layer 101 in the FWD 20 are removed from the crystal defect layer. It can be collected in 130 and quickly disappear. As a result, the FWD 20 is quickly turned off.

  Therefore, it is possible to provide the semiconductor device 100 with improved recovery characteristics of the FWD 20 without increasing the on-resistance of the IGBT 10.

  In the semiconductor device of the sixth embodiment, since the crystal defect layer 130 is formed by oxygen ion implantation and heat treatment, the region where the FWD 20 is formed is masked as shown in FIG. 3D in the second embodiment. Thus, the process of removing the silicon nitride film 154A in the trench 103A can be omitted, and the manufacturing process can be simplified.

[Embodiment 7]
FIG. 9 is a diagram illustrating the semiconductor device and the manufacturing method according to the seventh embodiment.

  The semiconductor device of the seventh embodiment is different from the semiconductor devices of the first to sixth embodiments in that a lifetime control layer is included instead of the crystal defect layer. For this reason, the manufacturing method is partly different from those of the first to sixth embodiments.

  As shown in FIG. 9A, the semiconductor device of the seventh embodiment includes a lifetime control layer 156 at the bottom of the trench 103B. For this reason, the crystal defect layer 130 is not formed in the n drift layer 101 below the trench 103B.

  As lifetime control layer 156, a layer having a higher defect density than n drift layer 101, such as silicon nitride (SiN) or polysilicon, may be used. Similarly, any layer may be used as long as holes can be quickly eliminated by applying a negative voltage.

  Before forming the gate oxide layers 104A and 104B shown in FIG.2 (b), the lime time control layer 156 has a resist 152 formed only in a region where the IGBT 10 is formed, and is formed at the bottom of the trench 103B, for example, It can be produced by depositing silicon nitride (SiN) or polysilicon.

  Thereafter, gate oxide layers 104A and 104B are formed by thermal oxidation, and further, p base layer 102, p + contact layer 105, n + diffusion layer 106, p collector layer 107, n collector layer 108, gate electrode 110, and gate electrode By forming 120, the semiconductor device 700 shown in FIG. 9B is obtained. Here, the crystal defect layer 130 finally formed by the thermal oxidation process for forming the gate oxide film also effectively works to improve the recovery characteristics of the FWD 20.

  In such a semiconductor device 700, when the IGBT 10 is turned on (that is, when the FWD 20 is turned off), the switch 131 (see FIG. 1) is closed and a negative voltage is applied to the gate electrode 120. When the IGBT 10 is turned off, the switch 131 (see FIG. 1) is opened, and application of a negative voltage to the gate electrode 120 is cut off.

  Since the negative voltage applied when the FWD 20 is turned off is applied to the lifetime control layer 156, when the FWD 20 is turned off, the remaining carriers remaining in the n drift layer 101 in the FWD 20 are removed from the lifetime. It can be collected in the control layer 156 and quickly extinguished. As a result, the FWD 20 is quickly turned off.

  Therefore, even in the semiconductor device of the seventh embodiment including the lifetime control layer 156 instead of the crystal defect layer 130, the semiconductor device 100 in which the recovery characteristics of the FWD 20 are improved without increasing the on-resistance of the IGBT 10 is provided. can do.

  In the above first to seventh embodiments, the semiconductor device including the n-type drift layer has been described. However, the semiconductor device including the p-type drift layer is provided while changing the conductivity type of each region. You can also In this case, when driving the semiconductor device, the polarity of the voltage applied to each terminal may be reversed.

  The semiconductor device according to the exemplary embodiment of the present invention has been described above. However, the present invention is not limited to the specifically disclosed embodiment, and does not depart from the scope of the claims. Various modifications and changes are possible.

10 IGBT
20 FWD
100, 700 Semiconductor device 101 n drift layer 102 p base layer 103A, 103B trench 104A, 104B gate oxide layer 105 p + contact layer 106 n + diffusion layer 107 p collector layer 108 n collector layer 110, 120 gate electrode 130 crystal defect layer 151 silicon Oxide film 152 Resist 153 Buffer layer 154, 154A, 154B Silicon nitride film 155 Oxygen ion implantation layer 155A Silicon oxide layer 156 Lifetime control layer

Claims (1)

A first trench region, a first gate formed in the first trench region, and an emitter and a collector disposed apart from each other in the thickness direction of the semiconductor layer. And controlling the electric current flowing in the thickness direction of the semiconductor layer by controlling the potential of the first gate, and
A second trench region, a second gate formed in the second trench region, and a thickness direction of the semiconductor layer are formed in a second region adjacent to the first region in the semiconductor layer. And a FWD having a crystal defect region or a lifetime control region formed at the bottom of the second trench and controlled in potential by the second gate,
A semiconductor device that collects residual carriers in the semiconductor layer in the crystal defect region or the lifetime control region by controlling the potential of the second gate when the FWD is off.