JP2001015744A - Power semiconductor device - Google Patents

Abstract

(57) [Summary] In a SuperFET structure, when a guard ring is used at an end of an element, a guard ring must be provided in both an upper layer and a floating doping layer, and there is a problem that an element area is increased. SOLUTION: A trench structure 10 is used at a termination in a SuperFET structure. As a result, the upper layer and the intermediate doping layer can be terminated at the same time, the effective area of the element in the chip is increased, and the IC can be realized. That is, the termination of the intermediate doping layer can be reliably obtained in a smaller area than in the case where the guard ring is used, and an effect equivalent to that of the bevel structure can be obtained by separation at the chip level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly, to a technique for terminating a semiconductor device.

[0002]

2. Description of the Related Art A power device chip is composed of an operating portion and a terminal portion of the device. The operating portion of the element has a function of, for example, switching and rectification, and a pattern having the same basic structure is developed in the chip plane direction, and a number of basic structures are connected in parallel in the chip. On the other hand, the termination part is to separate the operating part of the element from the chip end or other parts on the chip without lowering the withstand voltage to be satisfied by the element, or to perform special processing on the chip end, thereby The purpose is to minimize the decrease in withstand voltage. In a normal power MOSFET or IGBT, the chip end is separated from the operating portion of the element by planar termination using a guard ring as shown in FIG. Further, in a GTO or thyristor that carries an element chip for each circular wafer, a structure in which an electric field escapes to a chip end face without concentrating the electric field is possible by using a bevel structure as a terminal at a chip level as shown in FIG.

As described above, in the conventional device, the terminal structure of the device can be formed by the planar structure or the bevel structure. However, a structure (Sup) having a recently proposed buried layer (intermediate doping layer) with a floating potential is used.
In the erFET structure, the planar structure cannot be used because the depletion layer below the buried layer cannot escape to the chip surface even if the planar structure is used.

[0004] Even if a planar structure is possible, a normal power M
A floating doping layer exists in the drift layer of the OSFET. When a guard ring is used at the end of the device, the guard ring must be provided on both the upper layer and the floating doping layer, and the device area increases. As described above, there is a problem that the area of the terminal portion increases and the effective area decreases. On the other hand, when applying an element structure using a buried layer floating on a small chip,
Bevel structure is not possible.

[0005]

As described above, in the device structure having the buried intermediate layer, even if the planar structure is used, the depletion layer below the buried layer cannot escape to the chip surface. Can not do. Further, even if a planar structure is possible, there is a disadvantage that the area of the terminal portion increases and the effective area decreases, and on the other hand, an element structure using a buried layer floating on a small chip is applied. In this case, there is a problem that a bevel structure is impossible.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is directed to a semiconductor device having a buried potential floating layer by forming a structure such as a trench at the end of a chip. The terminal of the element is configured without deterioration of the withstand voltage.

That is, the present invention provides a first conductive type semiconductor layer,
A first main electrode electrically connected to the first conductivity type semiconductor layer; a first second conductivity type semiconductor layer selectively formed on a surface of the first conductivity type semiconductor layer; A second main electrode electrically connected to the first second conductivity type semiconductor layer; and a plurality of second floating second conductivity type semiconductor layers embedded in the first conductivity type semiconductor layer. Provided is a power semiconductor device, wherein a groove is formed from a surface of the device so as to reach the second second conductivity type semiconductor layer at a terminal portion of the device.

The present invention also provides a first semiconductor layer of a first conductivity type, a first main electrode formed on the first semiconductor layer of the first conductivity type, and a semiconductor layer of the first conductivity type. A first second conductivity type semiconductor layer selectively formed on the surface of the semiconductor layer, and a second first conductivity type semiconductor layer selectively formed on the surface of the first second conductivity type semiconductor layer A second main electrode formed on a surface of the first second conductivity type semiconductor layer and the second first conductivity type semiconductor layer, and the second first conductivity type semiconductor;
A first second conductivity type semiconductor layer; a control electrode formed on the first first conductivity type semiconductor layer via a gate insulating film; and a control electrode embedded in the first first conductivity type semiconductor layer. A semiconductor device having a plurality of second conductive semiconductor layers having a plurality of floating potentials, wherein the second second semiconductor layer is provided at the terminal end of the device.
Provided is a power semiconductor element, wherein a groove is formed from the element surface so as to reach a conductive semiconductor layer.

In the above-mentioned present invention, an element having a structure formed on a low-resistance first conductivity type substrate, wherein a groove at an end portion is formed so as to reach the low-resistance first conductivity type substrate. Is desirable.

It is preferable that the groove at the terminal end is formed in a ring shape so as to surround the element part.

[0011] It is desirable that a plurality of such grooves at the terminal end be formed adjacent to each other.

It is desirable that the width of the groove is 0.5 μm or more.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a sectional view of a first embodiment. As shown in FIG. 1, a high-concentration first conductivity type semiconductor layer (drain layer, n + substrate) 2 is formed on the back side of the first first conductivity type semiconductor layer (n drift layer) 1. A first main electrode (drain electrode) 3 is formed on the first conductivity type semiconductor layer 2. Further, a first second conductivity type semiconductor layer (p-well) 4 is selectively formed on the surface of the first first conductivity type semiconductor layer 1, and the first second conductivity type semiconductor layer is formed. On the surface of the layer 4, a second first conductivity type semiconductor layer (n source) 5 is selectively formed.

A second main electrode (source electrode) 6 is formed on the surface of the first second conductivity type semiconductor layer 4 and the second first conductivity type semiconductor layer 5, and A gate insulation is provided on the first conductivity type semiconductor (n source) 5, the first second conductivity type semiconductor layer (p-well) 4, and the first first conductivity type semiconductor layer (n drift layer) 1. A control electrode 8 is formed via the film 7 to constitute a MOSFET.

Further, the first first conductivity type semiconductor layer 1
The second second conductivity type semiconductor layer 9 having a plurality of floating potentials.
Are embedded to form a SuperFET structure. The first semiconductor layer 9 around the second second conductivity type semiconductor layer 9
A depletion layer is formed in the first conductivity type semiconductor layer (n drift layer) 1 described above, and this depletion layer can improve the breakdown voltage when the element is turned off. A groove 10 is formed at the terminal end portion of the element from the element surface (source side) so as to reach the second second conductivity type semiconductor layer (buried layer) 9, and the terminal structure of the element is formed by the groove. It is configured.

The groove 10 is constructed as follows. That is, a groove 10 is dug at the end of the SuperFET structure, and the surface is oxidized to form a silicon oxide film 11. After forming a SuperFET structure by crystal growth and doping, which will be described later, a groove 10 is formed by vertically etching Si by RIE. The impurity concentration of the drift layer is 1 × 1
0 ¹⁵ cm ⁻³ , the intermediate doped layer has a depth of 2 μm,
¹⁰ × 10 17 cm ^{- 3,} and arranged in the drift layer in 10μm intervals in the depth direction. The width of the groove is 0.5 μm, and the oxide film thickness on the groove surface is about 0.1 μm.

By forming such a groove 10, a guard ring becomes unnecessary, and the same effect as in the bevel structure can be obtained at the terminal end of the element.

(Second Embodiment) FIG. 2 is a sectional view of a second embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals. Hereinafter, the MOSFET structure is omitted. By digging the plurality of trenches 20, the intermediate doping layer 9a is divided, and the same effect as that of the guard ring can be obtained. Reference numeral 21 denotes a silicon oxide film on the surface of the groove 20.

(Third Embodiment) FIG. 3 is a sectional view of a third embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals. The uppermost layer of the element is formed of the p-layer 32 formed by crystal growth, and only the grown p-layer 4 is engraved to form the groove 30, whereby a shape similar to that of the guard ring is obtained, and a similar effect can be obtained. Reference numeral 31 denotes a silicon oxide film on the surface of the groove 30.

(Fourth Embodiment) FIG. 4 is a sectional view of a fourth embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals. A deep groove 40 can be easily formed by etching using an acid instead of RIE. 41 is a silicon oxide film on the surface of the groove 40. Further, the intermediate doping layer 9b is formed by being divided.

(Fifth Embodiment) FIG. 5 is a sectional view of a fifth embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals. First, a groove is formed by a method other than wet etching, and then a deep groove 50 is formed by using an acid. Reference numeral 51 denotes a silicon oxide film on the surface of the groove 50. Also,
The intermediate doping layer 9c is divided and formed.

(Sixth Embodiment) FIG. 6 is a sectional view of a sixth embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals. After the formation of the trench structure, a hole is filled with poly-Si 62 having high versatility in order to prevent dust from entering the trench 60. In this case, the oxide film thickness of the silicon oxide film 61 in the groove is 0.6 μm. The intermediate doping layer 9d is divided and formed.

(Seventh Embodiment) FIG. 7 is a sectional view of a seventh embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals. When a high voltage is applied between the top and bottom surfaces of the substrate, when the trench 70 is filled with a conductive material, and when the thickness of the oxide film is small, an inversion channel is formed in the trench cross section, and conduction occurs. Therefore, a hole is filled using an insulating material (for example, polyimide, BCB, etc.) 72. Thus, the thickness of the silicon oxide film 71 can be reduced to about 0.1 μm. The intermediate doping layer 9e is divided and formed.

(Eighth Embodiment) FIG. 8 shows a top view of an eighth embodiment. The hatched portion in the figure shows the pattern of the intermediate doping layer when the trench is terminated.

(Ninth Embodiment) FIG. 9 shows a top view of a ninth embodiment. The hatched portion in the figure shows the pattern of the intermediate doping layer when planar termination is performed.

(Tenth Embodiment) FIGS. 10, 11, and 12
FIG. 14 shows a schematic view of the doping method according to the tenth embodiment. A mask filled with a doped glass serving as an impurity diffusion source in a heat-resistant mask having a doping pattern formed thereon is heated by irradiating infrared rays by bringing the substrate and the mask into contact with each other. The doping glass contacts the substrate, and the substrate is doped by solid phase diffusion from the contacting doping glass. As a mask, a mask having a form as shown in FIG. 11 is used, a quartz glass is used as a heat-resistant mask, and a glass (PSG) added with phosphorus and a glass (B
A mask is prepared by pouring and sintering the solution of SG). Further, as shown in FIG. 12, a mask is used in which doping glass is provided on one surface of quartz glass and then patterned by etching. The mask opening width is 1 μm.
The doping concentration is controlled by the heating time and the temperature. In the case of PSG, the surface concentration is 1 × 1 at 40 ° C. at 1000 ° C. for 15 seconds.
0 ²¹ cm ⁻³ , and in the case of BSG, 1000 ° C. 15
The surface concentration becomes 1 × 10 ¹⁹ cm ⁻³ at a depth of 40 nm in seconds.

According to the present invention, steps such as forming a mask layer of SiO ₂ or the like, forming a resist pattern by light exposure, and performing doping by thermal diffusion, ion implantation, etc. have been performed. According to the invention, the steps can be shortened.

(Eleventh Embodiment) FIG. 13 is a schematic view of a doping apparatus according to an eleventh embodiment. A doping mask is set in the same manner as the mask of the stepper, the position of the substrate and the position of the mask are detected by mark detection using laser light, the stage is moved, and the position is adjusted.

(Twelfth Embodiment) FIGS. 14 and 15 show a first embodiment.
FIG. 2 is a schematic view of a semiconductor device manufacturing process and a semiconductor manufacturing apparatus according to a second embodiment. First, a diffusion layer is formed on a substrate by using the doping process of the tenth embodiment, crystal growth is performed, and doping is performed again by the same method, thereby forming a drift layer of a SuperFET. The repetitive operation is always performed in a vacuum atmosphere or an inert gas by an apparatus as shown in FIG. 15 in which a doping apparatus and a crystal growth apparatus are connected.

(Thirteenth Embodiment) FIGS. 16 and 17 show a first embodiment.
FIG. 3 shows a schematic cross-sectional view of a mask according to a third embodiment and a schematic view of a vapor deposition apparatus. FIG. 15 shows a structure in which the doping glass of the mask in the ninth embodiment is replaced with a metal. Metals include gallium, indium, aluminum, copper, gold,
A casting mask is prepared by dissolving silver or the like. As shown in FIG. 17, the mask is floated just above the substrate, and the mask is heated with infrared light from the back surface, so that the metal of the mask evaporates and is deposited on the surface of the substrate. The heating temperature is about 700 to 1100 ° C.
It should be 0.1 to 1 m for 00 to 1000 seconds. The mask is floated by 10 μm from the substrate. Mask pattern spacing is 2
Leave 0 μm.

Although the embodiment of the present invention has been described above, in the drawings, the depth of the trench is within the n− layer, but the trench may be extended to the n + layer. In this case, the effect can be obtained by using only one trench, and it can be electrically separated from peripheral elements. Although the embodiment of the present invention has been described using a semiconductor element using Si, the present invention can also be implemented with a compound semiconductor, and has been described only with SuperFET. However, the present invention can be implemented with an element having a layer in which a potential is floating. Become.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0034]

As described above, according to the element structure of the present invention, it is possible to easily form a planar structure.
Further, it is possible to suppress a decrease in the effective area due to an increase in the area of the terminal portion.

[Brief description of the drawings]

FIG. 1 shows a SuperFE according to a first embodiment of the present invention.
Sectional drawing of the trench termination structure of T structure.

FIG. 2 shows a SuperFE according to a second embodiment of the present invention.
Sectional drawing of the trench termination structure of T structure.

FIG. 3 is a diagram illustrating a SuperFE according to a third embodiment of the present invention.
Sectional drawing of the trench termination structure of T structure.

FIG. 4 is a diagram illustrating a SuperFE according to a fourth embodiment of the present invention.
Sectional drawing of the trench termination structure of T structure.

FIG. 5 shows a SuperFE according to a fifth embodiment of the present invention.
Sectional drawing of the trench termination structure of T structure.

FIG. 6 shows a SuperFE according to a sixth embodiment of the present invention.
Sectional drawing of the trench termination structure of T structure.

FIG. 7 shows a SuperFE according to a seventh embodiment of the present invention.
Sectional drawing of the trench termination structure of T structure.

FIG. 8 shows a SuperFE according to an eighth embodiment of the present invention.
FIG. 9 is a schematic pattern diagram of an intermediate doping layer when a trench is terminated at T.

FIG. 9 shows a SuperFE according to a ninth embodiment of the present invention.
FIG. 9 is a schematic pattern diagram of an intermediate doping layer when planar termination is performed at T.

FIG. 10 is a schematic view of a doping method according to a tenth embodiment of the present invention.

FIG. 11 is a sectional view of a doping mask according to a tenth embodiment of the present invention.

FIG. 12 is a sectional view of a doping mask according to a tenth embodiment of the present invention.

FIG. 13 is a configuration diagram of a doping apparatus according to an eleventh embodiment of the present invention.

FIG. 14 is a process cross-sectional view of a device manufacturing process according to a twelfth embodiment of the present invention.

FIG. 15 is a configuration diagram of an element manufacturing apparatus according to a twelfth embodiment of the present invention.

FIG. 16 is a sectional view of a metal diffusion mask according to a thirteenth embodiment of the present invention.

FIG. 17 is a schematic diagram of vapor deposition using a metal diffusion mask according to a thirteenth embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a conventional termination structure of a power element with a guard ring.

FIG. 19 is a cross-sectional view showing a bevel termination structure of a conventional power element.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st 1st conductivity type semiconductor layer (n drift layer) 2 ... High concentration 1st conductivity type semiconductor layer (drain layer, n + substrate) 3 ... 1st main electrode (drain electrode) 4 ... 1st 2nd conductivity type semiconductor layer (p-well) 5 2nd 1st conductivity type semiconductor layer (n source) 6 2nd main electrode (source electrode) 7 gate insulating film 8 ... control electrode 9 2nd 2nd conductivity type semiconductor layer (buried layer) 10 ... groove 11 ... silicon oxide film

Claims (5)

[Claims] A first conductive type semiconductor layer, a first main electrode electrically connected to the first conductive type semiconductor layer, and a first conductive type semiconductor layer selectively formed on a surface of the first conductive type semiconductor layer. A first second conductivity type semiconductor layer, a second main electrode electrically connected to the first second conductivity type semiconductor layer, and a plurality of potentials embedded in the first conductivity type semiconductor layer. A semiconductor device having a floating second second conductivity type semiconductor layer, wherein a groove is formed from an element surface to reach the second second conductivity type semiconductor layer at an end portion of the device. Characteristic power semiconductor device. 2. The semiconductor device according to claim 1, wherein said first semiconductor layer is a first conductivity type semiconductor layer.
A first main electrode formed on the first conductivity type semiconductor layer,
A first second conductivity type semiconductor layer selectively formed on the surface of the first first conductivity type semiconductor layer; and a first second conductivity type semiconductor layer selectively formed on the surface of the first second conductivity type semiconductor layer. A second first conductive type semiconductor layer; a second main electrode formed on a surface of the first second conductive type semiconductor layer and the second first conductive type semiconductor layer; A conductive semiconductor, the first second
A conductive semiconductor layer; a control electrode formed on the first first conductive semiconductor layer via a gate insulating film;
A semiconductor element having a plurality of floating second potential semiconductor layers embedded in the first conductivity type semiconductor layer, wherein the second second conductivity type semiconductor layer is disposed at an end of the element. A power semiconductor device, wherein a groove is formed from the surface of the device so as to reach. 3. An element having a structure formed on a low-resistance first-conductivity-type substrate, wherein a groove at an end portion is formed of the low-resistance first conductive type substrate.
3. The power semiconductor device according to claim 1, wherein the power semiconductor device is formed so as to reach the conductive type substrate. 4. The power semiconductor device according to claim 1, wherein the groove at the end portion is formed in a ring shape so as to surround the device portion. 5. The power semiconductor device according to claim 4, wherein a plurality of grooves at the end portion are formed adjacent to each other.