JP2010257004A - Circuit operation verification apparatus, semiconductor integrated circuit manufacturing method, circuit operation verification method, control program, and recording medium - Google Patents

Abstract

A circuit operation verification apparatus capable of performing accurate crosstalk noise verification in consideration of heat generated by wiring self-heating when calculating resistance of a wiring resistance element.
In a circuit operation verification apparatus for verifying whether or not a semiconductor integrated circuit having a plurality of circuit elements malfunctions due to crosstalk noise between signal wirings adjacent to each other in the circuit, a layout after placement and routing is achieved. On the other hand, a wiring information extraction unit 101 that extracts information on a resistance element as a resistance component of a signal wiring, a resistance value calculation unit 102 that calculates a temperature-dependent resistance value of the resistance element, and a temperature-dependent dependence of the resistance element A crosstalk noise calculation unit 103 that calculates temperature-dependent crosstalk noise based on the resistance value, and a crosstalk noise amount violation net is detected for each wiring connecting the gate cells as the circuit elements based on the temperature-dependent crosstalk noise. And a violation net detection unit 104.
[Selection] Figure 1

Description

  The present invention relates to a circuit operation verification apparatus, a semiconductor integrated circuit manufacturing method, a circuit operation verification method, a control program, and a recording medium, and in particular, designs an LSI (Large Scale Semiconductor Integrated Circuit) using automatic placement and routing of standard elements. When verifying whether or not a semiconductor integrated circuit having a plurality of circuit elements malfunctions due to crosstalk noise between adjacent signal wires, wiring is caused by Joule heat generated by current flowing through the signal wires. This relates to a circuit operation verification method that takes into account that the crosstalk noise fluctuates due to an increase in the resistance of the wiring, resulting in an increase in wiring resistance.

  With the recent high integration and high speed of LSI and multilayer wiring layers, the problem of crosstalk noise generated on the wiring via the capacitance between the signal wirings has become serious.

(1) Problem of crosstalk noise When this crosstalk noise exceeds a predetermined threshold (malfunction threshold), the circuit malfunctions. Therefore, it is very important to verify the influence of crosstalk noise at the design stage such as LSI layout. Is important to.

  FIG. 3 is a schematic diagram showing factors that determine the crosstalk noise shown in Non-Patent Document 1.

According to this Non-Patent Document 1, as shown in FIG. 3, the crosstalk noise is caused by an attack resistance driver cell output resistance R _a1 , a damage side driver cell output resistance R _v1 , attack wiring wiring resistance R _a2 , R _a3. , Wiring resistance R _v2 , R _{v3 of} damaged wiring, capacitances C _a1 , C _{a2 of} attack wiring, capacitances C _v1 , C _v2 of damage wiring, wiring capacitance C _c between attack wiring and damaged wiring It is necessary to consider the input capacity C _a3 of the attack side receiver cell and the input capacity C _v3 of the victim side receiver cell, which are expressed by the following equation (1). Here, the wiring and cells on the victim side are targets for verifying the influence of crosstalk noise. In FIG. 3, S indicates a signal source.

ただし、Ｖ_ｐｅａｋは、被害配線の終端側（レシーバセル側）でのクロストークノイズ電圧値、Ｖ_ｄｄは電源電圧値であり、他のパラメータは、以下のとおりである。

However, V _peak is a crosstalk noise voltage value on the terminal side (receiver cell side) of the damaged wiring, V _dd is a power supply voltage value, and other parameters are as follows.

（２）ＬＳＩ配線の自己発熱問題
半導体加工技術の進歩によるＬＳＩの高集積化・高速化とともに、ＬＳＩの電力密度の増加に伴う発熱問題が深刻になってきている。特に配線においては、配線に電流が流れることによって発生するジュール熱による配線の温度上昇、即ち、自己発熱の問題が深刻である。配線の温度が上昇すると、エレクトロマイグレーションによる信頼性の低下や、配線抵抗の増大により回路動作速度の低下が性能劣化を招く。ここで、配線抵抗Ｒと温度Ｔの関係は、一般に以下の式で近似される。

(2) Self-heating problem of LSI wiring Along with higher integration and higher speed of LSI due to advances in semiconductor processing technology, the heat generation problem accompanying an increase in power density of LSI has become serious. In particular, in the wiring, the temperature rise of the wiring due to Joule heat generated by the current flowing through the wiring, that is, the problem of self-heating is serious. When the temperature of the wiring rises, the reliability deteriorates due to electromigration, and the circuit operating speed decreases due to the increase in wiring resistance, leading to performance deterioration. Here, the relationship between the wiring resistance R and the temperature T is generally approximated by the following equation.

R = R ₀ (1 + β (T−T ₀ )) (2)
Where T is a temperature to be analyzed, T ₀ is a reference temperature, R ₀ is a resistance value when the temperature is T ₀ , and β is a temperature coefficient of the wiring. Here, the temperature coefficient β is approximately 0.003 in the case of Cu wiring currently used in semiconductor manufacturing.

  For example, if the temperature coefficient β is 0.003, the rate of change in resistance when the wiring rises by 100 ° C. from Equation (2) is 30%. That is, when the temperature rises due to the self-heating of the wiring, the wiring resistance increases, and it is inevitable that a decrease in the circuit operation speed causes performance deterioration.

  According to Non-Patent Document 2, it is predicted that the temperature rise of the wiring in the LSI manufactured using the fine process after 50 nm technology will be 300 to 700 ° C at the maximum, and the self-heating of the wiring will be in the future. It is an increasingly serious problem.

  Under such circumstances, when designing an LSI, it is important to perform the design considering the heat described above. The thermal analysis of LSI can be performed using commercially available CAD software, numerical simulation software, or mathematical expression processing software.

  Here, a method of thermal analysis is briefly shown. In general, the heat distribution of a three-dimensional object in an LSI can be obtained by solving a heat conduction equation (equation (3)) derived from the principle of energy conservation law.

cρ∂T / ∂t = k∂ ² T / ∂x ² + k∂ ² T / ∂y ²
+ K∂ ² T / ∂ z ² + q (3)
However, t is time and T is temperature. In addition, the internal heat generation per unit time / unit volume is represented by q (x, y, z, t), the specific heat of the substance is represented by c, the density is represented by ρ, and the thermal conductivity is represented by k.

  LSI thermal analysis is generally performed in a steady state. When the heat generation is in a steady state, there is no transient temperature change, so the left side of Equation (3) is zero. Therefore, a thermal circuit resistance network can be created by discretizing the heat conduction equation in which the left side of Equation (3) is replaced with 0 using the concept of control volumes and connecting the control volumes with resistors. A heat distribution is obtained by setting a heat source in the thermal circuit resistor network thus formed, modeling it as a thermal diffusion analysis model, and performing numerical analysis. Note that the concept of numerical analysis using a control volume is well known, and a description thereof is omitted here.

  Now, as an example of thermal analysis, let us consider the heat distribution of wiring when heat generated by current consumed by the wiring is used as a heat source. For simplicity, consider the heat distribution of a wiring having a structure as shown in FIG. The wiring 10 shown in FIG. 10 is a wiring having a wiring width w, a wiring thickness tm, a wiring length L, and a wiring height from the substrate 1 tox, both ends of which are connection contacts 10a to the substrate 1 and 10b. At this time, the heat distribution in the length direction of the wiring can be considered in one dimension (formula (4)).

^{cρ∂T / ∂t = k∂ 2 T /} ∂x 2 + q ... (4)
According to Non-Patent Document 3, a one-dimensional thermal diffusion equation in a steady state can be derived from the amount of heat generated inside the wiring and the amount of heat released by thermal diffusion in the insulating film. However, the electrical resistivity of the wiring, the thermal conductivity of the wiring, the temperature coefficient of the electrical resistance of the wiring, and the thermal conductivity of the insulating film necessary for derivation are values specific to the substance. Further, the RMS (Root Mean Square) current I _rms of the wiring depends on the operation of the LSI and is a value estimated by a power consumption simulation or the like. The heat distribution of the wiring thus obtained is shown in FIG. Here, it is assumed that the surface temperature of the substrate is uniform, and this temperature is T _ref . The horizontal axis of the heat distribution shown in FIG. 11 represents the position x (um) in the length direction of the wiring, and the vertical axis represents the temperature T (° C.) of the wiring. As can be seen from FIG. 11, the temperature of the wiring in the steady state is not uniform and is not uniform in the length direction, and the temperature is maximum (hereinafter referred to as ΔT _max ) near the center of the wiring. Due to the diffusion, the temperature decreases toward both ends connected to the substrate.

  Thus, the signal wiring in the LSI rises in temperature due to self-heating, and as a result, the resistance changes. When verifying crosstalk noise, it is necessary to consider the temperature change of the wiring.

(3) If the crosstalk noise verification crosstalk noise amount in consideration of the thermal and _{V peak,} the _{V peak} is a value represented by the aforementioned formula (1).

If there is a change in resistance due to the wiring temperature change as represented by the foregoing formula (2), the above formula (1) _{R a2,} R _a3, R _v2, the _{R v3,} resistance considering temperature R By substituting with ' _a2 , R' _a3 , R ' _v2 , R' _v3 , it is possible to obtain a crosstalk noise V ' _peak (equation (5)) considering the temperature.

ただし、Ｖ_ｄｄは電源電圧値であり、他のパラメータは、以下のとおりである。

However, _Vdd is a power supply voltage value, and other parameters are as follows.

今、式（５）に示す温度を考慮した配線抵抗Ｒ’_ａ２ 、Ｒ’_ａ３ 、Ｒ’_ｖ２ 、Ｒ’_ｖ３は各々Ｒ_ａ２ 、Ｒ_ａ３ 、Ｒ_ｖ２ 、Ｒ_ｖ３と異なることから、Ｖ_{’ｐｅａｋ}は式（１）に示すＶ_ｐｅａｋとは異なる値であり、配線の温度によって過小あるいは過大な見積もりとなる。

Now, since the wiring resistances R ′ _a2 , R ′ _a3 , R ′ _v2 , R ′ _v3 in consideration of the temperature shown in the equation (5) are different from R _a2 , R _a3 , R _v2 , R _v3 , _V′peak Is a value different from V _peak shown in equation (1), and is an underestimation or overestimation depending on the wiring temperature.

When designing an LSI, a predetermined value is given to the crosstalk noise amount V _peak in advance, and when the crosstalk noise amount obtained as a result of the analysis exceeds the specified value, the layout is corrected. Ensure that it is below the specified value. At this time, when the wiring temperature is not taken into account, the accuracy is deteriorated as compared with the case where the wiring temperature is taken into consideration. In other words, an underestimation compared to the case where the wiring temperature is taken into account may cause a malfunction, and conversely, an overestimation will force an unnecessary layout correction and increase the design period. .

It is common practice to consider the wiring temperature when performing crosstalk noise verification. In the known method, the maximum temperature specified as the guaranteed operation temperature of the device or the maximum temperature obtained by performing the thermal analysis is uniformly applied to the wiring as the analysis temperature of the entire chip, and the temperature fluctuation of the wiring is taken into consideration. Things have been done. This method assumes a uniform operating temperature as the analysis temperature of the entire chip and does not consider the local temperature rise of the wiring. Therefore, it cannot be accurately estimated, and the crosstalk noise amount V _peak is specified. If the value is less than the value, it is not subject to layout modification, and there is a risk of performance degradation. Alternatively, the amount of crosstalk noise V _{peak at a} location that does not need to be corrected exceeds a specified value, and unnecessary layout correction is forced, resulting in an increase in the design period.

  From this, it can be seen that in order to verify crosstalk noise without excess or deficiency in consideration of the self-heating of the wiring, it is necessary to accurately consider the change in resistance depending on temperature.

Crossstock Noise Estimation for Generic RC Trees, Masanori HASHIMOTO, Masao TAKAHASHI, and Hidetoshi ONODERA, IEICE TRANS. FUNDAMENTALS, VOL. E86-A, NO. 12 DECEMBER 2003. Scaling Analysis of Multilevel Interconnect Temperature for High-Performance ICs, Sungjun Im, Navin Srivastava, Kaustav Banenerhe, and K. Goodson, IEEE Transaction Electron Devices. Vol. 52. No. 12 December 2005. Electrothermal Analysis of VLSI Systems, Yi-Kan Cheng, Ching-Hang Tsai, Chin-Chi Teng, and Sung-Mo (Steve) Kang, Kluwer Academic Public, Inc. 2000.

  As described above, according to the known crosstalk noise verification method described above, the temperature difference between the wiring and the substrate due to the self-heating of the wiring is not taken into consideration. For this reason, when the temperature of the wiring rises, the resistance of the wiring resistance element increases as shown in Expression (2). Crosstalk noise verification using the conventional method does not take into account the resistance increase due to self-heating of the wiring, and the amount of crosstalk noise is estimated to be too small or too large. There is a possibility that it will not be possible, or there is a possibility that a part that does not require layout correction will be subject to correction and increase the design period.

  Conventionally, wiring temperature is generally considered when crosstalk noise verification is performed, but a constant temperature is uniformly given to the wiring as the analysis temperature of the entire chip, and local wiring Because the temperature rise is not taken into account, the crosstalk noise cannot be estimated accurately, the necessary layout correction is not performed, and the unnecessary layout correction is forced. There was a problem that verification could not be performed.

  The present invention has been made to solve the above-described problems, and performs accurate crosstalk noise verification in consideration of heat generated by wiring self-heating when calculating the resistance of the wiring resistance element. Circuit operation verification apparatus and circuit operation verification method capable of manufacturing a semiconductor integrated circuit using the circuit operation verification method by such a circuit operation verification apparatus, and for executing such a circuit operation verification method by a computer It is an object to obtain a control program and a recording medium storing such a control program.

  A circuit operation verification apparatus according to the present invention is a circuit operation verification apparatus that verifies whether or not a semiconductor integrated circuit having a plurality of circuit elements malfunctions due to crosstalk noise between adjacent signal wirings in the circuit. Then, from the circuit information indicating the basic layout of the semiconductor integrated circuit and the heat distribution information indicating the heat distribution in the semiconductor integrated circuit, the temperature-dependent resistance distribution in the signal wiring depending on the heat distribution in the signal wiring is calculated. A temperature-dependent resistance distribution deriving unit, and a crosstalk noise verification unit that calculates crosstalk noise between signal wirings according to the temperature-dependent resistance distribution in the signal wirings, thereby achieving the above object. Is done.

  According to the present invention, in the above circuit operation verification apparatus, as the heat distribution information, the energy consumption due to the resistance of the signal wiring generates heat inside the signal wiring, and the temperature of the signal wiring is increased. A heat distribution information storage unit for storing heat distribution information due to self-heating, and the temperature-dependent resistance distribution derivation unit is configured to connect the signal wiring based on the heat distribution information stored in the heat distribution information storage unit. It is preferable to calculate a temperature-dependent resistance distribution.

  According to the present invention, in the above circuit operation verification device, as the signal wiring information of the semiconductor integrated circuit, the resistance value of the resistance element which is a resistance component of the divided wiring obtained by dividing the signal wiring in the semiconductor integrated circuit into a plurality of A resistive element information deriving unit for deriving position information, the resistive element information deriving unit storing signal wiring information of the semiconductor integrated circuit as circuit information indicating the basic layout, and the signal A resistance element information extraction unit that extracts the resistance value and position information of the resistance element from the signal wiring information of the semiconductor integrated circuit stored in the wiring information storage unit, and the resistance value and position information of the extracted resistance element The temperature-dependent resistance distribution deriving unit stores the signal distribution based on the resistance value and the position information of the resistance element stored in the resistance element information storage unit. It is preferable to calculate the temperature-dependent resistance distribution at.

  According to the present invention, in the circuit operation verification apparatus, the temperature dependent resistance distribution deriving unit calculates the temperature dependent resistance in the signal wiring calculated from the heat distribution information in the signal wiring stored in the heat distribution information storage unit. It is preferable to have a temperature-dependent resistance element information storage unit that stores the distribution.

  In the above circuit operation verification device, the present invention includes a temperature coefficient storage unit that stores a temperature coefficient indicating a resistance variation specific to a wiring material, and the temperature-dependent resistance distribution deriving unit includes the temperature of each resistance element, It has a resistance calculation unit that calculates a temperature-dependent resistance value in consideration of the temperature of each resistance element by multiplying the difference from the reference temperature of each resistance element by the temperature coefficient stored in the temperature coefficient storage unit. preferable.

  According to the present invention, in the above circuit operation verification device, from the signal wiring information of the semiconductor integrated circuit stored in the signal wiring information storage unit, the output driving resistance of the driver cell, the input terminal capacitance of the receiver cell, and the signal wiring capacitance The information extraction unit includes a driver resistance storage unit that stores an output drive resistance of the driver cell, a receiver input capacitance storage unit that stores an input terminal capacitance of the receiver cell, and the signal A signal wiring capacity storage section for storing wiring capacity, and the output drive resistance of the driver cell, the input terminal capacity of the receiver cell, and the signal wiring capacity are transferred from each storage section to the crosstalk noise verification section. It is preferable to deliver.

  In the circuit operation verification apparatus according to the present invention, the crosstalk noise verification unit calculates temperature-independent resistance distribution information in the signal wiring included in the circuit information indicating the basic layout by the temperature-dependent resistance distribution deriving unit. The driver resistance extracted from the driver resistance storage unit, the receiver input capacitance storage unit, and the signal wiring capacitance storage unit based on the circuit information indicating the basic layout replaced with the temperature-dependent resistance distribution information in the signal wiring. It is preferable to calculate temperature-dependent crosstalk noise in the signal wiring from the receiver input capacitance and the signal wiring capacitance.

  According to the present invention, in the above circuit operation verification device, the crosstalk noise verification unit stores the calculation result of the temperature dependent crosstalk noise as temperature dependent crosstalk noise for each standard element constituting the basic layout. It is preferable to have a noise storage unit.

  The present invention compares the temperature-dependent crosstalk noise for each signal wiring stored in the crosstalk noise storage unit with a specified value of crosstalk for each signal wiring in the circuit operation verification device, It is preferable to include a violation net detection unit that detects a signal wiring whose talk noise violates the specified value as an error net.

  In the circuit operation verification apparatus according to the present invention, it is preferable that the violation net detection unit includes a specified value storage unit that stores a specified value of crosstalk for each signal wiring.

  A method of manufacturing a semiconductor integrated circuit according to the present invention is a method of manufacturing a semiconductor integrated circuit using a mask pattern obtained based on circuit information, and the circuit information is designed to operate at a reference temperature. The temperature-independent circuit information indicating the circuit configuration of the semiconductor integrated circuit reflects crosstalk noise due to self-heating of the wiring by the circuit operation verification processing by the circuit operation verification device according to claim 1. This is the temperature-dependent circuit information obtained by making such changes, whereby the above-mentioned object is achieved.

  The circuit operation verification method according to the present invention is a circuit operation verification method for verifying whether or not a semiconductor integrated circuit having a plurality of circuit elements malfunctions due to crosstalk noise between adjacent signal wirings in the circuit. Then, from the circuit information indicating the basic layout of the semiconductor integrated circuit and the heat distribution information indicating the heat distribution in the semiconductor integrated circuit, the temperature-dependent resistance distribution in the signal wiring depending on the heat distribution in the signal wiring is calculated. A temperature-dependent resistance distribution deriving step, and a crosstalk noise calculating step for calculating crosstalk noise between the signal wirings in accordance with the temperature-dependent resistance distribution in the signal wirings, whereby the above object is achieved. The

  According to the present invention, in the circuit operation verification method, as the heat distribution information, the energy consumption due to the resistance of the signal wiring generates heat inside the signal wiring, and the temperature of the signal wiring is increased. Heat distribution information by self-heating is stored in a heat distribution information storage unit, and in the temperature-dependent resistance distribution derivation step, based on the heat distribution information stored in the heat distribution information storage unit, It is preferable to calculate a temperature-dependent resistance distribution.

  In the circuit operation verification method, the present invention provides a resistance value of a resistance element, which is a resistance component of a divided wiring obtained by dividing a signal wiring in the semiconductor integrated circuit into a plurality of signal wiring information of the semiconductor integrated circuit. A resistive element information deriving step for deriving position information, and in the resistive element information deriving step, from the signal wiring information of the semiconductor integrated circuit stored in the signal wiring information storage unit as circuit information indicating the basic layout, The resistance value and position information of the resistance element are extracted and stored in the resistance element information storage unit. In the temperature-dependent resistance distribution derivation step, the resistance value and position of the resistance element stored in the resistance element information storage unit are extracted. Based on the information, the temperature-dependent resistance distribution in the signal wiring is calculated, whereby the above object is achieved.

  According to the present invention, in the circuit operation verification method, in the temperature-dependent resistance distribution derivation step, the temperature-dependent resistance in the signal wiring calculated from the heat distribution information in the signal wiring stored in the heat distribution information storage unit It is preferable to store the distribution in the temperature-dependent resistance element information storage unit.

  According to the present invention, in the circuit operation verification method, the temperature-dependent resistance distribution derivation step is stored in the temperature coefficient storage unit as a difference between the temperature of each resistance element and a reference temperature of each resistance element. It is preferable to have a resistance calculation step of calculating a temperature-dependent resistance value in consideration of the temperature of each resistance element by multiplying by a temperature coefficient.

  According to the present invention, in the above circuit operation verification method, from the signal wiring information of the semiconductor integrated circuit stored in the signal wiring information storage unit, the output driving resistance of the driver cell, the input terminal capacitance of the receiver cell, and the signal wiring capacitance And stored in the driver resistance storage unit, the receiver input capacitance storage unit, and the signal wiring capacitance storage unit, respectively, and in the crosstalk noise verification step, the driver cells stored in these storage units It is preferable to calculate the crosstalk noise between the signal wirings according to the temperature-dependent resistance distribution in the signal wiring from the output driving resistance of the receiver, the input terminal capacitance of the receiver cell, and the signal wiring capacitance.

  According to the present invention, in the circuit operation verification method, in the crosstalk noise verification step, temperature-independent resistance distribution information in the signal wiring included in the circuit information indicating the basic layout is calculated in the temperature-dependent resistance distribution derivation step. Based on the circuit information indicating the basic layout replaced with the temperature-dependent resistance distribution information in the signal wiring, the driver resistance extracted from the driver resistance storage unit, the receiver input capacitance storage unit, and the signal wiring capacitance storage unit, and the It is preferable to calculate the temperature-dependent crosstalk noise in the signal wiring from the receiver input capacitance storage section and the signal wiring capacitance.

  According to the present invention, in the circuit operation verification method, in the crosstalk noise verification step, the calculation result of the temperature dependent crosstalk noise is stored as a temperature dependent crosstalk noise for each standard element constituting the basic layout. It is preferable to store in the part.

  In the circuit operation verification method, the present invention compares the temperature-dependent crosstalk noise for each standard element stored in the crosstalk storage section with the specified crosstalk value for each standard element, and It is preferable to include a violation net detection step of detecting a signal wiring whose noise violates the specified value as an error net.

  In the circuit operation verification method according to the present invention, preferably, in the violating element detection step, a specified value of crosstalk for each standard element is stored in a specified value storage unit.

  The control program according to the present invention describes a processing procedure for causing a computer to execute each step of the circuit operation verification method, thereby achieving the above object.

  A storage medium according to the present invention is a computer-readable readable storage medium in which the control program is stored, whereby the above object is achieved.

  Hereinafter, the operation of the present invention will be described.

  In the present invention, in LSI design using automatic placement and routing of standard cells, information on the coordinates and temperature of heat distribution generated by self-heating of the wiring obtained in advance, and wiring resistance for each wiring material obtained separately. The crosstalk noise verification can be performed in consideration of the temperature rise caused by the self-heating of the wiring by referring to the value of and the coefficient of the wiring resistance change with respect to the temperature change.

  Further, in the present invention, as a result of crosstalk noise verification considering the temperature rise caused by the self-heating of the wiring, a net with a constraint violation can be detected, and it was not detected when the temperature rise was not taken into consideration. The net can be detected as a violation net, and high-precision verification without leakage can be performed.

  Further, in the present invention, as a result of crosstalk noise verification considering the temperature rise caused by the self-heating of the wiring, the net detected as a violation is not violated because the overestimation was made when the temperature rise was not taken into account. Sift off as a net, eliminating unnecessary layout modifications.

  As described above, according to the present invention, when calculating the resistance of a resistance element, which is the resistance component of a plurality of divided wirings obtained by dividing a signal wiring (net), heat generated by self-heating of each resistance element. Therefore, when crosstalk noise verification is performed, the amount of crosstalk noise is calculated using the resistance value of each resistance element. Talk noise verification can be performed.

FIG. 1 is a block diagram showing a configuration example of a main part of a circuit operation verification apparatus according to an embodiment of the present invention. FIG. 2 is a diagram for explaining the circuit operation verification apparatus according to the embodiment of the present invention, and shows a hardware configuration example of a main part of the circuit operation verification apparatus 100 shown in FIG. FIG. 3 is a schematic diagram illustrating factors that determine crosstalk noise in a conventional crosstalk noise verification method. FIG. 4 is a diagram for explaining the circuit operation verification apparatus according to the embodiment of the present invention, and shows the temperature dependence of the resistance. FIG. 5 is a diagram for explaining a circuit operation verification apparatus according to an embodiment of the present invention. A table (table) shows the relationship between the position coordinates in the LSI and the temperature obtained from the thermal analysis of the LSI (wiring). ) It is a figure indicated by T1. FIG. 6 is a diagram for explaining a circuit operation verification apparatus according to an embodiment of the present invention, in which the element names, position coordinates, and resistances of resistance elements as resistance components of the divided wiring obtained by dividing the signal wiring are shown. It is a figure which shows a value by table | surface (table) T2. FIG. 7 is a diagram for explaining a circuit operation verification apparatus according to an embodiment of the present invention, in which element names, position coordinates, and temperatures of resistance elements as resistance components of the divided wiring obtained by dividing the signal wiring are illustrated. It is a figure which shows the resistance value which considered dependence by table | surface (table) T3. FIG. 8 is a diagram for explaining a circuit operation verification apparatus according to an embodiment of the present invention, and shows resistance components of divided wiring obtained by dividing a signal wiring in an LSI chip as resistance elements. FIG. 9 is a diagram for explaining the circuit operation verification apparatus according to the embodiment of the present invention, and shows a prescribed value of crosstalk noise for each net by a table T4. FIG. 10 is a diagram for explaining an example of thermal analysis, and shows a wiring structure in which wiring is formed on a semiconductor substrate via an insulating film. FIG. 11 is a graph showing the heat distribution in the wiring structure shown in FIG. FIG. 12 is a diagram for explaining the circuit operation verification apparatus according to the embodiment of the present invention, and is a diagram illustrating the temperature at each position in the LSI as a result of the thermal analysis simulation of the LSI. FIG. 13 is a diagram for explaining a circuit operation verification apparatus according to an embodiment of the present invention, and shows an equivalent circuit used for analysis of temperature-dependent crosstalk noise. FIG. 14 is a diagram for explaining a circuit operation verification apparatus according to an embodiment of the present invention. The crosstalk noise verification method described as the prior art of the present invention and the crosstalk noise verification method according to the present invention The amount of noise is shown as a table (table) T5.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a semiconductor circuit operation verification apparatus (circuit operation verification apparatus) according to Embodiment 1 of the present invention.

  The circuit operation verification apparatus 100 according to the first embodiment is based on basic layout information of an LSI (large-scale semiconductor integrated circuit), and the resistance of a resistance element that is a resistance component of a divided wiring obtained by dividing a signal wiring in the LSI into a plurality of parts. A resistance element information extraction unit (resistance element information deriving unit) 101 that extracts a value and its position on an LSI chip (that is, on a mask layout), and a temperature coefficient storage unit 121 that stores a temperature coefficient of resistance of a signal wiring A heat distribution information storage unit 122 for storing heat distribution information obtained by thermal analysis of a semiconductor integrated circuit (LSI) in advance, and local generation caused by self-heating of the signal wiring based on the temperature coefficient and heat distribution information In consideration of various temperature information, a resistance value calculation unit (temperature-dependent resistance distribution deriving unit) 102 that calculates a temperature-dependent resistance value of each of the resistance elements is provided. .

  Here, the resistance element information extraction unit 101 includes a signal wiring information storage unit 111 that stores a parasitic element extraction file for signal wiring, and a parasitic element extraction file for signal wiring stored in the storage unit 111. A signal wiring resistance element information extraction unit 112 that extracts resistance element information and a signal wiring resistance element information storage unit 113 that stores resistance element information of the signal wiring extracted by the information extraction unit 112 are provided.

  Here, the storage unit 111 stores signal wiring information in the basic layout as circuit information (basic layout information) indicating the basic layout of the semiconductor integrated circuit obtained by the automatic placement and routing process. The information extraction unit 112 also determines the resistance value of the resistance element, which is the resistance component of the divided wiring obtained by dividing the signal wiring in the LSI chip from the information stored in the storage unit 111, on the LSI chip. The position on the mask layout is extracted. The information storage unit 113 stores the extracted position (coordinates) of the resistance element and the resistance value as a table T2 (FIG. 6).

  Specifically, in the signal wiring information storage unit 111, a parasitic element of signal wiring extracted by using a commercially available LPE (Layout Parameter Extraction) tool (parasitic circuit component extraction tool) or the like for the layout after wiring generation Contains extracted files. As shown in FIG. 3, this parasitic element extraction file includes connection information of resistance elements as parasitic resistances of parts of the signal wiring divided into a plurality of parts, resistance values of the resistance elements, parasitic capacitance values of the signal wirings, drivers A standard format file in which connection information of each cell (not shown) such as a cell and a receiver cell, and two-dimensional coordinate information where each resistance element is located on the layout is stored, and is usually a SPEF (Standard Parasitic Exchanged format). ) Or SPF (Standard Parasitic format).

  The signal wiring resistance element information storage unit 113 stores the coordinates and resistance values of the resistance elements extracted from the signal wiring information storage unit 111 as a table T2 (see FIGS. 6 and 8).

  Here, FIG. 8 is a diagram showing a resistance element which is a resistance component of the divided wiring obtained by dividing the signal wiring in the LSI chip into a plurality of parts.

  As shown in FIG. 8, the resistance component of the signal wiring (net) N in the LSI chip is represented by a plurality of resistance elements Rv1, Rv2, Rv3, Rv4,. In FIG. 8, X1 to X4 indicate connection nodes on one end side of each resistance element.

  FIG. 6 is a diagram showing the table T2. The table T2 is a table of resistor element names (Rv1, Rv2,..., Rvi, Ra1,... , And the X coordinate (Xv1, Xv2,..., Xvi, Xa1,..., Xai,...) And the Y coordinate (Yv1, Yv2,..., Yvi, Ya1) , ..., Yai, ...) and resistors (Resv1, Resv2, ..., Resvi, Resa1, ..., Resai, ...).

  Further, the heat distribution information storage unit 122 gives the current consumption value of the wiring previously obtained by the power consumption simulation to the layout after the generation of the wiring as a heat source, and uses commercially available CAD software or the like to generate the heat. The result obtained by performing the analysis simulation is stored. For example, when the result of the LSI thermal analysis simulation is represented by a graph as shown in FIG. 12, the heat distribution information storage unit 122 stores the result of the LSI thermal analysis simulation with each coordinate as shown in FIG. It is stored as a temperature correspondence table T1.

  In this correspondence table (table) T1, as heat distribution information, X coordinates (X1, Y1), (X2, Y1),..., (Xi, Y1),. Temperature at the position (T11, T21,..., Ti1,...).

  Here, FIG. 12 shows temperatures at positions (X1, Y1), (X2, Y1), (X3, Y1),..., (Xi, Y1),. T11, T21, T31,..., Tn1 are shown in a graph. However, in FIG. 12, only the X coordinate is shown as the horizontal axis. Further, FIG. 5 shows correspondence between positions (X1, Y1), (X2, Y1),..., (Xi, Y1),..., And temperatures T11, T21,. The relationship is shown by table T1.

  The temperature coefficient storage unit 121 stores a coefficient of resistance change with respect to a temperature change, which is a unique value in semiconductor manufacturing for each wiring material.

Figure 4 shows the temperature dependence of the resistance in the graph, in resistance when the [rho ₀ is the temperature T ₀ in FIG. 4, the T ₀ as a reference temperature, resistance [rho ₀ at the temperature T ₀ are known And At this time, it is generally well known that the wiring resistance change with respect to the temperature change can be approximated linearly. That is, as shown in FIG. 4, the temperature dependence of resistance can be expressed by equation (6). However, T ′ is a temperature to be analyzed, T ₀ is a reference temperature, r ′ is a resistance value at the temperature T ′, and β is a temperature coefficient of the wiring.

r ′ = ρ ₀ (1 + β (T′−T ₀ ))
= Ρ ₀ (1 + βT) (6)
However, T (= T′−T ₀ ) is a temperature change amount.

  Further, the resistance calculation unit 102 uses the above-described equation (6) to calculate a temperature-dependent signal wiring resistance calculation unit 114 that calculates a resistance value depending on the temperature of the resistance element that constitutes the signal wiring, and the calculation unit. And a temperature-dependent signal wiring resistance element information storage unit 115 that stores the resistance value calculated in 114. That is, in the resistance calculation unit 102, the resistance calculation unit 114 stores the temperature corresponding to the position coordinates of the resistance element stored in the storage unit 113 from the storage unit 122 and the temperature coefficient specific to the wiring material. Read from the unit 121 and calculate the temperature-dependent resistance value of each resistance element of the signal wiring according to the equation (6). The calculated temperature-dependent signal wiring resistance values of all the resistance elements are stored in the storage unit 115.

  In this temperature-dependent resistance information storage unit 115, the resistance value of the resistance element taking into account the temperature change calculated using the above equation (6) is stored as a table T3 together with the position (coordinates) of the resistance element. ing.

  FIG. 7 is a diagram showing the table T3. The table T3 has information on the resistance elements in the signal wirings. The resistance element names (Rv1, Rv2,..., Rvi, Ra1,... , And the X coordinate (Xv1, Xv2,..., Xvi, Xa1,..., Xai,...) And the Y coordinate (Yv1, Yv2,..., Yvi, Ya1) , ..., Yai, ...) and resistors (Res'v1, Res'v2, ..., Res'vi, Res'a1, ..., Res'ai, ...) It is out.

  Further, the circuit operation verification apparatus 100 according to the first embodiment is based on the basic layout information in which the resistance value of each resistance element in the basic layout information is replaced with the resistance value considering the temperature distribution in the wiring. A noise calculation unit (crosstalk noise verification unit) 103 that calculates temperature-dependent crosstalk noise of the network and a crosstalk noise storage unit that stores temperature-dependent crosstalk noise for each net (temperature-dependent crosstalk noise storage unit for each net) 118 and a violation net detection unit 104 that detects a violation net from temperature-dependent crosstalk noise for each net.

  Further, the circuit operation verification apparatus 100 extracts circuit information related to the temperature-dependent crosstalk noise analysis equivalent circuit shown in FIG. 13 from information stored in the signal wiring information storage unit 111 (information The information extraction unit 105 includes a storage unit 124 that stores output resistances (driver resistances) of the driver cells Agg1 and Vic1 in the equivalent circuit, and inputs of the receiver cells Agg2 and Vic2 in the equivalent circuit. The storage unit 125 stores a capacity (receiver input capacity), and the storage unit 126 stores a capacity of a signal wiring between these cells. The information stored in these storage units 124 to 126 is obtained from the information stored in the signal wiring information storage unit 111.

  Here, the noise calculation unit 103 includes a signal wiring parasitic element extraction file stored in the storage unit 116, a driver resistance stored in the storage unit 124, and a receiver stored in the storage unit 125. The input capacity and the signal wiring capacity stored in the storage unit 126 are transferred to a commercially available crosstalk noise analysis tool or the like to perform crosstalk noise analysis. This commercially available crosstalk noise analysis tool analyzes crosstalk noise for each net from these pieces of information. The temperature-dependent crosstalk noise amount obtained for each net is stored in the storage unit 118.

  That is, the noise calculation unit 103 replaces the resistance value of each resistance element in the parasitic element extraction file of the signal wiring stored in the storage unit 111 with the temperature dependent resistance of each resistance element stored in the storage unit 115. Based on the resistance value of the resistance element stored in the storage unit 116 for storing the parasitic element extraction file of the obtained signal wiring and the resistance information stored in the wiring information storage unit 116, the crosstalk noise analysis equivalent circuit A temperature-dependent crosstalk noise calculation unit 117 that calculates temperature-dependent crosstalk noise from the circuit information) and supplies it to the storage unit 118. In other words, the storage unit 116 stores basic layout information in which the resistance value of each resistance element in the basic layout information is replaced with a resistance value considering the temperature distribution in the wiring.

  Further, the violation net detection unit 104 compares the crosstalk noise amount for each net obtained as a result of the above-described crosstalk noise calculation with a specified value stored in the storage unit 123, and the crosstalk noise amount is specified. If the value is exceeded, a net that may cause a violation is stored in the error net storage unit 120, and the stored net is set as a layout correction target.

  That is, the crosstalk violation detecting unit 104 includes a specified value storage unit 123 that stores a specified value of crosstalk noise for each net, and a specified value of crosstalk noise for each net stored in the specified value storage unit 123. And a violation point detection unit 119 that supplies information on a net that may cause a violation to the error net storage unit 120 based on the crosstalk noise for each net stored in the storage unit 118. ing. In the error element storage unit 120, a net in which the amount of crosstalk noise stored in the storage unit 118 exceeds a specified value stored in the storage unit 123 is stored as an error net. Further, in the specified value storage unit 123 for the amount of crosstalk noise for each net, the crosstalk noise for all the nets NetA, NetB, NetC,..., Neti,. Specified amount values (allowable values) VthA, VthB, VthC,..., Vthi,. As the specified value, for example, a threshold value for preventing logical malfunction due to crosstalk noise, or a threshold value for preventing the influence of a change in signal delay caused by crosstalk noise on the operation timing of the circuit is set. Has been.

  FIG. 2 is a block diagram illustrating a hardware configuration example of a main part of the circuit operation verification apparatus of FIG.

  In FIG. 2, the circuit operation verification apparatus 100 according to the present embodiment is configured by a computer system. The operation input unit 2 such as a keyboard, a mouse, and a screen input device that enables various input commands, and the various input commands. A display unit 3 capable of displaying various images such as an initial screen, a selection guidance screen, and a processing result screen on the display screen, a CPU 4 (central processing unit) as a control means for performing overall control, and a CPU 4 A RAM 5 as a temporary storage means that works as a work memory at the time of activation, a ROM 6 as a computer-readable readable recording medium (storage means) in which a control program for operating the CPU 4 and various data used therefor are recorded, A database 7 for storing various data in the circuit operation verification process and making it referable The has.

  In addition to the input command from the operation input unit 2, the CPU 4 performs the above-described signal wiring resistance element extraction unit 112 and the temperature-dependent signal based on the control program read from the ROM 6 into the RAM 5 and various data used for the control program. The functions of the wiring resistance calculation unit 114, the temperature-dependent crosstalk noise calculation unit 117, and the crosstalk noise amount violation location detection unit 119 for each net in the layout are executed.

  The ROM 6 is configured by a readable recording medium (storage means) such as a hard disk, an optical disk, a magnetic disk, and an IC memory. The control program and various data used for the control program may be downloaded to the ROM 6 from a portable optical disk, a magnetic disk, an IC memory, or the like, or may be downloaded to the ROM 6 from a hard disk of a computer, or wirelessly, wired, or the Internet. It may be downloaded to the ROM 6 via the above.

  The hardware configuration of the main part of the circuit operation verification apparatus 100 shown in FIG. 2 is a computer-readable readable storage in which a control program in which processing procedures for causing a computer to execute the functions of the respective parts of the circuit operation verification apparatus shown in FIG. The data is stored in a medium, and a circuit operation verification process is automatically performed by a computer (CPU 4).

  The RAM 5 and the database 7 store various data generated as intermediate data during the circuit operation verification process by the CPU 4 each time and can refer to them as necessary. The database 7 may be configured as the same storage unit as the RAM 5.

  Next, the operation will be described.

  A highly accurate crosstalk noise calculation method taking temperature into account performed by the circuit operation verification apparatus according to the embodiment of the present invention will be described with reference to FIG.

  The crosstalk noise calculation method according to the first embodiment includes a first step of extracting signal wiring resistance element information for a layout after placement and routing, a second step of calculating a temperature-dependent signal wiring resistance element, A third step of calculating the temperature-dependent crosstalk noise, and a fourth step of detecting whether or not the signal wiring (hereinafter referred to as a net) connecting the gate cells is a crosstalk noise violation net. It is out.

  Hereinafter, the operation of the first embodiment will be described in detail.

  In the circuit operation verification apparatus 100 shown in FIG. 1, the heat distribution information storage unit 122 is supplied with the current consumption value of the wiring previously obtained by the power consumption simulation as a heat source, and the heat obtained by performing the thermal analysis simulation. Distribution information is stored. Here, the heat distribution information indicates the coordinates on the circuit layout of the LSI and the temperature at the coordinates.

  In the circuit operation verification apparatus 100, the information extraction unit 112 extracts the position coordinates on the layout of the resistive elements and the resistance values thereof from the signal wiring information storage unit 111 as the resistive element information of the signal wirings, and the signal wiring resistive elements Information is stored in the information storage unit 113 (first step).

  In the circuit operation verification apparatus 100, the resistance calculation unit 114 performs resistance calculation in consideration of temperature dependence on the resistance value of the resistance element stored in the first step. At this time, the temperature dependence coefficient of the wiring necessary for the temperature dependence resistance calculation stored in the storage unit 121 is referred to. Further, information stored in the heat distribution information storage unit 122 is referred to as the temperature of the signal wiring resistance element. The resistance calculation unit 114 stores the temperature-dependent signal wiring resistance element information calculated in this way in the temperature-dependent signal wiring resistance element information storage unit 115 (second step).

  In the circuit operation verification apparatus 100, the signal wiring resistance calculated in the second step is stored in the signal wiring information storage unit 116 in the same format as the signal wiring information storage unit 111, and this format is commercially available. This is a format that can be read by a crosstalk noise verification tool that is CAD software. Then, the crosstalk noise calculation unit 117 and the signal wiring information considering the temperature stored in the signal wiring information storage unit 116 and the drivers extracted from the signal wiring information storage unit 111 and stored in the storage units 124 to 126 are stored. The resistance, the receiver input capacitance, and the signal wiring capacitance are given to a crosstalk noise verification tool, which is commercially available CAD software, and temperature dependent crosstalk noise for each net in the layout is calculated (third step). In addition, the temperature-dependent crosstalk noise amount for each net of the layout obtained in the third step is stored in the storage unit 118.

  In the circuit operation verification apparatus 100, the detection unit 119 has the crosstalk noise for each net stored separately in the storage unit 123, for each cell or block calculated in the third step. Compared with the prescribed value of the quantity, the violating net is extracted, and information on the net is stored in the storage unit 120.

  Through the above first to fourth steps, it is possible to perform crosstalk noise verification with high accuracy and no leakage considering the temperature rise of the wiring resistance.

  According to the circuit operation verification apparatus 100 that verifies the crosstalk noise of the signal wiring in consideration of the temperature change caused by the self-heating of the wiring according to the present invention, the following effects can be expected.

  In LSI design using automatic placement and routing of standard cells, information on the heat distribution coordinates and temperature generated by the self-heating of the wiring obtained in advance, and the wiring resistance value for each wiring material obtained separately (reference temperature) For example, crosstalk noise verification considering temperature rise caused by self-heating of the wiring can be performed by referring to the resistance value at a normal temperature of 25 ° C.) and the coefficient of the wiring resistance change with respect to the temperature change.

  Further, according to the present invention, as a result of crosstalk noise verification considering the temperature rise caused by the self-heating of the wiring, a net with a constraint violation can be detected and is not detected when the temperature rise is not considered. Nets can be detected as violation nets, and high-precision verification without leakage can be performed.

  Further, according to the present invention, as a result of crosstalk noise verification considering the temperature rise caused by the self-heating of the wiring, the net detected as a violation because the overestimation was made when the temperature rise was not taken into account. Sift out as no net and eliminate unnecessary layout modifications.

  An example showing improvement in the accuracy of the effect of the present invention will be described with reference to FIGS. 13 and 14.

  With respect to layout data designed using automatic placement and routing of standard cells, as the circuit elements included in the layout data, driver / damage driver cells as shown in FIG. 13 and resistance elements, capacitive elements, and receivers connected to them are shown. Think of a cell.

  In FIG. 13, the attack side driver cell Agg1, the victim side driver cell Vic1, the attack side receiver cell Agg2, and the victim side receiver cell are all inverter cells. NetA is a damaged wiring element (net), and NetB is an attacking wiring element (net). Further, the attack-side wiring element (net) NetA includes a resistance component represented by series-connected resistance elements Ra1, Ra2, and Ra3, and a capacitance component represented by a plurality of substrate capacitive elements Ca1, Ca2, and Ca3. Have. Similarly, for the wiring element (net) on the damage side, a resistance component represented by series-connected resistance elements Rv1, Rv2, and Rv3 and a capacitance component represented by a plurality of substrate capacitive elements Cv1, Cv2, and Cv3 are provided. Have. In addition, a coupling capacitance represented by a capacitive element Cc is formed between the attack-side wiring element and the damage-side wiring element.

  Here, the attack-side driver cell Agg1 drives the attack-side wiring element NetB and outputs a signal to the attack-side receiver cell Agg2 via the wiring element. The victim-side driver cell Vic1 The wiring element NetA is driven, and a signal is output to the receiver cell Vic2 on the damage side via the wiring element.

  FIG. 14 shows a case where a temperature-dependent resistance calculation is performed by referring to a temperature corresponding to a resistance element of a signal wiring (net) from a separately obtained heat distribution, and as a result, there is a maximum 30% resistance change in the temperature. FIG. 4 shows NetA crosstalk noise according to a conventional method and NetA crosstalk noise according to the present invention.

  Specifically, case (1) and case (2) shown below are cases where the circuit configuration is the same and the temperature distribution in the net is different. When comparing case (1) and case (2), The difference in temperature distribution in the signal wiring (net) causes a resistance change of 30% at the maximum in the resistance elements constituting the net.

  In this case, the crosstalk noise amount according to the conventional method is 24 mv in both cases (1) and (2), whereas the crosstalk noise amount according to the present invention is 26.2 mv in case (1). In (2), it is 21.9 mv. That is, it can be seen that in the conventional method, the crosstalk noise was estimated to be under 2.2 mv in case (1), and over 2.1 mv in case (2).

  Thus, in the present embodiment, an accurate resistance value can be obtained by considering the heat generated by the wiring self-heating when calculating the resistance of the wiring resistance element. Accurate crosstalk noise verification can be performed by calculating the amount of crosstalk noise using the resistance value.

  In addition, the circuit operation verification apparatus of the first embodiment can be used in a method for manufacturing a semiconductor integrated circuit.

  Specifically, such a semiconductor integrated circuit manufacturing method is a method of manufacturing a semiconductor integrated circuit using a mask pattern obtained based on circuit information, and the circuit information operates at a reference temperature. The temperature-independent circuit information indicating the circuit configuration of the semiconductor integrated circuit designed as described above is changed to reflect the crosstalk noise due to the self-heating of the wiring by the circuit operation verification process by the circuit operation verification apparatus 100 of the first embodiment. Temperature-dependent circuit information obtained in this way.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. It is understood that the non-patent literature cited in the present specification should be incorporated by reference into the present specification in the same manner as the content itself is specifically described in the present specification. .

  The present invention considers heat generated by wiring self-heating when calculating the resistance of a wiring resistance element in the field of circuit operation verification apparatus, semiconductor integrated circuit manufacturing method, circuit operation verification method, control program, and recording medium. Thus, accurate crosstalk noise verification can be performed, and in LSI (Large-Scale Semiconductor Integrated Circuit) design using automatic placement and routing of standard elements, the performance and design period of the LSI are subject to circuit operation verification. Since it depends on the accuracy, it is useful in designing such an LSI.

2 Operation unit 3 Display 4 CPU
5 RAM
6 ROM
DESCRIPTION OF SYMBOLS 7 Database 100 Circuit operation verification apparatus 101 Wiring information extraction part 102 Resistance value calculation part 103 Crosstalk noise calculation part 104 Violation net detection part 105 Equivalent circuit information extraction part 111 Signal wiring information storage part 112 Signal wiring resistance element information extraction part 113 Signal Wiring resistance element information storage section 114 Temperature dependent signal wiring resistance calculation section 115 Temperature dependent signal wiring resistance element information storage section 116 Temperature dependent signal wiring information storage section 117 Temperature dependent crosstalk noise calculation section 118 Temperature dependent crosstalk noise storage section 119 Cross Talk noise violation point detection unit 120 Violation net storage unit 121 Temperature coefficient storage unit 122 Heat distribution information storage unit 123 Specified value storage unit 124 Driver resistance storage unit 125 Receiver input capacity storage unit 126 Signal wiring capacity storage unit

Claims (23)

A circuit operation verification device that verifies whether or not a semiconductor integrated circuit having a plurality of circuit elements malfunctions due to crosstalk noise between adjacent signal wirings in the circuit,
Temperature dependence for calculating a temperature dependent resistance distribution in the signal wiring depending on the heat distribution in the signal wiring from circuit information indicating a basic layout of the semiconductor integrated circuit and heat distribution information indicating heat distribution in the semiconductor integrated circuit A resistance distribution deriving unit;
A circuit operation verification apparatus comprising: a crosstalk noise verification unit that calculates crosstalk noise between signal wirings according to a temperature-dependent resistance distribution in the signal wirings. In the inspection circuit operation proof device according to claim 1,
As the heat distribution information, heat distribution for storing heat distribution information due to self-heating of the wiring, which is a phenomenon in which energy consumption due to resistance of the signal wiring generates heat inside the signal wiring and leads to a temperature rise of the signal wiring An information storage unit,
The temperature-dependent resistance distribution derivation unit is a circuit operation verification device that calculates a temperature-dependent resistance distribution in the signal wiring based on heat distribution information stored in the heat distribution information storage unit. The circuit operation verification device according to claim 1,
A resistance element information deriving unit for deriving a resistance value and position information of a resistance element which is a resistance component of a divided wiring obtained by dividing a signal wiring in the semiconductor integrated circuit into a plurality of signal wiring information of the semiconductor integrated circuit With
The resistance element information deriving unit
A signal wiring information storage unit for storing signal wiring information of the semiconductor integrated circuit as circuit information indicating the basic layout;
A resistance element information extraction unit that extracts the resistance value and position information of the resistance element from the signal wiring information of the semiconductor integrated circuit stored in the signal wiring information storage unit;
A resistance element information storage unit that stores the resistance value and position information of the extracted resistance element;
The temperature-dependent resistance distribution deriving unit calculates a temperature-dependent resistance distribution in the signal wiring based on a resistance value and position information of the resistance element stored in the resistance element information storage unit. In the circuit operation verification device according to claim 2,
The temperature dependent resistance distribution deriving unit is:
A circuit operation verification apparatus having a temperature-dependent resistance element information storage unit that stores a temperature-dependent resistance distribution in the signal wiring calculated from heat distribution information in the signal wiring stored in the heat distribution information storage unit. In the circuit operation verification apparatus according to claim 3,
It has a temperature coefficient storage unit that stores a temperature coefficient indicating resistance variation inherent to the wiring material,
The temperature-dependent resistance distribution deriving unit multiplies the difference between the temperature of each resistive element and the reference temperature of each resistive element by the temperature coefficient stored in the temperature coefficient storing unit, and A circuit operation verification apparatus having a resistance calculation unit that calculates a temperature-dependent resistance value in consideration of temperature. The circuit operation verification device according to claim 1,
An information extraction unit that extracts the output driving resistance of the driver cell, the input terminal capacitance of the receiver cell, and the signal wiring capacitance from the signal wiring information of the semiconductor integrated circuit stored in the signal wiring information storage unit;
The information extraction unit
A driver resistance storage section for storing the output drive resistance of the driver cell;
A receiver input capacity storage for storing the input terminal capacity of the receiver cell;
A signal wiring capacity storage unit for storing the signal wiring capacity;
A circuit operation verification device that transfers the output drive resistance of the driver cell, the input terminal capacitance of the receiver cell, and the signal wiring capacitance from each storage unit to the crosstalk noise verification unit. In the circuit operation verification device according to claim 6,
The crosstalk noise verification unit
The circuit showing the basic layout in which the temperature-independent resistance distribution information in the signal wiring included in the circuit information showing the basic layout is replaced with the temperature-dependent resistance distribution information in the signal wiring calculated by the temperature-dependent resistance distribution deriving unit. Based on the information, the driver resistance, the receiver input capacitance, and the signal wiring capacitance extracted from the driver resistance storage unit, the receiver input capacitance storage unit, and the signal wiring capacitance storage unit, respectively, and the temperature dependence in the signal wiring Circuit operation verification device that calculates crosstalk noise. In the circuit operation verification apparatus according to claim 7,
The crosstalk noise verification unit includes a crosstalk noise storage unit that stores a calculation result of the temperature dependent crosstalk noise as temperature dependent crosstalk noise for each standard element constituting the basic layout. The circuit operation verification apparatus according to claim 8,
The temperature-dependent crosstalk noise for each signal wiring stored in the crosstalk noise storage unit is compared with the specified crosstalk value for each signal wiring, and the crosstalk noise violates the specified value. A circuit operation verification apparatus including a violation net detection unit that detects a signal wiring as an error net. In the circuit operation verification apparatus according to claim 9,
The violation net detection unit is a circuit operation verification device having a specified value storage unit for storing a specified value of crosstalk for each signal wiring. A method of manufacturing a semiconductor integrated circuit using a mask pattern obtained based on circuit information,
11. The circuit operation verification process by the circuit operation verification apparatus according to claim 1, wherein the circuit information includes temperature-independent circuit information indicating a circuit configuration of a semiconductor integrated circuit designed to operate at a reference temperature. Thus, a method of manufacturing a semiconductor integrated circuit, which is temperature-dependent circuit information obtained by changing to reflect crosstalk noise due to self-heating of the wiring. A circuit operation verification method for verifying whether a semiconductor integrated circuit having a plurality of circuit elements malfunctions due to crosstalk noise between adjacent signal wires in the circuit,
Temperature dependence for calculating a temperature dependent resistance distribution in the signal wiring depending on the heat distribution in the signal wiring from circuit information indicating a basic layout of the semiconductor integrated circuit and heat distribution information indicating heat distribution in the semiconductor integrated circuit A resistance distribution derivation step;
A circuit operation verification method including a crosstalk noise calculation step of calculating crosstalk noise between signal wirings according to a temperature-dependent resistance distribution in the signal wirings. The circuit operation verification method according to claim 12,
As the heat distribution information, heat distribution information is stored as heat distribution information due to self-heating of the wiring, which is a phenomenon in which energy consumption due to the resistance of the signal wiring generates heat inside the signal wiring and leads to a temperature rise of the signal wiring. Stored in the department,
In the temperature dependent resistance distribution derivation step, a circuit operation verification method for calculating a temperature dependent resistance distribution in the signal wiring based on heat distribution information stored in the heat distribution information storage unit. The circuit operation verification method according to claim 12,
A resistance element information deriving step for deriving a resistance value and position information of a resistance element that is a resistance component of a divided wiring obtained by dividing the signal wiring in the semiconductor integrated circuit into a plurality of signal wiring information of the semiconductor integrated circuit Including
In the resistance element information deriving step,
From the signal wiring information of the semiconductor integrated circuit stored in the signal wiring information storage unit as circuit information indicating the basic layout, the resistance value and position information of the resistance element are extracted and stored in the resistance element information storage unit,
In the temperature dependent resistance distribution deriving step, a circuit operation verification method for calculating a temperature dependent resistance distribution in the signal wiring based on a resistance value and position information of the resistance element stored in the resistance element information storage unit. The circuit operation verification method according to claim 13,
In the temperature dependent resistance distribution derivation step, the temperature dependent resistance distribution in the signal wiring calculated from the heat distribution information in the signal wiring stored in the heat distribution information storage section is stored in the temperature dependent resistance element information storage section. Circuit operation verification method. The circuit operation verification method according to claim 14,
In the temperature-dependent resistance distribution derivation step, the difference between the temperature of each resistance element and the reference temperature of each resistance element is multiplied by the temperature coefficient stored in the temperature coefficient storage unit, A circuit operation verification method including a resistance calculation step for calculating a temperature-dependent resistance value in consideration of temperature. The circuit operation verification method according to claim 12,
From the signal wiring information of the semiconductor integrated circuit stored in the signal wiring information storage unit, the output driving resistance of the driver cell, the input terminal capacitance of the receiver cell, and the signal wiring capacitance are extracted, and the driver resistance storage unit, , Store in the receiver input capacity storage section and the signal wiring capacity storage section,
In the crosstalk noise verification step, according to the temperature-dependent resistance distribution in the signal wiring from the output driving resistance of the driver cell, the input terminal capacity of the receiver cell, and the signal wiring capacity stored in these storage units. A circuit operation verification method for calculating crosstalk noise between signal lines. The circuit operation verification method according to claim 17,
In the crosstalk noise verification step, the temperature-independent resistance distribution information in the signal wiring included in the circuit information indicating the basic layout is converted into the temperature-dependent resistance distribution information in the signal wiring calculated in the temperature-dependent resistance distribution derivation step. Based on the circuit information indicating the replaced basic layout, from the driver resistance, the receiver input capacitance storage unit, and the signal wiring capacitance storage unit, the driver resistance, the receiver input capacitance storage unit, and the signal wiring capacitance, respectively. A circuit operation verification method for calculating temperature-dependent crosstalk noise in the signal wiring. The circuit operation verification method according to claim 18,
A circuit operation verification method in which, in the crosstalk noise verification step, a calculation result of the temperature dependent crosstalk noise is stored in a crosstalk noise storage unit as temperature dependent crosstalk noise for each standard element constituting the basic layout. The circuit operation verification method according to claim 19,
A temperature-dependent crosstalk noise for each standard element stored in the crosstalk storage unit is compared with a specified value of crosstalk for each standard element, and the signal in which the crosstalk noise violates the specified value A circuit operation verification method including a violation net detection step of detecting a wiring as an error net. The circuit operation verification method according to claim 20,
In the violation element detection step, a circuit operation verification method for storing a specified value of crosstalk for each standard element in a specified value storage unit.   A control program in which a processing procedure for causing a computer to execute each step of the circuit operation verification method according to any one of claims 12 to 21 is described.   A computer-readable readable storage medium in which the control program according to claim 22 is stored.

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