JP2009301444A - Element layout wiring apparatus, manufacturing method of semiconductor integrated circuit, element layout wiring method, control program, and recording medium - Google Patents

Abstract

Delay improvement can be performed at an early stage of designing a semiconductor integrated circuit, and an accurate resistance value of wiring between circuit elements can be obtained in consideration of a temperature rise due to self-heating of wiring between circuit elements. As a result, the delay can be effectively reduced by inserting a repeater for the wiring.
In an element placement and routing apparatus, a signal delay time deriving means for deriving a signal delay time in each wiring in consideration of an average temperature of each wiring of a semiconductor integrated circuit, and an average temperature in each wiring Repeater optimum value determining means 100a for determining the optimum size and the optimum number of repeater cells to be inserted in the wiring so as to reduce the signal delay time in the wiring based on the signal delay time considering the The basic layout of the integrated circuit is changed to a layout in which the determined number of repeaters are inserted into the wiring that requires the insertion of the repeater cells.
[Selection] Figure 1

Description

  The present invention relates to an element placement and routing apparatus, a semiconductor integrated circuit manufacturing method, an element placement and routing method, a control program, and a recording medium, and in particular, an LSI (large-scale semiconductor integrated circuit) design using automatic placement and routing of standard elements. In the method, when a repeater is inserted into the wiring so as to reduce a signal delay in a relatively long signal wiring connecting circuit elements, the wiring resistance increases due to an increase in wiring temperature due to Joule heat. The present invention relates to a technique for inserting a repeater cell in consideration of a delay time variation in wiring between circuit elements.

  Conventionally, there is a method of designing an LSI using an automatic placement and routing method of standard elements (standard cells). However, with the high integration of semiconductor integrated circuits, signal delay and current density in wiring due to the reduction of design rules. Heat generation in wiring due to an increase in the number of wires has become a problem, and countermeasures against such a problem are necessary.

(1) Wiring delay reduction by inserting repeater Generally, delay between gates, that is, delay amount from one fan's fan-in (output end) to fan-in (input end) of another gate following that one gate (delay) Time) Td can be expressed as the following equation (1). Here, the gate is a functional block such as an inverter circuit, and is configured using one or more standard cells.

Td = Tgate + Twire (1)
Here, Tgate is the sum of the gate delay that does not depend on the wiring load, the gate delay related to the wiring load, and the delay that depends on the bluntness of the previous stage. Here, the gate delay that does not depend on the wiring load is a signal delay amount inherent to the gate, the gate delay relating to the wiring load is a signal delay amount in the gate caused by inserting the gate into the circuit, and Twire represents a wiring delay amount that is a signal delay amount unique to the wiring.

  As the design rule of the semiconductor integrated circuit is reduced, in the delay represented by the expression (1), the proportion of the wiring delay (Twire) is larger than the gate delay (Tgate). As a result, it is an indispensable problem to consider wiring delay in the layout wiring design of an LSI chip (semiconductor integrated circuit chip). This is because, as the transistor device is miniaturized, the gate delay is reduced while the wiring resistance is increased.

  In order to design a high-speed semiconductor integrated circuit, it is necessary to reduce the value of each term in Equation (1). In particular, since the wiring delay (Twire) is dominant as described above, it can be said that reduction of the wiring delay (Twire) in the equation (1) is an essential issue for speeding up.

  To solve this problem, there is a method to reduce the total delay time by inserting a repeater cell (delay adjustment cell: buffer cell) in the middle of the wiring when the wiring is relatively long, such as inter-block wiring connecting functional blocks. well known.

  For example, as shown in FIG. 10, when the functional block (output side gate) 11 and the functional block (input side gate) 12 are connected by the wiring 10, the drive cell belonging to the functional block 11 drives the entire wiring 10. If the capacity is not sufficient, the repeater cell is inserted into the wiring 10 formed between the functional blocks, and the wiring 10 is divided by the repeater cell that compensates for the driving force.

  Conventional repeater insertion includes a method in which the signal delay time of the wiring is analytically obtained to divide the wiring into equal intervals (Non-Patent Document 1), or a delay analysis tool virtually inserts a repeater into the wiring to limit the delay. A method of estimating whether or not the value is satisfied by trial and error by circuit simulation or the like has been adopted.

  FIG. 3 is a diagram for explaining the former method of analytically obtaining the signal delay time and dividing the wiring into equal intervals. The repeater cell (hereinafter simply referred to as a repeater) is used for the wiring 10 shown in FIG. .) Are inserted.

In this method, as shown in FIG. 3, k repeaters Rp1 to Rpk having the same size (that is, the same driving capability) are inserted into a signal wiring having a wiring length L at equal intervals, and the entire delay time is evenly divided. This is a method for obtaining the delay time k times as long as each wiring. When such a technique disclosed in Non-Patent Document 1 is used, the signal delay time T _pd from the input terminal Vin of the first-stage repeater Rp1 to the output terminal _Vout of the last-stage repeater Rpk _in FIG. It is represented by (2).

ここで、式（２）のＣ_ｉｎｔ、Ｒ_ｉｎｔはそれぞれ、前記配線１０の容量、抵抗であり、図３のＣＬは信号の受け側ゲート（図１０のレシーバセル１２）の入力容量である。また、Ｃ_０、Ｒ_０は最小サイズのリピータの入力容量と出力抵抗であり、ｈは挿入しようとするリピータの、最小サイズのリピータに対する電流駆動能力の比率を示す。即ち、リピータの電流駆動能力は、リピータを構成するトランジスタのＷｇ／Ｌｇ（ゲート幅／ゲート長）に比例して大きくなり、トランジスタのＷｇ／Ｌｇ比をｈ倍にすると、リピータの出力抵抗と入力容量は、各々Ｒ_０／ｈ、ｈＣ_０となる。なお、式（２）では、ＣＬはｈＣ_０として計算している。上記式（２）をｋ、ｈで偏微分して∂Ｔ_ｐｄ／∂ｋと∂Ｔ_ｐｄ／∂ｈをゼロとおくと、次式（３）、（４）のように最適な分割数ｋと最適なリピータサイズｈを求めることができる。

Here, C _int and R _int in equation (2) are the capacitance and resistance of the wiring 10, respectively, and CL in FIG. 3 is the input capacitance of the signal receiving gate (receiver cell 12 in FIG. 10). C ₀ and R ₀ are the input capacity and output resistance of the repeater of the minimum size, and h indicates the ratio of the current drive capability of the repeater to be inserted to the repeater of the minimum size. That is, the current drive capability of the repeater increases in proportion to the Wg / Lg (gate width / gate length) of the transistor constituting the repeater. When the Wg / Lg ratio of the transistor is multiplied by h, the output resistance of the repeater and the input The capacities are R ₀ / h and hC ₀ , respectively. In equation (2), CL is calculated as hC _0. When the above equation (2) is partially differentiated by k and h, and ∂T _pd / ∂k and ∂T _pd / ∂h are set to zero, the optimal division number k as in the following equations (3) and (4) And the optimum repeater size h can be obtained.

上記式（３）および式（４）で求めた、サイズｈのリピータＲｐをｋ個だけ、該配線１０に等間隔に挿入することにより、最適な遅延の改善を実現できる。なお、図４は、図３に示すリピータとして、最小サイズのｋ個のリピータ（ｈ＝１）、つまりリピータＲｓ１〜Ｒｓｋを用いた場合の配線分割の例を示す。

By inserting only k repeaters Rp of size h obtained by the above formulas (3) and (4) into the wiring 10 at an equal interval, the optimum delay improvement can be realized. 4 shows an example of wiring division when k repeaters (h = 1) of the minimum size, that is, repeaters Rs1 to Rsk are used as the repeaters shown in FIG.

  If this method is used, the delay is improved by repeater insertion while estimating the delay using the analytical expression (Equation (2)) at the rough wiring stage after the automatic layout is completed. There is an advantage that improvement can be made.

  On the other hand, in the latter repeater insertion method, a repeater or delay element is virtually inserted on the target wiring, a delay time is calculated by circuit simulation or the like, and trial and error are repeated until the delay constraint is satisfied. Is. Since this method inserts repeaters at the final stage of layout completion, it is necessary to correct the layout again when delay improvement is required, which affects the placement of adjacent elements and the layout of wiring. There is a risk. Moreover, there is a drawback that it takes a lot of processing time due to circuit simulation.

(2) Self-heating problem of LSI wiring Along with higher integration and higher speed of LSI due to advances in semiconductor processing technology, the heat generation problem accompanying an increase in power density of LSI has become serious. In particular, in the wiring, the temperature rise of the wiring due to Joule heat generated by the current flowing through the wiring, that is, the problem of self-heating is serious. When the temperature of the wiring rises, the reliability deteriorates due to electromigration, and the circuit operating speed decreases due to the increase in wiring resistance, leading to performance deterioration. Here, the relationship between the wiring resistance r and the temperature T is generally approximated by the following equation.

r = r ₀ (1 + β (T−T ₀ )) (5)
Where T is a temperature to be analyzed (temperature in a heat generation state), T ₀ is a reference temperature (environment temperature), r ₀ is a resistance value when the temperature is T ₀ , and β is a temperature coefficient of the wiring. Here, the temperature coefficient β is approximately 0.003 in the case of Cu wiring currently used in semiconductor manufacturing. In this case, from equation (5), the rate of change in resistance when the temperature of the wiring rises by 100 ° C. is 30%. In other words, when the temperature of the wiring rises due to the self-heating of the wiring, it is inevitable that the wiring resistance increases and the reduction in the circuit operation speed causes performance deterioration. According to Non-Patent Document 2, it is predicted that the temperature rise of the wiring in the LSI manufactured using the fine process after 50 nm technology will be 300 to 700 ° C at the maximum, and the self-heating of the wiring will be in the future. It is an increasingly serious problem.

  Under such circumstances, when designing an LSI, it is important to perform the design considering the heat described above. The thermal analysis of LSI can be performed using commercially available CAD software, numerical simulation software, or mathematical expression processing software. Here, a method of thermal analysis is briefly shown. In general, the heat distribution of a three-dimensional object in an LSI can be obtained by solving a heat conduction equation (equation (6)) derived from the principle of energy conservation law.

cρ∂T / ∂t = k∂ ² T / ∂x ² + k∂ ² T / ∂y ²
+ K∂ ² T / ∂ z ² + q (6)
However, t is time and T is temperature. In addition, the internal heat generation per unit time / unit volume is represented by q (x, y, z, t), the specific heat of the substance is represented by c, the density is represented by ρ, and the thermal conductivity is represented by k.

  LSI thermal analysis is generally performed in a steady state. When the heat generation is in a steady state, there is no transitional temperature change, so the left side of Equation (6) is zero. Therefore, a thermal circuit resistance network can be created by discretizing the heat conduction equation in which the left side of equation (6) is replaced with 0 using the concept of control volumes and connecting the control volumes with resistors. A heat distribution is obtained by setting a heat source in the thermal circuit resistor network thus formed, modeling it as a thermal diffusion analysis model, and performing numerical analysis. Note that the concept of numerical analysis using a control volume is well known, and a description thereof is omitted here.

Now, as an example of thermal analysis, let us consider the heat distribution of wiring when heat generated by current consumed by the wiring is used as a heat source. For the sake of simplicity, consider the heat distribution of a wiring having a structure as shown in FIG. A wiring 10 shown in FIG. 6 is a wiring having a wiring width w, a wiring thickness t _m , a wiring length L, and a wiring height from the substrate 1 to t _ox , and both ends thereof are connected to the substrate 1. 10a. At this time, the heat distribution in the length direction of the wiring can be considered in one dimension (formula (7)).

^{cρ∂T / ∂t = k∂ 2 T /} ∂x 2 + q ... (7)
According to Non-Patent Document 3, a one-dimensional thermal diffusion equation in a steady state can be derived from the amount of heat generated inside the wiring and the amount of heat released by thermal diffusion in the insulating film. However, the electrical resistivity of the wiring, the thermal conductivity of the wiring, the temperature coefficient of the electrical resistance of the wiring, and the thermal conductivity of the insulating film necessary for derivation are values specific to the substance. Further, the RMS (Root Mean Square) current Irms of the wiring depends on the operation of the LSI and is a value estimated by a power consumption simulation or the like. FIG. 7 shows the heat distribution in the wiring 10 thus obtained. Here, it is assumed that the surface temperature of the substrate is uniform, and this temperature is Tref (= T ₀ ). The horizontal axis of the heat distribution shown in FIG. 7 represents the position x (um) in the length direction of the wiring, and the vertical axis represents the temperature T (° C.) of the wiring. As can be seen from FIG. 7, the temperature of the wiring in the steady state is not uniform and is not uniform in the length direction, and the temperature becomes maximum (hereinafter referred to as ΔTmax) near the center of the wiring. Due to the diffusion, the temperature decreases toward both ends connected to the substrate.
Circuits, Interconnections, and Packaging for VLSI, H.C. B. Bakoglu, Addison-Wesley Publishing Company, 1990. Scaling Analysis of Multilevel Interconnect Temperature for High-Performance ICs, Sungjun Im, Navin Srivastava, Kaustav Banenerhe, and K. Goodson, IEEE Transaction Devices. Vol. 52. No. 12 December 2005. Electrothermal Analysis of VLSI Systems, Yi-Kan Cheng, Ching-Hang Tsai, Chin-Chi Teng, and Sung-Mo (Steve) Kang, Kluwer Academic Public. 2000.

  As described above, the temperature in the LSI wiring increases due to self-heating, and as a result, the resistance changes. When a repeater is inserted to improve the delay, it is necessary to consider the temperature change of the wiring.

  However, according to the repeater cell insertion method according to the first method described above, the temperature difference between the wiring and the substrate due to the self-heating of the wiring as described above is not taken into consideration. When the temperature of the wiring rises, the resistance value of the wiring resistance increases as shown by the equation (5). In the conventional repeater insertion according to the first method, the wiring delay is underestimated by not considering the increase in resistance due to the self-heating of the wiring. As a result, even if the wiring can be improved by the repeater insertion, it is no longer necessary. Repeater insertion is unnecessary, or an optimally sized repeater cannot be determined, and it may be determined that further delay improvement is impossible.

  Further, in the second method described above, that is, in a method in which the delay analysis tool virtually inserts a repeater and estimates whether or not the delay constraint value is satisfied by trial and error by circuit simulation or the like, when the circuit scale increases, There is a problem that a large amount of processing time is required for delay analysis. That is, it is not practical to repeat the repeater insertion while looking at the delay constraint of every path. In addition, since the estimation is made at the stage when the layout is completed, it takes time for the modification and the development period is deteriorated as compared with the modification at the early stage of development.

  The present invention has been made to solve the above-described problems, can improve the delay at an early stage of design, and considers a temperature rise due to self-heating of wiring between circuit elements. Using the element arrangement and wiring apparatus, the element arrangement and wiring apparatus, the element arrangement and wiring method, and the element arrangement and wiring apparatus that can effectively reduce the delay by inserting the repeater It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit, a control program for causing a computer to execute the element placement and routing method, and a storage medium storing the control program.

  An element placement and routing apparatus according to the present invention is an element placement and routing apparatus for creating a layout of a plurality of circuit elements constituting a semiconductor integrated circuit and a layout of wirings positioned between the circuit elements. The average temperature of each wiring is obtained from the circuit information indicating the layout and the heat distribution information indicating the heat distribution in the semiconductor integrated circuit, and the signal delay time in each wiring is derived by the temperature dependent resistance considering the average temperature of each wiring. And determining the size and number of repeater cells to be inserted in the wiring so that the signal delay time in the wiring is reduced, based on the signal delay time deriving means to be performed and the signal delay time in consideration of the average temperature of each wiring A repeater optimum value determining means, and a basic layout of the semiconductor integrated circuit created based on the circuit information for wiring that requires insertion of the repeater cell. It is those repeater cell size as the decision has a repeater arrangement means for changing only inserted layout number determined the above-described object can be achieved.

  The present invention provides a heat distribution information storage unit for storing heat distribution information by self-heating of each wiring obtained by heat distribution analysis of the semiconductor integrated circuit, and a heat distribution information storage unit in the element placement and wiring apparatus. It is preferable to have an average temperature calculation unit that calculates the average temperature of each wiring from the stored heat distribution information, and an average temperature storage unit that stores the calculated average temperature of each wiring.

  The present invention provides the above-described element placement and routing apparatus, further comprising a schematic wiring information storage unit that stores information related to a schematic wiring that is a wiring in the basic layout of the semiconductor integrated circuit, and the schematic wiring information storage unit includes a wiring for the schematic wiring. It is preferable that the length is stored as a correspondence table in which the signal net name for specifying the schematic wiring is associated with the wiring length of the schematic wiring.

  The element placement and routing apparatus includes a delay parameter storage unit that stores a delay parameter that affects a signal delay in wiring between the circuit elements, and the signal delay time deriving unit includes the delay parameter storage unit. It is preferable to derive the signal delay time in the wiring corresponding to the temperature-dependent resistance in the wiring based on the delay parameter stored in.

  According to the present invention, in the element placement and routing apparatus, the delay parameter storage unit preferably includes a resistance storage unit that stores a resistance per unit length specific to a wiring material constituting the wiring as the delay parameter.

  In the element placement and routing apparatus according to the present invention, it is preferable that the delay parameter storage unit includes a capacity storage unit that stores a capacity per unit length specific to a wiring material constituting the wiring as the delay parameter.

  In the element placement and routing apparatus according to the present invention, it is preferable that the delay parameter storage unit includes a temperature coefficient storage unit that stores a temperature coefficient of resistance specific to a wiring material constituting the wiring as the delay parameter.

  In the element placement and routing apparatus according to the present invention, it is preferable that the delay parameter storage unit includes an element input capacitance storage unit that stores input capacitances of all circuit elements constituting the semiconductor integrated circuit as the delay parameters. .

  In the element placement and routing apparatus according to the present invention, the delay parameter storage unit preferably includes an element output resistance storage unit that stores output resistances of all circuit elements constituting the semiconductor integrated circuit as the delay parameter. .

  In the element placement and routing apparatus according to the present invention, it is preferable that the device includes a delay constraint storage unit that stores signal delay time constraints set for all wirings positioned between the circuit elements in the semiconductor integrated circuit. .

  In the element placement and routing apparatus according to the present invention, the signal delay time deriving unit is configured to calculate the delay in consideration of the temperature dependence of each wiring based on the average temperature of each wiring stored in the average temperature storage unit. And a temperature-dependent delay calculation unit that calculates a signal delay time in each wiring, and a temperature-dependent delay storage unit that stores the signal delay time in each wiring calculated by the temperature-dependent delay calculation unit It is preferable.

  According to the present invention, in the element placement and routing apparatus, the optimum repeater value determining means refers to an average temperature of each wiring, considers temperature dependence of the wiring, and determines an optimum repeater cell to be inserted into the wiring. It is preferable to have a repeater optimum value determining unit for determining a proper size and optimum number, and a repeater optimum value storing unit for storing the optimum size and optimum number obtained by the repeater optimum value determining means.

  According to the present invention, in the element placement and routing apparatus, the repeater placement means selects the repeater cell having the optimum size based on the optimum size and number of repeater cells stored in the repeater optimum value storage unit. It is preferable to insert the same number of wires into the wiring.

  A method of manufacturing a semiconductor integrated circuit according to the present invention is a method of manufacturing a semiconductor integrated circuit using a mask pattern obtained based on circuit information, and the circuit information is created by the above-described element placement and wiring apparatus. In addition, the layout of the circuit elements and wirings of the semiconductor integrated circuit is shown, whereby the above object is achieved.

  An element arrangement and wiring method according to the present invention is an element arrangement and wiring method for creating a layout of a plurality of circuit elements constituting a semiconductor integrated circuit and a wiring layout for connecting the preceding stage circuit element and the subsequent stage circuit element. A repeater cell insertion step of inserting a repeater cell so that a signal delay time in the wiring is reduced, and the repeater cell insertion step includes a rise in temperature of the wiring due to Joule heat generated by current flowing in the wiring In consideration of the above, the step of deriving the signal delay time of each of the plurality of wirings in the semiconductor integrated circuit, and the constraint violation that is the wiring causing the delay time constraint violation based on the signal delay time of each wiring Extracting a net; determining an optimal layout of repeater cells to be inserted for the constraint violating net; and Boss was based on the optimal layout of the repeater cell, which comprises the step of inserting the repeater cell in 該制 about violation net, the objects can be achieved.

  According to the present invention, in the element placement and routing method, the step of deriving the signal delay time includes calculating an average temperature of the wiring based on heat distribution information by self-heating of the wiring obtained by a heat distribution analysis of the semiconductor integrated circuit. An average temperature calculation step to be obtained, and a step of storing the obtained average temperature in the average temperature storage unit, and the temperature in the wiring based on the average temperature of each wiring stored in the average temperature storage unit It is preferable to derive a signal delay time corresponding to the dependency resistance.

  According to the present invention, in the element arrangement and wiring method, the wiring for connecting the preceding circuit element and the subsequent circuit element is included in the basic layout of the semiconductor integrated circuit as a plurality of schematic wirings. Are preferably stored in the schematic wiring information storage unit as a correspondence table in which the signal net name for specifying each schematic wiring and the wiring length of each schematic wiring are associated with each other.

  In the element placement and wiring method according to the present invention, it is preferable that the resistance per unit length unique to the wiring material constituting the wiring is stored in the resistance storage section.

  In the element placement and routing method according to the present invention, it is preferable that the capacity per unit length unique to the wiring material constituting the wiring is stored in a capacity storage unit.

  In the element placement and routing method according to the present invention, it is preferable that input capacitances of all circuit elements constituting the semiconductor integrated circuit are stored in an element input capacitance storage unit.

  In the element placement and routing method according to the present invention, it is preferable that output resistances of all circuit elements constituting the semiconductor integrated circuit are stored in an element output resistance storage unit.

  According to the present invention, in the element placement and routing method, signal delay time constraints set for all wirings located between the circuit elements in the semiconductor integrated circuit are stored in a delay constraint storage unit. preferable.

  In the element placement and routing method according to the present invention, the step of deriving the signal delay time considers the temperature dependence of each wiring based on the average temperature of each wiring stored in the average temperature storage unit. It is preferable to include a step of performing a delay calculation to calculate a signal delay time in each wiring, and a step of storing the calculated signal delay time in each wiring in a temperature-dependent delay storage unit.

  According to the present invention, in the element placement and routing method, in the step of determining the optimum size and the optimum number of the repeater cells, the temperature dependence of the constraint violation net is considered with reference to the average temperature of the constraint violation net. Thus, it is preferable that the optimum size and number of repeater cells to be inserted into the constraint violation net are determined, and the determined optimum size and number of repeater cells are stored in the optimum repeater value storage unit.

  In the element placement and routing method according to the present invention, it is preferable that, in the repeater placement step, an optimum number of repeaters are inserted into the constraint violation net in an optimum number.

  According to the present invention, in the element placement and routing method, the layout of the plurality of circuit elements constituting the semiconductor integrated circuit and the layout of the wiring between the circuit elements in the preceding stage and the succeeding stage are subjected to constraints on delay time by automatic layout processing. An automatic layout step for creating a basic layout in which repeater cells are inserted without considering the temperature dependence of the resistance of the wiring so as to satisfy, as a step before the repeater cell insertion step, the repeater cell insertion step Includes a delay verification step for verifying a delay time in consideration of the temperature distribution due to the self-heating of the wiring in the basic layout, and according to the result of the delay verification, the repeater cell of the repeater cell with respect to the constraint violation net in the basic layout. It is preferable to perform insertion.

  In the element placement and routing method according to the present invention, the repeater cell insertion step includes a step of obtaining an average temperature of the wiring from a temperature distribution due to the self-heating of the wiring in the basic layout, and the delay verification step It is preferable to verify the delay time of the wiring based on the average temperature.

  In the element placement and routing method according to the present invention, the repeater cell insertion step includes a delay improvement determination step of determining whether or not delay improvement is possible when a repeater cell is inserted into the constraint violation net, It is preferable that a repeater cell is inserted into the constraint violation net only when delay improvement is possible.

  The control program according to the present invention describes a processing procedure for causing a computer to execute each step of the element placement and routing method described above, and thereby the above-described object is achieved.

  The recording medium according to the present invention stores the above-described control program, thereby achieving the above object.

  The operation of the present invention will be described below.

  In the present invention, in the element placement and routing apparatus, the signal delay time deriving means for deriving the signal delay time in each wiring in consideration of the average temperature of each wiring in the semiconductor integrated circuit, and the average temperature in each wiring A repeater optimum value determining means for determining an optimum size and optimum number of repeater cells to be inserted in the wiring so as to reduce the signal delay time in the wiring based on the considered signal delay time, and a semiconductor integrated circuit The basic layout is changed to a layout in which the determined number of repeaters are inserted into the wiring that requires the insertion of the repeater cell, so that delay improvement can be performed at an early stage of design. In addition, an accurate resistance value of the wiring between the circuit elements can be obtained in consideration of a temperature rise due to self-heating of the wiring between the circuit elements. This makes it possible to determine the optimum size and the optimum number of repeaters to be inserted into the wiring by estimating the circuit delay using this resistance value when the delay is reduced by the repeater insertion of the wiring. Therefore, it is possible to effectively reduce delay by inserting repeaters.

  In the present invention, the semiconductor integrated circuit further includes a delay constraint storage unit that stores signal delay time constraints set for all the wirings positioned between the circuit elements, and stores the delay constraint storage unit in the delay constraint storage unit. Based on the specified signal delay time constraint, the wire with the signal delay time calculated considering the resistance distribution due to the temperature distribution of the wire is extracted as a constraint violation net, so the violation net can be extracted reliably. Can be done.

  For example, the violation net extracting unit extracts the violation net by a simple process of comparing the signal delay time constraint of the wiring stored in the delay constraint storage unit with the signal delay time of the derived wiring. can do.

  In the present invention, the delay improvement determination unit for determining whether or not the delay improvement is possible by inserting the repeater cell with respect to the constraint violation net is provided. Therefore, the size of the repeater cell and the number of insertions are determined according to the determination result. An operation to determine is performed. For this reason, it is possible to avoid useless processing such as insertion of a repeater cell for a wiring for which delay improvement cannot be obtained by insertion of a repeater cell.

  As described above, according to the present invention, the average temperature of each wiring is obtained from the circuit information indicating the basic layout of the semiconductor integrated circuit and the heat distribution information indicating the heat distribution in the semiconductor integrated circuit, and the average temperature of each wiring is determined. A signal delay time deriving means for deriving a signal delay time in each wiring due to the temperature-dependent resistance considered, and a signal delay time in the wiring based on the signal delay time considering the average temperature of each wiring It is necessary to insert the repeater cell into a repeater optimum value determining means for determining the size and number of repeater cells to be inserted so as to reduce the basic layout of the semiconductor integrated circuit created based on the circuit information. Repeater placement means for changing the layout to a layout in which the determined number of repeater cells are inserted in the wiring is provided at an early stage of design. In addition, it is possible to obtain an accurate resistance value of wiring between circuit elements in consideration of a temperature rise due to self-heating of the wiring between circuit elements, thereby reducing delay by inserting a repeater. Can be done automatically.

  First, as a basic principle of the present invention, a repeater insertion method in consideration of a temperature change due to self-heating of wiring will be described.

In general, when considering a wiring delay model of a circuit including a driver resistance (output resistance) R ₀ , a wiring resistance R _int , a wiring capacity C _int , and a receiver input capacity CL as shown in FIG. The delay D to the output terminal Vout can be expressed as follows using the well-known Sakurai equation.

  Note that Sakurai's formula can be found in the document “T. Sakurai, Application of Wiring Delay in MOSFET LSI, IEEE Journal of Solid-State Circuits, vol. SC-18, pp. 418-426, Aug. 1983. Is disclosed.

D = 0.4R _int C _int
+ 0.7 (R ₀ C _int + R ₀ CL + R _int CL) (8)
If there is a resistance change due to temperature change of the wiring as represented by the aforementioned formula (5), the R _int of formula (8), by replacing in considering the temperature of the wiring resistance value R _'int, A signal delay time D ′ (equation (9)) in consideration of the temperature of the wiring can be obtained.

D ′ = 0.4R ′ _int C _int
+ 0.7 (R ₀ C _int + R ₀ CL + R ′ _int CL) (9)
Now, the average temperature of the wiring having a one-dimensional temperature distribution as shown in FIG. 7 is obtained. FIG. 8 shows an average temperature T _ave added to the temperature distribution in FIG. Here, the average temperature is obtained by dividing the area of the temperature distribution obtained as a result of the thermal analysis by the wiring length L. That is, assuming that the temperature distribution of the wiring is T (x), the average temperature T _avg is expressed by the following equation (10).

ただし、Ｔ（ｘ）は、式（７）を解析的に解いて得られた解析式、あるいは、数値的に解いて得られた結果から多項式等の近似式をあてはめることにより容易に求めることができる。

However, T (x) can be easily obtained by applying an analytical expression obtained by analytically solving Expression (7) or an approximate expression such as a polynomial from the result obtained by numerically solving. it can.

When the average temperature T _avg of the wiring thus obtained is applied to T in Expression (5), the resistance of the resistance element in consideration of the temperature can be obtained. If the wiring resistance considering the temperature is R ′ _int , R ′ _int is expressed by the following equation (11).

R ′ _int = R _int (1 + β (T _avg −T0)) (11)
Then, by replacing _{R int} of formula (2) with R _'int of formula (11), the signal delay time is determined in consideration of the temperature of the wiring.

また、最適なリピータの数ｋ、および、リピータのサイズｈについても同様に、式（３）および（４）のＲ_ｉｎｔを、式（１１）のＲ’_ｉｎｔで置き換えることにより、配線の温度を考慮して求めることができる。

The number of optimal repeater k, and, similarly, the size h of the repeater, the _{R int} of formula (3) and (4), by replacing R _'int of formula (11), the temperature of the wire It can be determined in consideration.

今、式（１１）より、Ｒ’ｉｎｔ ＞ Ｒｉｎｔ であるので、ｋ’ ＞ ｋ、ｈ’ ＜ ｈとなり、配線の温度を考慮することにより必要なリピータの数は増加し、最適なリピータのサイズは小さくなるケースがあることがわかる。即ち、配線の温度を考慮したリピータ挿入を行わない場合、十分な遅延改善が行われない可能性がある。遅延による性能劣化を防ぐためには、遅延改善を最適にしておく必要がある。

Now, from equation (11), since R′int> Rint, k ′> k, h ′ <h, and the number of necessary repeaters increases by considering the wiring temperature, and the optimal repeater size It can be seen that there are cases where becomes smaller. That is, if repeater insertion is not performed in consideration of the wiring temperature, there is a possibility that sufficient delay improvement is not performed. In order to prevent performance degradation due to delay, it is necessary to optimize delay improvement.

  From the above, it can be seen that in order to improve the signal delay time by the optimum repeater insertion in consideration of the self-heating of the wiring, it is necessary to consider the change in resistance depending on the temperature.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram showing functional blocks of an element placement and routing apparatus according to Embodiment 1 of the present invention.

  The element placement and wiring apparatus 100 according to the first embodiment creates a layout of a plurality of circuit elements constituting a semiconductor integrated circuit and wirings located between the circuit elements.

  That is, the element placement and wiring apparatus 100 according to the present embodiment calculates the average temperature of each wiring from the heat distribution information storage unit 132 that stores heat distribution information obtained in advance by thermal analysis of the semiconductor integrated circuit, and the heat distribution information. An average temperature calculation unit 104 that performs the automatic layout and wiring process, and a schematic wiring information storage unit 131 that stores wiring (schematic wiring) information in the basic layout as circuit information indicating the basic layout of the semiconductor integrated circuit. A signal delay time deriving unit 101 for deriving a temperature-dependent delay time in each wiring based on the wiring information after the rough wiring stored in the general wiring information storage unit 131 and the average temperature of each wiring; The violation net extracting means 102 for extracting and storing the wiring (violating net) that violates the delay time constraint based on the temperature-dependent delay time, and the violation net And a repeater optimum value determining means 103 for determining the optimum size and the optimum number of repeaters to be inserted to.

  Here, in the schematic wiring information storage unit 131, the wiring length of the schematic wiring is stored as a correspondence table in which the signal net name for specifying the schematic wiring is associated with the wiring length of the schematic wiring. The wiring length information stored in the schematic wiring information storage unit 131 is wiring information such as the wiring length between circuit elements after performing schematic wiring for realizing the function of the semiconductor integrated circuit. The information is information on the wiring in which the repeater cell is inserted without considering the temperature of each wiring.

  Further, the heat distribution information storage unit 132 stores heat distribution information obtained by giving the current consumption value of the wiring obtained in advance by the power consumption simulation as a heat generation source and performing the thermal analysis simulation. Here, the heat distribution information indicates the coordinates on the layout and the temperature at the coordinates. Also, the heat distribution information storage unit 132 gives the current consumption value of the wiring obtained by the power consumption simulation in advance to the layout after the wiring generation as a heat source, and performs thermal analysis using commercially available CAD software or the like. It includes a temperature distribution storage unit 11 (see FIG. 12) that stores the temperature distribution information obtained as a function of the position of the wiring.

  Further, as shown in FIG. 12, the average temperature calculation unit 104 is configured to display the temperature distribution of each wiring stored in the temperature distribution storage unit 11 and the wiring extracted from the wiring length data table of the general wiring information storage unit 131. Using the length, the average temperature calculation unit 13 that calculates the average temperature of the wiring using the calculation method shown in the above formula (10), and the average temperature storage unit 111 that stores the calculated average temperature of the wiring, have.

  Further, the element placement and wiring apparatus 100 obtains the average temperature of each wiring from the circuit information indicating the basic layout of the semiconductor integrated circuit and the heat distribution information indicating the heat distribution in the semiconductor integrated circuit. In addition to the signal delay time deriving means 101 for deriving the signal delay time in each wiring due to the temperature dependent resistance considering temperature, the wiring is connected to the wiring based on the signal delay time considering the average temperature in each wiring. A repeater optimum value determining means 100a for determining the optimum size and optimum number of repeater cells to be inserted so as to reduce the signal delay time in the wiring, and a basic layout of the semiconductor integrated circuit created based on the circuit information A repeater that changes to a layout in which the determined number of repeaters are inserted into the wiring that requires insertion of the repeater cell And a join the club 121.

  The element placement and routing apparatus 100 includes a delay parameter storage unit 100b that stores a delay parameter that affects a signal delay in wiring between the circuit elements, and all of the elements located between the circuit elements in the semiconductor integrated circuit. And a delay constraint storage unit 122 for storing the signal delay time constraint set for each of the wires.

  Further, the signal delay time deriving means 101 is configured to perform the wiring based on the wiring length information stored in the general wiring information storage unit 131 and the average temperature of each wiring stored in the average temperature storage unit 111. A temperature-dependent delay calculation unit 112 for deriving a signal delay time in the wiring corresponding to the temperature-dependent resistance in the circuit, and a temperature-dependent delay storage unit 113 for storing delay time information indicating the derived signal delay time in the wiring. And have.

  The delay parameter storage unit 100b stores a delay parameter that affects the signal delay in the wiring between the circuit elements. The temperature dependent delay calculation unit 112 stores the delay parameter in the delay parameter storage unit 100b. The signal delay time in the wiring corresponding to the temperature-dependent resistance in the wiring is derived based on the delay parameter.

  Specifically, the delay parameter storage unit 100b includes a resistance capacity storage unit (unit length) that stores, as the delay parameter, a resistance and a capacity given per unit length specific to the wiring material constituting the wiring. Per-wire resistance / capacity storage unit) 114, and a temperature coefficient storage unit 115 storing a temperature coefficient of a resistance inherent to the wiring material constituting the wiring as a delay parameter for each wiring material, , An element information storage unit (cell input capacitance and output resistance information storage unit) that stores input capacitance and output resistance given in advance as delay parameters for all circuit elements (cells) constituting the semiconductor integrated circuit. 116.

  In addition, the wiring resistance / capacity storage unit 114 per unit length is obtained using a commercially available three-dimensional field solver, a two-dimensional LPE (Layout Parameter Extraction) tool (parasitic circuit component extraction tool), or the like. The wiring resistance / capacitance value per unit length for each wiring material is stored. The temperature coefficient storage unit 115 of the wiring resistance stores a coefficient of resistance change with respect to a temperature change, which is a unique value in semiconductor manufacturing for each wiring material.

FIG. 5 shows the temperature dependence of resistance. In [rho ₀ is the resistance at the temperature T ₀ of FIG. 5, the T ₀ to be referred to as reference temperature (environmental temperature), resistance [rho ₀ at the temperature T ₀ is assumed to be known. At this time, it is generally well known that the wiring resistance change with respect to the temperature change can be approximated linearly. That is, as described in FIG. 5, the temperature dependence of resistance can be expressed by Expression (15). Where T ′ is the temperature to be analyzed, T ₀ is the reference temperature, ρ ₀ is the resistance value when the temperature is T ₀ , and β is the temperature coefficient of the wiring.

r = ρ ₀ (1 + β (T′−T ₀ ))
= Ρ ₀ (1 + βT) (15)
However, T is a temperature change amount. The reference temperature T ₀ is the environmental temperature, for example, the temperature of the substrate surface.

In addition, as shown in FIG. 14, the storage unit 116 for cell input capacitance and output resistance includes an input capacitance _CL and an output resistance R ₀ for all functional cells (cells other than repeater cells) used in the semiconductor integrated circuit, The input capacitor _CL and the output resistance _R0 related to the repeater cells 11 and 12 to be inserted shown in FIG. 15 are stored.

  Further, the repeater optimum value determining means 100a is configured to determine whether the signal delay time calculated by the calculation unit 112 causes a constraint violation based on the signal delay time constraint stored in the delay constraint storage unit 122 (constraint). A violation net extracting means 102 for extracting a violation net), and an optimum value determination unit 119 for a repeater for determining the optimum size and the optimum number of repeaters to be inserted into the extracted constraint violation net.

  Here, the violation net extraction unit 102 is configured to determine the signal delay time constraint of the wiring stored in the delay constraint storage unit 122 and the signal delay of the derived wiring stored in the temperature-dependent delay storage unit 113. Based on the comparison with time, the violation net extraction unit 117 for extracting the violation net, the violation net storage unit 118 for storing information for specifying the extracted violation net, and a repeater cell are inserted into the constraint violation net A delay improvement determination unit 118a that determines whether or not delay improvement is possible. As shown in FIG. 13, the optimum value determining unit 119 for the repeater calculates the optimum number of repeaters to be inserted into the constraint violation net, and the optimum number of repeaters to be inserted into the constraint violation net. The repeater optimum size calculation unit 22 for calculating the size is used, and only when the delay can be improved, the calculation unit 21 and 22 calculate the size and the number of the repeaters, and the optimum value storage unit 120 of the repeater performs these calculations. The calculated size and number of items are stored. The repeater insertion unit 121 constitutes the repeater insertion device 103 together with the optimum value determination unit 119 and the optimum value storage unit 120 of the repeater.

  FIG. 2A is a block diagram illustrating a hardware configuration example of a main part of the element placement and routing apparatus illustrated in FIG.

  As shown in FIG. 2A, the element placement and routing apparatus 100 according to the present embodiment is configured by a computer system, and includes an operation input unit 2 such as a keyboard, a mouse, and a screen input device that enables various input commands. , A display unit 3 that can display various images such as an initial screen, a selection guidance screen, and a processing result screen on a display screen according to various input commands, and a CPU (central processing unit) that performs overall control. (Processing device) 110a, RAM 4 as temporary storage means that works as a work memory when the CPU 110a is started, a computer-readable readable recording medium (storage) in which a control program for operating the CPU 110a and various data used therefor are recorded. ROM5 as means) and various data in element placement and wiring processing can be stored and referred to And a database 6 for the.

  In addition to the input command from the operation input unit 2, the CPU 110a, based on the control program read from the ROM 5 into the RAM 4 and various data used therefor, the temperature-dependent delay calculation unit 101 and the violation net extraction unit 102 described above. The functions of the delay improvement determination unit 102a and the optimum value determination unit 103 of the repeater are respectively executed.

  The ROM 5 is configured by a readable recording medium (storage means) such as a hard disk, an optical disk, a magnetic disk, and an IC memory. The control program and various data used for the control program may be downloaded to the ROM 5 from a portable optical disk, a magnetic disk, an IC memory, or the like, or may be downloaded from the hard disk of the computer to the ROM 5, or wirelessly, wired, or the Internet. It may be downloaded to the ROM 5 via the above.

  The element placement and routing apparatus 100 having the hardware configuration shown in FIG. 2A has a control program in which a processing procedure for causing a computer to execute the functions of the element placement and routing apparatus 100 shown in FIG. The data is stored in a readable storage medium, and the following element placement and wiring processing is automatically performed by a computer (CPU 110a).

  The RAM 4 and the database 6 store various data generated as intermediate data during the element placement and routing process by the CPU 110a each time and can refer to them as necessary. The database 6 may be integrated with the RAM 4 and configured as the same storage means.

  Next, the operation will be described.

  FIG. 2B is a diagram showing an operation flow of the element placement and wiring apparatus 100 of the first embodiment. Here, an optimum repeater insertion process in consideration of the temperature of the semiconductor integrated circuit will be described.

  The element placement and routing apparatus 100 according to the present embodiment creates a basic layout including a schematic wiring of a semiconductor integrated circuit (step S1), and schematically shows information (schematic wiring information) indicating the schematic wiring included in the created basic layout. The information is stored in the information storage unit 131. However, the rough wiring information may be created in advance based on the basic function of the semiconductor integrated circuit and stored in the rough wiring information storage unit 131. Here, this basic layout is obtained by applying a repeater insertion process that does not consider the temperature of the wiring to the wiring connecting the gates. The wiring information storage unit 131 stores wiring material and wiring length information (wiring length data) after the generation of the schematic wiring. This wiring length data is stored as a correspondence table between signal wiring names and their wiring lengths.

  Next, in the element placement and routing apparatus 100, the average temperature calculation unit 13 calculates the average temperature of all signal wirings for the layout after the rough wiring, and stores this in the average temperature storage unit 111.

A method for obtaining the average temperature of the wiring will be described with reference to FIG. In the temperature distribution storage unit 11 of FIG. 12, the current consumption value of the wiring previously obtained by the power consumption simulation is given as a heat source, and the temperature distribution information obtained by performing thermal analysis using commercially available CAD software or the like is obtained. Stored. The average temperature calculation unit 13 extracts the temperature distribution information and the wiring length from the temperature distribution information stored in the temperature distribution storage unit 111 and the wiring length information stored in the schematic wiring information storage unit 131, and The average temperature T _{ave of the} wiring is calculated using the equation (10). The average temperature obtained by the average temperature calculation unit 13 is stored in the average temperature storage unit 111 shown in FIGS.

  Subsequently, in the element placement and routing apparatus 100, the temperature-dependent signal delay time of all signal nets is calculated.

  That is, the temperature-dependent delay calculation unit 112 performs the temperature-dependent delay calculation represented by the above formula (9) using the calculated average temperature of each wiring (step S2), and calculates the obtained delay amount. Store in the temperature dependent delay storage unit 113 (step S3). At this time, the wiring resistance / capacitance per unit length, the temperature dependence coefficient of the wiring, and the values of the cell input capacitance and output resistance necessary for the temperature-dependent delay calculation are stored in the storage units 114 and 115 shown in FIG. , 116.

Specifically, the temperature-dependent delay calculation unit 112 performs delay calculation in consideration of temperature for all nets using the above-described equations (8) and (9). In the equations (8) and (9), the wiring resistances R _int and C _int are calculated from the approximate wiring information storage unit 131 to the wiring capacitance c0 per unit length stored in the storage unit 114 and the wiring resistance ρ0 at the reference temperature. Calculated by multiplying the referenced wiring length L. The temperature coefficient of the wiring resistance is stored in the storage unit 115, the output resistance _R0 of the driver cell and the input capacitance CL of the receiver cell is stored in the storage unit 116, and the average temperature T ( x) refers to each of the storage units 111.

  The delay determined in consideration of the temperatures of all nets is stored in the temperature-dependent delay storage unit 113.

  Next, the element placement and routing apparatus 100 extracts nets that violate delay constraints (violating nets).

  That is, the violation net extraction unit 117 compares the calculated delay amount in each wiring with the delay constraint stored in the delay violation constraint unit 122, extracts the violating net (step S4), Information for identifying the violation net is stored in the violation net storage unit 118 (117 in FIG. 1), and the violation net is stored (step S5).

  Thereafter, the delay improvement determination unit 118a determines whether or not delay improvement is possible by inserting a repeater into the violation net based on information specifying the violation net stored in the violation net storage unit 118. A determination is made (step S6).

  Thereafter, the repeater insertion apparatus 103 performs processing for inserting an optimum repeater into the extracted violation net only when the delay improvement determination unit 118a determines that delay improvement is possible (steps S7 and S8). .

  That is, the repeater optimum value determination unit 119 performs a temperature-dependent delay calculation after the repeater insertion represented by the above-described equation (12) for the violation net stored in the violation net storage unit 118, and the equation (13). The optimal value of the repeater is calculated by solving the equation represented by (14). Specifically, the optimum number of repeater calculator 21 calculates the optimum number of repeaters to be inserted into the violation net, and the optimum size calculator 22 of the repeater calculates the optimum size of repeaters to be inserted into the violation net. (Step S7), the optimum number and the optimum size are stored in the optimum value storage unit 120 of the repeater.

  Thereafter, the repeater insertion unit 121 inserts the determined optimum number of repeaters having the determined optimum size into the violation net (step S8).

  For example, in order to reduce the wiring delay of FIG. 14, consider that k repeaters having a current driving capability of h are equally inserted on the wiring and divided as shown in FIG. Here, the current driving capability h indicates a ratio to the driving capability of the repeater having the minimum size. The optimum number k and size h of repeaters thus obtained are stored in the optimum value storage unit 120 of the repeater. Then, the repeater insertion unit 121 takes out the optimum number and optimum size of repeaters stored in the storage unit 120, and arranges the repeaters evenly on the layout based on these optimum values.

  Through the above steps, it is possible to achieve an optimum delay improvement by inserting a repeater in consideration of the temperature rise of the wiring resistance due to the self-heating of the wiring.

  As described above, according to the most element arrangement wiring device 100 in consideration of the temperature change caused by the self-heating of the wiring according to the present invention, the following effects can be expected.

  In LSI design using automatic placement and routing of standard cells, heat distribution information (that is, information indicating the correspondence between coordinates and temperature) that has been obtained in advance, and units for each wiring material that have been obtained separately By referring to the wiring resistance / capacitance value per length, the coefficient of the wiring resistance change with respect to the temperature change, and the input capacitance and output resistance of the cell, it is possible to calculate the delay considering the temperature rise caused by the wiring self-heating. it can.

  Further, according to the present invention, as a result of delay calculation in consideration of the temperature rise caused by the self-heating of the wiring, the optimum number of repeaters to be inserted and its size are determined in consideration of the temperature with respect to a net having a constraint violation. As a result, the delay reduction effect can be optimized.

  An example showing the improvement of the accuracy of the effect of the present invention is shown below. For layout data designed using automatic placement and routing of standard cells, as a circuit configuration included in the layout data, a driver cell and a receiver cell constituted by inverter elements as shown in FIG. Consider a wiring of length L.

  The solid line in FIG. 9 represents the one-dimensional heat distribution of the wiring portion 10 in FIG. 16 obtained as a result of the thermal analysis simulation. That is, the X axis (horizontal axis) in FIG. 9 is the position in the wiring having the wiring length L, and the Y axis (vertical axis) is the temperature T (° C.).

  As shown in FIG. 9, in this example, the heat distribution T (x) of the wiring is an exponential function (T (x) = a · exp (x)) with respect to the position x in the wiring having the wiring length L. Here, a is a coefficient. Moreover, the broken line of FIG. 9 is the average temperature calculated | required from the temperature distribution shown as a continuous line.

FIG. 11 shows the number of repeaters (k _opt ) and the size of the repeaters (k _opt ) when considering the temperature rise due to self-heating of the wiring shown in the temperature distribution of FIG. 9 on the wiring 10 shown in FIG. h _opt ) and delay reduction rate are shown in comparison with the number of repeaters (k _org ), the size of those repeaters (h _org ), and the delay reduction effect when the temperature according to the conventional method is not taken into consideration.

  In this example, the delay reduction effect by the conventional method is 33.4%, whereas the delay reduction effect by the method of the present invention is 40.1%, and the method of the present invention considering the temperature rise due to the self-heating of the wiring. And the conventional method that does not take into account the temperature rise due to the self-heating of the wiring, there is a difference in the size and the number of inserted repeaters that optimize the delay reduction. According to the method of the present invention, the delay is more effective than the conventional method. Reduction can be realized.

  As described above, in the element placement and routing apparatus 100 according to the first embodiment, the signal delay time deriving means 101 for deriving the signal delay time in each wiring in consideration of the average temperature of each wiring of the semiconductor integrated circuit, and each wiring Repeater optimum value determining means 100a for determining the optimum size and the optimum number of repeater cells to be inserted in the wiring so as to reduce the signal delay time in the wiring based on the signal delay time considering the average temperature at And the basic layout of the semiconductor integrated circuit is changed to a layout in which the determined number of repeaters are inserted into the wiring that requires the insertion of the repeater cell. The delay can be improved at an early stage, and the accurate resistance value of the wiring between the circuit elements can be obtained in consideration of the temperature rise due to the self-heating of the wiring between the circuit elements. Rukoto can, so as to adjust a delay reduction by repeater insertion for wiring effectively.

  In the present embodiment, the semiconductor integrated circuit further includes a delay constraint storage unit 122 that stores signal delay time constraints set for all wirings positioned between the circuit elements. Based on the stored signal delay time constraint, the wire with the signal delay time calculated considering the resistance distribution due to the temperature distribution of the wire is verified and extracted as a constraint violation net. Can be reliably extracted.

  For example, the violation net extraction unit 102 performs the simple verification process of comparing the signal delay time constraint of the wiring stored in the delay constraint storage unit with the signal delay time of the derived wiring, and performs the violation net extraction. Can be extracted.

  Further, in the first embodiment, the delay improvement determining unit 118a that determines whether or not delay improvement is possible by inserting a repeater cell into the constraint violation net is provided. Therefore, according to the determination result, the size of the repeater cell, An operation for determining the number of insertions is performed. For this reason, it is possible to avoid useless processing such as inserting a repeater cell into a wiring in which delay improvement due to insertion of the repeater cell cannot be obtained.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range from the description of specific preferred embodiments of the present invention based on the description of the present invention and common general technical knowledge. It is understood that the documents cited in the present specification should be incorporated by reference into the present specification in the same manner as the content itself is specifically described in the present specification.

  The present invention relates to an element placement and routing apparatus, an element placement and routing method, a method of manufacturing a semiconductor integrated circuit using the element placement and routing apparatus, a control program for causing a computer to execute the element placement and routing method, and the control In the field of storage media in which programs are stored, delay can be improved at an early stage of design using an automatic placement and routing method for semiconductor integrated circuits, and temperature rise due to self-heating of wiring between circuit elements is taken into account. Therefore, it is possible to obtain an accurate resistance value of wiring between circuit elements, which can effectively reduce delay by inserting a repeater, and is useful in a technique for designing an LSI using an automatic placement and routing method. It is.

FIG. 1 is a block diagram showing a configuration example of a main part of an element placement and routing apparatus according to Embodiment 1 of the present invention. FIG. 2 is a diagram for explaining the element arrangement and wiring apparatus of the above embodiment, and shows a hardware configuration example (FIG. (A)) and an operation flow (FIG. (B)). FIG. 3 is a circuit diagram illustrating a state in which a repeater is inserted into the wiring in the semiconductor integrated circuit and the wiring is divided. FIG. 4 is a circuit diagram showing a case where a repeater of the minimum size is used as the repeater shown in FIG. FIG. 5 is a graph for explaining the temperature dependence of resistance in a graph. FIG. 6 is a diagram for explaining an example of thermal analysis and shows a wiring structure in which wiring is formed on a semiconductor substrate via an insulating film. FIG. 7 is a graph showing the heat distribution (temperature distribution) in the wiring structure shown in FIG. FIG. 8 is a diagram showing an average temperature T _ave of the wiring having the heat distribution (temperature distribution) shown in FIG. FIG. 9 is a diagram for explaining the heat distribution (temperature distribution) of the wiring used to explain the effects of the present invention. As the heat distribution of the wiring, the relationship between the position in the wiring length direction and the temperature is an exponential function. Shows what it is. FIG. 10 is a diagram for explaining an example of wiring into which a repeater cell is inserted, and shows two front-stage and rear-stage functional blocks constituting the semiconductor integrated circuit and wiring between these functional blocks. FIG. 11 is a diagram for explaining the effect of the present invention, and shows the improvement of the delay reduction rate in comparison with the method according to the present invention and the conventional method. FIG. 12 is a block diagram illustrating a specific configuration of the average temperature calculation means 104 in the element placement and routing apparatus according to the first embodiment of the present invention. FIG. 13 is a block diagram illustrating a specific configuration of the optimum value determination unit 119 of the repeater in the element placement and routing apparatus according to the first embodiment of the present invention. FIG. 14 is a circuit diagram for explaining the basic principle of the present invention, and shows a wiring delay model of the circuit. FIG. 15 is a diagram for explaining the output resistance and input capacitance of the repeater cell used in the element placement and routing apparatus of Embodiment 1 of the present invention. FIG. 16 is a diagram for explaining the effect of the present invention. In addition to the output resistance and input capacitance of the two front-stage and rear-stage functional cells used in the element placement and routing apparatus of the first embodiment, FIG. It shows the resistance and capacitance of the connected wiring.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Temperature distribution storage part 13 Average temperature calculation part 21 Optimal number calculation part of repeater 22 Optimum size calculation part of repeater 100 Element arrangement | positioning wiring apparatus 100a Repeater optimal value determination means 100b Delay parameter storage part 101 Temperature dependent delay calculation means 102 Delay constraint violation Net extraction unit 102a Delay improvement determination unit 103 Repeater optimum value determination unit 104 Average temperature calculation unit 111 Average temperature storage unit 111a Average temperature calculation unit 112 Temperature dependent delay calculation unit 113 Temperature dependent delay storage unit 114 Wiring resistance / capacitance per unit length Storage unit 115 Temperature coefficient storage unit of resistance for each material of wiring 116 Cell input capacity and output resistance storage unit 117 Delay constraint violation net extraction unit 118 Delay constraint violation net storage unit 118a Delay improvement determination unit 119 Repeater optimum value determination device 120 Li Optimum value storage unit 121 repeater insertion unit 122 delay constraint storage section 131 general routing information storage unit 132 the thermal distribution information storage unit over data

Claims (30)

An element placement and routing apparatus for creating a layout of a plurality of circuit elements constituting a semiconductor integrated circuit and a layout of wirings located between the circuit elements,
An average temperature of each wiring is obtained from circuit information indicating a basic layout of the semiconductor integrated circuit and heat distribution information indicating heat distribution in the semiconductor integrated circuit, and each wiring by a temperature-dependent resistance considering the average temperature of each wiring. Signal delay time deriving means for deriving the signal delay time of
Repeater optimum value determining means for determining the size and number of repeater cells inserted into the wiring so as to reduce the signal delay time in the wiring based on the signal delay time considering the average temperature of each wiring;
The basic layout of the semiconductor integrated circuit created based on the circuit information is changed to a layout in which the determined number of repeater cells are inserted into the wiring that requires the insertion of the repeater cells. An element placement and routing device comprising: repeater placement means for performing In the element arrangement wiring device according to claim 1,
A heat distribution information storage unit for storing heat distribution information obtained by self-heating of each wiring obtained by heat distribution analysis of the semiconductor integrated circuit;
An average temperature calculation unit for calculating an average temperature of each wiring from the heat distribution information stored in the heat distribution information storage unit;
An element placement and routing apparatus having an average temperature storage unit for storing the calculated average temperature of each wiring. In the element arrangement wiring device according to claim 1,
A schematic wiring information storage unit that stores information about a schematic wiring that is a wiring in a basic layout of the semiconductor integrated circuit;
The schematic wiring information storage unit stores a wiring length of the schematic wiring as a correspondence table in which a signal net name for specifying the schematic wiring and a wiring length of the schematic wiring are associated with each other. In the element arrangement wiring device according to claim 1,
A delay parameter storage unit that stores a delay parameter that affects a signal delay in wiring between the circuit elements;
The signal delay time deriving means includes:
An element placement and routing apparatus that derives a signal delay time in the wiring according to a temperature-dependent resistance in the wiring based on a delay parameter stored in the delay parameter storage unit. In the element arrangement wiring device according to claim 4,
The delay parameter storage unit is an element placement and routing apparatus including a resistance storage unit that stores, as the delay parameter, a resistance per unit length unique to a wiring material constituting the wiring. In the element arrangement wiring device according to claim 4,
The element placement and routing apparatus, wherein the delay parameter storage unit includes a capacitance storage unit that stores, as the delay parameter, a capacity per unit length unique to a wiring material constituting the wiring. In the element arrangement wiring device according to claim 4,
The element placement and routing apparatus, wherein the delay parameter storage unit includes a temperature coefficient storage unit that stores, as the delay parameter, a temperature coefficient of resistance specific to a wiring material constituting the wiring. In the element arrangement wiring device according to claim 4,
The element placement and routing apparatus, wherein the delay parameter storage unit includes an element input capacitance storage unit that stores input capacitances of all circuit elements constituting the semiconductor integrated circuit as the delay parameter. In the element arrangement wiring device according to claim 4,
The element placement and routing apparatus, wherein the delay parameter storage unit includes an element output resistance storage unit that stores output resistances of all circuit elements constituting the semiconductor integrated circuit as the delay parameter. In the element arrangement wiring device according to claim 2,
An element placement and routing apparatus including a delay constraint storage unit that stores signal delay time constraints set for all wirings positioned between the circuit elements in the semiconductor integrated circuit. In the element arrangement wiring device according to claim 10,
The signal delay time deriving means includes:
Based on the average temperature of each wiring stored in the average temperature storage unit, a delay calculation considering the temperature dependence of each wiring is performed to calculate a signal delay time in each wiring. And
A device placement and routing apparatus comprising: a temperature-dependent delay storage unit that stores a signal delay time in each wiring calculated by the temperature-dependent delay calculation unit. In the element arrangement wiring device according to claim 11,
The repeater optimum value determining means includes:
A repeater optimum value determining unit for determining the optimum size and the optimum number of repeater cells to be inserted into the wiring in consideration of the temperature dependence of the wiring with reference to the average temperature of each wiring;
An element placement and routing apparatus having a repeater optimum value storage unit for storing an optimum size and optimum number obtained by the repeater optimum value determining means. In the element arrangement wiring device according to claim 12,
The repeater placing means inserts the optimum number of repeater cells having the optimum size into the wire based on the optimum size and number of repeater cells stored in the optimum repeater value storage unit. apparatus. A method of manufacturing a semiconductor integrated circuit using a mask pattern obtained based on circuit information,
A method for manufacturing a semiconductor integrated circuit, wherein the circuit information indicates a layout of circuit elements and wiring of the semiconductor integrated circuit created by the element placement and wiring apparatus according to claim 1. An element arrangement and wiring method for creating a layout of a plurality of circuit elements constituting a semiconductor integrated circuit and a layout of wiring for connecting the preceding stage circuit element and a subsequent stage circuit element,
Including a repeater cell insertion step of inserting a repeater cell so that a signal delay time in the wiring is reduced;
The repeater cell insertion step includes:
Deriving the signal delay time of each of the plurality of wirings in the semiconductor integrated circuit in consideration of the temperature rise of the wiring due to Joule heat generated by current flowing through the wirings;
Extracting a constraint violation net that is a wiring causing a violation of the delay time constraint based on the signal delay time of each wiring;
Determining an optimal layout of repeater cells to be inserted for the constraint violation net;
Inserting the repeater cell into the constraint violation net based on the determined optimum layout of the repeater cell. In the element placement and wiring method according to claim 15,
Deriving the signal delay time includes:
An average temperature calculating step for obtaining an average temperature of the wiring from heat distribution information by self-heating of the wiring, which is obtained by heat distribution analysis of the semiconductor integrated circuit;
Storing the determined average temperature in an average temperature storage unit,
An element placement and wiring method for deriving a signal delay time corresponding to a temperature-dependent resistance in each wiring based on an average temperature of each wiring stored in the average temperature storage unit. In the element placement and wiring method according to claim 15,
The wiring connecting the preceding stage circuit element and the subsequent stage circuit element is included as a plurality of schematic wirings in the basic layout of the semiconductor integrated circuit,
The element arrangement and wiring method in which the wiring length of each schematic wiring is stored in the schematic wiring information storage unit as a correspondence table in which a signal net name for specifying each schematic wiring and a wiring length of each schematic wiring are associated with each other. In the element placement and wiring method according to claim 15,
The element placement and wiring method in which the resistance per unit length inherent to the wiring material constituting the wiring is stored in the resistance storage section. In the element placement and wiring method according to claim 15,
The element placement and wiring method in which the capacity per unit length inherent to the wiring material constituting the wiring is stored in a capacity storage unit. In the element placement and wiring method according to claim 15,
An element placement and routing method in which input capacitances of all circuit elements constituting the semiconductor integrated circuit are stored in an element input capacitance storage unit. In the element placement and wiring method according to claim 15,
An element placement and routing method in which output resistances of all circuit elements constituting the semiconductor integrated circuit are stored in an element output resistance storage unit. In the element placement and wiring method according to claim 15,
In the semiconductor integrated circuit, an element placement and routing method in which signal delay time constraints set for all wirings located between the circuit elements are stored in a delay constraint storage unit. The element placement and wiring method according to claim 16,
Deriving the signal delay time includes:
Based on the average temperature of each wiring stored in the average temperature storage unit, performing a delay calculation considering the temperature dependency of each wiring, calculating a signal delay time in each wiring;
And storing the calculated signal delay time in each wiring in a temperature-dependent delay storage unit. In the element placement and wiring method according to claim 15,
In the step of determining the optimum size and the optimum number of the repeater cells,
The optimum size and number of repeater cells to be inserted into the constraint violation net are determined by referring to the average temperature of the constraint violation net and considering the temperature dependence of the constraint violation net.
The element placement and routing method in which the optimum size and optimum number of the determined repeater cells are stored in the optimum repeater value storage unit. In the element arrangement wiring method according to claim 24,
In the repeater placement step, an element placement and routing method wherein an optimum number of repeaters are inserted into the constraint violation net. In the element placement and wiring method according to claim 15,
As a layout of a plurality of circuit elements constituting the semiconductor integrated circuit and a layout of a wiring between circuit elements at the preceding stage and the succeeding stage, the temperature dependence of the resistance of the wiring so that the wiring satisfies the constraint of delay time by an automatic layout process Including an automatic layout step of creating a basic layout in which repeater cells are inserted without taking into account the steps as a step before the repeater cell insertion step,
The repeater cell insertion step includes:
A delay verification step for verifying a delay time in consideration of a temperature distribution due to self-heating of the wiring in the basic layout,
An element placement and routing method for inserting a repeater cell into a constraint violation net in the basic layout in accordance with a result of the delay verification. In the element placement and wiring method according to claim 26,
The repeater cell insertion step includes:
Obtaining an average temperature of the wiring from a temperature distribution due to self-heating of the wiring in the basic layout,
In the delay verification step, an element placement and wiring method for verifying a delay time of the wiring based on an average temperature of the wiring. In the element placement and wiring method according to claim 27,
The repeater cell insertion step includes:
A delay improvement determining step of determining whether or not delay improvement is possible when a repeater cell is inserted for the constraint violation net;
An element placement and routing method which is a step of inserting a repeater cell into the constraint violation net only when the delay can be improved.   A control program in which a processing procedure for causing a computer to execute each step of the element placement and routing method according to any one of claims 15 to 28 is described.   A computer-readable storage medium storing the control program according to claim 29.

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