JP2010245474A - Manufacturing method of semiconductor device - Google Patents

Abstract

A semiconductor device is provided that can be reduced in size as compared with a case where connection wiring between an aluminum electrode pad of a semiconductor chip and an electrode pad of a substrate is formed by an inkjet method.
Semiconductor chips 12, 13 having a conductive layer formed outside the first electrode pads of active surfaces 12a, 13a, 14b on which first electrode pads 12b, 13b, 14b are formed are mounted on a mounting surface 11a. In this method, the semiconductor device 10, 24, 26 is mounted with the surface opposite to the active surface facing the mounting surface with respect to the substrate 11 on which the two-electrode pad 16 is formed. A slope forming step S2 for forming slopes 19, 20, 2, and 23 made of an insulating material for relaxing a step between the mounting surface and the active surface so as to cover the conductive layer, and a catalyst layer by discharging catalyst ink onto the slope Catalyst layer forming steps S3 and S4 for forming the electrode layer, and electroless plating step S8 for forming the connection wirings 17a, 17b, 25a and 25b by forming a plating film on the first electrode pad, the second electrode pad and the catalyst layer, S9.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which a semiconductor chip is mounted on a substrate with a surface opposite to an active surface facing the substrate.

  In so-called face-up mounting in which a semiconductor chip is mounted on a substrate with the surface opposite to the active surface facing the mounting surface of the substrate, the aluminum electrode pad of the semiconductor chip and the wiring pattern (electrode pad) of the substrate are gold wires. A wire bonding method in which wires such as aluminum wires are connected is adopted.

  In the wire bonding method, a connection mode in which a wire is directly bonded to an aluminum electrode pad of a semiconductor chip is used. An oxide film is formed on the surface of the aluminum electrode pad by contact with the atmosphere. However, with the wire bonding method described above, the oxide film is removed by deformation of the wire during bonding or ultrasonic vibration applied during bonding. Therefore, the aluminum electrode pad and the wire are metal-bonded.

  However, in the wire bonding method, due to the variation between the wires at the time of bonding, the wire loop collapses at the time of filling and embedding with the mold resin, causing a short circuit between the wires, resulting in a decrease in yield. In recent years, demands for miniaturization and thinning have increased, and higher density has been demanded. For this reason, these problems are more closely highlighted. Furthermore, the occupied space of the wire has been a great hindrance to the reduction in the size of the mounting substrate and the downsizing of the semiconductor device.

  Therefore, in order to solve such problems, a so-called inkjet method (droplet) in which conductive ink in which conductive fine particles are dispersed in a solvent is discharged as fine droplets, dried and fired to form connection wiring. (Discharge method) has been proposed (see, for example, Patent Document 1). As shown in FIG. 7, the semiconductor device in which the connection wiring is formed by the inkjet method includes an aluminum electrode pad 43 of the semiconductor chip 42 and a wiring pattern 44 of the substrate 41 bonded to the substrate 41 via an adhesive (not shown). In the meantime, an insulating slope (slope) 45 connected from the surface of the substrate 41 to the active surface 42a of the semiconductor chip 42 is formed of resin. A connection wiring 46 formed using conductive ink along the surface of the slope 45 is provided so as to connect the aluminum electrode pad 43 and the wiring pattern 44. In the inkjet method, the wiring is formed in accordance with the landing position of the conductive ink droplets. Therefore, in addition to giving a high degree of freedom to the shape and position of the connection wiring, the space for providing the connection wiring is Compared to the wire occupying space of the wire bonding method, it is greatly reduced.

JP 2006-147650 A

  By the way, when the wiring formed by the ink jet method is connected to the aluminum electrode pad of the semiconductor chip, the oxide film removing action such as wire deformation and ultrasonic vibration in the wire bonding method is not exhibited on the aluminum electrode pad. Therefore, when forming the connection wiring using the ink jet method, before forming the oxidation resistant metal film such as oxide film removal and under bump metal (UBM) on the surface of the aluminum electrode pad by the plating method. It is necessary to provide a process.

  However, in general, around the semiconductor chip, a guide ring that defines the area of each semiconductor chip on the wafer, and an evaluation terminal used for investigating the causes of problems that occur at each stage of semiconductor chip design, manufacturing, etc. (TEG: Test Element Group) is provided. Since the guide ring and the TEG have conductivity, when an oxidation-resistant metal film is formed on the surface of the aluminum electrode pad by a plating method, as shown in FIG. An oxidation resistant metal film 48 is deposited as a plating film on the ring 47 and TEG (not shown).

In general, the active surface 42a of the semiconductor chip 42 is usually made of a highly heat-resistant material such as polyimide if it is an organic insulating film as a passivation film, or if the passivation film is an inorganic material, SiO ₂ or An inorganic insulating film 49 such as SiN is formed. As shown in FIG. 7, the oxidation-resistant metal film 48 is deposited to the same height as or higher than the surface of the inorganic insulating film 49, and there are variations within the substrate. Therefore, the resin forming the slope 45 corresponds to the guide ring 47 and TEG in order to ensure insulation between the oxidation resistant metal film 48 formed on the guide ring 47 or TEG and the connection wiring 46. The thickness of the portion to be formed must be thicker than that in the case where the oxidation-resistant metal coating 48 is not provided.

  In addition, in the inkjet method, when the thick connection wiring 46 is formed, it is necessary to repeatedly discharge, dry, and fire the conductive ink many times, which increases the number of steps and uses a lot of expensive conductive ink. There is also a problem that the manufacturing cost becomes high.

  The present invention has been made in view of the above problems, and an object thereof is an ink jet method using conductive ink for connection wiring between an aluminum electrode pad of a semiconductor chip and an electrode pad (wiring pattern) of a substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor device which is smaller and thinner than a case where the semiconductor device is formed, which is low in cost and high in reliability.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a semiconductor chip in which a conductive layer is formed outside the first electrode pad on the active surface on which the first electrode pad is formed. A method of manufacturing a semiconductor device, wherein a surface opposite to the active surface is mounted on the mounting surface with respect to the substrate on which the second electrode pad is formed, wherein a step between the mounting surface and the active surface A slope forming step of forming a slope made of an insulating material that relaxes the conductive layer so as to cover the conductive layer between the first electrode pad and the second electrode pad; and the first electrode pad and the second electrode pad A catalyst layer forming step of forming a catalyst layer by discharging catalyst ink on the slope to form a connection wiring for electrically connecting the first electrode pad, the second electrode pad, and the catalyst layer A plating film is formed on And a non-electrolytic plating step of forming the connection wirings.

  Here, “the conductive layer formed outside the first electrode pad” is a problem that occurs at each stage of the design, manufacture, etc. of the guide ring that defines the area of each semiconductor chip on the wafer and the semiconductor chip. It means a conductive layer that constitutes an evaluation terminal (TEG: Test Element Group) used for factor investigation. In addition, “step difference between the mounting surface and the active surface of the semiconductor chip” literally means the difference between the mounting surface and the active surface when the active surface is not covered with the passivation film, but the active surface is the passivation film. Means a difference between the mounting surface and the surface of the passivation film.

  According to this configuration, unlike the case where the connection wiring for connecting the first electrode pad and the second electrode pad is formed by the ink jet method, the semiconductor chip is formed when the oxidation-resistant metal film is formed on the first electrode pad. An oxidation-resistant metal film is not formed on a conductive layer such as a guide ring formed outside the first electrode pad. Therefore, the connection wiring connecting the first electrode pad and the second electrode pad, and the thickness of the slope portion formed so as to cover the conductive layer in order to ensure the insulation between the conductive layer, the connection wiring is inkjet Therefore, the thickness of the semiconductor device can be reduced as compared with the case where the semiconductor device is formed by a method, and the semiconductor device can be downsized.

  In the method for producing a semiconductor device of the present invention, the catalyst ink is obtained by dispersing a coupling agent carrying a plating catalyst in a solvent. According to this configuration, since the catalyst layer is formed on the slope via the coupling agent having high adhesion to the slope, the adhesion between the connection wiring and the slope can be improved without complicating the manufacturing process. .

  In the method for manufacturing a semiconductor device of the present invention, the plating catalyst is palladium, and the coupling agent is a silane coupling agent. According to this structure, a commercial item can be used for a plating catalyst and a coupling agent, and acquisition becomes easy. Palladium is preferable as a plating catalyst because many kinds of metals suitable for the material of the connection wiring can be deposited by electroless plating.

  In the method of manufacturing a semiconductor device of the present invention, the first electrode pad and the second electrode pad are aluminum electrode pads, and the electroless plating process includes an oxide film removing process and a zincate processing process. When the first electrode pad and the second electrode pad are made of aluminum or aluminum alloy, the oxide film existing on the surface of the aluminum electrode pad is removed, and the surface of the aluminum electrode pad is electrolessly plated. It is necessary to make the metal easy to precipitate. According to this configuration, the electroless plating for forming the connection wiring can be performed in a state where the surface of the aluminum electrode pad is easily deposited by the zincate process. Therefore, after forming the oxidation-resistant metal film by electroless plating after the zincate treatment, the time required from the removal of the oxide film to the completion of the formation of the connection wiring can be shortened compared to the case where the connection wiring is formed by the inkjet method. it can.

  In the semiconductor device manufacturing method of the present invention, a plurality of the semiconductor chips are stacked, and the connection wiring for connecting the first electrode pads and the second electrode pads on each semiconductor chip is formed on the substrate. It is formed so as not to overlap in the thickness direction. According to this configuration, it is possible to simultaneously form the plating film of the connection wiring that connects each first electrode pad on each semiconductor chip and the second electrode pad of the substrate, and the connection wiring for each semiconductor chip has a thickness. Compared to the structure overlapping in the direction, the time required for manufacturing can be shortened. In addition, the distance (height) to the mounting surface of the portion corresponding to the slope of the connection wiring for the semiconductor chip stacked on the top is lower than the structure in which the connection wiring for each semiconductor chip overlaps in the thickness direction. can do.

  In the method for manufacturing a semiconductor device according to the present invention, a gold plating layer is formed on a surface of the connection wiring. According to this configuration, the conductivity and oxidation resistance of the connection wiring can be improved as compared with the case where no gold plating layer is present on the surface. Further, the cost can be reduced without using a large amount of expensive Au.

(A) is a partial schematic perspective view of the semiconductor device of 1st Embodiment, (b) is the fragmentary sectional view cut | disconnected in the location of the connection wiring for semiconductor chips of the 1st layer, (c) is the elements on larger scale. . 6 is a flowchart showing a manufacturing process of a semiconductor device. The partial perspective view of the state where the semiconductor chip was joined to the substrate. (A) is a partial perspective view of the state in which the slope was formed, (b) is a partial perspective view of the state in which the catalyst pattern was formed. (A) is a perspective view in the state where a semiconductor chip was laminated in the manufacturing process of the semiconductor device of a 2nd embodiment, and (b) is a fragmentary sectional view of a semiconductor device. The partial model perspective view of the semiconductor device of another embodiment. The fragmentary sectional view of the semiconductor device of a prior art.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. In the following drawings, the film thicknesses and dimensional ratios of the components are appropriately changed in order to make the drawings easy to see.

  As shown in FIGS. 1A, 1 </ b> B, and 1 </ b> C, the semiconductor device 10 includes a substrate 11, a semiconductor chip 12 stacked on the mounting surface 11 a of the substrate 11, and an active surface 12 a of the semiconductor chip 12. And a semiconductor chip 13 stacked thereon. The semiconductor chip 12 is bonded to the mounting surface 11a with an adhesive (not shown) with the surface opposite to the active surface 12a facing the mounting surface 11a of the substrate 11. The semiconductor chip 13 is bonded to the active surface 12a with an adhesive (not shown) with the surface opposite to the active surface 13a facing the active surface 12a of the semiconductor chip 12. That is, the semiconductor chips 12 and 13 are mounted on the substrate 11 by so-called face-up mounting in which the surface opposite to the active surfaces 12a and 13a is mounted on the mounting surface 11a of the substrate 11.

  First electrode pads 12b and 13b are formed on the active surfaces 12a and 13a of the semiconductor chips 12 and 13, and a guide ring 15 made of a conductive layer is formed outside the first electrode pads 12b and 13b. The first electrode pads 12b and 13b are electrically connected to the second electrode pad 16 formed on the mounting surface 11a of the substrate 11 via connection wirings 17a and 17b, respectively. The first electrode pads 12b and 13b and the second electrode pad 16 are aluminum electrode pads made of aluminum or aluminum alloy.

  The second electrode pads 16 are formed at an equal pitch along one side of the substrate 11 on the mounting surface 11a. On the other hand, the first electrode pads 12b and 13b are arranged in a staggered manner so that the first electrode pads 12b and 13b are twice the pitch of the second electrode pad 16 and face each other with respect to the second electrode pad 16. It is formed as follows. That is, the connection wiring 17a that connects the first electrode pad 12b and the second electrode pad 16 and the connection wiring 17b that connects the first electrode pad 13b and the second electrode pad 16 are formed so as not to overlap each other. Yes. In the semiconductor device 10, first electrode pads 12b and 13b and connection wirings 17a and 17b are similarly formed on the side not shown.

  As shown in FIGS. 1B and 1C, the active surfaces 12a and 13a are covered with a passivation film 18 except for portions where the first electrode pads 12b and 13b and the guide ring 15 are formed. In FIG. 1A, illustration of the passivation film 18 is omitted. That is, the surface of the passivation film 18 becomes the surface of the semiconductor chips 12 and 13 on the active surfaces 12a and 13a side.

  Between the second electrode pad 16 on the mounting surface 11a and the end surface of the first semiconductor chip 12, a slope 19 made of an insulating material that relaxes the step between the mounting surface 11a and the surface of the passivation film 18 is formed. . The slope 19 is formed so as to extend along the end face of the semiconductor chip 12, one end (lower end) is close to the second electrode pad 16, and the other end is on the passivation film 18 of the semiconductor chip 12. The guide ring 15 is formed so as to extend to a position corresponding to the end of the guide ring 15.

  Between the first electrode pad 12b of the first semiconductor chip 12 and the end face of the second semiconductor chip 13, a step between the passivation film 18 of the semiconductor chip 12 and the surface of the passivation film 18 of the semiconductor chip 13 is formed. A slope 20 made of an insulating material to be relaxed is formed. The slope 20 is formed so as to extend along the end face of the semiconductor chip 13, one end (lower end) is close to the first electrode pad 12 b, and the other end is on the passivation film 18 of the semiconductor chip 13. The guide ring 15 is formed so as to extend to a position corresponding to the end of the guide ring 15. Therefore, the step between the mounting surface 11 a and the surface of the passivation film 18 that is the active surface 13 a of the second-layer semiconductor chip 13 is relaxed by the two slopes 19 and 20.

  The slopes 19 and 20 are made of, for example, an epoxy thermosetting resin. As shown in FIG. 1C, the catalyst pattern 21 as the catalyst layer is formed so as to pass over the slopes 19 and 20, and the connection wirings 17a and 17b are formed on the catalyst pattern 21. . The slopes 19 and 20 are formed continuously in a portion where the catalyst pattern 21 for the connection wiring 17b is formed. In addition, you may abbreviate | omit this continuous part.

Next, a method for manufacturing the semiconductor device 10 described above will be described.
As shown in FIG. 2, the manufacturing method of the semiconductor device 10 includes a semiconductor chip bonding step S1, a slope forming step S2, a catalyst pattern forming step S3, a firing step S4, an acidic degreasing step S5, and a nitric acid cleaning step S6. And a zincate treatment step S7, an electroless Ni plating step S8, and an electroless Au plating step S9. By the catalyst pattern forming step S3 and the firing step S4, catalyst ink is applied to the wiring forming region connecting the first electrode pad 12b and the second electrode pad 16 and the wiring forming region connecting the first electrode pad 13b and the second electrode pad 16. A catalyst layer forming step of forming a catalyst layer by discharging is configured. Further, the first electrode pads 12b and 13b and the second electrode pad 16 are electrically connected by the acid degreasing step S5, the nitric acid cleaning step S6, the zincate treatment step S7, the electroless Ni plating step S8, and the electroless Au plating step S9. An electroless plating process for forming connection wirings 17a and 17b to be connected is configured.

  In the semiconductor chip bonding step S1, first, the semiconductor chip 12 is bonded onto the mounting surface 11a of the substrate 11 via a resin adhesive with the surface opposite to the active surface 12a facing the mounting surface 11a. The Next, the semiconductor chip 13 is bonded onto the passivation film 18 of the semiconductor chip 12 through a resin adhesive with the surface opposite to the active surface 13a facing the active surface 12a of the semiconductor chip 12. . As a result, as shown in FIG. 3, two semiconductor chips 12 and 13 are stacked on the substrate 11 in a face-up state.

  In the slope forming step S <b> 2, an insulating slope 19 that relaxes the step between the mounting surface 11 a of the substrate 11 and the surface of the passivation film 18 of the semiconductor chip 12, the surface of the passivation film 18 of the semiconductor chip 12, and the passivation film of the semiconductor chip 13. The slope 20 made of an insulating material that relaxes the step difference from the surface 18 is formed. The slopes 19 and 20 are formed so as to cover the guide ring 15. The slopes 19 and 20 are formed by an ink jet method (droplet discharge method) in which a liquid containing an insulating material is discharged as a droplet from a liquid discharge head of a liquid ejecting apparatus. In this embodiment, as the liquid ejecting apparatus, an inkjet printer including an ejection head (inkjet head) having a structure in which a plurality of liquids (inks) are separately supplied to a plurality of nozzle groups of one head is used. The liquid ejecting apparatus discharges the liquid for slope formation and the catalyst ink in the catalyst pattern forming step S3.

  First, in order to form a slope 19 that relaxes a step between the mounting surface 11a of the substrate 11 and the surface of the passivation film 18 of the semiconductor chip 12, the liquid material adheres to the entire end surface of the semiconductor chip 12 on the first electrode pad 12b side. Then, ejection is performed so as to reach a position corresponding to the first electrode pad 12b on the surface of the passivation film 18. Further, in order to form a slope 20 that relaxes the step between the surface of the passivation film 18 of the semiconductor chip 12 and the surface of the passivation film 18 of the semiconductor chip 13, the liquid material is formed on the entire end surface of the semiconductor chip 13 on the first electrode pad 13 b side. At the same time, it is discharged so as to reach a position corresponding to the first electrode pad 13b on the surface of the passivation film 18. Next, heat treatment is performed to cure the thermosetting resin while drying the liquid, thereby completing the formation of the slopes 19 and 20 and the state shown in FIG.

  In the catalyst pattern forming step S3, catalyst ink (catalyst liquid) is ejected onto the slopes 19 and 20 by the ink jet method, and the catalyst pattern 21 is drawn in a shape that matches the shape of the connection wirings 17a and 17b. The state shown in FIG. As the catalyst ink, an ink in which a coupling agent carrying a plating catalyst is dispersed in a solvent is used. Specifically, a silane coupling agent having an amino group that is a functional group capable of supporting palladium as a plating catalyst, for example, alkyltrialkoxysilanes (so-called amino-based silane coupling agents) is used. And the OH group which exists on the surface of slopes 19 and 20 and the silanol group (Si-OH) which the alkoxy group of the silane coupling agent hydrolyzed will be in the state couple | bonded by the hydrogen bond. The catalyst pattern 21 is very thin and is formed of, for example, a monomolecular film.

  In the firing step S4, the dehydration condensation reaction between the OH groups present on the surfaces of the slopes 19 and 20 and the silanol groups (Si—OH) of the silane coupling agent proceeds, and the silane coupling agent and the slopes 19 and 20 are hydrogen. It will be in the state couple | bonded by the covalent bond stronger than coupling | bonding. In addition, the dehydration condensation reaction proceeds between silanol groups (Si—OH) of adjacent silane coupling agents, and adjacent silane coupling agents are also bonded by a strong covalent bond. As a result, the catalyst pattern 21 can maintain sufficient adhesion to the slopes 19 and 20.

  In order to smoothly perform the dehydration condensation reaction in which the coupling agent is fixed to the slopes 19 and 20, the firing temperature is 100 ° C or higher, preferably 120 ° C. If the boiling point of the organic solvent in which the coupling agent is dispersed is equal to or lower than this temperature, the firing temperature is 100 ° C. or higher, preferably 120 ° C. However, the organic solvent in which the dispersion state of the coupling agent carrying the catalyst in the catalyst ink and the wet spread state when the catalyst ink is ejected from the ink jet head and landed on the mounting surface 11a of the substrate 11 are in an appropriate state. Since the boiling point of is 150 ° C. or higher, the firing temperature is preferably 150 to 250 ° C. which is higher than the boiling point of the organic solvent in which the coupling agent is dispersed.

  In the acidic degreasing step S5, organic substances adhering to the surfaces of the first electrode pads 12b and 13b and the second electrode pad 16 are removed. The acidic degreasing treatment is performed by immersing the semiconductor device 10 after the baking step S4 in an acidic degreasing solution and washing with water. As the acidic degreasing solution, a known one used as a pretreatment for electroless plating, for example, a commercially available acidic degreasing solution can be used.

  In the nitric acid cleaning step S6, the semiconductor device 10 that has undergone the acidic degreasing step S5 is immersed in nitric acid, and the oxidation present on the surfaces of the first electrode pads 12b and 13b and the second electrode pad 16 formed of aluminum electrode pads. The coating is removed by the etching action of nitric acid. After immersion in nitric acid, washing with water is performed.

  In the zincate treatment step S7, in order to deposit a wiring material (for example, Ni) on aluminum, zinc (Zn :) is formed on the surfaces of the first electrode pads 12b and 13b and the second electrode pad 16 formed of aluminum electrode pads. Zincate treatment, which is a treatment for precipitating zinc), is performed. In the zincate process, a known zincate process is performed on the semiconductor device 10 after the nitric acid cleaning step S6.

  In the electroless Ni plating step S8, Ni is deposited on the first electrode pads 12b and 13b, the second electrode pad 16 and the catalyst pattern 21 by immersing the semiconductor device 10 after the zincate treatment in an electroless Ni plating bath. Thus, the Ni layer is formed.

  In the electroless Au plating step S9, the semiconductor device 10 after the electroless Ni plating step S8 is immersed in an electroless Au plating bath, whereby the first electrode pads 12b and 13b, the second electrode pad 16 and the catalyst pattern 21 are formed. Au is deposited on the Ni layer formed in (1) to form an Au layer. As a result, as the connection wirings 17a and 17b that electrically connect the first electrode pads 12b and 13b and the second electrode pad 16, a plating layer having a stacked structure of an Ni layer and an Au layer is formed. And it will be in the state shown in FIG.1 (c) in which the connection wiring 17a, 17b was formed on each slope 19,20. The connection wirings 17a and 17b are drawn without distinguishing between the Ni layer and the Au layer.

Thus, the manufacture of the semiconductor device 10 in which the two semiconductor chips 12 and 13 are stacked on the substrate 11 is completed.
According to the manufacturing method of the semiconductor device 10 of the above embodiment, the following effects can be obtained.

  (1) The manufacturing method of the semiconductor device 10 includes the slopes 19 and 20 made of an insulating material for relaxing the step between the mounting surface 11a of the substrate 11 and the active surfaces 12a and 13a of the semiconductor chips 12 and 13, and the first electrode pads 12b. , 13 b and the second electrode pad 16, a slope forming step S <b> 2 is formed so as to cover the conductive guide ring 15. Then, a catalyst pattern forming step S3 for forming a catalyst pattern 21 by discharging catalyst ink to a wiring forming region connecting the first electrode pads 12b, 13b and the second electrode pad 16 on the slopes 19, 20; An electroless plating process for forming connection wirings 17a and 17b for electrically connecting the pad 12b and the second electrode pad 16 to each other. Therefore, unlike the case where the connection wirings 17a and 17b for connecting the first electrode pads 12b and 13b and the second electrode pad 16 are formed by the ink jet method, the conductive oxidation-resistant metal film is formed on the conductive guide ring 15. Is not formed. As a result, the thickness of the slopes 19 and 20 formed so as to cover the guide ring 15 in order to ensure the insulation between the connection wirings 17a and 17b and the guide ring 15, and the connection wirings 17a and 17b are made by the ink jet method. Therefore, the semiconductor device 10 can be reduced in size as compared with the case where the semiconductor device 10 is formed.

  Further, since the connection wirings 17a and 17b are formed by electroless plating, the connection wirings 17a and 17b having a desired thickness can be formed by adjusting the plating time. Even when the thick connection wirings 17a and 17b are required, they can be easily formed only by lengthening the plating time. Further, compared to the case where the connection wirings 17a and 17b are formed by the inkjet method, the degree of freedom (selectable types) of selection of the metal material constituting the connection wirings 17a and 17b is increased, and the connection wirings 17a and 17b themselves are thin films. Multi-layering is also easy.

  (2) The catalyst ink is obtained by dispersing a coupling agent carrying a plating catalyst in a solvent. Therefore, since the catalyst pattern 21 (catalyst layer) is formed on the slopes 19 and 20 via the coupling agent having high adhesion to the slopes 19 and 20, the connection wirings 17a and 17b can be formed without complicating the manufacturing process. Adhesion with the slopes 19 and 20 can be enhanced.

  (3) The plating catalyst is palladium, and the coupling agent is a silane coupling agent. Therefore, a commercial item can be used for a plating catalyst and a coupling agent, and acquisition becomes easy. Palladium is preferable as a plating catalyst because many kinds of metals suitable for the material of the connection wirings 17a and 17b can be deposited by electroless plating.

  (4) The first electrode pads 12b and 13b and the second electrode pad 16 are aluminum electrode pads, and the electroless plating step includes a nitric acid cleaning step S6 (oxide film removal step) and a zincate treatment step S7. Therefore, the electroless plating for forming the connection wirings 17a and 17b can be performed in a state where the surface of the aluminum electrode pad is easily deposited by the zincate treatment. Therefore, after forming the oxidation resistant metal film by electroless plating after the zincate treatment, it is required from the removal of the oxide film to the completion of the formation of the connection wirings 17a and 17b as compared with the case where the connection wirings 17a and 17b are formed by the ink jet method. Time can be shortened.

  (5) A gold plating layer is formed on the surfaces of the connection wirings 17a and 17b. Therefore, the conductivity and oxidation resistance of the connection wirings 17a and 17b can be improved as compared with the case where no gold plating layer is present on the surface.

  (6) The connection wirings 17 a and 17 b that connect the first electrode pads 12 b and 13 b and the second electrode pads 16 on the two stacked semiconductor chips 12 and 13 do not overlap in the thickness direction of the substrate 11. It is formed in a state. Therefore, the plating film of the connection wirings 17a and 17b can be formed at the same time, and the time required for manufacturing can be shortened as compared with the structure in which both the connection wirings 17a and 17b overlap in the thickness direction. Moreover, the distance (height) to the mounting surface 11a of the part corresponding to the slope 19 of the connection wiring 17b can be made low compared with the structure where both the connection wirings 17a and 17b overlap in the thickness direction.

(Second Embodiment)
Next, a second embodiment will be described with reference to FIGS. In this embodiment, the number of semiconductor chips stacked on the substrate and the connection wiring that connects the first electrode pad of the different semiconductor chip and the second electrode pad of the substrate are formed so as to overlap in the thickness direction of the substrate. This is different from the first embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 5A, a first semiconductor chip 12, a second semiconductor chip 13, and a third semiconductor chip 14 are sequentially stacked on the substrate 11. Twelve second electrode pads 16 are formed on the mounting surface 11a in parallel with one side of the substrate 11, that is, with the number of columns equal to the number of the semiconductor chips 12, 13, and 14 at an equal pitch. On the active surfaces 12 a, 13 a, and 14 a of the semiconductor chips 12, 13, and 14, first electrode pads 12 b, 13 b, and 14 b are formed in a row at the same pitch as the second electrode pads 16, respectively. The first electrode pads 12b, 13b, 14b and the second electrode pad 16 are arranged so as to be positioned on a straight line one by one.

  As shown in FIG. 5B, the slope 19 for relaxing the step between the mounting surface 11a and the surface of the passivation film 18 of the first semiconductor chip 12 is formed in the same manner as in the first embodiment. However, the slope 22 for relaxing the step between the mounting surface 11a and the surface of the passivation film 18 of the second layer semiconductor chip 13 is formed so as to cover the connection wiring 17a, and the passivation of the mounting surface 11a and the third layer semiconductor chip 14 is performed. A slope 23 that relaxes a step with respect to the surface of the film 18 is formed so as to cover the connection wiring 17b.

  In the case of manufacturing the semiconductor device 24, after the semiconductor chips 12, 13, and 14 are stacked on the substrate 11, first, there is no need to start from the slope forming step S2 in order to form the connection wiring 17a of the first semiconductor chip 12. Each step up to the electrolytic Au plating step S9 is performed. Next, in order to form the connection wiring 17b of the second layer semiconductor chip 13, the steps from the slope formation step S2 to the electroless Au plating step S9 are performed, and then the connection wiring 17c of the third layer semiconductor chip 14 is formed. In order to form, it is necessary to implement each process from slope formation process S2 to electroless Au plating process S9. In the slope forming step S2 for forming the slope 19 so that the plating film is not formed on the guide ring 15 on each of the semiconductor chips 12, 13, and 14, portions of the slopes 22 and 23 that cover the guide ring 15 Is formed. The remaining portion of the slope 22 is formed in the slope forming step S2 when the connection wiring 17b is formed after the connection wiring 17a is formed, and the remaining portion of the slope 23 is formed after the formation of the connection wiring 17b. It is formed in the slope forming step S2 when forming 17c.

  Therefore, no plating film is formed on the guide ring 15 of each semiconductor chip 12, 13, 14. However, a plating film twice as thick as the plating film formed on the first electrode pad 12b is formed on the first electrode pad 13b and the second electrode pad 16 corresponding to the first electrode pad 13b. A plating film having a thickness three times that of the plating film formed on the first electrode pad 12b is formed on the first electrode pad 14b and the second electrode pad 16 corresponding to the first electrode pad 14b. FIG. 5B shows the same thickness. Therefore, when the thickness of the passivation film 18 of each semiconductor chip 12, 13, 14 is the same, the plating film corresponding to the first electrode pads 13 b, 14 b protrudes from the surface of the passivation film 18 in the semiconductor chips 13, 14. It becomes a state but there is no problem. In order to avoid that the plating film corresponding to the first electrode pads 13b and 14b protrudes from the surface of the passivation film 18, the thickness of the periphery of the first electrode pads 13b and 14b in the semiconductor chips 13 and 14 is set. You may form thickly.

Therefore, according to this 2nd Embodiment, in addition to the effect similar to (1)-(5) of 1st Embodiment, the following effects can be acquired.
(7) Connection wirings 17a, 17b, and 17c that connect the first electrode pads 12b, 13b, and 14b of different semiconductor chips and the second electrode pad 16 of the substrate 11 are formed so as to overlap in the thickness direction of the substrate 11. Yes. Accordingly, the connection wirings 17a, 17b, and 17c are not overlapped in the thickness direction of the substrate 11, that is, the arrangement interval of the first electrode pads 12b, 13b, and 14b is formed to be an integral multiple of the arrangement pitch of the second electrode pads 16. Compared with the case where it does, the length of the width direction (arrangement direction of the 1st electrode pads 12b, 13b, and 14b) of semiconductor chips 12 and 13 can be shortened.

In addition, you may change embodiment as follows.
In the case where the connection wirings 17a and 17b are formed by electroless plating after the zincate treatment step S7, the connection wirings 17a and 17b are not limited to the laminated structure of the Ni layer and the Au layer. For example, a plurality of metal layers are laminated by forming connection wirings 17a and 17b with any one metal selected from Ni, Cu, Pd, Au, and Ag, or by performing electroless plating of a plurality of selected metals. Alternatively, the connection wirings 17a and 17b may be formed by alloy plating made of a plurality of metals (for example, Ni layer / Cu layer, Ni layer / Pd layer / Au layer). For example, electroless Ni plating, electroless Cu plating, and electroless Au plating may be continuously performed, and the connection wirings 17a and 17b may have a three-layer structure including an Au layer, a Cu layer, and a Ni layer from the surface layer side. Since the Ni layer is excellent as an underlayer for Cu plating, the Cu layer is preferably formed on the Ni layer.

  The semiconductor chips 12, 13, and 14 are conductive layers formed outside the first electrode pads 12b, 13b, and 14b of the active surfaces 12a, 13a, and 14a on which the first electrode pads 12b, 13b, and 14b are formed. A structure in which a TEG (an evaluation terminal) is formed in addition to the guide ring 15 may be used. Moreover, you may use what did not have the guide ring 15 but in which only TEG was formed.

  The semiconductor device is not limited to a configuration in which the first electrode pads 12b, 13b, and 14b of the semiconductor chips 12, 13, and 14 are directly connected to the second electrode pads 16 of the substrate 11 by the connection wirings 17a, 17b, and 17c, respectively. For example, as shown in FIG. 6, the semiconductor is configured such that the second electrode pad 16 is connected to the first electrode pad 12b by the connection wiring 25a, and the first electrode pad 12b is connected to the first electrode pad 13b by the connection wiring 25b. The same configuration may be applied to the device 26 or to a semiconductor device in which three or more semiconductor chips 12 are stacked. Moreover, the structure which has the connection wiring 17a, 17b, 17c of both structures and the connection wiring 25a, 25b may be sufficient.

  The semiconductor device is not limited to a multilayer chip semiconductor device in which semiconductor chips are stacked in two or three layers, and may be a semiconductor device having four or more layers or a single semiconductor chip. Further, the semiconductor chip is not limited to the one in which the first electrode pads are arranged along two opposing sides, but the first electrode pad is formed on only one side, or the semiconductor chip 12 is arranged along four sides. You may apply to what was done.

  The silane coupling agent used for the catalyst ink is not limited to having an amino group as a functional group capable of supporting palladium as a plating catalyst, and may have, for example, an imidazole group.

  The catalyst pattern forming step S3 is not limited to the method of forming the catalyst pattern 21 by discharging the catalyst ink in which the coupling agent supporting the plating catalyst is dispersed in the solvent onto the slope 19 or the like. For example, after a coupling agent (silane coupling agent) solution capable of supporting a plating catalyst (palladium) is discharged onto the slopes 19 and 20 to form a coupling agent layer, a Pd catalyst conversion treatment is performed to form a catalyst pattern. 21 may be formed.

  -The catalyst layer forming step, i.e., the catalyst pattern 21 formation time, is not limited to before the electroless plating step, but after the zincate treatment step S7, i.e., the metal in the electroless plating bath by electroless plating. You may carry out before making it deposit as a plating film.

The catalyst metal of the plating catalyst is not limited to palladium, but may be a metal capable of adsorbing (supporting) zinc or nickel, such as gold.
-The insulating material constituting the slopes 19, 20, 22, and 23 is not limited to epoxy-based thermosetting resins. For example, phenol-based or melamine-based thermosetting resins or photo-curing resins are used. Or you may.

  The catalyst pattern 21 may be formed so as to cover the first electrode pads 12b, 13b, 14b and the second electrode pad 16. Since the catalyst pattern 21 is very thin, for example, is formed of a monomolecular film, current and electrical signals are conducted between the first electrode pad 12b and the like, the second electrode pad 16 and the connection wiring 17a without any trouble. .

  S2 ... slope forming step, S7 ... zincate treatment step constituting electroless plating step, S8 ... electroless Ni plating step constituting electroless plating step, S9 ... electroless Au plating step constituting electroless plating step, 10 , 24, 26 ... semiconductor device, 11 ... substrate, 11a ... mounting surface, 12, 13, 14 ... semiconductor chip, 15 ... guide ring as a conductive layer, 12a, 13a, 14a ... active surface, 12b, 13b, 14b ... 1st electrode pad, 16 ... 2nd electrode pad, 17a, 17b, 17c, 25a, 25b ... Connection wiring, 19, 20, 22, 23 ... Slope.

Claims (6)

The semiconductor chip in which the conductive layer is formed outside the first electrode pad on the active surface on which the first electrode pad is formed is opposite to the active surface with respect to the substrate on which the second electrode pad is formed on the mounting surface. A method of manufacturing a semiconductor device mounted with the surface thereof facing the mounting surface,
A slope forming step of forming a slope made of an insulating material that relaxes a step between the mounting surface and the active surface so as to cover the conductive layer between the first electrode pad and the second electrode pad;
A catalyst layer forming step of forming a catalyst layer by discharging catalyst ink on the slope in order to form a connection wiring for electrically connecting the first electrode pad and the second electrode pad;
A method of manufacturing a semiconductor device comprising: an electroless plating step of forming a plating film on the first electrode pad, the second electrode pad, and the catalyst layer to form the connection wiring.   The method for manufacturing a semiconductor device according to claim 1, wherein the catalyst ink is obtained by dispersing a coupling agent carrying a plating catalyst in a solvent.   The method for manufacturing a semiconductor device according to claim 2, wherein the plating catalyst is palladium, and the coupling agent is a silane coupling agent.   The said 1st electrode pad and the said 2nd electrode pad are aluminum electrode pads, The said electroless-plating process is provided with the oxide film removal process and the zincate process process of any one of Claims 1-3. Semiconductor device manufacturing method.   A plurality of the semiconductor chips are stacked, and the connection wirings connecting the first electrode pads and the second electrode pads on each semiconductor chip are formed so as not to overlap in the thickness direction of the substrate. The manufacturing method of the semiconductor device of any one of Claims 1-4.   The method for manufacturing a semiconductor device according to claim 1, wherein a gold plating layer is formed on a surface of the connection wiring.

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