JP2010129144A - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device capable of speeding up reading / writing while suppressing an increase in chip area is realized.
A semiconductor memory device according to the present invention includes a plurality of memory cells 110 to 11n connected to a pair of bit line pairs (BL, / BL) and arranged in one column along the bit line pair, and bit lines The semiconductor memory device includes a read / write acceleration circuit 22 connected to a line pair and disposed in a dummy cell region 22 adjacent to the memory cell region 21 in which the memory cells 110 to 11n are disposed.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor memory device used in a system LSI.

  System LSIs (Large Scale Integrated circuits) use semiconductor storage devices having various storage capacities, word numbers, and bit numbers. In these semiconductor memory devices, an SRAM macro prepared so that a memory macro having an arbitrary configuration can be generated from a common unit block is used. In such a conventional semiconductor memory device, dummy cells are arranged at the periphery of the memory cell area of the memory cell array in the SRAM macro in order to reduce the influence of the dimensional variation of the element accompanying the miniaturization of the manufacturing process technology, the so-called microloading effect. A dummy cell region is provided.

  On the other hand, in such a conventional semiconductor memory device, the complementary signal (read data) transferred from the SRAM cell (memory cell) to the bit line pair is amplified by a read circuit arranged outside the memory cell array, and the semiconductor memory device. Is output outside of. In order to speed up the read operation from the semiconductor memory device, it is desirable to make the timing in the read circuit as fast as possible, but if the timing is too fast, the input potential difference supplied from the bit line pair to the read circuit becomes insufficient, The semiconductor memory device will malfunction. Therefore, in order to operate the semiconductor memory device at high speed, it is necessary to set an optimal timing according to the memory capacity of the semiconductor memory device (see, for example, “Patent Document 1”).

  However, in the conventional semiconductor memory device, when the capacity is increased, the read cell current from the memory cell becomes relatively smaller than the capacity of the bit line, so that the variation in the cell current for each memory cell becomes relatively large. There is a problem that it is difficult to increase the speed by the method of setting the optimum timing according to the storage capacity of the storage device. That is, if the variation in cell current for each memory cell is large, the bit line waveform at the time of reading becomes dull, and the variation in reading speed for each memory cell also increases, so that the worst value of timing in the reading circuit becomes extremely slow. was there.

In addition, in order to reduce the variation in the reading speed for each memory cell, the bit line pair is divided short, that is, if the number of divisions of the memory cell array is increased, the required dummy cell area is increased correspondingly and the influence on the chip area is affected. There was a problem that it could not be ignored.
JP 2007-250020 A

  The present invention provides a semiconductor memory device capable of speeding up reading / writing while suppressing an increase in chip area.

  According to one aspect of the present invention, a plurality of memory cells connected to a pair of bit line pairs and arranged in one column along the bit line pair, and connected to the bit line pair, the plurality of memories There is provided a semiconductor memory device having read / write acceleration means arranged in a dummy cell region adjacent to a memory cell region in which cells are arranged.

  According to the present invention, it is possible to suppress variations in the read / write speed in the bit line pairs, so that access to the memory cell can be speeded up.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention. Here, for the sake of explanation, a memory cell connected to a pair of bit lines (BL, / BL) and a portion related to reading / writing thereof are shown.

  A semiconductor memory device according to an embodiment of the present invention includes (n + 1) memory cells 110 to 11n, a read / write acceleration circuit 12 (hereinafter referred to as “R / W acceleration circuit 12”), and a Domino R / W circuit. 13 is provided.

  Memory cells 110-11n, R / W acceleration circuit 12, and domino R / W circuit 13 are connected to a pair of bit lines BL, / BL (hereinafter also referred to as "bit line pairs") arranged in parallel. The memory cells 110 to 11n are arranged in the memory cell region 21, the R / W acceleration circuit 12 is arranged in the dummy cell region 22, and the domino R / W circuit 13 is arranged in the peripheral circuit region 23.

  The dummy cell region 22 is disposed close to the memory cell region 21, and the peripheral circuit region 23 is disposed opposite to the memory cell region 21 with the dummy cell region 22 interposed therebetween.

  The memory cells 110 to 11n are arranged densely sequentially along the bit line pair, the R / W acceleration circuit 12 is arranged close to the memory cell 110, and the domino R / W circuit 13 is connected to one end of the bit line pair. ing.

  In the memory cell region 21, (n + 1) word lines (hereinafter referred to as “wl <0> to <n>”) are arranged in a direction orthogonal to the bit line pair, and the memory cells 110 to 11n are respectively provided. It is connected to corresponding wl <0> to <n>.

  Further, a sense signal line (hereinafter referred to as “acl”) is disposed in the dummy cell region 22 in a direction orthogonal to the bit line pair, and the R / W acceleration circuit 12 is connected to acl.

  The memory cells 110 to 11n are so-called 6Tr type SRAM cells each composed of two p-type MOSFETs (hereinafter referred to as “PMOS”) and four n-type MOSFETs (hereinafter referred to as “NMOS”). Yes, 1-bit data is stored based on complementary signals of the bit line pair.

  For example, as shown in FIG. 1, the memory cell 110 includes two PMOSs (m50 and m60) and four NMOSs (m10 to m40), the drain of m10 is connected to BL, and the gate of m10 Is connected to wl <0>, the drain of m20 is connected to / BL, the gate of m20 is connected to wl <0>, the drain of m30 is connected to the source of m10, and the source of m30 , The drain of m40 is connected to the source of m20, the source of m40 is connected to Vss, the drain of m50 is connected to the drain of m30, and the source of m50 is the power supply potential (hereinafter referred to as “Vss”). The gate of m50 is connected to the gate of m30 and the drain of m40, and the drain of m60 is connected to the drain of m40. The source of m60 is connected to Vdd, and the gate of m60 is connected to the gate of m40 and the drain of m20.

  The memory cell 11n has the same configuration as the memory cell 110. The difference between the memory cell 11n and the memory cell 110 is that the gates of m1n and m2n are connected to wl <n>.

  The R / W acceleration circuit 12 is composed of two PMOSs (m5d and m6d) and four NMOSs (m1d to m4d). The drain and source of m1d are connected to BL, and the drain and source of m2d are connected to / BL. Connected, the drain of m3d is connected to BL, the source of m3d is connected to acl, the drain of m4d is connected to / BL, the source of m4d is connected to acl, and the drain of m5d is connected to the drain of m3d , M5d source is connected to Vdd, m5d gate is connected to m3d gate and m4d drain, m6d drain is connected to m4d drain, m6d source is connected to Vdd, and m6d gate is m4d. And the drain of m3d.

  In addition, the R / W acceleration circuit 12 uses a base pattern (layout pattern such as a diffusion layer and a gate layer) of a conventional dummy cell arranged around the memory cell region 21 as it is to suppress the microloading effect. is doing. In particular, the diffusion layer forming the source and drain of m1d to m6d and the gate layer made of the polysilicon wiring forming the gate of m1d to m6d are the same as those of the memory cells 110 to 11n because the influence of the microloading effect is large. The shape layout pattern is arranged at the same pitch.

  Therefore, the base pattern of the R / W acceleration circuit 12 has the same shape as the memory cells 110 to 11n, and the layout block of the R / W acceleration circuit 12 has the same block size as the memory cells 110 to 11n. For this reason, the R / W acceleration circuit 12 does not affect the chip size.

  It should be noted in FIG. 1 that the gates of m1d and m2d are floating, the source and drain of m1d are connected to BL, and the source and drain of m2d are connected to / BL. This is because the ground pattern of the memory cells 110 to 11n is used as it is to suppress the above-described microloading effect.

  The Domino R / W circuit 13 is a main read / write circuit provided in the peripheral circuit region 23 and is disposed relatively far away from the R / W acceleration circuit 12.

Next, the operation of the semiconductor memory device having the above configuration will be described.
FIG. 2 is a waveform diagram showing the operation of the semiconductor memory device according to the embodiment of the present invention. Here, as an example, a portion related to a read operation from the memory cells 110 to 11n is shown.

  WL indicates the waveform of the word line selected from wl <0> to <n>. Further, here, a case where data such that BL becomes “Low” is read from the memory cell selected by WL is shown.

  First, when WL is changed from “Low” to “High” at time T1, a current flows from BL to the memory cell and the potential of BL starts to decrease. The potential drop of BL greatly varies due to variations in charge supply capability among the memory cells, the position of the selected memory cell, and variations in the wiring capacity of the bit line pairs.

  Next, when acl is changed from “High” to “Low” at time T2, the R / W acceleration circuit 12 is activated and the bit line pair is sensed. T2 is set in consideration of the above-described variation in potential drop of BL (± 5σ). Specifically, the R / W acceleration circuit 12 is set to be activated when the potential difference between the bit line pair becomes ˜100 mV.

  When the R / W acceleration circuit 12 is activated, BL is suddenly sensed “Low”, and when the potential difference between the bit lines is sufficiently established in the domino R / W circuit 13 connected to the end of the BL, the main domino is detected. The R / W circuit 13 is activated and sensed.

  In this way, by using the R / W acceleration circuit 12, it is possible to suppress variations in reading time to the BL (Ta to Tb: @ ± 5σ) and to connect to the end of the BL having a large wiring capacity. The sense timing in the Domino R / W circuit 13 can be greatly shortened, and high-speed data reading becomes possible.

  Although not shown, the write time can be shortened by using the R / W acceleration circuit 12 for the write operation, and the transistor size of the write driver in the domino R / W circuit 13 can be reduced. Can be small.

  According to the above embodiment, since the variation in the read / write speed in the bit line pair (BL, / BL) can be suppressed, the access to the memory cells 110 to 11n can be speeded up.

  Further, according to the above embodiment, the transistor size of the write driver in the domino R / W circuit 13 can be reduced.

  In the above embodiment, the Domino R / W circuit 13 is connected to one bit line pair (BL, / BL). However, the present invention is not limited to this, and a plurality of bit line pairs are connected. Is also applicable to a so-called multi-column configuration in which a single Domino R / W circuit 13 is connected via a selection circuit. In this case, by operating the R / W acceleration circuit 12 even in a non-selected column, there is an effect that a non-selected bit line pair is stabilized.

  In the above embodiment, the m1d and m2d sources and drains of the R / W acceleration circuit 12 are short-circuited so that the m3d drain is connected to BL and the m4d drain is connected to / BL. Is not limited to this. For example, instead of short-circuiting the sources and drains of m1d and m2d, as shown in FIG. 3, the gates of m1d and m2d are connected to Vdd and m1d and m2d are always turned on. Alternatively, the drain of m3d and BL may be electrically connected, and the drain of m4d and / BL may be electrically connected. In this way, it is possible to obtain the same effect using the base pattern of the memory cells 110 to 11n as it is.

1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention. FIG. 6 is a waveform diagram showing the operation of the semiconductor memory device according to the example of the invention. FIG. 6 is a circuit diagram showing another read / write acceleration circuit 12 in the semiconductor memory device according to the embodiment of the present invention.

Explanation of symbols

110 to 11n memory cell 12 read / write acceleration circuit (R / W acceleration circuit)
13 Domino R / W circuit 21 Memory cell region 22 Dummy cell region 23 Peripheral circuit region BL, / BL Bit line wl <0> to wl <n> Word line

Claims (5)

A plurality of memory cells connected to a pair of bit line pairs and arranged in one column along the bit line pair;
A semiconductor memory device comprising read / write acceleration means connected to the bit line pair and disposed in a dummy cell region adjacent to the memory cell region in which the plurality of memory cells are disposed.   2. The semiconductor memory device according to claim 1, wherein the read / write acceleration means has a layout width in a direction orthogonal to the bit line pair that is the same as a layout width of the memory cell.   2. The semiconductor memory device according to claim 1, wherein the layout pattern of the read / write acceleration means has the same shape as the layout pattern of the memory cell. The read / write acceleration means includes
A first n-type MOS transistor having a drain connected to one of the bit line pairs and a gate connected to a power source;
A second n-type MOS transistor having a drain connected to the other of the bit line pair and a gate connected to a power source;
A third n-type MOS transistor having a drain connected to the source of the first n-type MOS transistor and a source connected to the sense signal line;
A fourth n-type MOS transistor having a drain connected to the source of the second n-type MOS transistor and a source connected to the sense signal line;
The drain is connected to the drain of the third n-type MOS transistor, the source is connected to the power supply, and the gate is connected to the gate of the third n-type MOS transistor and the drain of the fourth n-type MOS transistor. A first p-type MOS transistor;
The drain is connected to the drain of the fourth n-type MOS transistor, the source is connected to the power supply, and the gate is connected to the gate of the fourth n-type MOS transistor and the drain of the third n-type MOS transistor. The semiconductor memory device according to claim 1, further comprising a second p-type MOS transistor. The read / write acceleration means includes
A first n-type MOS transistor having a drain and a source connected to one of the bit line pairs;
A second n-type MOS transistor having a drain and a source connected to the other of the bit line pair;
A third n-type MOS transistor having a drain connected to the source of the first n-type MOS transistor and a source connected to the sense signal line;
A fourth n-type MOS transistor having a drain connected to the source of the second n-type MOS transistor and a source connected to the sense signal line;
The drain is connected to the drain of the third n-type MOS transistor, the source is connected to the power supply, and the gate is connected to the gate of the third n-type MOS transistor and the drain of the fourth n-type MOS transistor. A first p-type MOS transistor;
The drain is connected to the drain of the fourth n-type MOS transistor, the source is connected to the power supply, and the gate is connected to the gate of the fourth n-type MOS transistor and the drain of the third n-type MOS transistor. The semiconductor memory device according to claim 1, further comprising a second p-type MOS transistor.

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