JP2010171369A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it easy to set a trimming code that has taken into consideration errors due to variations in the manufacturing step. <P>SOLUTION: The semiconductor device generates a trimming code TMRC (=TMRC1) that adjusts an output voltage Va of a power source to be adjusted 1 while varying it, stores the trimming code TMRC in a trimming code storage circuit 3 when the output voltage Va of the power source to be adjusted 1 reaches a value corresponding to a target voltage Vt, and sets the output voltage Va of the power source to be adjusted 1 based on the stored trimming code TMRC (=TMRC2). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device for adjusting circuit characteristics and the like.

  In a semiconductor device, for example, by a process called a power supply voltage trimming process, the voltage of the internal power supply is adjusted for each chip by fuse trimming or the like to set circuit characteristics. In the conventional power supply voltage trimming process, first, the power supply voltage is read as numerical information using the function of the memory tester or the function installed in the device under test. Then, from the difference between the read numerical value and the target numerical value, a person or in many cases a computer numerically processes the trimming code. This trimming code is information for setting the connection state of the fuse, and the trimming fuse is cut by giving the trimming code to the fuse trimmer. The problem with this method is that if there is an error in the trimming code and the voltage adjusted thereby, the error is directly linked to the error in the trimming result. That is, in the power supply voltage trimming process, the power supply voltage is usually adjusted by changing (or selecting) the connection state of the adjustment circuit by trimming the fuse. In this case, the connection state based on the same trimming code is naturally the same regardless of the device characteristics. However, depending on the configuration of the adjustment circuit, the relationship between the change in the connection state and the voltage adjustment width (or adjustment value) varies depending on the device characteristics. The variation in the relationship between the connection state change and the adjusted voltage appears as an error with respect to the target value of the trimming result of the power supply voltage.

  In general, the adjustment circuit is designed such that the dividing point of the resistance element, the number of elements, and the like are changed by a trimming code. In this case, the characteristics of the element depend on the manufacturing process, and in recent years when the diameter of the wafer is enlarged, the difference between chips cannot be ignored. Therefore, in the past, in order to confirm the validity of the trimming code, a test mode was used to reproduce the state after fuse trimming in a pseudo manner using the trimming code, and the state after fuse trimming was reproduced. Measurements, errors are recognized, and trimming codes are changed (for example, see Patent Document 1). However, this method is obviously a troublesome process.

  Also, since the test mode setting is volatile, it must be set every time the power is turned on.There are many settings depending on the nature of the trimming code, and the test time increases as the number of test items increases. (For example, refer to Patent Document 2). As other prior art documents, there are Patent Document 3 and Non-Patent Document 1.

JP-A-7-144101 JP 2008-053259 A JP 2003-152092 A

Akira Nakamori, “Introduction to Microprocessor Architecture”, CQ Publishing Co., Ltd., April 1, 2004, Appendix6 High-speed arithmetic unit

  As described above, in the semiconductor device, setting a trimming code in consideration of an error due to a variation in a manufacturing process becomes a problem.

  In the trimming method described in Patent Document 1, a switching element is provided in series with the fuse element, and the power supply voltage can be adjusted repeatedly by controlling on / off of the switching element. The switching element can be turned on / off at a higher speed than the time required for trimming the fuse element. However, since the repeated adjustment is performed by repeatedly measuring and comparing the voltage and changing the trimming code, a process such as setting the trimming code a plurality of times is required.

  In addition, there are many setting locations in the semiconductor device, and the increase in test time becomes a problem as the number of test items with power-on increases.

  In the semiconductor device of the present invention, the power supply control unit is generated while changing the control signal for adjusting the output voltage of the adjusted power supply unit, and the output voltage of the adjusted power supply unit based on the control signal becomes the control target voltage. The control signal when a corresponding value is obtained is stored, and the output voltage of the adjusted power supply unit is set based on the stored control signal.

  According to the present invention, the control signal when the output voltage of the adjusted power supply unit becomes a value corresponding to the control target voltage is stored, and the output voltage setting of the adjusted power supply unit is set based on the stored control signal. It can be performed. According to this, since the control signal can be automatically changed and set to a value corresponding to the semiconductor device, it is possible to easily set the control signal in consideration of an error due to variations in the manufacturing process.

The schematic diagram for demonstrating the matching principle of the power supply voltage in embodiment of the semiconductor device of this invention. 1 is a block diagram showing a circuit configuration of an embodiment of a semiconductor device of the present invention. The block diagram which shows the circuit structure of the modification of embodiment of FIG. FIG. 4 is a circuit diagram showing a configuration example of the regulated power supply 1 of FIGS. 2 and 3. FIG. 4 is a block diagram illustrating a configuration example of a trimming code generation / storage circuit 2 in FIGS. 2 and 3; The schematic diagram for demonstrating the principle for detecting (recording) the junction temperature at the time of trimming adjustment in other embodiment of the semiconductor device of this invention. The block diagram which shows the circuit structure of other embodiment of the semiconductor device of this invention. The block diagram which shows the circuit structure of the modification of embodiment of FIG. FIG. 9 is a circuit diagram showing a configuration example of the regulated power supply 1b of FIGS. 7 and 8; FIG. 9 is a circuit diagram showing a configuration example of a temperature-dependent power source 7 in FIGS. 7 and 8. FIG. 9 is a block diagram illustrating a configuration example of a control circuit for supplying test mode 1 to 3 signals TM1 to 3 to the semiconductor devices of FIGS. 2, 3, 7, and 8. FIG. 12 is a waveform diagram showing an operation until a trimming code is determined in test mode 1 in the control circuit 8 of FIG. FIG. 12 is a waveform diagram showing an operation when confirming a trimming result in test mode 3 in the control circuit 8 of FIG. 11. The block diagram which shows the circuit structure (semiconductor device 100e) of other embodiment of the semiconductor device of this invention. FIG. 15 is a block diagram showing a configuration example of a trimming code generation / storage circuit 211 in FIG. 14. FIG. 16 is a circuit diagram showing a configuration example of a decoder 222 in FIG. 15. FIG. 15 is a circuit diagram illustrating a configuration example of the regulated power supply 213 in FIG. 14. FIG. 15 is a schematic diagram for explaining a state of search by linear search in the semiconductor device 100e of FIG. FIG. 15 is a schematic diagram for explaining a state of search by binary search in the semiconductor device 100e of FIG. FIG. 15 is a block diagram showing a configuration example (trimming code generation / storage circuit 211a) of the trimming code generation / storage circuit 211 of FIG. 14; FIG. 21 is a block diagram showing a detailed configuration example of a trimming code generation / storage circuit 211a of FIG. 20; FIG. 22 is a circuit diagram showing a configuration example of a 1-bit full adder 351 and the like in FIG. 21. FIG. 15 is a block diagram illustrating a configuration example of a control circuit for supplying test mode 0 to 3 signals to the semiconductor device 100e of FIG. 14; FIG. 15 is a timing chart for explaining an operation at the time of binary search in the semiconductor device 100e of FIG. 14; 15 is a timing chart for explaining the operation in the test mode 3 in the semiconductor device 100e of FIG. FIG. 15 is a timing chart for explaining an operation during linear search in the semiconductor device 100e of FIG. 14; FIG. The block diagram which shows the circuit structure (semiconductor device 100f) of further another embodiment of the semiconductor device of this invention. FIG. 15 is a circuit diagram showing a modified example (trimmed circuit 215a) of the trimmed circuit 215 in FIG. 14; FIG. 15 is a block diagram showing another configuration example (trimming code generation / storage circuit 211b) of the trimming code generation / storage circuit 211 of FIG. 14; FIG. 15 is a block diagram showing another configuration example (trimming code generation / storage circuit 211c) of the trimming code generation / storage circuit 211 of FIG. 14; FIG. 31 is a block diagram showing a detailed configuration example of a trimming code generation / storage circuit 211c of FIG. 30; 15 is another timing chart for explaining an operation at the time of binary search in the semiconductor device 100e of FIG.

  Hereinafter, embodiments of a semiconductor device according to the present invention will be described with reference to the drawings. First, with reference to FIG. 1, the principle of adjusting the power supply voltage at the time of trimming in the present embodiment will be described. FIG. 1 is an explanatory diagram showing the relationship between the output voltage Va of a regulated power supply whose power supply voltage is adjusted and the target voltage (control target voltage) Vt for adjustment. Here, it is assumed that the output voltage Va of the power source to be adjusted can be adjusted by a trimming code (control signal).

  In the present embodiment, the voltage Va to be adjusted is gradually changed while changing the value indicated by the trimming code, the trimming code crossing the target voltage Vt is detected, and fuse trimming is performed using the code. FIG. 1 shows a state where the output voltage Va of the regulated power supply is gradually approached from a state higher than the target voltage Vt. In the present embodiment, it is important to pay attention not to the trimming code but to determine whether or not the adjusted voltage Va matches the target voltage Vt. By changing the trimming code for each semiconductor device in this manner, trimming of a desired voltage can be performed in consideration of manufacturing variations.

  Next, a configuration example of a circuit used for adjusting the power supply voltage will be described with reference to FIG. FIG. 2 is a block diagram illustrating a configuration example of the semiconductor device according to the present embodiment. However, FIG. 2 shows a part of the internal configuration of the semiconductor device of the present embodiment, that is, a configuration part used for power matching that is a feature of the present embodiment. That is, the semiconductor device of the present embodiment can be configured as, for example, a semiconductor memory device, but other configurations such as a memory cell array in that case are not shown.

  A semiconductor device 100a shown in FIG. 2 includes a power supply 1 to be adjusted whose output voltage is adjusted by a trimming code TRMC, a trimming code generation / storage circuit 2, a trimming code storage circuit 3, a selector 4, and a comparator 5. Configured. Among these, the trimming code generation / storage circuit 2, the trimming code storage circuit 3, the selector 4, and the comparator 5 excluding the regulated power supply 1 constitute a power supply control unit 10a. Is generated while changing the trimming code TRMC for adjusting the output voltage of the regulated power supply 1 (the regulated power supply unit), and the output voltage Va of the regulated power supply 1 based on the trimming code TRMC corresponds to the target voltage Vt. Then, the trimming code TRMC is stored, and the output voltage Va of the regulated power supply 1 is set based on the stored trimming code TRMC. Here, the trimming code TRMC is a signal output from the selector 4 having the trimming code TRMC1 and the trimming code TRMC2 as two input signals, and the selection output of the selector 4 is determined based on the control signal S1.

  The power source 1 to be adjusted includes a voltage adjustment circuit 11 to which a reference voltage Vref is input from a terminal 66 and a circuit to be trimmed 12 whose operation state is set according to the input trimming code TRMC. The regulated power supply 1 changes the output voltage Va according to the reference voltage Vref input to the voltage regulating circuit 11 and the operation state set in the trimmed circuit 12 and outputs the changed output voltage Va.

  The trimming code generation / storage circuit 2 receives the test mode 1 signal TM1 from the terminal 61 and generates the trimming code TMRC1 while changing the level of the input signal CR (in this example, “L”). Functions as a control signal generation circuit that stores and holds the trimming code TRMC1 that is being generated). The test mode 1 signal TM1 is a pulse signal that is repeated a predetermined number of times. The trimming code TMRC1 output from the trimming code generating / storing circuit 2 is input to the “0” terminal of the selector 4 and also connected to the terminal 63 via the switch circuit 62 that is ON / OFF controlled by the test mode 2 signal TM2. Is output to the outside.

  The trimming code memory circuit 3 is a non-volatile memory circuit using a fuse element or EEPROM (Electrically Erasable Programmable Read Only Memory). The trimming code TRMC1 when the level of the comparison result (output signal CR) of the comparator 5 changes is obtained. In addition to storing the signal to represent, the selection signal S1 of the selector 4 is changed from “0” to “1” and stored. A signal representing the trimming code TRMC1 stored in the trimming code storage circuit 3 is input to the “1” terminal of the selector 4 as the trimming code TRMC2. Here, in this example, the signal representing the trimming code TRMC1 stored in the trimming code storage circuit 3 is the trimming code TRMC1 that is temporarily output from the terminal 63, the fuse trimmer, etc. from the outside again via an input circuit (not shown). It is memorized by inputting using.

  The selector 4 is a selection circuit that inputs either the trimming code TRMC 1 output from the trimming code storage circuit 3 or the trimming code TRMC 2 stored in the trimming code storage circuit 3 to the trimmed circuit 12. The selector 4 selects the trimming code TRMC1 input to the “0” terminal when the selection signal S1 is “0”, and the trimming code TRMC2 input to the “1” terminal when the selection signal S1 is “1”. Select to output.

  The comparator 5 is constituted by an open-loop differential amplifier, and compares the output voltage Va of the regulated power supply 1 with the target voltage Vt applied from the outside via the terminal 67 and outputs a comparison result. The output CR of the comparator 5 is input to the trimming code generating / storing circuit 2 and output from the terminal 65 to the outside via the switch circuit 64 that is controlled to be turned on / off by the test mode 3 signal TM3. Here, the terminal 65 is provided in the semiconductor device 100a in such a form that it can be connected even after the semiconductor device 100a is packaged (for example, by providing a circuit that can be connected to an external input / output pin via a selector or the like). It is desirable to keep it. Further, in this embodiment, the pad 68 for monitoring the output signal CR of the comparator 5 in the case of, for example, the test mode 1 (usually before packaging in the manufacturing process) is provided. Still better.

  In the configuration shown in FIG. 2, since the terminal 67 is used so that the target voltage Vt can be applied from the outside of the semiconductor device 100a, it has a form that can be connected to a device such as an external tester as a pad or a pin. Suppose you are. On the other hand, what is connected to other circuits in the same semiconductor device 100a such as the terminal 66 does not necessarily have to be connected to the outside of the semiconductor device 100a using a pad or the like.

  Next, an operation example of the configuration shown in FIG. 2 will be described with reference to the block diagram of FIG. In this example, the trimming code TRMC is changed in the test mode 1 to adjust the adjusted power supply output voltage Va, and the trimming code storage circuit based on the trimming code TRMC in the adjusted state in the test mode 2 (more precisely, the trimming code TRMC1). 3 is written, and the adjustment value of the adjusted power supply output voltage Va based on the trimming code TRMC (more precisely, the trimming code TRMC2) stored in the trimming code storage circuit 3 in the test mode 3 is compared with the target voltage Vt. The operation shall be performed.

  In the initial state, the adjusted voltage Va is set to be higher than the target voltage Vt. Further, it is assumed that the value of the selection signal S1 of the selector 4 stored in the trimming code storage circuit 3 is “0”.

  In the test mode 1, by inputting a repeated pulse signal as the test mode 1 signal TM1, the trimming code generation / storage circuit 2 is driven, and the trimming code TRMC is generated so that the regulated voltage Va gradually decreases. As a result of adjusting the trimmed circuit 12, the regulated power supply 1 gradually lowers the regulated power supply output voltage Va. This adjusted power supply output voltage Va is inputted to a comparator 5 having a reference of a separately applied target voltage Vt as a reference, and the voltage is compared for each generated trimming code TRMC. In the figure, the regulated power supply output voltage Va is input to the inverting input terminal of the comparator 5 and the target voltage Vt is input to the non-inverting input terminal. For this reason, the comparison result is switched from “L” to “H” when the two voltages intersect.

  The comparison result (signal CR) is returned to the trimming code generation / storage circuit 2, and the trimming code generation / storage circuit 2 receives the switching in which the signal CR has changed to "H" level, and the trimming code at that time Store TRMC1. Since the trimming code TRMC1 thus stored is volatile, the trimming code TRMC1 can be taken out in the test mode 2 to be recorded in the trimming code storage circuit 3 including a fuse element as a nonvolatile storage circuit. In the test mode 2, the test mode 2 signal TM2 becomes “H” level, the switch circuit 62 is turned on, and the trimming code TRMC1 is output from the terminal 63. The extracted result is used for fuse trimming of the trimming code storage circuit 3. That is, the trimming code storage circuit 3 performs writing based on the trimming code TRMC1, and thereafter outputs the same signal as the trimming code TRMC1 written as the signal trimming code TRMC2. When the trimming code TRMC1 is stored, the signal S1 stored in the trimming code storage circuit 3 is updated from “0” to “1”.

  Accordingly, thereafter, the selector 4 outputs the trimming code TRMC2 input to the “1” terminal as the trimming code TRMC. Then, the operation state of the trimming circuit 12 is set by the trimming code TRMC output from the selector 4, and the regulated power supply output voltage Va becomes a regulated value.

  Further, the voltage Va after fuse trimming can be confirmed by using the test mode 3 and applying the target voltage Vt. That is, in the test mode 3, the test mode 3 signal TM3 becomes “H” level, the switch circuit 64 is turned on, and the comparison result CR of the comparator 5 is output from the terminal 65. While changing the target voltage Vt and monitoring the comparison result CR and detecting when the level of the signal CR changes, the voltage Va after fuse trimming can be confirmed.

  Next, FIG. 3 shows another example of the power supply voltage matching circuit configuration described with reference to FIG. A semiconductor device 100b illustrated in FIG. 2 includes a regulated power supply 1 and a power control unit 10b. In addition, the same code | symbol is used for the same thing as the structure shown in FIG. The difference between the embodiment shown in FIG. 3 and FIG. 2 is that the trimming code TRMC1 recorded by the trimming generation / storage circuit 2 in the power supply control unit 10b is input to the trimming code storage circuit 3a in the test mode 2. . When the trimming code storage circuit 3a is electrically programmable like an electric fuse or EEPROM, fuse trimming can be performed by itself using this trimming code. Other configurations and operations are the same as those of the embodiment shown in FIG.

  FIG. 4 is an example of the configuration of the regulated power supply 1 of FIGS. 2 and 3. 4 includes a differential amplifier 111 and a P-channel MOS (Metal Oxide Semiconductor) transistor 112 in which the output of the differential amplifier 111 is connected to the gate. . The trimmed circuit 12 is composed of a plurality of resistors 121 connected in series and a plurality of switch circuits 122 for extracting each connection point. A reference voltage Vref is input to the non-inverting input terminal of the differential amplifier 111, and a voltage obtained by dividing the voltage Va output from the drain of the P-channel MOS transistor 112 by the resistor 121 is input to the inverting input terminal. Since each switch circuit 122 is ON / OFF controlled by the trimming code TRMC, the voltage division ratio is adjusted by the trimming code TRMC. Therefore, the value of the adjusted power supply output voltage Va is set based on the trimming code TRMC. As described above, in the regulated power supply 1 of FIG. 4, the voltage to be compared with the reference voltage Vref is variable by the trimming code TRMC, and the regulated power supply output voltage Va can be adjusted.

  FIG. 5 is a configuration example of the trimming code generating / storing circuit 2 shown in FIGS. The trimming code generation / storage circuit 2 of FIG. 5 includes an n-bit counter 21 and a decoder 22 that decodes the n-bit output of the counter 21 and outputs the trimming code TRMC1 in parallel on 2 n signal lines. The AND circuit 23 is configured to input a count clock signal to the counter 21. The AND circuit 23 receives the test mode 1 signal TM1 and a signal obtained by inverting the signal CR indicating the comparison result. In the test mode 1, since a repetitive pulse signal is input as the test mode 1 signal TM1, the counter 21 can be driven by counting the test mode 1 signal TM1 and the trimming code TMRC1 while the comparison result CR is “L”. Can be changed. After that, when the comparison result becomes “H”, the output of the AND circuit 23 is fixed at “L”, so that the counter 21 stops and the trimming code TRMC1 at that time is held. Here, it is assumed that the counter 21 is initialized at the start of operation.

  Next, another embodiment of the present invention will be described with reference to FIGS. In the present embodiment illustrated in FIG. 7, the two voltages compared by the comparator 5 are changed as compared with the above-described embodiment. That is, the comparator 5 in FIG. 7 compares the regulated power supply output voltage Vr having no temperature dependence with the output voltage Vd of the power supply having a temperature dependence. Here, the output voltage Vr of the regulated power supply 1b is the temperature-independent power supply 11b that outputs the temperature-independent voltage Vbg generated by using the element inside the semiconductor device, and the output voltage Vbg is the trimming code TRMC. Is generated by a regulated power supply 1b including a trimmed circuit 12b that outputs an output voltage Vr adjusted based on the above. The voltage Vd is an output voltage of the temperature-dependent power supply 7 that generates a voltage Vd that depends on the temperature generated by using an element inside the semiconductor device. That is, in this embodiment, the regulated power supply output voltage Va of the above embodiment is output to the regulated power supply output voltage Vr output from the power supply 11b that is not temperature dependent, and the target voltage Vt is output from the power supply 7 that is temperature dependent. Each is replaced with the output voltage Vd.

  The principle of adjusting the power supply voltage in this embodiment will be described with reference to FIG. FIG. 6 shows the relationship between the temperature-dependent output voltage Vr of the regulated power supply 1b and the temperature-dependent power supply 7 output voltage Vd, with the horizontal axis representing temperature and the vertical axis representing voltage. . For example, the output voltage Vd of the power supply 7 having temperature dependence changes depending on the temperature. The output voltage Vd decreases as the temperature increases. It is assumed that the voltage when the current junction temperature value in the semiconductor device 100b is Tj0 is V1. In this case, it is assumed that the output voltage Vr having no temperature dependence is V2. Here, the trimming code is changed, and the voltage Vr is changed to V1 so as to coincide with the voltage Vd. In this way, the temperature-dependent voltage Vd value V1 under the current temperature condition can be stored as the temperature-independent voltage Vr value for which the trimming code is set. If such trimming is performed, when a test such as measurement of characteristics of the semiconductor device 100b is performed at the junction temperature Tj0, the temperature at which the voltage Vd and the voltage Vr coincide with each other by changing the ambient temperature of the semiconductor device. If the conditions can be set, the junction temperature of the semiconductor device can be made to coincide with the trimming adjustment temperature, that is, Tj0 in this example.

  Here, a technical background in which such a configuration is adopted will be described. When discussing device characteristics, ambiguity of junction temperature has been a problem. Naturally, it is the characteristics of a large number of transistors that influence the characteristics of the device. Therefore, the temperature of the PN junction that is created at the same time, not the ambient temperature, the so-called junction temperature is an important factor. Become. When evaluating the correlation of characteristics between different processes, for example, what is measured at the junction temperature ≈ ambient temperature, such as the wafer state, is affected by the package encapsulation state, and even adjacent chips, such as multichip packages. In this state, it is extremely difficult to evaluate the bonding temperature in the same state. Therefore, conventionally, by carefully measuring the thermal resistance of the encapsulating material and using the method of estimating the junction temperature of the internal device from the package surface temperature, that is, using the value obtained by converting the package surface temperature to the junction temperature, The junction temperature is predicted, and the ambient temperature is adjusted so that the predicted value becomes a desired temperature. This method is clearly indirect and prone to errors. Therefore, the device memorizes the junction temperature of the reference process, and reads it in the process in which it is desired to compare it, so that a desired evaluation can be performed.

  In recent years, with the diversification of users on the mobile side, there has been a demand for an optimum operating environment under actual temperature conditions under various needs. In addition, in the DRAM (Dynamic Random Access Memory) for Mobile (mobile), where the BareDie business is the mainstream, the temperature correlation in the test environment after the wafer (wafer) test state and the customer PKG (packaging) is very difficult. Is the situation. Against such a background, according to the method shown in the present embodiment, it is possible to smoothly adjust the characteristics and contribute to the reduction of power consumption.

  As shown in FIG. 6, in this embodiment, the power supply Vr that does not depend on temperature is gradually changed while changing the trimming code, and the trimming code that intersects the power supply Vd that has temperature dependence at the current junction temperature Tj0 is detected. Then, fuse trimming is performed with the code. FIG. 6 shows a state in which the power supply Vr having no temperature dependence is gradually approached from a state higher than the power supply Vd having the temperature dependence at Tj0.

The circuit configuration of the present embodiment will be described in more detail with reference to FIG.
A semiconductor device 100c shown in FIG. 7 includes a regulated power supply 1b, a trimming code generation / storage circuit 2, a trimming code storage circuit 3, a selector 4, a comparator 5, and a temperature-dependent power supply 7. ing. Among these, the trimming code generation / storage circuit 2, the trimming code storage circuit 3, the selector 4, the comparator 5, and the temperature-dependent power source 7 excluding the regulated power source 1b constitute the power source control unit 10c. . 7, the same reference numerals are used for the same components as those in FIG. In the semiconductor device 100c shown in FIG. 7, the configuration of the regulated power supply 12b and the voltage input to the comparator 5 are different from the configuration example of the semiconductor device 100a shown in FIG.

  In the semiconductor device 100c shown in FIG. 7, in the initial state, the regulated voltage Vr is set to a value higher than the temperature-dependent voltage Vd. The trimming code generation / storage circuit 2 is driven in the test mode 1, and the trimming code TRMC is generated so that the regulated voltage Vr gradually decreases. As a result of adjusting the trimmed circuit 12b, the power supply 11b having no temperature dependence gradually reduces the regulated power supply output voltage Vr. This adjusted power supply output voltage Vr is input to a comparator 5 having a voltage Vd applied from a temperature-dependent power supply 7 as a reference, and the voltage is compared for each generated trimming code TRMC. In FIG. 7, the regulated power supply output voltage Vr is input to the inverting input terminal, and the target voltage is input to the non-inverting input terminal. Therefore, at the intersection where the levels of both voltages are switched, the comparison result CR by comparing the voltages is “L”. To “H”. The comparison result CR is returned to the above-described trimming code generation / storage circuit 2, and the trimming code generation / storage circuit 2 receives "H" switching and records the trimming code TRMC1 at that time. Since the trimming code TRMC1 recorded in this way is volatile, the trimming code TRMC1 can be taken out in the test mode 2 to be recorded in a fuse element or the like which is a nonvolatile memory circuit. The extracted result is used for fuse trimming of the trimming code storage circuit 3. If the test mode 3 is used while changing the temperature after trimming the fuse of the trimming code storage circuit 3, it is possible to determine whether the current junction temperature is higher or lower than the junction temperature when the trimming code is stored. That is, the comparison result CR of the comparator 5 is a signal indicating that the output voltage Vr of the regulated power supply 1b has a value corresponding to the voltage Vd that is the control target voltage. The comparison result CR can be output to the outside via the switch circuit 64 and the terminal 65.

  Next, FIG. 8 shows a modification of the embodiment shown in FIG. A semiconductor device 100d shown in FIG. 8 includes a regulated power supply 1b and a power supply control unit 10d. In FIG. 8, the same components as those in FIG. 3 or FIG. The difference from FIG. 7 is that the trimming code TRMC1 recorded by the trimming generation / storage circuit 2 in the power supply control unit 10d is input to the trimming code storage circuit 3a in the test mode 2. When the trimming code storage circuit 3a is electrically programmable like an electric fuse or EEPROM, fuse trimming can be performed by itself using the trimming code TRMC1. When laser fuse trimming is used, the temperature recording process is limited to a wafer process or the like so that laser fuse cutting is possible. However, if electrical programming is possible, recording can be performed even after packaging.

  FIG. 9 is an example of the regulated power supply 1b (power supply without temperature dependence) in FIGS. A voltage Vbg output from a bandgap reference circuit generally known as a power supply 11b that does not depend on temperature is resistance-divided based on the trimming code TRMC in the circuit to be trimmed 12b. Vr can be adjusted. The band gap reference circuit shown as the power supply 11b having no temperature dependence in FIG. 9 amplifies the temperature characteristic of the forward voltage of the PN junction having a negative temperature gradient and the temperature characteristic of the thermal voltage having a positive temperature gradient. This is a power supply circuit that is canceled out by the above-described circuit, and is a well-known circuit. 9 includes a plurality of resistors 121 connected in series and a plurality of switch circuits 122 for extracting each connection point. Each switch circuit 122 is ON / OFF controlled by a trimming code TRMC.

  FIG. 10 shows an example of the temperature-dependent power supply 7 shown in FIGS. The diode 72 is biased by the constant current source 71, and a negative temperature dependent voltage Vd is obtained.

  In the above embodiment, the voltage Vr that does not depend on the temperature is used as the voltage that is compared with the voltage Vd that depends on the temperature. However, the voltage that is not dependent on the temperature is not necessarily limited. However, any voltage having a temperature gradient different from the voltage Vd may be used. In addition, the output voltage Vr of the regulated power supply 1b is set as a voltage that does not depend on temperature (that is, a voltage within a predetermined range in which the gradient of the temperature gradient is predetermined), and is trimmed and adjusted. This may be trimmed as a temperature-dependent voltage.

  As described above, according to the embodiment described with reference to FIG. 7 and FIG. 8, a voltage having temperature dependence is used as temperature information, and this is used as trimming information of a voltage having a different temperature dependence, for example, a voltage having no temperature dependence. By comparing the voltage with temperature dependence and the trimmed voltage, it is possible to detect later whether the current junction temperature is higher or lower than the temperature indicated by the trimming information. Therefore, a characteristic test or the like can be performed by easily reproducing the temperature at the time of trimming.

  Next, referring to the block diagram of FIG. 11, the control for supplying the test mode signal TM1, the test mode signal TM2, and the test mode signal TM3 in the configuration shown in FIG. 2, FIG. 3, FIG. 7, and FIG. The circuit 8 will be described. The control circuit 8 shown in FIG. 11 includes n first stage input circuits 81 for inputting an n-bit external address ADD and n latch circuits 82 for taking in the external address ADD. The control circuit 8 includes a first-stage input circuit 83 for inputting an external input clock CK that designates an external address ADD and an external input command CMD fetch timing. Further, the control circuit 8 includes m first-stage input circuits 84 for inputting an m-bit external input command CMD, a TMRS (test mode register set) command decoder 85 for decoding the external input command CMD, and a TRMS command decoder. A timing adjustment delay line 86 for delaying 85 output signals and a test mode decoder 87 are provided, and they are combined.

  In the above configuration, the output of the input circuit 83 is used as an input clock signal for the n latch circuits 82 and also becomes an input clock signal for the TRMS command decoder 85. Further, the n-bit output of the n latch circuits 82 becomes the n-bit TMRS internal address A and is input to the test mode decoder 87. The external input command CMD is a signal abstracted from an externally input RAS (Row Address Strobe) signal, CAS (Column Address Strobe) signal, etc., and accesses the test mode decoder 87 as the external input command CMD. A command (TMRS command) to be used is set in advance. When the TRMS command decoder 85 detects a command (TMRS command) for accessing the preset test mode decoder 87, it generates a predetermined clock signal to be supplied to the test mode decoder 87 for a predetermined time. This clock signal is delayed for a predetermined time by the timing adjustment delay line 86 and is used as a TRMS command clock pulse CLK which is a clock (or a one-shot flag of the TRMS command) that is stopped except for the TRMS input cycle to the test mode decoder 87. Input to the clock input of the decoder 87.

  The test mode decoder 87 takes in the TRMS internal address A in synchronization with the TRMS command clock pulse CLK, and decodes the TRMS internal address A to obtain the test mode 1 signal TM1, the test mode signal TM2, and the test mode signal TM3. Generate and output. That is, the control circuit 8 shown in FIG. 11 synchronizes with the external input clock CK, the external input command CMD input from the external command terminal 88, and a predetermined code input as the external input address ADD from the external input address terminal 89. Is decoded by the test mode decoder 87, and one of the signals TM1, TM2 and TM3 for activating a predetermined test mode among the test modes 1, 2, and 3 is output.

  FIG. 12 is a waveform diagram showing an operation until the trimming code TRMC1 is determined by repeating the test mode 1 a predetermined number of times in the control circuit 8 of FIG. The TRMS command is input from the external command terminal 88 and the test mode 1 is selected by the code “a1” input from the external input address terminal 89. When the semiconductor device of FIG. 2 or FIG. 3 is considered, the command “TRMS” and the address “a1” are repeatedly input until the adjusted power supply output voltage Va matches the target voltage Vt (time t1, t2). . On the other hand, in the semiconductor device of FIG. 7 or FIG. 8, the command “TRMS” and the address “a1” are repeatedly input until the regulated voltage Vr matches the target voltage Vd (time t1, t2).

  Next, when the semiconductor device of FIG. 2 or FIG. 3 is considered, after the adjusted power supply output voltage Va coincides with the target voltage Vt (transition of Va and Vt comparison result signal CR is confirmed using the pad 68 or the like). At (time tk), the code input from the external input address terminal 89 is set to “a2”, and the test mode 2 is selected (time tk + 1). Here, trimming information (trimming code TRMC1) is obtained from the terminal 63, and the trimming information is recorded in the trimming code storage circuit 3. On the other hand, when the semiconductor device of FIG. 7 or FIG. 8 is considered, after the regulated power supply output voltage Vr matches the target voltage Vd (time tk), the code input from the external input address terminal 89 is set to “a2”. Then, test mode 2 is selected (time tk + 1). Here, trimming information (trimming code TRMC1) is obtained from the terminal 63, and the trimming information is recorded in the trimming code storage circuit 3. Even when the terminal for confirmation such as the pad 68 is not waited, the command “TRMS” and the address “a1” may be repeatedly input for the total number of trimming codes (2 to the power of n). Even after TM1 continues to be input, the counter 21 continues to be stopped by the gate 23 after the comparison coincidence, so that the optimum trimming code held at any time continues to be held. This may be acquired later using test mode 2.

  On the other hand, FIG. 13 is a waveform diagram showing an operation when the trimming result is checked using the test mode 3 in the control circuit 8 of FIG. By inputting the TRMS command from the external command terminal 88 and inputting the code “a3” from the external input address terminal 89, selecting the test mode 3, and repeating this input (time t1, t2,..., Tk , Tk + 1), the comparison result CR of the comparator 5 can be detected at the terminal 65.

  In the embodiment in which the comparator 5 described with reference to FIGS. 2 and 3 compares the regulated power supply output voltage Va and the target voltage Vt, a voltage that gradually increases as the target voltage Vt is input from the terminal 67. When the adjusted regulated power supply output voltage Va inside the semiconductor device indicated by a chain line is exceeded (in FIG. 13, immediately after time tk + 1), the comparison result CR changes from “L” to “H”. Here, when the switch circuit 64 is turned on by the test mode 3 signal TM3, a pulse signal is generated at the terminal 65 (immediately after the time tk + 1). By detecting the pulse signal at the terminal 65, it is possible to confirm that the regulated power supply output voltage Va is substantially the same value as the input voltage Vt.

  On the other hand, in the embodiment in which the comparator 5 described with reference to FIGS. 7 and 8 compares the regulated power supply output voltage Vr (voltage not dependent on temperature) and the output voltage Vd (temperature dependent voltage), the object to be measured By changing the ambient temperature of this semiconductor device, the internal power supply voltage Vd (temperature dependent voltage) is gradually increased. When the power supply voltage Vd exceeds the adjusted regulated power supply output voltage Vr inside the semiconductor device indicated by the chain line (immediately after time tk + 1 in FIG. 13), the comparison result CR changes from “L” to “H”. . Here, when the switch circuit 64 is turned on by the test mode 3 signal TM3, a pulse signal is generated at the terminal 65 (immediately after the time tk + 1). By detecting the pulse signal at the terminal 65, the junction temperature Tj of the power supply 7 having temperature dependence at this time is substantially the same value as the junction temperature Tj0 of the power supply 7 having temperature dependence at the time of trimming adjustment. Can be confirmed.

  As described above, the control circuit 8 of FIG. 11 is provided in the semiconductor device, so that the voltage change of the terminal 65 is monitored by using the external input / output terminal or the like after the chip constituting the semiconductor device is packaged, for example. By doing so, it is possible to detect the output voltage Va of the adjusted power supply circuit 1 subjected to trimming adjustment or to detect the junction temperature during trimming.

According to the present invention, the power control units 10a, 10b, 10c, and 10d are generated while changing a control signal (for example, a trimming code) for adjusting the output voltage of the power source unit 1 or 1b to be adjusted. Based on this, the output voltage of the adjusted power supply unit can be set (for example, power supply trimming based on a trimming code). The power supply control units 10a, 10b, 10c, and 10d store a control signal when the value corresponds to the control target voltage, and set the output voltage of the adjusted power supply unit based on the stored control signal. According to this, since the control signal can be automatically changed and set to a value corresponding to the semiconductor device, it is possible to easily set the control signal in consideration of an error due to variations in the manufacturing process.
Further, the regulated power supply units 1 and 1b have the trimming circuit 12 or 12b whose operation state is set according to the input control signal, the reference voltage and the operation state set in the trimming circuit, The output voltage is changed according to the output. According to this configuration, since adjustment by trimming can be performed without adjusting the reference voltage, the output voltage can be changed with a simple configuration.

The power supply control units 10a, 10b, 10c, and 10d are generated while the trimming code generation / storage circuit 2 changes the control signal. The comparator 5 compares the output voltage Va of the adjusted power supply unit 1 with the control target voltage. The trimming code storage circuit 3 stores the control signal (trimming code TRMC) when the comparison result of the comparator 5 changes. The selector 4 inputs either the control signal (trimming code TRMC1) output from the trimming code generation / storage circuit 2 or the control signal (TRMC2) stored in the trimming code storage circuit 3 to the trimmed circuit 12 or 12b. To do. According to this configuration, by controlling each unit based on the binary output signal of the comparator 5, the configuration of each unit can be easily simplified.
The trimming code storage circuit 3 stores a control signal (trimming code TRMC) output from the trimming code generation / storage circuit 2. According to this configuration, the control signal can be stored in the trimming code generation / storage circuit 2 without supplying a signal for trimming from the outside.

The trimming code generation / storage circuit 2 includes a counter circuit 21 that counts an input clock signal and a decoder 22 that outputs a control signal (trimming code TRMC) based on the count value of the counter circuit 21. The trimming code generating / storing circuit 2 generates the control signal (trimming code TRMC) while changing it, holds the count value when the comparison result of the comparator 5 changes, and generates a control signal (comparison result CR) based thereon. Output. According to this configuration, for example, the count value can be easily held in the counter by stopping the count operation, and the control signal output in terms of timing can be used by outputting the held control signal. Can be easier.
In addition, a control target voltage is input from the outside to the semiconductor devices 100a and 100b. According to this configuration, the accuracy and stability of the control target voltage can be easily increased, and the accuracy and stability of the trimming result of the output voltage of the adjusted power supply unit can be improved.

Further, the output voltage of the regulated power supply unit 1 is a voltage having a first temperature gradient generated using an element inside the semiconductor device, and the control target voltage Vt uses an element inside the semiconductor device 100c or 100d. And a voltage having a second temperature gradient different from the first temperature gradient generated. According to this configuration, since the control signal when the voltage having the first temperature gradient becomes a value corresponding to the voltage having the second temperature gradient is stored, the junction temperature inside the semiconductor device at the time of storage, etc. Can be stored as the value of the control signal.
In addition, the semiconductor device 100c or 100d is within a predetermined range in which one of the first and second temperature gradients is predetermined. According to this configuration, the range in which the voltages having the first and second temperature gradients have values corresponding to each other can be limited to some extent, and trimming accuracy and the like can be easily improved.
The adjusted power supply unit 1 includes a trimmed circuit 12 or 12b whose operation state is set according to an input control signal (trimming code TRMC), and a voltage having a first temperature gradient and the trimmed circuit The output voltage is changed according to the operation state set to 12 or 12b and output. According to this configuration, since adjustment by trimming can be performed without adjusting the voltage having the first temperature gradient, the output voltage can be changed with a simple configuration.

The control target voltage is a voltage generated using a circuit in which a constant current source 71 composed of elements inside the semiconductor devices 100c and 100d and a diode 72 are connected in series.
In addition, the output voltage of the regulated power supply unit 1b is a voltage generated using a band gap reference circuit composed of elements inside the semiconductor devices 100c and 100d. According to this configuration, a voltage having a temperature gradient can be realized with a simple configuration.
Further, when the output voltage of the adjusted power supply unit 1b becomes a value corresponding to the control target voltage, a signal indicating the output is output. According to this configuration, when each voltage reaches a corresponding value, it is output. Therefore, even after packaging the semiconductor device, for example, the temperature condition such as the junction temperature at the time of storing the control signal (trimming) is reproduced. can do.

  Note that the semiconductor devices described in the present invention correspond to the semiconductor devices 100a, 100b, 100c, and 100d, and 100e and 100f. The power supply control unit described in the present invention corresponds to the power supply control units 10a, 10b, 10c, and 10d, and 10e and 10f. The regulated power supply unit described in the present invention corresponds to the regulated power supply units 1 and 1b and 213. The circuit to be trimmed according to the present invention corresponds to the circuit to be trimmed 12 or 12b or 215 or 215a. The control signal generation circuit according to the present invention corresponds to the trimming code generation / storage circuit 2 and 211, 211a, 211b, and 211c. The comparison circuit described in the present invention corresponds to the comparator 5 and the comparison circuit 216. The nonvolatile memory circuit described in the present invention corresponds to the trimming code storage circuit 3 and the trimming code nonvolatile memory circuit 217. The selection circuit described in the present invention corresponds to the selector 4 and the selector 212. The counter circuit described in the present invention corresponds to the counter 21. The control signal output circuit described in the present invention corresponds to the decoder 22.

  Next, still another embodiment of the present invention will be described with reference to FIGS. In the following, first, the background art of another embodiment will be described again, and then another embodiment will be described in detail.

[Background technology]
Trimming of the internal power supply potential is performed using a fuse. In the wafer inspection process when trimming is performed only with fuses, first, through a fuse blow process for determining an internal power supply potential, a desired internal power supply potential is obtained, and then a defective bit to be redundantly repaired is inspected. Then, based on the result, a redundant relief fuse blow step is performed. That is, two fuse blow processes are performed. In the wafer inspection process, the fuse blow process is an extremely time-consuming process. Therefore, the control circuit built in the chip achieves the same effect as fuse trimming, and when inspecting a defective bit to be redundantly repaired, the control circuit is used without performing the fuse blow process for determining the internal power supply potential. There is one in which an inspection is performed with a desired internal power supply potential. In this way, the fuse blow process for determining the internal power supply potential is incorporated into the redundant relief fuse blow process, and the fuse blow process is completed once. A technique for realizing the same effect as fuse trimming by the control circuit is pseudo trimming. The details are as described in Patent Document 1.

  In pseudo-trimming, first, the internal power supply potential is measured with a tester, separately compared with the target potential determined by the measurer, the trimming code used for pseudo-trimming is calculated by calculation, and the trimming code is measured from the tester by the test program. Done by giving to the device. However, the internal power supply potential measured by the tester is likely to pick up noise from an external measurement system because the tester jig probe and wiring are interposed. For this reason, in order to compensate for the measurement accuracy, a method of calculating the average value by repeatedly performing many measurements is often used. In addition, voltage value monitoring time on the tester side and determination time for comparing values are also required, and overall, the pseudo trimming time is never short. This is a problem caused by the fact that there is a comparison circuit in the tester that compares the values. Therefore, in order to solve this problem, a comparison circuit is built in the chip, the target potential is statically input to the input terminal of the chip, and the result of comparing the internal power supply potential by pseudo trimming with the target value is output to the outside Thus, Patent Document 3 proposes a method of measuring only the result with a tester. According to this, noise from an external measurement system is not picked up, and it is not necessary to perform measurement many times with a tester. However, the trimming codes having the same comparison result should be different for each chip existing in the wafer, and it takes time to calculate the trimming code for each chip from the test result for each chip by the tester.

  In the pseudo trimming, the optimum trimming code is searched out from an unknown state, so a search algorithm needs to be considered. In the simplest search of all trimming codes, so-called linear search, the data to be verified is all kinds of trimming codes, and it is obvious that the time for calculating the optimum trimming code from the test result increases. When using a high-speed and complicated search algorithm, such as an algorithm such as binary search, there are many results depending on the monitoring result while monitoring the comparison result of each chip with each chip for each test for each trimming code. It is necessary to select and search a test program of an appropriate trimming code for each chip. Even if this can be realized, it is obvious that the time required to calculate the optimum trimming code becomes longer when the test is carried out while making judgments one by one.

  In order to cope with this, as in the above-described embodiment of the present invention described with reference to FIGS. 1 to 13, the comparison result from the comparison circuit is fed back inside the chip, and the optimum trimming code is held in each chip. You just have to do it. In this case, the determined optimum trimming code only needs to be read by the tester after the test is completed, and the tester need not calculate. As a structure, the semiconductor device 100e shown in FIG. 14 corresponding to the embodiment of the present invention shown in FIG. 2 can be considered. In the semiconductor device 100e of FIG. 14, reference numeral 211 denotes a trimming code generation / storage circuit. When a clock signal is input in the test mode 1, a trimming code is generated each time. The trimming code passes through the selector 212 and enters the adjusted power supply 213, and the adjusted power supply 213 outputs the adjusted potential Va corresponding to the trimming code. The adjusted potential Va enters the comparison circuit 216 to which the target potential Vt is separately supplied from the outside, and as a result, the comparison circuit 216 outputs the comparison result. The comparison result enters the trimming code generation / storage circuit 211. In this way, the regulated power supply 213 and the power supply control unit 10e in FIG. 14 have a closed loop configuration. If the trimming code is determined to be the optimum trimming code based on the comparison result, the trimming code generating / storing circuit 211 holds the trimming code and can read the optimum trimming code again in the test mode 2.

  In FIG. 14, the adjusted power source 213 includes a potential adjusting circuit 214 and a trimmed circuit 215 for adjusting the potential. The power control unit 10e includes a trimming code generation / storage circuit 211, a selector 212, a comparison circuit 216, a trimming code nonvolatile storage circuit 217, and the like. The comparison result output of the comparison circuit 216 represents “Va> Vt” at the “Low” level and “Va <Vt” at the “High” level. The trimming code output from the trimming code generation / storage circuit 211 is input to one input (“0” input) of the selector 212, and the trimming code nonvolatile storage circuit 217 is input to the other input (“1” input). The output trimming code is input. A selection signal output from the trimming code nonvolatile memory circuit 217 is input to the selection input of the selector 212. This selection signal becomes “1” when the nonvolatile memory circuit is used, and becomes “0” when the nonvolatile memory circuit is not used. The selector 212 selects the input “1” and the input “0”. However, the output of the selector 212 is set so as to select and output the input “0”, that is, the trimming code output from the trimming code generation / storage circuit 211 when searching for the trimming code.

  As a method of easily searching for the optimal trimming code and holding the comparison result with this configuration, a method using a linear search can be considered. At that time, the trimming code generating / storing circuit 211 takes the form shown in FIG. The counter 221 is moved by a clock-like signal in the test mode 1, but the clock that enters the counter 221 is stopped by the logic gate 223 when the comparison result is OK (that is, “High” level). That is, the decoder 222 in FIG. 15 and the adjusted power source 213 in FIG. 14 are configured so that the adjusted potential Va in FIG. 14 gradually changes as the counter 221 counts up. For example, the decoder 222 of FIG. 15 is configured as shown in FIG. 16, and the regulated power supply 213 of FIG. 14 is configured as shown in FIG. These are diagrams in the case of n = 4.

In the trimming code generating / storing circuit 211 of FIG. 15, the logic gate 223 is a two-input AND circuit in which one is a negative logic input, and the comparison result that is the output of the comparison circuit 216 in FIG. The other input is a test mode 1 clock-like signal. The counter 221 is an n-bit counter (n is a natural number), counts a clock-like signal output from the logic gate 223, and counts each bit as a counter bit c0, c1,..., C (n−1). (However, the following is not limited to the counter output,
A signal input to the decoder 222 or the like will be referred to as counter bits c0, c1,..., C (n−1)). The decoder 222 inputs n signals representing the n-bit binary number output from the counter 221, expands the signal to 2 n (= 2 ^ n) signals, and decodes signals u 0, u 1,. u (2 ^ n-1) is output. In the decoded signals u0, u1,..., U (2 ^ n-1), one of the signals corresponding to the counter bits c0, c1,. The signal group is “0”. For example, when the counter bits c0, c1,..., C (n−1) represent “0”, the decode signal u0 is “1” and the other decode signals u1,. When the counter bits c0, c1,..., C (n−1) represent “1”, the decode signal u1 is “1” and the other decode signals u0, u2,. -1) becomes "0".

  The decoder 222 shown in FIG. 16 includes 16 4-input AND circuits 300 to 315 that receive the counter bits c0 to c3. The outputs of the 4-input AND circuits 300, 301,. Signals u0, u2,..., U15. The decode signals u0, u2,..., U15 are signals corresponding to the trimming code in FIG. However, in the 4-input AND circuits 300 to 315, 0 to 4 of the 4 inputs are negative logic inputs so as to correspond to the output signals. For example, in the AND circuit 300, when all four inputs are negative logic inputs and the counter bits c0 to c3 are all “0”, the output is “1”.

  In the adjusted power supply 213 in FIG. 17, the potential adjustment circuit 214 is composed of an operational amplifier circuit 41 and a P-channel MOS transistor 42. The adjusted potential Va is output from the drain of the transistor 42. Further, a predetermined reference potential Vref is input to the non-inverting input of the operational amplifier circuit 41, and a potential obtained by dividing the potential to be adjusted Va by the trimming circuit 215 at a predetermined ratio is input to the inverting input. The trimming circuit 215 includes a resistor RA, 15 resistors R, and a resistor RB that are connected in series. One terminal not connected to the resistor R of the resistor RA is the adjusted potential Va, and one terminal not connected to the resistor R of the resistor RB is the ground potential. Further, the resistor RA, the resistor RB, and the resistor R are resistance elements having a resistance value RA, a resistance value RB, and a resistance value R, respectively. The trimming circuit 215 further includes 16 switches 400 to 415 for selecting any one of the nodes of the resistors RA, R, and RB. These switches 400 to 415 are on / off controlled (turned on at “1”) by trimming codes u0 to u15 output from the selector 212 of FIG. According to such a configuration, the adjusted potential Va can be changed by changing the switch that is turned on among the switches 400 to 415 by the trimming code.

  According to the above configuration, the regulated potential Va output from the regulated power supply 213 changes as the counter 221 counts up. Then, the comparison result, which is the output of the comparison circuit 216, is switched when the target potential Vt and the adjusted potential Va are substantially equal. That is, the trimming code when the counter 221 counts up and the comparison result is switched is the optimum code, and the clock entering the counter 221 is stopped by the logic gate 223 in FIG. Thereafter, even if the clock signal in the test mode 1 continues to be generated, the trimming code is stopped and the optimum trimming code is retained. With this mechanism, even when a test pattern for pseudo-trimming is performed by the tester in a batch on the wafer, the trimming is stopped for the chip that has been trimmed and the optimum code is retained, and the chip that has not been trimmed is optimal. You can continue trimming until you find the code. However, the search algorithm used here is a linear search.

  A state of the search by the linear search is shown in FIG. FIG. 18 is a diagram for the case of 4 bits, that is, 16 trimming codes. In FIG. 18, the vertical axis represents the potential to be adjusted Va or the target potential Vt, and the horizontal axis represents times t0, t1,..., T15 at which the clock-like signal input in the test mode 1 changes by one pulse. It's time. In the linear search, the adjusted power supply Va is scanned in increments of resolution ΔV to search for an intersection with the target potential Vt. In FIG. 18, the intersection is detected at time t11, but considering worst, it is necessary to scan until time t15. That is, 16 scans are required for 4 bits, 32 scans for 5 bits, and 1024 scans for 10 bits. The search is for O (2 ^ n) as an order ("O" represents O-notation), and it becomes difficult to cope with trimming with high resolution or a wide adjustment range. On the other hand, a binary search of order O (n) is well known as the fastest random search algorithm. In this case, 4 scans are required for 4 bits, 5 scans for 5 bits, and 10 scans for 10 bits.

  As described above, improvements are being studied for trimming and pseudo-trimming, but on-chip pseudo-trimming by binary search is desired. Hereinafter, another embodiment of the present invention will be described in detail.

[Description of Other Embodiments and Effects of Present Invention 1]

  First, with reference to FIG. 19, a binary search characteristic of this embodiment will be considered. FIG. 19 is a diagram for the case of having 4 bits, that is, 16 trimming codes. In FIG. 19, the vertical axis represents the potential to be adjusted Va or the target potential Vt, and the horizontal axis represents time t0, t1,..., T4 when the clock-like signal input in the test mode 1 changes. . Note that the count-up direction and the potential direction are reversed for convenience. The time t0 is in the initial state, that is, the regulated power supply Va is at the position of the counter {c3, c2, c1, c0} = “0000” which is the input value of the decoder 222. However, in the following, it is assumed that four (or a plurality of 5 or more) numbers of 0 or 1 surrounded by “” represent a binary number of 4 bits (or 5 or more bits). Here, when the adjusted potential Va and the target potential Vt are compared, since Va> Vt, the most significant bit c3 is counted up, and Va reaches the position of “1000” at time t1. Then, since Va> Vt, it counts up with respect to the next lower bit c2, and Va reaches the position of “1100” at time t2. Then, since Va <Vt, it counts down with respect to the next lower bit c1, and Va reaches the position of “1010” at time t3. Then, since Va> Vt, the least significant bit c0 is counted up, and Va comes to the position “1011” at time t4. Thus, the trimming with the resolution ΔV is completed. The search ends with four searches for the 4-bit adjustment range, and is certainly a search for O (n). Here, when looking at the adjustment value at the time of the search, the first time has moved from “0000” to “1000”, + “1000” adjustment (−8ΔV), and the second time has moved from “1000” to “1100”. + “0100” adjustment (−4ΔV), the third time is moved from “1100” to “1010”, − “0010” adjustment (+ 2ΔV), the fourth time is moved from “1010” to “1011” Cage + “0001” adjustment (−ΔV). That is, the value to be added or subtracted is generated and held by bit shift such as “1000”, “0100”, “0010”, “0001” for each search, and is added to or subtracted from the current counter value. Such a circuit may be determined from the comparison result.

  Considering this, the trimming code generation / storage circuit 211 of FIG. 14 may be changed as shown in FIG. 20 (however, the configuration corresponding to the trimming code generation / storage circuit 211 of FIG. It is shown as a generation / storage circuit 211a). In FIG. 20, reference numeral 221a is a binary search circuit, and reference numeral 222 is a decoder similar to that in FIG. Reference numeral 31 denotes a bit shifter, in which the most significant bit is set to “1” as the initial value, the others are set to “0”, and “1” is shifted to the right (lower direction) by the clock signal in the test mode 1. Also, “0” is entered in the vacant bit. Reference numeral 32 denotes an adder / subtracter, which performs addition when the comparison result corresponding to the current counter value held by the latch circuit indicated by reference numeral 33 is “Low”, and subtracts when the comparison result is “High”. That is, the adjustment value held in the bit shifter 31 is added to or subtracted from the current counter value held in the latch circuit 33 according to the comparison result. The output values of the bit shifter 31 and the latch circuit 33 are updated by the clock-like signal in the test mode 1, and the trimming operation stage advances accordingly.

  FIG. 21 shows FIG. 20 more specifically. The case of 4 bits is taken as an example. The bit shifter 31 includes a DQ flip-flop 321 with a set terminal and DQ flip-flops 331 to 333 with a reset terminal. The DQ flip-flop 321 with a set terminal is arranged at a position corresponding to the most significant bit c3 of the counter, and the DQ flip-flops 331 to 333 with a reset terminal are arranged in addition to the initial value “1000” in the test mode 0. Can be set. The shift operation is performed in synchronization with the clock-like signal in the test mode 1, but the input of the highest-order DQ flip-flop 321 is grounded, and “0” is set in the empty bit. The adder / subtractor 32 is configured based on a 4-bit full adder in which four 1-bit full adders 351 to 354 are connected. The 1-bit full adders 351 to 354 may be general full adders as shown in FIG.

  What is considered now is internal power supply potential trimming, and it is not necessary to increase the speed in the order of ns (nanoseconds), and it may be simple. Of course, when the number of bits of the addition number increases and the carry propagation time can no longer be ignored, a CLA (Carry Look Ahead) circuit, a BCLA (Block Carry Look Ahead) circuit, and a CSA (Carry Save Adder) are combined. A high-speed adder may be used. These high-speed computing units are as described in Non-Patent Document 1, for example. The 4-bit full adder configured as described above inputs the current counter value taken out from the latch circuit 33 to one terminal A, and inputs the outputs of the selectors 341 to 344 to the other terminal B. The selectors 341 to 344 exist for adding 2's complement as subtraction. In other words, the selectors 341 to 344 are exclusive ORs. When the comparison result is “High”, the adder / subtracter 32 performs subtraction. At this time, the selectors 341 to 344 select the inverted signal on the “1” side, and the carry Ci−1 of the full adder 354 of the least significant bit. Since the comparison result is input to “0001”, “0001” is also added, and two's complement addition, that is, subtraction is performed. The latch circuit 33 includes DQ flip-flops 361 to 364 with a reset terminal, and an initial value “0000” can be set in the test mode 0.

  In FIG. 21, the latch circuit 33 uses the clock rise edge as a trigger, whereas the bit shifter 31 uses the clock fall edge as a trigger unlike the case shown in FIG. This is based on the assumption that the data transfer operation is difficult such as being away. The bit shifter 31 and the latch circuit 33 are connected to each other as a master / slave operation to ensure data transfer. This will be described later. Of course, when there is no such concern, there is no problem in synchronizing with the same clock edge as shown in FIG. However, in this case, it is necessary to change the set / reset timing of the DQ flip-flop in the bit shifter 31 according to the circuit configuration.

  In FIG. 21, the input D of the DQ flip-flop 321 is grounded, the output Q is connected to the input D of the DQ flip-flop 331, and the “0” input (input signal r3) of the positive logic input of the selector 341 is used. ) And a negative logic input “1” (in this case, a signal obtained by inverting the signal r3 becomes a selected signal). A test mode 0 signal is input to the set terminal S of the DQ flip-flop 321 and a test mode 1 signal is input to the clock terminal. The output Q of the DQ flip-flop 331 is connected to the input D of the DQ flip-flop 332, and the positive logic input “0” (input signal r2) of the selector 342 and the negative logic input “1” (this) In this case, a signal obtained by inverting the signal r2 becomes a selected signal). The test mode 0 signal is input to the reset terminal R of the DQ flip-flop 331, and the test mode 1 signal is input to the clock terminal. The output Q of the DQ flip-flop 332 is connected to the input D of the DQ flip-flop 333, and the positive logic input “0” (input signal r 1) and the negative logic input “1” input (this is input) In this case, a signal obtained by inverting the signal r1 becomes a selected signal). A test mode 0 signal is input to the reset terminal R of the DQ flip-flop 332, and a test mode 1 signal is input to the clock terminal. The output Q of the DQ flip-flop 333 is a “0” input (input signal r0) of the positive logic input of the selector 344 and a “1” input of the negative logic input (in this case, a signal obtained by inverting the signal r0 is the selected signal). Connected). The test mode 0 signal is input to the reset terminal R of the DQ flip-flop 333, and the test mode 1 signal is input to the clock terminal.

  Further, in FIG. 21, the outputs of the selectors 341 to 344 are connected to the inputs B of the full adders 351 to 354, respectively. The selectors 341 to 344 receive the comparison result (the output of the comparison circuit 216 in FIG. 14) as a selection signal. The Q outputs of the DQ flip-flops 361 to 364 are input to the inputs A of the full adders 351 to 354, respectively. Outputs S of full adders 351 to 354 are respectively input to D inputs of DQ flip-flops 361 to 364 (each signal is shown as signals S3 to S0). The carry signal output Ci of the full adder 352 is input to the carry signal input Ci-1 of the full adder 351. The carry signal output Ci of the full adder 353 is input to the carry signal input Ci-1 of the full adder 352. The carry signal output Ci of the full adder 354 is input to the carry signal input Ci-1 of the full adder 353. The carry signal input Ci-1 of the full adder 354 receives the comparison result signal. The test mode 0 signal is input to the reset terminals of the DQ flip-flops 361 to 364, and the test mode 1 signal is input to the clock terminal. The Q outputs of the DQ flip-flops 361 to 364 become counter bits C 3 to C 0 that are input signals to the decoder 222.

  FIG. 22 is a circuit diagram (a) showing a configuration example of the 1-bit full adders 351 to 354 of FIG. 21 and a truth table (b) thereof. In this example, the 1-bit full adders 351 to 354 include two exclusive OR circuits 371 and 372 and three non-logical output logical product circuits (NAND circuits) 373 to 375. The two inputs A and B are input to the exclusive OR circuit 371 and the NAND circuit 374, respectively, and the carry signal Ci-1 from the lower order is input to the exclusive OR circuit 372 and the NAND circuit 373. The output of the exclusive OR circuit 371 is input to the exclusive OR circuit 372 and the NAND circuit 373, and the output of the NAND circuit 373 and the output of the NAND circuit 374 are input to the NAND circuit 375. Then, the output of the exclusive OR circuit 372 becomes the output S indicating the calculation result of the bit, and the NAND circuit 375 becomes the output Ci indicating the carry.

  As described above, various pseudo trimming related operations are performed by starting the test mode from an external input. FIG. 23 shows a circuit for starting the test mode from the outside. When an external input command CMD and an external input address ADD are input while maintaining a predetermined setup / hold with respect to the rising edge of the external input clock CK, each input signal passes through the first stage circuits 51, 56 and 57, and the clock CK is The command CMD is input to the TMRS command decoder 52 and the address ADD is input to the external address acquisition circuit 53, both to the external address acquisition circuit 53 and the TMRS command decoder 52. In the external address fetch circuit 53, the address ADD is fetched in synchronization with the clock CK and output as the TMRS internal address TA. The TMRS command decoder 52 decodes the command CMD in synchronization with the clock CK, and outputs a one-shot pulse when the result is “TMRS”. Further, the one-shot pulse (TCLK) passes through the timing adjustment delay line 54, the phase is delayed with respect to the TMRS internal address TA, and is used as a clock for the test mode decoder 55 to capture the TMRS internal address TA. . The test mode decoder 55 determines the test mode 0 when the TMRS internal address TA = “a0”, the test mode 1 when the TMRS internal address TA = “a1”,. The test mode flag (test mode 0 to 3 signals) is output as a one-shot pulse. As described above, test modes 0, 1, 2, and 3 are activated.

  A pseudo trimming operation in test mode 1 and a trimming code output operation in test mode 2 will be described with reference to FIG. From here on, {c3, c2, c1, c0} etc. are abbreviated as {c} etc. First, at time t2, the test mode command “TMRS” is input together with the address “a0” in order to set the bit shifter 31 of FIG. 21 and the flip-flops 361 to 364 of the latch circuit 33 to initial values. Then, TCLK of the TMRS pulse is generated, and the test mode decoder 55 of FIG. 23 takes in the internal address TA and generates a test mode 0 pulse. This is the trigger for test mode 0. Accordingly, the bit shifter 31 in FIG. 21 is set to {r} = “1000”, and the latch circuit 33 in FIG. 21 is set to {c} = “0000”. As a result, the value of the bit shifter 31 becomes “1000” to be added first, the trimming code is set to the initial state “u0” (that is, only u0 is “1”, and so on), and the adjusted potential Va is the initial value. Vmax, the comparison result is “Low”, and the adder / subtractor 32 of FIG. 21 adds {r} and {c}, sets the previous stage {s} of the latch circuit 33 of FIG. 21 to “1000”, and performs a binary search. Is ready. Then, pseudo trimming in test mode 1 is started from time t4.

  When the address “a1” is input together with the TMRS command at time t4, the test mode 1 pulse is output as in the case of the test mode 0, and the latch circuit 33 in FIG. 21 takes in “1000” of the previous stage {s}, { c} is set to “1000” and the output is held. As a result, the trimming code changes to “u8”, and the adjusted potential Va drops by eight steps. At this time, the comparison result is not changed from the initial state, and the bit shifter 31 in FIG. 21 is not switched because of clock fall edge synchronization. The adder / subtractor 32 in FIG. “0000” which is addition of “1000” of c} is output to {s}. Slightly, the comparison result is changed in response to the eight-step decrease in the adjusted potential Va. However, in FIG. 24, Va is still higher than the target potential Vt, so the comparison result does not change.

  When Va becomes lower than the target potential Vt at time t5, the adder / subtractor 32 in FIG. 21 performs subtraction, and the output {s} is changed again. However, the value of {s} so far is invalid data and is not taken into the latch circuit 33 of FIG. Subsequently, although the test mode 1 pulse falls, the bit shifter 31 in FIG. 21 updates the value, and {r} becomes “0100”. 21 is added to the current counter value {c} by the comparison result “Low” in the adder / subtractor 32 of FIG. 21, and {s} is the valid data “L” to be fetched by the latch circuit 33 of FIG. 1100 ". Here, the reason why {r} is held so far is that when the latch circuit 33 in FIG. 21 fetches {s}, {r} is reliably held and data is reliably propagated. The closed loop constituted by the adder / subtractor 32 and the latch circuit 33 in FIG. 21 is considered to be arranged at a short distance, and it is considered that there is no problem in data propagation, but the bit shifter 31 may be arranged at a distance. Because there is no. More specifically, assuming that the bit shifter 31 and the latch circuit 33 in FIG. 21 are designed to switch at the same timing, the clocks reaching the latch circuit 33 reach the bit shifter 31 because they are arranged apart from each other. It will be understood that data slipping occurs if it is later than the clock. This is to take measures against such a situation. Of course, if these are arranged close to each other, or if the wiring route of the clock is carefully routed so that it first enters the latch circuit 33 and then enters the bit shifter 31, such consideration is not necessary, and the same clock edge. There is no problem to synchronize. However, it is necessary to change the set / reset timing of the DQ flip-flops 321 and 331 to 333 of the bit shifter 31 according to the circuit configuration. This is one trimming cycle.

  Similarly, if the test mode 1 is repeated at times t5, t6, and t7 so that the bit number of {c} is obtained, the pseudo trimming is completed. Finally, when the address “a2” is input together with the command TMRS at an appropriate time, in the figure, at time t32, the test mode 2 pulse is generated, and the pseudo trimming result code “u11” held by the absence of the test mode 1 pulse is generated. Is output to the trimming code output. This output is output to the outside of the chip from a DQ pad (that is, a data input / output pad in a semiconductor memory device) through a data path or the like. Fuse trimming may be performed based on the trimming code extracted here.

  Incidentally, FIG. 26 shows waveforms when the above-described series of operations is performed by linear search. This also shows the case of 4-bit trimming. It can be seen that the pseudo trimming requires more time than the binary search of FIG.

  FIG. 25 shows a method of confirming the trimming result using the test mode 3. The target potential Vt is input from the outside, the test mode 3 is entered, the comparison result is output (this output passes through the data path, etc., and finally is output from the DQ pad, etc.). It is shown that the internal power supply potential can be specified by scanning while scanning the external input value of Vt. The externally applied potential of the target potential Vt when the comparison coincidence information is obtained becomes the internal power supply potential.

[Explanation 2 of Other Embodiments and Effects of the Present Invention]

  Another consideration will be given to the binary search of FIG. FIG. 19 is a diagram for the case of having 4 bits, that is, 16 trimming codes. Note that the count-up direction and the potential direction are reversed for convenience. The time t0 is in the initial state, that is, the regulated power supply Va is at the position of the counter {c3, c2, c1, c0} = “0000”. At this time, since the adjusted potential Va should be in the counter range “1111” to “0000”, an intermediate value of the counter is calculated so that the adjusted potential Va is in the middle. For this purpose, an upper limit value “10000” obtained by adding “1” to “1111” of the adjustment range and an adjustment range lower limit value “00000” may be added and divided by two. As a result, an intermediate value “01000” is obtained. At this time, when the adjusted potential Va and the target potential Vt are compared, Va> Vt, and the target potential Vt should be in the lower half, that is, the upper half of the counter value “1111” to “1000”. Adding the value “01000” and dividing it by 2 gives the intermediate value “01100”. Similarly, when the adjusted potential Va and the target potential Vt are compared at this time, Va <Vt, and the target potential Vt should be in the upper half, that is, the lower half of the counter value “1011” to “1000”. 01100 ”and the lower limit“ 01000 ”are added and divided by 2, an intermediate value“ 01010 ”is obtained. At this time, when the adjusted potential Va and the target potential Vt are compared, Va> Vt, and the target potential Vt should be in the lower half, that is, the upper half of the counter value “1011” to “1010”. Adding the value “01010” and dividing it by 2 gives the intermediate value “01011”. That is, an arithmetic unit that calculates an intermediate value from an upper limit value and a lower limit value is prepared, and a circuit that replaces the intermediate value of the previous calculation with the upper limit value or the lower limit value may be used depending on the comparison result.

  Considering this, the trimming code generation / storage circuit 211 shown in FIG. 14 may be changed as shown in FIG. 30 (however, the configuration corresponding to the trimming code generation / storage circuit 211 in FIG. 14 is trimmed). This is shown as a code generation / storage circuit 211c). In FIG. 30, reference numeral 221b is a binary search circuit, and reference numeral 222 is a decoder similar to that in FIG. Reference numeral 36 is a latch circuit that holds the upper limit value, and the initial value is “1” only at the highest level, such as “10... 0”, and reference numeral 37 is a latch circuit that holds the lower limit value. "0" like "... 0". Reference numeral 38 denotes an adder / subtracter which operates as an adder because the selection signal for addition / subtraction is grounded. Reference numeral 39 denotes a bit shifter, which is shifted to the right, and is equivalent to a 1/2 operation. The output of the bit shifter 39 is fed back to the latch circuits 36 and 37. Reference numeral 35 denotes a gate for controlling the taking in of the lower limit value, which generates a clock when the comparison result is “Low” and a clock signal in the test mode 1 is input, and outputs the bit shifter 39 to the lower limit latch circuit 37. Let it be captured. Reference numeral 34 denotes a gate for controlling the capturing of the upper limit value. When the comparison result is “High” and the clock of the test mode 1 is input, the clock is generated and the output of the bit shifter 39 is captured by the upper limit latch circuit 36. . These sequential circuit operations are updated by a clock-like signal in the test mode 1, and the stage of the trimming operation advances accordingly.

  FIG. 31 shows FIG. 30 more specifically. The case of 4 bits is taken as an example. In FIG. 31, a circuit corresponding to the upper limit latch circuit 36 and the lower limit latch circuit 37 of FIG. 30 is a block 43, a circuit corresponding to the adder / subtractor 38 is a block 44, and a circuit corresponding to the bit shifter 39 is a block 45. As shown respectively. Flip-flops corresponding to the lower limit latch circuit 37 are prepared for 5 bits, and all are DQ flip-flops with a reset terminal, such as reference numerals 511, 513, 515, 517 and 519. Flip-flops corresponding to the upper limit latch circuit 36 are also prepared for 5 bits, the uppermost latch circuit is a DQ flip-flop 500 with a set terminal, and other DQ flip-flops with a reset terminal such as 512, 514, 516 and 518 Is. Test mode 0 is connected to these set / reset terminals. As a result, the initial value of the operation is set to “10000” for the upper limit value {ra4, ra3, ra2, ra1, ra0} and “00000” for the lower limit value {rb4, rb3, rb2, rb1, rb0} in the test mode 0. Can be set. The adder / subtracter 38 for adding the upper limit value and the lower limit value is composed of a 5-bit full adder to which 1-bit full adders indicated by reference numerals 521 to 525 are connected. Only the full adder is configured by grounding the carry Ci-1 of the least significant bit, but of course, only the least significant bit may be a half adder. The 1-bit full adders 521 to 525 may be general full adders as shown in FIG. 22 (indicated by reference numerals 351 to 354 in FIG. 22), for example. What is considered now is internal power supply potential trimming, and it is not necessary to increase the speed in the order of ns (nanoseconds), and it may be simple. Of course, when the bit number of the addition number increases and the carry propagation time cannot be ignored, a high-speed addition combining a CLA (CarryLookAhead) circuit, a BCLA (Block CarryLookAhead) circuit, or even a CSA (CarrySave Adder), etc. A vessel may be used. These high-speed computing units are as described in Non-Patent Document 1, for example.

  The circuit corresponding to the bit shifter 39 is represented by a connection in FIG. 31, and outputs the ground (“0”) as the most significant bit, and the most significant addition result (the output of the 1-bit full adder 521) as the next bit. Is output as the least significant bit, and the least significant bit of the addition result (the output of the 1-bit full adder 524) is output, and the least significant bit of the addition result is discarded. ing. All these bits are returned to the latch circuits 36 and 37 (DQ flip-flops 500 and 511 to 519), and {c3, c2, c1, and c0} excluding the most significant bit are input to the decoder 222. Thereby, 1/2 calculation is performed. The gates 34 and 35 are gates for controlling the fetching of the latch circuits 36 and 37, and are controlled in accordance with the result "High" / "Low" in synchronization with the test mode 1. When the result is “Low”, the lower limit {rb} is replaced, and when the result is “High”, the upper limit {ra} is replaced.

  As described above, various pseudo trimming related operations are performed by starting the test mode from an external input. This point is as described in [Other Embodiments of the Present Invention and Description 1 of Effects].

  A pseudo trimming operation in test mode 1 and a trimming code output operation in test mode 2 will be described with reference to FIG. First, at time t2, as a first stage of pseudo-trimming, the test mode command TMRS is set to an address “in order to set the flip-flops 500, 511 to 519 in the block 43 corresponding to the latch circuits 36 and 37 of FIG. a0 ". Then, TCLK of the TMRS pulse is generated, and the test mode decoder 55 of FIG. 23 takes in the internal address TA and generates a test mode 0 pulse. This is the trigger for test mode 0. Thus, the DQ flip-flops 500, 512, 514, 516 and 518 in FIG. 31 corresponding to the latch circuit 36 in FIG. 30 are set to {ra} = “10000”, and the DQ flip-flop in FIG. 511, 513, 515, 517 and 519 are set to {rb} = “00000”. Addition / subtraction is performed in the adder / subtractor 38, and the shifted bit {c} in the shifter 39 becomes {1000}. As a result, the trimming code becomes “u8”, and as a result, the adjusted potential Va is set to an intermediate value in the adjustment range. Subsequently, the comparison circuit 216 in FIG. 14 performs comparison with the target potential Vt. In this case, since the potential to be adjusted Va> the target potential Vt, the comparison result is “Low”. This completes the first stage of pseudo trimming.

  Next, when the address “a1” is input together with the TMRS command at time t4 as the second stage of the pseudo trimming, the test mode 1 pulse is output as in the case of the test mode 0, and the latch circuits 36 and 37 in FIG. Takes in the value according to the comparison result. In this case, since the comparison result is “Low”, the latch circuit 37 side takes in and the lower limit value {rb} is updated to “01000”. Addition / subtraction is performed in the adder / subtracter 38, and the shifted bit {c} in the shifter 39 becomes “1100”. As a result, the trimming code becomes “u12”, and as a result, the adjusted potential Va is set to an intermediate value in the new adjustment range. Subsequently, the comparison circuit 216 in FIG. 14 performs comparison with the target potential Vt. In this case, since the potential to be adjusted Va <target potential Vt, the comparison result is “High”. Thereby, in the next cycle, the upper limit value {ra} is updated to “01100”.

  Next, if the test mode 1 is entered at times t6 and t7 as the third and fourth stages, the trimming is completed. When test mode 0 is performed once and (test mode 1 is performed by the number of trimming bits-1) times, the test is completed.

  Finally, when the address “a2” is input together with the command TMRS at an appropriate time, in the figure, at time t32, the test mode 2 pulse is generated, and the pseudo trimming result code “u11” held by the absence of the test mode 1 pulse is generated. Is output to the trimming code output. This output is output from the DQ pad or the like to the outside of the chip through a data path or the like. Fuse trimming may be performed based on the trimming code extracted here.

  The test mode 3 is the same as that described in [Other Embodiments of the Invention and Description 1 of Effects].

[Description of Other Embodiments and Effects of Present Invention 3]

  A method of changing the configuration of FIG. 14 and returning the trimming code output in the test mode 2 to the trimming code nonvolatile memory circuit 217a as shown in FIG. 27 can be considered. 27 is a block diagram showing the semiconductor device 100f and the power supply control unit 10f. In FIG. 27, the same components as those in FIG. If the trimming code nonvolatile memory circuit 217a is electrically controllable like an electric fuse, the trimming code nonvolatile memory circuit 217a can be trimmed with the optimum code searched by pseudo trimming by binary search. Become. That is, it is possible to perform high-speed automatic trimming by searching for an optimum code by high-speed binary search and performing trimming based on the result. It does not matter what configuration the trimming code nonvolatile memory circuit 217a has.

[Description of Other Embodiments and Effects of Present Invention 4]

  The circuit to be trimmed 215 in FIG. 17 is of a type that selects a tap taken out from a resistance-divided node. However, in the case of a variable resistor 215a as shown in FIG. 28A, as shown in FIG. Further, by weighting the resistance, the trimming code generation / storage circuit 211 of FIG. 14 is simplified. Specifically, resistors R, 2R, 4R, and 8R having resistance values R, 2R, 4R, and 8R are connected in series, and switches 420, 421, and 422 are turned on with counter bits c0, c1, c2, and c3. 423 is connected in parallel. According to this, the counter bits c0, c1, c2, and c3 can be used as trimming codes. That is, the configuration corresponding to the decoder 222 can be omitted as in the trimming code generation / storage circuit 211b of FIG. 29, and the configuration can be made up of the binary search circuit 221a, and the circuit scale can be reduced. It is efficient that the weighting is 2 ^ n as shown in FIG.

  As described above, in another embodiment of the present invention, the circuit to be trimmed 215 that changes the generated value by pseudo-trimming, and the comparison circuit 216 that compares the generated value with the target value input from the outside. And a trimming code generating / storing circuit 211 having binary search circuits 221a and 221b that determine the pseudo trimming value by binary search in response to the comparison result, are built in the chip and are pseudo-trimmed by binary search on-chip. By performing the above, the pseudo trimming time can be shortened. Further, by storing the trimming value in an electrically controllable nonvolatile storage medium (trimming code nonvolatile storage circuits 217 and 217a), high-speed automatic trimming can be realized.

  In another embodiment of the present invention, the power supply control units 10e and 10f are generated while changing the trimming code (control signal), and the trimming code is changed while changing the amount of the change. The trimming code is generated while increasing or decreasing by the amount. Further, the trimming code generation / storage circuits (control signal generation circuits) 211a, 211b, and 211c receive the comparison result of the comparison circuit 216 and are generated while changing the trimming code (control signal) by binary search. Yes. Further, the trimmed circuit 215a includes a plurality of weighted resistance elements R, 2R, 4R, and 8R and a plurality of switches 420 to 423 that short-circuit the resistance elements in accordance with a trimming code (control signal). It is configured.

  The components of the embodiment of the present invention described with reference to FIGS. 14 to 32 are appropriately combined with or replaced with the components of the embodiment of the present invention described with reference to FIGS. Is possible.

DESCRIPTION OF SYMBOLS 100a ... Semiconductor device, 1 ... Adjusted power supply, 2 ... Trimming code generation / storage circuit, 3 ... Trimming code storage circuit, 4 ... Selector, 5 ... Comparator, 10a ... Power supply control part, 11 ... Voltage adjustment circuit, 12 ... Trimming circuit, 62, 64 ... switch circuit, 65 ... terminal

Claims (17)

The power supply control unit is generated while changing the control signal for adjusting the output voltage of the adjusted power supply unit, and the output voltage of the adjusted power supply unit based on the control signal becomes a value corresponding to the control target voltage The control signal is stored, and the output voltage of the adjusted power supply unit is set based on the stored control signal. The adjusted power supply unit is
A trimming circuit in which an operation state is set according to the input control signal;
The semiconductor device according to claim 1, wherein an output voltage is changed according to a reference voltage and an operation state set in the circuit to be trimmed. The power control unit
A control signal generating circuit for generating the control signal while changing the control signal;
A comparison circuit for comparing the output voltage of the regulated power supply unit and the control target voltage;
A nonvolatile memory circuit that stores the control signal when the comparison result of the comparison circuit changes;
3. A selection circuit that inputs either the control signal output from the control signal generation circuit or the control signal stored in the nonvolatile memory circuit to the circuit to be trimmed. Semiconductor device. The nonvolatile memory circuit is
The semiconductor device according to claim 3, wherein a control signal output from the control signal generation circuit is stored. The control signal generating circuit is
A counter circuit for counting input clock signals;
A control signal output circuit that outputs the control signal based on the count value of the counter circuit,
4. The semiconductor according to claim 3, wherein the semiconductor signal is generated while changing the control signal, holds a count value when the comparison result of the comparison circuit changes, and outputs a control signal based on the count value. 5. apparatus. The semiconductor device according to claim 1, wherein the control target voltage is input from the outside. The output voltage of the regulated power supply unit is a voltage having a first temperature gradient generated using an element inside the semiconductor device,
The semiconductor device according to claim 1, wherein the control target voltage is a voltage having a second temperature gradient different from the first temperature gradient generated using an element inside the semiconductor device. The semiconductor device according to claim 7, wherein one of the first and second temperature gradients is within a predetermined range. The adjusted power supply unit is
A trimming circuit in which an operation state is set according to the input control signal;
8. The semiconductor device according to claim 7, wherein an output voltage is changed in accordance with a voltage having the first temperature gradient and an operation state set in the circuit to be trimmed. The power control unit
A control signal generating circuit for generating the control signal while changing the control signal;
A comparison circuit for comparing the output voltage of the regulated power supply unit and the control target voltage;
A nonvolatile memory circuit that stores the control signal when the comparison result of the comparison circuit changes;
The control circuit according to claim 7, further comprising: a selection circuit that inputs either the control signal output from the control signal generation circuit or the control signal stored in the nonvolatile memory circuit to the trimming circuit. Semiconductor device. The nonvolatile memory circuit is
The semiconductor device according to claim 10, wherein a control signal output from the control signal generation circuit is stored. The semiconductor device according to claim 7, wherein the control target voltage is a voltage generated using a circuit in which a constant current source composed of an element in the semiconductor device and a diode are connected in series. The semiconductor device according to claim 7, wherein an output voltage of the regulated power supply unit is a voltage generated using a bandgap reference circuit configured by an element inside the semiconductor device. The semiconductor device according to claim 7, further comprising a circuit that outputs a signal indicating the output voltage of the adjusted power supply unit when the output voltage of the adjusted power supply unit becomes a value corresponding to the control target voltage. The power control unit
A control signal generating circuit that generates the control signal while changing the amount of the change, and generating the control signal while increasing or decreasing the amount of the control signal while changing the amount of the change;
A comparison circuit for comparing the output voltage of the regulated power supply unit and the control target voltage;
A nonvolatile memory circuit that stores the control signal when the comparison result of the comparison circuit changes;
3. A selection circuit that inputs either the control signal output from the control signal generation circuit or the control signal stored in the nonvolatile memory circuit to the circuit to be trimmed. Semiconductor device. The control signal generating circuit is
16. The semiconductor device according to claim 15, wherein the semiconductor device is generated while receiving the comparison result of the comparison circuit and changing the control signal by binary search. The semiconductor device according to claim 15, wherein the circuit to be trimmed includes a plurality of weighted resistance elements and a plurality of switches that short-circuit the plurality of resistance elements.

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