JP3761612B2 - Semiconductor integrated circuit and test method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and a test method therefor, and more particularly, to a semiconductor circuit device including a memory in which data can be written and read at any time, and a test method for the memory circuit.
[0002]
[Prior art]
In recent years, with the increase in data processing speed of information processing apparatuses, it has been required to increase the data reading speed of memory circuits. In addition, semiconductor integrated circuit (hereinafter referred to as LSI) devices are becoming more and more multifunctional and denser due to user requirements. Multifunctional LSIs tend to incorporate complex logic circuits and memory circuits on a single substrate. When testing such an LSI memory circuit, a complicated test pattern and a high-performance test apparatus are required. Generally, in order to evaluate the performance of a memory circuit, it is necessary to measure the access time (data read speed) and the write pulse width. The access time is the time from when the address is specified to the memory circuit until the data is read, and the write pulse width is the pulse width of the write enable signal. The write enable signal is a control signal for setting a data write or read operation. Both signals are the main parameters of the memory circuit.
[0003]
10A to 10C are explanatory diagrams of a memory circuit testing method according to a conventional example. In FIG. 10A, reference numeral 1 denotes a memory circuit (RAM macro) in which data can be written and read at any time, and includes a plurality of memory cells. A memory tester 2 performs a test for evaluating the performance of the memory circuit. The memory tester 2 inputs a test pattern to the memory circuit 1, generates a strobe signal (STRB) for searching from when the address is specified until data is output, and similarly, from the time when the address is specified. It has a function of expanding the pulse width of the write enable signal until data is output.
[0004]
Address AD_X, Address AD_YThe data DIN, the write enable signal WE, the chip select signal CS and the power supply VCC are supplied from the memory tester 2 to the memory circuit 1, and the output data DOUT is output from the memory circuit 1 to the memory tester 2. The memory tester 2 and the memory circuit 1 are connected by a ground line GND.
Next, a case where the access time (TAA) of the memory circuit 1 is measured will be described. First, the memory tester 2 sets both the chip select signal CS and the write enable signal WE to “L” (low) level, and then addresses AD_X= 0, AD_Y= 0 is specified and data DIN = 1 is written to the memory cell. Further, the memory tester 2 has an address AD_X= 1, AD_Y= 1 is specified and data DIN = 0 is written to the memory cell.
[0005]
Thereafter, the memory tester 2 sets the write enable signal WE to the “H” (high) level to enter the data read state, and the address AD_X= 0, AD_YSpecify = 0 and expect output of data DOUT = 1. At this time, in the memory tester 2, as shown in FIG._X= 0, AD_YThe time when = 0 is stored. Address AD_X= 0, AD_YWhen = 0 is designated, the strobe signal (STRB) starts to detect (search) the output of the data DOUT = 1. This search is continued until the data DOUT = 1 reaches the output terminal of the memory circuit 1. This search is executed by repeatedly generating a test pattern. When the data DOUT = 1 is obtained, the time when the data was obtained is stored.
[0006]
In the memory tester 2, the address AD is obtained from the time when the data DOUT = 1 is obtained._X= 0, AD_YBy subtracting the time at which = 0 is specified, the access time can be calculated.
Next, a case where the pulse width (TWW) of the write enable signal to the memory circuit 1 is measured will be described. First, the memory tester 2 sets both the chip select signal CS and the write enable signal WE to the “L” (low) level. Then, in order to initialize the memory circuit 1, the address AD_X= 0, AD_Y= 0 is specified and data DIN = 0 is written to the memory cell. Further, the memory tester 2 has an address AD_X= 1, AD_Y= 1 is specified and data DIN = 1 is written to the memory cell.
[0007]
Thereafter, the memory tester 2 reads the address AD_X= 0, AD_Y= 0 is specified, data DIN = 0 of the memory cell is rewritten to 1, and output of data DOUT = 1 is expected. At this time, the memory tester 2 changes the write enable signal WE from the “L” level to the “H” level to enter the data reading state. Then, in the memory tester 2, as shown in FIG._X= 0, AD_YThe pulse width of the write enable signal WE is gradually increased from the time when = 0 is designated until the data DOUT = 1 is output.
[0008]
This expansion of the pulse width is executed by repeatedly generating a test pattern. The pulse width when data DOUT = 1 is obtained as the pulse width of the write enable signal.
[0009]
[Problems to be solved by the invention]
However, when the data reading speed of the memory circuit is increased, in the method of searching the access time by the strobe signal, it is necessary to make the operation speed of the strobe signal several times higher than the data reading speed in order to shorten the sample timing. Then, the search accuracy from the time when the address is designated until the data is obtained must be increased. As a result, the higher the data reading speed of the memory circuit, the higher the quality tester is required.
[0010]
Further, when measuring the pulse width of the write enable signal WE, the memory tester 2 must generate a test pattern for gradually increasing the pulse width of the write enable signal WE for each address of the memory circuit 1. . This expansion of the pulse width must be continued from the time when the address is designated until the data is output, so that a complicated test pattern is required. For this reason, the higher the accuracy of the pulse width, the higher the quality of the tester is required.
[0011]
  As the data reading speed of the memory circuit is increased in this way, it is necessary to use a high-accuracy test device and a complicated test pattern, so that it becomes more difficult to measure the data reading speed and the write pulse width. The problem of increased testing coststhere were.
  The present invention was created in view of the problems of the conventional example, and does not depend on a complicated test pattern or a high-accuracy test apparatus even when the data reading speed of the memory circuit is increased. The memory circuitOne of the parameters required for performance evaluationEasy measurement of write pulse widthit canSemiconductor integrated circuit and test method thereofTo provideWith the goal.
[0012]
[Means for Solving the Problems]
  In order to solve the above-described problems of the prior art, according to one embodiment of the present invention.Implementation of semiconductor integrated circuitsFig. 5 and Fig. 6 as formsAs shown inWith multiple memory cells for storing dataMemory circuit(20)When,TheReturn the output of the memory circuit to the address input.TheFeedback circuit for oscillating memory circuits(11) and a plurality of types of sample signals (WEa, WEb, WEc, WEd) based on a write permission signal (WE) from the outside,Test mode signal(TMw)And pulse selection signalIn response to (S1, S2)Of pulse width sample signalOne of themOne write enable signal(WEx)Output to the memory circuit asAnd a write pulse generation circuit (29).It is characterized by that.
[0013]
In the semiconductor integrated circuit of the present invention, the feedback circuit includes a first logic circuit that outputs a feedback signal generated from a test mode signal and an output signal of the memory circuit, a feedback signal of the first logic circuit, and an external address. It comprises a second logic circuit for outputting the internal address generated from the above to the memory circuit.
[0015]
  According to another aspect of the present invention, a method for testing a semiconductor integrated circuit according to the above aspect is provided. This test method is a test method of a semiconductor integrated circuit having a memory circuit and a function of causing the memory circuit to oscillate by feeding back an output of the memory circuit to an address input.In advance,Multiple typesGenerate a sample signal with pulse width,Any one of the plurality of types of pulse width sample signalsAs a write enable signalSaidInput to the memory circuit,TheAn address is input to the memory circuit to put the memory circuit in a data write state, and the memory circuit oscillates.When notSample signal with other pulse widthInput to the memory circuit to write data,When the memory circuit oscillatesConcernedWrite enable signal pulse width from sample signal pulse widthCharacterized by seeking.
[0018]
  According to the semiconductor integrated circuit and the test method thereof according to the present invention,When a test mode signal and a pulse selection signal are input,Multiple types generated in the write pulse generatorOf pulse width sample signalOne of themOne as a write enable signalmemorySince it is output to the circuit, by checking the oscillation state of the memory circuit, the memorycircuitThe pulse width of the write enable signal, which is the main parameter ofConcernedIt can be obtained from the pulse width of the sample signal.
[0019]
  That is, the test mode signal and the pulse selection signal areWrite pulse generationWhen input to the circuit, one of the sample signals of any pulse width according to the pulse selection signal is selected.,thisThe selected sample signal is input to the memory circuit as a write permission signal. When an address is specified for this memory circuit, the memory circuit enters a data write state. Then, the oscillation of the memory circuit is confirmed. If the memory circuit oscillates, it can be determined that data has been written to the memory cell.
[0020]
  If the memory circuit does not oscillate, data is not written to the memory cell.(Write enable signal) is input to the memory circuit and dataSet to write state. As a result, if the memory circuit oscillates, the pulse width of the write enable signal is reduced by detecting the pulse width of the sample signal at this time.simplyTo askit can.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. 1 to 9 are explanatory diagrams of a semiconductor integrated circuit and a test method thereof according to an embodiment of the present invention.
(1) First embodiment
FIG. 1 shows a configuration diagram of a semiconductor integrated circuit according to the first embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a RAM macro (hereinafter simply referred to as a RAM) having a memory cell group 14 for storing data, which is an example of a memory circuit. The RAM 10 is a memory in which data can be written and read at any time. The RAM 10 includes an address buffer 12, an X decoder 13, a memory cell group 14, a Y decoder 15, a sense amplifier 16, an I / O buffer 17, and a timing generation circuit 18.
[0022]
The address buffer 12 inputs addresses ADo to ADn based on the timing control signal. The X decoder 13 decodes the column address ADx based on the timing control signal. A word line selection signal obtained by decoding the column address ADx is output from the X decoder 13 to the memory cell group 14. The memory cell group 14 stores data or outputs data based on the word line selection signal and the bit line selection signal.
[0023]
The Y decoder 15 generates a row address AD based on the timing control signal._YDecode. Row address AD_YThe bit line selection signal that is the result of decoding is output from the Y decoder 15 to the sense amplifier 16. The sense amplifier 16 selects a bit line based on the timing control signal and the bit line selection signal. Based on the write enable signal WE, the I / O buffer 17 puts data into a write state or puts data into a read state. The timing generation circuit 18 generates various timing control signals based on the chip select signal CS and the write enable signal WE.
[0024]
A feedback circuit 11 oscillates the RAM 10 by feeding back the output of the RAM 10 to an address input. FIG. 2A shows a configuration diagram of a feedback circuit connected to the RAM 10. In FIG. 2A, reference numeral 101 denotes a two-input AND circuit that feeds back the feedback signal Sf to the two-input OR circuits 102 and 103, and is an example of a first logic circuit. The feedback signal Sf is a test mode signal TM._RAnd the data (output signal) DOUT of the RAM 10 are taken.
[0025]
3 is a test mode signal TM_RIs a terminal to set the from the outside. The terminal 3 is provided around the RAM 10. In the embodiment of the present invention, when the access time is measured, the test mode signal TM_RIs set to “H” level to operate (turn on) the feedback circuit 11. The signal TM_RIs set to the “L” level, the feedback circuit 11 is in a non-operating (off) state.
[0026]
Reference numeral 102 denotes a two-input OR circuit that inputs the internal address AX as a column address of the RAM 10 and constitutes a second logic circuit. The internal address AX is a logical sum of the feedback signal Sf and the external column address ADx.
Reference numeral 103 denotes a two-input OR circuit that inputs the internal address AY as a row address of the RAM 10 and constitutes a second logic circuit. The internal address AY is the feedback signal Sf and the external row address AD._YAnd the logical OR.
[0027]
In this way, the two-input AND circuit 101 is connected to the test mode signal TM._RWhen the feedback signal Sf is generated from the output data DOUT of the RAM 10, the feedback signal Sf is output from the two-input AND circuit 101 to the two-input OR circuits 102 and 103. The two-input OR circuits 102 and 103 have a feedback signal Sf and external addresses ADx, AD._YTo generate internal addresses AX and AY. Since the internal addresses AX and AY are output from the two-input OR circuit 102 to the RAM 10, the feedback circuit 11 can feed back the output data DOUT of the RAM 10 as the internal addresses AX and AY.
[0028]
In FIG. 2A, 14A to 14D in the RAM 10 indicate four memory cells. In the embodiment of the present invention, data “1” is written in the memory cell 14A. This data “1” is written by designating “0, 0” to the addresses AX, AY. Data “0” is written in the memory cell 14D. This data “0” is written by designating “1, 1” to the addresses AX, AY. In the embodiment of the present invention, data is not written in the memory cells 14B and 14C. Therefore, “1,0” is not specified for the addresses AX, AY, and “0, 1” is not specified. In FIG. 2A, reference numeral 200 denotes a frequency counter that measures the oscillation frequency when the RAM 10 oscillates.
[0029]
FIG. 2B shows a waveform diagram of output data when the RAM 10 oscillates. In the embodiment of the present invention, when the RAM 10 oscillates, data “1” and “0” are alternately output. Therefore, the access time can be measured from the cycle of repeatedly reading the data “1” and “0”. Here, if T is a cycle for repeatedly reading data “1” and “0”, the access time (TAA) is T / 2.
[0030]
Next, a method for measuring the access time will be described as a method for testing a semiconductor integrated circuit having the RAM 10 with reference to FIGS. In advance, as shown in FIG. 4, the test mode signal TM_RIs set to the “L” level, and the feedback circuit 11 is inactivated (off). Then, “0, 0” is designated as the address input of the RAM 10 and data “1” is written into the memory cell 14A. Further, “1, 1” is designated as the address input of the RAM 10 and data “0” is written into the memory cell 14D. At this time, the pulse width of the write enable signal WE is TWW. This will be described in the second embodiment.
[0031]
After that, external addresses ADx and AD_YTest mode signal TM with_RIs set to the “H” level as shown in FIG. 4 to operate (turn on) the feedback circuit 11. Then, in FIG. 3A, the output of the two-input OR circuit 102, that is, the internal address AX becomes “0”, and the output of the two-input OR circuit 103, that is, the internal address AY becomes “0”. Therefore, since the addresses AX and AY specify “0, 0”, data “1” is read out. Since the data “1” is output to the two-input AND circuit 101, the output of the AND circuit 101, that is, the feedback signal is inverted to “1”.
[0032]
As a result, in FIG. 3B, the output of the two-input OR circuit 102, that is, the internal address AX becomes “1”, and the output of the two-input OR circuit 103, that is, the internal address AY becomes “1”. Accordingly, since the addresses AX and AY specify “1, 1”, data “0” is read out. Since this data “0” is output to the two-input AND circuit 101, the output of the AND circuit 101, that is, the feedback signal is inverted to “0”.
[0033]
Accordingly, the data “1” of the memory cell 14A and the data “0” of the memory cell 14D are alternately read, and this data “1” or “0” is alternately fed back to the address input of the RAM 10. As a result, the RAM 10 oscillates, and if the oscillation frequency of the RAM 10 is measured by the frequency counter 200, the access time (data read speed) can be calculated from the oscillation frequency (see FIG. 2B or FIG. 4).
[0034]
Thus, in the semiconductor integrated circuit according to the first embodiment of the present invention, when the data “1” of the memory cell 14A and the data “0” of the memory cell 14D of the RAM 10 are alternately read, the feedback circuit 11 Since the data “1” of the memory cell 14A and the data “0” of the memory cell 14D are fed back to the address input of the RAM 10, the RAM 10 oscillates.
[0035]
Therefore, by measuring the oscillation frequency of the RAM 10 with the frequency counter 200, the access time can be easily measured by T / 2 from the cycle T in which the data “1” and “0” are repeatedly read.
As described above, since the access time can be easily measured, even when the data reading speed of the memory circuit is increased, it does not depend on a complicated test pattern or a highly accurate test apparatus. In addition, since the main parameters of the memory circuit can be measured at the stage of the primary test (test in the wafer state), the operation prediction at the time of completion of the multifunctional LSI in which a complex logic circuit or memory circuit is incorporated on one substrate can be realized. It is possible to sort good and defective products. As a result, the process schedule after the primary test can be easily established, and the wafer process process and feedback to the design can be facilitated.
[0036]
Furthermore, since the access time of the memory circuit can be easily measured even in the final test (test in a state assembled in a package), it does not depend on a high-performance tester or a complicated test pattern. Thereby, a significant test cost can be reduced.
(2) Second embodiment
FIG. 5 shows a configuration diagram of a semiconductor integrated circuit according to the second embodiment of the present invention. Unlike the first embodiment, the second embodiment is a variable-pulse signal generator (hereinafter simply referred to as a WPG circuit) that outputs a write enable signal (write permission signal) WEx to the I / O buffer 17 of the RAM 20. Is provided.
[0037]
That is, the semiconductor integrated circuit according to the second embodiment of the present invention includes a feedback circuit 11 and a RAM 20 as shown in FIG. In FIG. 5, the RAM 20 includes an address buffer 12, an X decoder 13, a memory cell group 14, a Y decoder 15, a sense amplifier 16, an I / O buffer 17, a timing generation circuit 28 and a WPG circuit 29.
[0038]
  The WPG circuit 29 is a circuit that outputs a write enable signal WEx to the I / O buffer 17.Write pulse generationIt is an example of a circuit. The write enable signal WEx is,It is generated by the WPG circuit 29 to which the test mode signal TMw and the pulse selection signals S1, S2 are input. The WPG circuit 29Generated internally as described below4 types of pulse width sample signal(In the example of FIG. 6, one of the signals indicated by WEa, WEb, WEc, and WEd)One is output to the I / O buffer 17 as a write enable signal WEx.. thisAn internal configuration diagram of the WPG circuit 29 will be described in detail with reference to FIG.
[0039]
The functions of the address buffer 12, the X decoder 13, the memory cell group 14, the Y decoder 15, the sense amplifier 16, the I / O buffer 17, and the timing generation circuit 28 are the same as those in the first embodiment. Since it is the same, the description is omitted.
FIG. 6 shows an internal configuration diagram of the WPG circuit 29. In FIG. 6, 4 is a test mode signal TM._WIs a terminal to set the from the outside. The terminal 4 is provided around the RAM 20. In the embodiment of the present invention, the test mode signal TM is measured when the write pulse width is measured._WIs set to “H” level to operate (turn on) the WPG circuit 29. The signal TM_WIs set to the “L” level, the WPG circuit 29 is brought into a non-operating (off) state.
[0040]
Reference numerals 5 and 6 denote two terminals for setting the pulse selection signals S1 and S2 from the outside. Terminals 5 and 6 are provided around the RAM 20. Signals S1 and S2 are signals for selecting one of four types of sample signals WE1, WE2, WE3, and WE4 when measuring the write pulse width. The signals S1 and S2 are input to the terminals by combining 2-bit data “0” and “1”.
[0041]
30 is a test mode signal TM_WIs an inverter that inverts. 31 is an inverter for inverting the pulse selection signal S1. 32 is an inverter for inverting the pulse selection signal S2. 33 is an inverted test mode signal TM_W, A 4-input NOR circuit that outputs a sample signal WEa obtained by taking a negative OR of the write enable signal WE and the pulse selection signals S1 and S2. Here, the pulse width of the sample signal WEa is a.
[0042]
34 is an inverted test mode signal TM_W, A 4-input OR circuit that outputs a logical OR of the write enable signal WE, the pulse selection signal S1, and the inverted pulse selection signal S2. 35 is an inverted test mode signal TM_W, A 4-input OR circuit that outputs a logical OR of the write enable signal WE, the inverted pulse selection signal S1, and the pulse selection signal S2. Reference numeral 36 denotes an inverted test mode signal TM._W, A 4-input OR circuit that outputs a signal obtained by ORing the write enable signal WE and the inverted pulse selection signals S1 and S2.
[0043]
An inverter 37 delays the output signal of the 4-input OR circuit 34 and outputs a sample signal WEb. The pulse width of the sample signal WEb is b. Reference numerals 38 and 39 respectively denote inverters that delay the output signal of the 4-input OR circuit 35 and output the sample signal WEc. The pulse width of the sample signal WEc is c.
Reference numerals 40, 41, and 42 respectively denote inverters that delay the output signal of the 4-input OR circuit 36 and output the sample signal WEd. The pulse width of the sample signal WEd is d. The relationship between the pulse widths of the four sample signals WEa to WEd is set to a <b <c <d.
[0044]
Reference numeral 43 denotes a 5-input OR circuit that takes the logical sum of the write enable signal WE and the sample signals WEa, WEb, WEc, and WEd and outputs one of the four sample signals WEx. The output of the 5-input OR circuit 43 is input to the I / O buffer 17 as a write enable signal candidate.
Next, the function of the WPG circuit will be described. During normal operation in which the write pulse width of the RAM 20 is not measured, as shown in FIG._WBecomes “L” level. Accordingly, the WPG circuit 29 is turned off. As a result, the write enable signal WE having a pulse width inputted from the outside is output to the I / O buffer 17 of the RAM 20 as it is regardless of the logic of the pulse selection signals S1 and S2.
[0045]
Further, during a test operation for measuring the write pulse width of the RAM 20, as shown in FIG._WBecomes “H” level. Accordingly, the WPG circuit 29 is turned on. As a result, when the pulse selection signals S1 and S2 are “0, 0”, the sample signal WEa having the pulse width a is output from the 5-input OR circuit 43 to the I / O buffer 17 as a write enable signal candidate.
[0046]
Further, when the pulse selection signals S1 and S2 are “0, 1”, the sample signal WEb having a pulse width b is output from the 5-input OR circuit 43 to the I / O buffer 17 as a write enable signal candidate. Further, when the pulse selection signals S1 and S2 are “1, 0”, the sample signal WEc having a pulse width c is output from the 5-input OR circuit 43 to the I / O buffer 17 as a candidate for the write enable signal. Similarly, when the pulse selection signals S1 and S2 are “1, 1”, the sample signal WEd having the pulse width d is output from the 5-input OR circuit 43 to the I / O buffer 17 as a write enable signal candidate.
[0047]
Next, a method for measuring the pulse width of the write enable signal will be described with reference to FIG. In advance, the WPG circuit 29 as shown in FIG. 6 can output the four kinds of sample signals WEa to WEd having the pulse widths a to d as shown in FIG.
Further, as shown in FIG. 9, the test mode signal TM_RRemains at “L” level and the test mode signal TM_WIs set to “H” level, and the chip select signal CS is set to “L” level. Then, in order to write data in the RAM 20, the address AD_X= 0, AD_Y= 0 is specified. At this time, “0, 0” is input to the pulse selection signals S 1 and S 2, and the sample signal WEa having the pulse width a is input from the WPG circuit 29 to the I / O buffer 17. In the embodiment of the present invention, a sample signal having a narrow pulse width is gradually set to a sample signal having a wide pulse width.
[0048]
As a result, the data DIN = 1 is written into the memory cell by the write enable signal WEx. However, if the pulse width a of the selected signal WEa is narrow, the data DIN cannot be written into the memory cell. Note that whether or not the data DIN = 1 is written to the memory cell depends on the test mode signal TM as described in the first embodiment._RIs set to “H” level, the output data is fed back to the address input, and it is confirmed whether or not the RAM 20 oscillates.
[0049]
Therefore, when the sample signal WEa does not oscillate, the test mode signal TM_RTo “L” level. Then, “0, 1” is input to the pulse selection signals S1 and S2 in order to select the sample signal WEb having a pulse width wider than a. Address AD_X= 1, AD_Y= 1 is specified, and data DIN = 0 is written to the memory cell.
[0050]
Then, the sample signal WEb having the pulse width b is input from the WPG circuit 29 to the I / O buffer 17. Then, test mode signal TM_RIs set to “H” level to confirm whether or not the RAM 20 oscillates. Thereby, when the RAM 20 oscillates, the data DIN can be written by the sample signal WEb having the pulse width b. It can be seen that data cannot be written below the pulse width b of the sample signal WEb, and the write pulse width which is the main parameter of the RAM 20 can be grasped.
[0051]
Thus, in the semiconductor integrated circuit according to the second embodiment of the present invention, the test mode signal TM_WWhen the pulse selection signals S1 and S2 are input, one of the four types of sample signals WEa to WEd having the pulse widths a to d is output from the WPG circuit 29 to the I / O buffer 17 of the RAM 20 as the write enable signal WEx. By confirming the oscillation state of the RAM 20, the pulse width of the write enable signal WE, which is a main parameter of the memory, can be obtained from the pulse width of the sample signal WEx.
[0052]
If the RAM 20 does not oscillate, the data DIN has not been written in the memory cell, so that the pulse selection signals S1 and S2 are input again to select a sample signal with another pulse width, and the remaining pulse width sample signal. Is output from the WPG circuit 29 to the I / O buffer 17 of the RAM 20 as a write enable signal WE. Then, the RAM 20 is set in a write state. As a result, if the RAM 20 oscillates, the pulse width of the write enable signal WE can be obtained by detecting the pulse width of the sample signal.
[0053]
Thus, unlike the conventional example, a test pattern for gradually increasing the pulse width of the write enable signal WE is not required until data is output from the time when the address is designated, and a complicated test is performed for each address. It is not necessary to generate a pattern, and the burden on the memory tester can be reduced.
Thereby, even when the data reading speed of the RAM 20 is increased, the write pulse width of the RAM 20 can be easily measured without depending on a complicated test pattern or a high-precision test apparatus.
[0054]
【The invention's effect】
As described above, in the semiconductor integrated circuit of the present invention, since the feedback circuit feeds back the output of the memory circuit to the address input, the memory circuit oscillates. Therefore, by measuring the oscillation frequency of the read data, the access time can be measured by a half cycle of this oscillation frequency.
[0055]
In another semiconductor integrated circuit of the present invention, when a test mode signal and a pulse selection signal are input, one of several types of pulse width sample signals is output from the signal output circuit to the memory circuit as a write enable signal. By confirming the oscillation state of the circuit, the pulse width of the write permission signal can be obtained from the pulse width of the sample signal.
[0056]
This greatly contributes to the provision of a semiconductor integrated circuit with a built-in memory capable of a simple test.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram of a feedback circuit and a waveform diagram of output data according to each embodiment of the present invention.
FIG. 3 is an operation supplement diagram of the memory macro according to the first embodiment of the present invention.
FIG. 4 is an operation waveform diagram during a memory test according to the first embodiment of the present invention.
FIG. 5 is a configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 6 is a configuration diagram of a pulse generation circuit according to a second embodiment of the present invention.
FIG. 7 is an operation waveform diagram (part 1) of the pulse generation circuit according to the second embodiment of the present invention;
FIG. 8 is an operation waveform diagram (part 2) of the pulse generation circuit according to the second embodiment of the present invention;
FIG. 9 is an operation waveform diagram during a memory test according to the second embodiment of the present invention.
FIG. 10 is an explanatory diagram of a testing method of a memory circuit according to a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Memory circuit, 2 ... Memory tester, 11 ... Feedback circuit, 12 ... Address buffer, 13 ... X decoder, 14 ... Memory cell group, 15 ... Y decoder, 16 ... Sense amplifier, 17 ... I / O buffer, 18, DESCRIPTION OF SYMBOLS 28 ... Timing generation circuit, 101 ... Two input AND circuit, 102, 103 ... Two input OR circuit, 14A-14D ... Memory cell, 200 ... Frequency measuring device, 29 ... Pulse generator, 30-32, 37-42 ... Inverter 33... 4 input NOR circuit, 34 to 36... 4 input OR circuit, 43... 5 input OR circuit, 51 to 54.

Claims (3)

A memory circuit comprising a plurality of memory cells for storing data;
A feedback circuit for oscillating the memory circuit by feeding the output of the memory circuit to the address input, and generates a sample signal of a plurality of kinds of pulse widths based on a write enable signal from the outside, the test mode signal and the pulse selection signal And a write pulse generating circuit for outputting any one of the plurality of types of pulse width sample signals to the memory circuit as a write permission signal. The feedback circuit includes a first logic circuit for outputting a feedback signal generated from the test mode signal and the output signal of the memory circuit,
The semiconductor integrated circuit according to claim 1, characterized in that a second logic circuit for outputting an internal address generated from the feedback signal and the external address of the first logical circuit to the memory circuit. In a test method for a semiconductor integrated circuit having a memory circuit and a function of oscillating the memory circuit by feeding back an output of the memory circuit to an address input,
Generate sample signals of multiple types of pulse widths in advance,
And inputs to the memory circuit as a write enable signal to any one of the sample signals of the plurality several pulse widths, and the memory circuit in the data write state by entering an address in the memory circuit,
When the memory circuit does not oscillate , input a sample signal of another pulse width to the memory circuit to enter a data write state,
The method of testing a semiconductor integrated circuit in which the memory circuit and obtains the pulse width of the write enable signal from the pulse width of the sample signal when the oscillation.

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