JP2010147380A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, capable of preventing the generation of embedding failure in a trench contact, irrespective of the material of upper electrode. <P>SOLUTION: In order to expose an n<SP>+</SP>-type emitter region 5 or a body p layer 6 (p-type base region 3), an opening end of a contact hole 10a formed on an interlayer insulating film 10 is retracted, and the opening width of the contact hole 10a is expanded. In this way, an aspect ratio of the depth of a contact trench 11 plus the thickness of the interlayer insulating film 10 to the opening width of the contact hole 10a is made smaller than that in a conventional manufacturing method. Thus, an upper electrode 12 can be unfailingly embedded into the contact trench 11. Accordingly, the embedding failure in the contact trench 11 can be prevented irrespective of the material of the upper electrode 12. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device in which an IGBT (insulated gate field effect transistor) and a free wheel diode (hereinafter simply referred to as a diode) are formed in the same chip.

Conventionally, in a semiconductor device including an IGBT and a diode on the same chip, an n ⁺ type layer serving as a cathode layer is formed in the diode formation region, and a p ⁺ type layer serving as a collector layer is formed in the IGBT formation region. And in patent document 1, with respect to the semiconductor device which integrated IGBT and the diode, a trench contact part is further formed between several trench gates, and the upper electrode which functions as an emitter electrode and an anode electrode in a trench contact part is formed. It is disclosed that the recovery loss Err is reduced and the recovery operation is improved by making Schottky contact.
JP 2007-214541 A

  In the structure as described above, the aspect ratio of the trench contact for improving the recovery operation is a value obtained by dividing the total value of the trench depth and the thickness of the interlayer insulating film by the width of the trench contact. Therefore, for example, if the width of the trench contact is 1.0 μm, if the depth of the trench contact is 0.5 μm or more, the aspect ratio becomes too large, and the upper electrode that functions as the emitter electrode and the anode electrode is formed. If it is made of Al which is a general electrode material, a filling defect in the trench contact occurs. Therefore, a treatment such as filling the trench contact with a tungsten plug (W-Plug) or the like is necessary so that the electrode surface can be flattened, resulting in a complicated manufacturing process and an increase in manufacturing cost.

  An object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing the occurrence of a filling defect in a trench contact regardless of the electrode material of the upper electrode.

  To achieve the above object, according to the present invention, a MOS device including a base region (3), an emitter region (5), and a gate electrode (7) formed in a gate trench (4) is formed. After that, a step of forming an interlayer insulating film (9), a first mask (20) having an opening corresponding to the contact hole (10a) on the interlayer insulating film (9) are disposed, and then the first mask is formed. Etching in a state covered with one mask (20) to form a contact hole (10a) in the interlayer insulating film (9), and after removing the first mask (20), the interlayer insulating film (9 ) As a mask to form a contact trench (11), and after forming the contact trench (11), contact holes (10 formed in the interlayer insulating film (9)) ) By retreating the opening end of the contact hole 10a to widen the opening width of the contact hole 10a and the upper electrode so that the contact trench 11 is buried through the contact hole 10a having the wide opening width. And 12) forming a step.

  In this way, the opening end of the contact hole (10a) is retracted to widen the opening width of the contact hole (10a). For this reason, the aspect ratio defined by the depth of the contact trench (11) with respect to the opening width of the contact hole (10a) + the thickness of the interlayer insulating film (10) is smaller than that of the conventional one, and the upper electrode (12) is reliably It can be embedded in the contact trench (11). Therefore, it is possible to suppress the occurrence of filling defects in the contact trench (11) regardless of the electrode material of the upper electrode (12).

  In the second aspect of the present invention, in the step of forming the contact hole (10a), after performing isotropic etching using the first mask (20), etching for forming the contact hole (10a) is performed. By doing so, the opening end of the contact hole (10a) is tapered.

  Thus, if the opening end of the contact hole (10a) is tapered, the opening end can be tapered even if the opening end of the contact hole (10a) is retracted. It becomes easy to enter. For this reason, the effect of Claim 1 can be acquired more.

  In the third aspect of the present invention, in the step of widening the opening width of the contact hole (10a), wet or dry etching is performed with the interlayer insulating film (9) exposed, thereby forming the interlayer insulating film (9). It is characterized by thinning at the same time.

  As described above, by performing wet or dry etching with the interlayer insulating film (9) exposed, a step of widening the opening width of the contact hole (10a) can be performed. By performing this method, the interlayer insulating film 10 can be thinned at the same time, and the aspect ratio can be further reduced. Thereby, the effect of Claim 1 can be acquired more.

  In the invention according to claim 4, after performing the step of widening the opening width of the contact hole (10a), the second mask (21) in which the opening for exposing the contact trench (11) is formed is disposed, The method includes a step of forming a taper by etching the side surface of the contact trench (11) while being covered with the second mask (21).

  As described above, if the side surface of the contact trench (11) is etched to be tapered, the upper electrode (12) is more likely to enter. For this reason, the effect of Claim 1 can be acquired more.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a schematic cross-sectional view showing a cross-sectional structure of a semiconductor device in which an IGBT and a diode according to this embodiment are integrated. Hereinafter, with reference to this figure, the semiconductor device having the IGBT according to the present embodiment will be described.

  The semiconductor device shown in FIG. 1 is an integrated IGBT and diode. An IGBT and a diode are formed in a cell region of the semiconductor device, and a breakdown voltage structure is formed in an outer peripheral region provided so as to surround the outer periphery. In FIG. 1, a part of the cell region, specifically, an IGBT is formed. Only the vicinity of the boundary position between the region and the diode formation region is shown.

As shown in FIG. 1, p ⁺⁺ -type collector layer 1a and the n ⁺⁺ type cathode layer on the surface of the (first conductivity type layer) 1b, from p ⁺⁺ -type collector layer 1a and the n ⁺⁺ type cathode layer 1b Also, an n ⁻ type drift layer 2 having a low impurity concentration is provided. For example, the p ⁺⁺ type collector layer 1a has a p type impurity concentration of about 1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ⁻³ , and the n ⁺⁺ type cathode layer 1b has an n type impurity concentration of 1 × 10 ¹⁷ to 1 × 1. × 10 ²⁰ cm ^-3 approximately, n ^- -type drift layer 2, n-type impurity concentration is set to about 1 × 10 ¹⁴ cm ^-3.

A p-type base region 3 is formed in the surface layer portion of the n ⁻ -type drift layer 2. For example, the p-type base region 3 has a thickness of about 5 μm and an impurity concentration of about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ .

Then, a plurality of gate trenches 4 are formed so as to penetrate the p-type base region 3 and reach the n ⁻ -type drift layer 2, and the p-type base region 3 is separated into a plurality by the gate trench 4. Has been. Specifically, the gate trenches 4 are formed at a plurality of predetermined pitches (intervals), for example, a stripe structure in which the gate trenches 4 extend in parallel in the depth direction (the vertical direction on the paper) of FIG. Alternatively, it is formed in an annular structure by extending in parallel and then being routed at the tip.

The p-type base region 3 is divided into a plurality of portions by the adjacent gate trenches 4, and n ⁺ -type emitter regions 5 are formed in contact with the side surfaces of the gate trenches 4 in the surface layer portion of each divided p-type base region 3 The body p layer 6 is formed at a position spaced from the side surface of the gate trench 4. The n ⁺ -type emitter region 5 is exposed by being formed on the outermost surface of the p-type base region 3, and the n-type impurity concentration on the surface is about 1 × 10 ²⁰ cm ⁻³ . The body p layer 6 is a high-concentration layer provided for adjusting the withstand voltage, and is also used as a part constituting part of the p-type base region 3 for contact. In the present embodiment, the body p layer 6 is formed at a position deeper than the n ⁺ -type emitter region 5, and the p-type impurity concentration on the surface is about 1 × 10 ²⁰ cm ⁻³ . The n ⁺ -type emitter region 5 and the body p-layer 6 are sufficiently higher in concentration than the p-type base region 3.

The n ⁺ -type emitter region 5 has a higher impurity concentration than the n ⁻ -type drift layer 2, terminates in the p-type base region 3, and is disposed so as to be in contact with the side surface of the gate trench 4. Yes. More specifically, the structure extends in a rod shape along the longitudinal direction of the gate trench 4 and terminates inside the tip of the gate trench 4.

  Each gate trench 4 includes a gate insulating film 7 formed so as to cover the inner wall surface of each gate trench 4, and a gate composed of doped Poly-Si formed on the surface of the gate insulating film 7. It is embedded with the electrode 8.

  Among these, the gate electrode 8 is electrically connected to each other in a cross section different from that of FIG. 1, and is gated through a doped Poly-Si layer (not shown) formed on the thermal oxide film 9 and the interlayer insulating film 10. It is electrically connected to wiring (not shown).

Further, contact trenches 11 are formed at positions different from the gate trenches 4 formed in the IGBT formation region and the diode formation region, specifically, between the gate trenches 4. The contact trench 11 is shallower than the gate trench 4 and has a structure that penetrates the n ⁺ -type emitter region 5 and exposes the body p layer 6 (p-type base region 3) on the bottom surface. For example, the contact trench 11 has a depth of 1 to 1.5 μm and a width of 1 to 1.5 μm. Here, the body p layer 6 is formed to be deeper than the bottom surface of the contact trench 11, but the contact trench 11 is deeper than the body p layer 6, and the contact trench 11 The body p layer 6 may be arranged on the side surface.

An upper electrode 12 is formed so as to fill the contact holes 10a and 10b and the n ⁺ -type emitter region 5 formed in the interlayer insulating film 10 and the contact trench 11. The upper electrode 12 functions as an emitter electrode in the IGBT and also functions as an anode electrode in the diode. The upper electrode 12 is electrically connected to the n ⁺ -type emitter region 5 and is connected to the body p through the contact trench 11 and the like. The layer 6 and the p-type base region 3 are also electrically connected. The upper electrode 12 is made of, for example, Al.

The contact hole 10 a for contacting the n ⁺ -type emitter region 5 and body p layer 6 formed in the interlayer insulating film 10 and the upper electrode 12 with the upper electrode 12 has an opening width wider than that of the contact trench 11. The aspect ratio defined by the depth of the contact trench 11 with respect to the opening width of the contact hole 10a + the thickness of the interlayer insulating film 10 is made smaller than the conventional one. For this reason, it has a structure that can suppress the occurrence of a filling defect in the contact trench 11 regardless of the electrode material of the upper electrode 12.

  Note that a doped Poly-Si layer 13 is formed on the surface of the thermal oxide film 9 on the left side of the drawing with respect to the gate trench 4. This doped Poly-Si layer 13 is used as, for example, a temperature-sensitive diode, a gate wiring, or an electrode constituting an outer peripheral region. A contact hole 10c is formed in the interlayer insulating film 10 so as to expose the doped Poly-Si layer 13, and an electrode 14 electrically connected to the doped Poly-Si layer 13 is formed through the contact hole 10c. ing.

Further, a lower electrode 15 is formed on the back side of the p ⁺⁺ type collector layer 1a and the n ⁺⁺ type cathode layer 1b. The lower electrode 15 functions as a collector electrode in the IGBT and also functions as a cathode electrode in the diode, and is in ohmic contact with both the p ⁺⁺ type collector layer 1a and the n ⁺⁺ type cathode layer 1b. .

  With the structure as described above, a semiconductor device in which the IGBT and the diode according to the present embodiment are integrated is configured. Then, the manufacturing method of the semiconductor device which integrated IGBT and the diode of this embodiment is demonstrated. 2 to 5 are cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment.

First, in the step shown in FIG. 2A, a basic element structure is formed by a manufacturing method similar to the conventional one. For example, an n-type semiconductor substrate is prepared, a p-type base region 3, an n ⁺ -type emitter region 5 and a body p-layer 6 are formed on the main surface side, and then a gate trench 4 is formed. A trench gate structure is formed by forming the gate insulating film 7 and the gate electrode 8 in the trench 4 for use. In addition, by performing heat treatment, the thermal oxide film 9 is formed on the surface of the gate electrode 8, the surface of the p-type base region 3, and the like, and then the doped Poly-Si layer 13 is formed and patterned, and the oxide film and the like are further formed. For example, the interlayer insulating film 10 is formed with a thickness of about 8000 mm. Then, after thinning the n-type semiconductor substrate from the back side, a p ⁺⁺ collector layer 1a and an n ⁺⁺ cathode layer 1b are formed by ion implantation of p-type impurities or n-type impurities, and further below The basic element structure is formed by forming the electrode 15.

In the step shown in FIG. 2B, a region where a contact hole 10a is to be formed on the interlayer insulating film 10, that is, a region where the n ⁺ -type emitter region 5 and the body p layer 6 are electrically connected to the upper electrode 12. After the mask 20 having an opening is disposed, the interlayer insulating film 10 is isotropically etched while being covered with the mask 20. For example, wet etching such as HF or BHF or isotropic dry etching such as CDE can be used as an etching material. As a result, the interlayer insulating film 10 is etched wider than the opening of the mask 20, and the etched side surfaces become tapered. For this reason, the opening end of the contact hole 10a formed in a later step can be tapered.

In the step shown in FIG. 3A, anisotropic etching is performed this time using the same mask 20 as in the step shown in FIG. For example, dry etching using CF ₄ , CHF ₃ , Ar, or the like as an etching material can be used. As a result, a contact hole 10 a that penetrates through the interlayer insulating film 10 and the thermal oxide film 9 and reaches the body p layer 6 and the n + -type emitter region 5 is formed. However, at this time, the width of the contact hole 10a is still the same as the width of the contact trench 11.

  In the step shown in FIG. 3B, after removing the mask 20, the body p layer 6 and the n + type emitter region 5 are anisotropically etched using the interlayer insulating film 10 and the thermal oxide film 9 as a mask. For example, wet etching such as HF or BHF or dry etching such as CDE can be used as an etching material. As a result, contact trenches 11 having the same width as the contact holes 10a formed in the interlayer insulating film 10 are formed.

In the step shown in FIG. 4A, the width of the contact hole 10a is expanded by retreating the opening end of the contact hole 10a by wet or dry etching the interlayer insulating film 10 in the lateral direction. For example, HF or BHF is used as an etching material in the case of wet etching, and CF ₄ , CHF ₃ , Ar, or the like is used as an etching material in the case of dry etching, so that the opening end of the contact hole 10a is in each direction. It can be retracted by 0.1 μm or more. Since the retreat amount at this time is substantially uniform on each side surface of the contact hole 10a, the tapered opening end remains tapered even after retreat.

  In addition, since the surface of the interlayer insulating film 10 is also removed by the etching at this time, the film thickness of the interlayer insulating film 10 can be reduced to, for example, 4000 mm or less. Therefore, it is possible to realize both the thinning of the interlayer insulating film 10 and the expansion of the opening width of the contact hole 10a.

  If a mask that covers the region other than the contact hole 10a is arranged and then wet or dry etching is performed, only the opening end of the contact hole 10a is retreated, and the interlayer insulating film 10 is thinned. It can also be in a state where it is not performed.

  In the step shown in FIG. 4B, a mask 21 in which the regions for forming the contact trenches 11 and the contact holes 10b and 10c are to be formed is disposed on the interlayer insulating film 10. At this time, the contact trench 11 is set to have an opening width (for example, about 1.6 μm) of the mask 21 so as to be wider than the currently formed opening width (for example, about 1.0 μm). Then, isotropic etching is performed. For example, wet etching such as HF or BHF or isotropic dry etching such as CDE can be used as an etching material. Accordingly, the side surface can be tapered by partially removing the interlayer insulating film 10 in the regions where the contact holes 10b and 10c are to be formed, the opening end of the contact trench 11 is widened, and the side surface of the contact trench 11 is expanded. The taper angle with respect to the horizontal direction of the substrate becomes gentle.

In the step shown in FIG. 5A, anisotropic etching is performed using the mask 21 used in the step shown in FIG. For example, dry etching using CF ₄ , CHF ₃ , Ar, or the like as an etching material can be used. As a result, the interlayer insulating film 10 and the thermal oxide film 9 are removed in the opening portion of the mask 21, and contact holes 10b and 10c are formed.

  5B, an electrode material such as Al is formed on the surface of the interlayer insulating film 10, and the upper electrode 12 and the electrode 14 are formed by patterning. At this time, since the opening end of the contact hole 10a is retreated and the opening width of the contact hole 10a is widened, it is defined by the depth of the contact trench 11 with respect to the opening width of the contact hole 10a + the thickness of the interlayer insulating film 10. An aspect ratio becomes smaller than before, and the upper electrode 12 is reliably embedded in the contact trench 11. In the present embodiment, since the interlayer insulating film 10 is thinned, the aspect ratio can be further reduced, and the upper electrode 12 is more reliably embedded in the contact trench 11. Furthermore, in this embodiment, since the taper angle of the side surface of the contact trench 11 is made gentle, the upper electrode 12 can be more easily embedded in the contact trench 11. Therefore, it is possible to suppress the occurrence of the filling failure of the upper electrode 12 in the contact trench 11.

  As described above, according to the manufacturing method of the semiconductor device of the present embodiment, the opening end of the contact hole 10a is retracted and the opening width of the contact hole 10a is widened. 11 can be embedded. Therefore, it is possible to suppress the occurrence of a filling defect in the contact trench 11 regardless of the electrode material of the upper electrode 12.

  Further, in the method of manufacturing the semiconductor device according to the present embodiment, since the interlayer insulating film 10 is thinned, the above effect can be further obtained. In the present embodiment, since the taper angle of the side surface of the contact trench 11 is made gentle, the above effect can be further obtained.

  Furthermore, in the steps shown in FIGS. 2B and 4B, the opening ends (side surfaces) of the contact holes 10b and 10c are tapered by performing isotropic etching. It becomes easier for the upper electrode 12 and the electrode 14 to enter, and it is possible to suppress the occurrence of imbedding defects in these places.

(Other embodiments)
In the above embodiment, an n-channel type IGBT in which the first conductivity type is an n-type and the second conductivity type is a p-type has been described as an example. However, for a p-channel type IGBT in which the conductivity type of each part is reversed. The present invention can also be applied. In this case, the IGBT forming region becomes an n ⁺⁺ type collector layer, and a p − type drift layer, an n type base region, and a p ⁺ type emitter region are formed thereon. In the diode forming region, a p ⁺⁺ type anode region is formed. As a result, a PN junction having the p-type drift layer as an anode and the n-type base region as a cathode is formed.

In the present invention, the first conductivity type layer refers to the back side of the diode formation region, that is, the n ⁺⁺ type cathode layer 1b and the p channel type in the case of a diode formed on the same chip as the n channel type IGBT. In the case of a diode formed of the same chip as the IGBT, it means a p ⁺⁺ type anode layer.

It is a figure which shows the cross-sectional structure of the semiconductor device which integrated IGBT and diode concerning 1st Embodiment of this invention. FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 2; FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 3; FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 4;

Explanation of symbols

1a p ⁺⁺ type collector layer 1b n ⁺⁺ type cathode layer 2 n ⁻ type drift layer 3 p type base region 4 gate trench 5 n ⁺ type emitter region 6 body p layer 7 gate insulating film 8 gate electrode 9 thermal oxide film DESCRIPTION OF SYMBOLS 10 Interlayer insulating film 10a-10c Contact hole 11 Contact trench 12 Upper electrode 15 Lower electrode 20, 21 Mask

Claims (4)

A first conductivity type layer (1b) provided in the diode formation region and a second conductivity type collector layer (1a) formed in the IGBT formation region;
A first conductivity type drift layer (2) disposed on the first conductivity type layer (1b) and the collector layer (1a);
A second conductivity type base region (3) formed on the drift layer (2);
A gate trench (4) that is formed to penetrate the base region (3) and reach the drift layer (2), thereby separating the base region (3) into a plurality of parts;
A first conductivity type emitter region (5) formed in the base region (3) separated into a plurality, and in contact with the side surface of the gate trench (4) in the base region (3); ,
A gate insulating film (7) formed on the surface of the gate trench (4);
A gate electrode (8) formed on the gate insulating film (7) in the gate trench (4);
The emitter region (5) and the base region are arranged on the gate electrode (8), the emitter region (5) and the base region (3), and at a position different from the gate trench (4). An interlayer insulating film (10) in which a contact hole (10a) exposing (3) is formed;
A contact trench (11) formed in the contact hole (10a) for exposing the base region (3) through the emitter region (5);
An upper electrode (12) provided to fill in the contact trench (11) and electrically connected to the emitter region (5) and the base region (3);
A lower electrode (15) formed on the back side of the collector layer (1a),
The gate formed in the collector layer (1a), the drift layer (2), the base region (3), the emitter region (5) and the gate trench (4) provided in the IGBT formation region The electrode (7) constitutes an IGBT,
A diode is formed by a PN junction formed by the first conductivity type layer (1b) and the drift layer (2) and the second conductivity type base region (3), and the IGBT and the diode are integrated. A method for manufacturing a semiconductor device comprising:
After forming the MOS device including the gate electrode (7) formed in the base region (3), the emitter region (5), and the gate trench (4), the interlayer insulating film (9) is formed. Forming a film;
A first mask (20) having an opening corresponding to the contact hole (10a) is disposed on the interlayer insulating film (9), and then etched while being covered with the first mask (20). Forming the contact hole (10a) in the interlayer insulating film (9);
Forming the contact trench (11) by performing etching using the interlayer insulating film (9) as a mask after removing the first mask (20);
Forming the contact trench (11), and then receding the opening end of the contact hole (10a) formed in the interlayer insulating film (9) to widen the opening width of the contact hole (10a); ,
Forming the upper electrode (12) so that the contact trench (11) is buried through the contact hole (10a) whose opening width is widened. Production method.   In the step of forming the contact hole (10a), isotropic etching is performed using the first mask (20), and then etching for forming the contact hole (10a) is performed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the opening end of the hole (10a) is tapered.   In the step of widening the opening width of the contact hole (10a), the interlayer insulating film (9) is simultaneously thinned by performing wet or dry etching with the interlayer insulating film (9) exposed. The method for manufacturing a semiconductor device according to claim 1, wherein:   After performing the step of widening the opening width of the contact hole (10a), a second mask (21) having an opening for exposing the contact trench (11) is disposed, and the second mask (21) 4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a taper by etching a side surface of the contact trench in a state where the contact trench is covered. Method.

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