JP2010034851A - PLL circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit capable of suppressing both of power consumption and output noise. <P>SOLUTION: The PLL circuit is provided with a phase comparator 1, a charge pump 2, a loop filter 3, a voltage controlled oscillator 4 and a frequency divider 5, the frequency divider 5 is configured using CMOS logic circuits, and the phase comparator 1 and the charge pump 2 are configured using ECL circuits loaded with bipolar transistors. By configuring the PLL circuit in such a manner, both of the power consumption and the output noise are suppressed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a PLL circuit that oscillates a clock signal synchronized with a reference signal.

FIG. 5 is a configuration diagram showing a general PLL circuit (see, for example, Patent Document 1).
In the figure, a phase comparator 101 (indicated as “PFD” in the figure) compares the phase of the reference signal input from the Refin terminal with the frequency of the frequency-divided signal output from the frequency divider 105, and the frequency of the reference signal and the frequency-divided signal are divided. A process of outputting a phase comparison signal indicating the phase difference of the signals is performed.
The charge pump 102 (denoted as “CP” in the figure) performs a process of outputting a current pulse having a polarity corresponding to the phase comparison signal output from the phase comparator 101.

The loop filter 103 removes the AC wave component contained in the current pulse output from the charge pump 102 and smoothes it, and executes the process of outputting the smoothed signal as the control voltage of the voltage controlled oscillator 104.
A voltage controlled oscillator 104 (denoted as “VCO” in the figure) performs a process of oscillating a clock signal having a frequency corresponding to the control voltage output from the loop filter 103.
The frequency divider 105 divides the clock signal oscillated by the voltage controlled oscillator 104 by N, and performs processing of outputting the clock signal after N division to the phase comparator 101 as a divided signal.

Next, the operation will be described.
When the phase comparator 101 receives the reference signal from the Refin terminal and receives the frequency-divided signal output from the frequency divider 105, the phase comparator 101 compares the phase of the reference signal and the frequency-divided signal, and the reference signal and the frequency-divided signal A phase comparison signal indicating the phase difference is output to the charge pump 102.

When the charge pump 102 receives the phase comparison signal from the phase comparator 101, the charge pump 102 outputs a current pulse having a polarity corresponding to the phase comparison signal to the loop filter 103.
For example, when the phase of the reference signal is delayed from the phase of the divided signal, the phase of the reference signal and the phase of the divided signal are matched by delaying the phase of the clock signal oscillated by the voltage controlled oscillator 104. A current pulse having a negative polarity is output to the loop filter 103.
On the other hand, if the phase of the reference signal is ahead of the phase of the divided signal, the phase of the reference signal and the phase of the divided signal are matched by advancing the phase of the clock signal oscillated by the voltage controlled oscillator 104. A positive polarity current pulse is output to the loop filter 103.

When the loop filter 103 receives a current pulse from the charge pump 102, the loop filter 103 removes and smoothes the AC wave component (high-frequency component) contained in the current pulse, and the smoothed signal is controlled by the voltage control oscillator 104. Output as.
When receiving a control voltage from the loop filter 103, the voltage controlled oscillator 104 oscillates a clock signal having a frequency corresponding to the control voltage.
When the frequency divider 105 receives the clock signal from the voltage controlled oscillator 104, the frequency divider 105 divides the clock signal, for example, by N, and outputs the clock signal after N division to the phase comparator 101 as a divided signal.

Here, the block of the phase comparator 101, the charge pump 102, and the frequency divider 105 in the PLL circuit of FIG. 5 employs a logic configuration corresponding to the operating frequency.
That is, a block having a high operating frequency is configured using an ECL circuit having a bipolar transistor capable of high-speed operation or an SCL circuit having a MOS transistor.
On the other hand, a block with a low operating frequency is configured using a CMOS logic circuit that operates at low speed but consumes little power.

In a PLL circuit generally used in the RF band, the operating frequency of the frequency divider 105 is high, and the operating frequencies of the phase comparator 101 and the charge pump 102 are low.
Therefore, the frequency divider 105 is configured using an ECL circuit on which a bipolar transistor is mounted, and the phase comparator 101 and the charge pump 102 are configured using a CMOS logic circuit.
By configuring each block of the PLL circuit in this way, it is possible to suppress power consumption while ensuring the operation speed of the entire PLL circuit.

On the other hand, when the phase comparison frequency is high, as shown in FIG. 6, it is conceivable to configure all the blocks of the PLL circuit with ECL circuits.
In this case, power consumption increases, but high-speed operation is possible.

  As a contrivance for realizing low noise, a circuit that reduces the noise of the charge pump 102 by configuring the charge pump 102 using a MOS transistor is also considered. However, in the case of a MOS transistor, a bipolar transistor As compared with, flicker noise is large, so there is a limit to reducing noise.

JP 2001-111418 (paragraph numbers [0014] to [0016], FIG. 1)

Since the conventional PLL circuit is configured as described above, power consumption can be suppressed by configuring the phase comparator 101 and the charge pump 102 using a CMOS logic circuit (see FIG. 5). There were problems such as difficulty in reducing output noise.
That is, the output noise of the PLL circuit is represented by the product of the noise generated in each block and the transfer function from each block to the output. The noise of the entire PLL circuit is compared with the phase comparator 101 and the charge. Since the noise contribution of the pump 102 is large, when the phase comparator 101 and the charge pump 102 are configured using a CMOS logic circuit, the noise is significantly increased and it is difficult to suppress the output noise to be small.

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain a PLL circuit capable of suppressing both power consumption and output noise.

  The PLL circuit according to the present invention includes a phase comparator, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider. The frequency divider is configured using a CMOS logic circuit, and a bipolar transistor is mounted. A phase comparator and a charge pump are configured using the ECL circuit.

  According to the present invention, the ECL includes a phase comparator, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider, and constitutes a frequency divider using a CMOS logic circuit and is equipped with a bipolar transistor. Since the circuit includes the phase comparator and the charge pump, there is an effect that both power consumption and output noise can be suppressed.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a PLL circuit according to Embodiment 1 of the present invention. In the figure, a phase comparator 1 (indicated as “PFD” in the figure) is a reference signal input from a Refin terminal and a frequency divider. The phase of the frequency-divided signal output from 5 is compared, and a process of outputting a phase comparison signal indicating the phase difference between the reference signal and the frequency-divided signal is performed.
Here, the PLL circuit is shown with the phase comparator 1 mounted, but not only the phase of the reference signal and the divided signal is compared, but also the function of comparing the frequency of the reference signal and the divided signal. You may make it mount the phase frequency comparator with which it is equipped.
That is, the phase comparator 1 in the PLL circuit of FIG. 1 is not limited to a so-called phase comparator, but is a concept including a phase frequency comparator.

The charge pump 2 (denoted as “CP” in the drawing) performs a process of outputting a current pulse having a polarity corresponding to the phase comparison signal output from the phase comparator 1.
The loop filter 3 removes an AC wave component contained in the current pulse output from the charge pump 2 and smoothes it, and executes a process of outputting the smoothed signal as a control voltage of the voltage controlled oscillator 4.

The voltage controlled oscillator 4 (denoted as “VCO” in the figure) performs a process of oscillating a clock signal having a frequency corresponding to the control voltage output from the loop filter 3.
The frequency divider 5 divides the clock signal oscillated by the voltage controlled oscillator 4 by N, and performs a process of outputting the N-divided clock signal to the phase comparator 1 as a divided signal.

Next, the operation will be described.
When the phase comparator 1 receives the reference signal from the Refin terminal and receives the frequency-divided signal output from the frequency divider 5, the phase comparator 1 compares the phase of the reference signal and the frequency-divided signal, and the reference signal and the frequency-divided signal A phase comparison signal indicating the phase difference between the two is output to the charge pump 2.

When the charge pump 2 receives the phase comparison signal from the phase comparator 1, the charge pump 2 outputs a current pulse having a polarity corresponding to the phase comparison signal to the loop filter 3.
For example, when the phase of the reference signal is delayed from the phase of the divided signal, the phase of the reference signal and the phase of the divided signal are matched by delaying the phase of the clock signal oscillated by the voltage controlled oscillator 4. A current pulse having a negative polarity is output to the loop filter 3.
On the other hand, when the phase of the reference signal is ahead of the phase of the divided signal, the phase of the reference signal and the phase of the divided signal are matched by advancing the phase of the clock signal oscillated by the voltage controlled oscillator 4. A current pulse having a positive polarity is output to the loop filter 3.

When receiving a current pulse from the charge pump 2, the loop filter 3 removes an AC wave component (high-frequency component) contained in the current pulse and smoothes it, and converts the smoothed signal to a control voltage of the voltage controlled oscillator 4. Output as.
When receiving a control voltage from the loop filter 3, the voltage controlled oscillator 4 oscillates a clock signal having a frequency corresponding to the control voltage.
When the frequency divider 5 receives the clock signal from the voltage controlled oscillator 4, the frequency divider 5 divides the clock signal, for example, by N, and outputs the clock signal after the N frequency division to the phase comparator 1 as a divided signal.

Here, the frequency divider 5 in the PLL circuit of FIG. 1 is configured by using a CMOS logic circuit, and the phase comparator 1 and the charge pump 2 are configured by using an ECL circuit in which a bipolar transistor is mounted. .
In this case, the bottleneck of the operating frequency of the PLL circuit is the frequency divider 5 configured using a CMOS logic circuit.
However, by using a fine-process MOS transistor, a frequency dividing operation can be performed even in a high frequency region.
The noise characteristic is higher than that of a frequency divider using a bipolar transistor, but due to the characteristic of a block called a frequency divider, the contribution of noise to the entire PLL circuit is small.

On the other hand, since the phase comparator 1 and the charge pump 2 are configured using an ECL circuit equipped with a bipolar transistor, the noise characteristics are good.
For the above reasons, when considering the overall characteristics of the PLL circuit, it is possible to realize a PLL circuit with low power consumption and low output noise.

  As apparent from the above, according to the first embodiment, the phase comparator 1, the charge pump 2, the loop filter 3, the voltage controlled oscillator 4 and the frequency divider 5 are provided, and a CMOS logic circuit is used. Since the phase comparator 1 and the charge pump 2 are configured by using the ECL circuit that constitutes the frequency divider 5 and that includes a bipolar transistor, it is possible to suppress both power consumption and output noise. Play.

Embodiment 2. FIG.
FIG. 2 is a block diagram showing a PLL circuit according to Embodiment 2 of the present invention. In the figure, the same reference numerals as those in FIG.
The frequency divider 6 divides the clock signal oscillated by the voltage controlled oscillator 4 by 2, and performs a process of outputting the clock signal after the frequency division.
The frequency divider 7 divides the frequency-divided clock signal output from the frequency divider 6 by N / 2 and outputs the frequency-divided clock signal to the phase comparator 1 as a frequency-divided signal. To implement.

In the first embodiment, the frequency divider 5 configured using the CMOS logic circuit is mounted. However, as shown in FIG. 2, when the frequency divider has a two-stage configuration, A frequency divider 6 that is a first-stage frequency divider is configured using an ECL circuit equipped with a bipolar transistor, and a frequency divider 7 that is a second-stage frequency divider is configured using a CMOS logic circuit. Also good.
However, in FIG. 2, an example in which the frequency divider 6 that is a frequency divider in the previous stage divides the clock signal by 2, and the frequency divider 7 that is a frequency divider in the subsequent stage divides the clock signal by N / 2. However, this is only an example, and the frequency dividers 6 and 7 may perform other frequency divisions.

  In the PLL circuit of FIG. 2, compared to the PLL circuit of FIG. 1, a part of the frequency divider (the previous frequency divider 6) is configured using an ECL circuit in which a bipolar transistor is mounted. Although the power is increased, a higher speed operation can be realized.

In the second embodiment, the example in which the frequency divider 6 in the previous stage divides the clock signal oscillated by the voltage controlled oscillator 4 by 2 has been shown. For example, the prescaler in the previous stage of the pulse swallow type frequency divider is used in the previous stage. The case where it is regarded as the frequency divider 6 is also included.
In such a case, in addition to the signal path from the previous frequency divider 6 to the subsequent frequency divider 7, a feedback path from the subsequent frequency divider 7 to the previous frequency divider 6 is also added.

  As is apparent from the above, according to the second embodiment, when the frequency divider is a frequency divider having a two-stage configuration, the subsequent-stage frequency divider 7 is configured by using a CMOS logic circuit, and the bipolar transistor. Since the previous stage frequency divider 6, the phase comparator 1, and the charge pump 2 are configured using the ECL circuit equipped with the above-described circuit, the power consumption is larger than that in the first embodiment, but the speed is higher. The effect which can implement | achieve an operation | movement is show | played.

Embodiment 3 FIG.
FIG. 3 is a block diagram showing a PLL circuit according to Embodiment 3 of the present invention. In the figure, the same reference numerals as those in FIG.
In the first embodiment, the PLL circuit includes the phase comparator 1, the charge pump 2, the loop filter 3, the voltage controlled oscillator 4, and the frequency divider 5. However, as shown in FIG. The circuit may be composed of the phase comparator 1, the loop filter 3, the voltage controlled oscillator 4 and the frequency divider 5 without mounting the charge pump 2.

The PLL circuit of FIG. 3 can be applied, for example, when the phase comparator 1 is a voltage output type phase comparator and the loop filter 3 is configured using an active element.
The PLL circuit of FIG. 3 also has the effect of suppressing both power consumption and output noise, as in the first embodiment.

  3 shows a configuration in which the charge pump 2 in the PLL circuit in FIG. 1 is omitted, but as shown in FIG. 4, the configuration in which the charge pump 2 in the PLL circuit in FIG. 2 is omitted. Also good.

Embodiment 4 FIG.
In the first embodiment, as the low-noise circuit, the ECL circuit including the bipolar transistor is used to configure the phase comparator 1 and the charge pump 2 (see FIG. 1). The phase comparator 1 and the charge pump 2 may be configured by using a CML circuit having a MOS transistor instead of an ECL circuit having a bipolar transistor.
Also in this case, as in the first embodiment, there is an effect that both power consumption and output noise can be suppressed.
Note that this configuration is effective in a CMOS process in which bipolar transistors cannot be used.

  In the second embodiment, as the low-noise circuit, an ECL circuit equipped with a bipolar transistor is used to constitute the previous-stage frequency divider 6, phase comparator 1 and charge pump 2. As shown (see FIG. 2), instead of an ECL circuit having a bipolar transistor, a CML circuit having a MOS transistor is used, and the frequency divider 6, the phase comparator 1 and the charge pump in the previous stage are used. 2 can be configured, and the same effect as in the second embodiment can be obtained.

  In the third embodiment, the low-noise circuit includes the phase comparator 1 using an ECL circuit equipped with a bipolar transistor (see FIG. 3). The phase comparator 1 may be configured using a CML circuit mounting a MOS transistor instead of an ECL circuit mounting a transistor, and the same effect as in the third embodiment can be obtained. .

  Further, in the third embodiment, as the low noise circuit, an ECL circuit equipped with a bipolar transistor is used to constitute the previous-stage frequency divider 6 and phase comparator 1 ( 4), the frequency divider 6 and the phase comparator 1 in the previous stage may be configured by using a CML circuit having a MOS transistor instead of an ECL circuit having a bipolar transistor. The same effects as in the third embodiment can be obtained.

1 is a configuration diagram illustrating a PLL circuit according to a first embodiment of the present invention. It is a block diagram which shows the PLL circuit by Embodiment 2 of this invention. It is a block diagram which shows the PLL circuit by Embodiment 3 of this invention. It is a block diagram which shows the PLL circuit by Embodiment 3 of this invention. It is a block diagram which shows a general PLL circuit. It is a block diagram which shows a general PLL circuit.

Explanation of symbols

  1 phase comparator, 2 charge pump, 3 loop filter, 4 voltage controlled oscillator, 5 frequency divider, 6 previous frequency divider, 7 subsequent frequency divider, 101 phase comparator, 102 charge pump, 103 loop filter, 104 Voltage controlled oscillator, 105 divider.

Claims (8)

  A phase comparator that compares the phases of the reference signal and the frequency-divided signal and outputs a phase comparison signal indicating a phase difference between the reference signal and the frequency-divided signal, and a phase comparison signal output from the phase comparator A charge pump that outputs a current pulse of polarity, a loop filter that removes and smoothes an AC wave component contained in the current pulse output from the charge pump, and outputs a smoothed signal; and the loop filter A voltage-controlled oscillator that oscillates a clock signal having a frequency corresponding to the smoothing signal output from the frequency divider, divides the clock signal oscillated by the voltage-controlled oscillator, and uses the divided clock signal as a divided signal. In a PLL circuit including a frequency divider that outputs to a phase comparator, the frequency divider is configured using a CMOS logic circuit and a bipolar transistor is mounted. Using an ECL circuit, PLL circuit, characterized by constituting the phase comparator and the charge pump.   A phase comparator that compares the phases of the reference signal and the frequency-divided signal and outputs a phase comparison signal indicating a phase difference between the reference signal and the frequency-divided signal, and a phase comparison signal output from the phase comparator A charge pump that outputs a current pulse of polarity, a loop filter that removes and smoothes an AC wave component contained in the current pulse output from the charge pump, and outputs a smoothed signal; and the loop filter A voltage-controlled oscillator that oscillates a clock signal having a frequency corresponding to the smoothing signal output from the frequency divider, divides the clock signal oscillated by the voltage-controlled oscillator, and uses the divided clock signal as a divided signal. In a PLL circuit having a frequency divider that outputs to a phase comparator, when the frequency divider is a frequency divider having a two-stage configuration, a CMOS logic circuit is used to Form, using the ECL circuit mounted with the bipolar transistor, the front stage of the frequency divider, PLL circuit, characterized by constituting the phase comparator and the charge pump.   Included in the phase comparator that compares the phase of the reference signal and the divided signal and outputs a phase comparison signal indicating the phase difference between the reference signal and the divided signal, and the phase comparison signal output from the phase comparator A loop filter that removes and smoothes alternating current wave components and outputs a smoothed signal, and a voltage-controlled oscillator that oscillates a clock signal having a frequency corresponding to the smoothed signal output from the loop filter, A PLL circuit including a frequency divider that divides a clock signal oscillated by the voltage controlled oscillator and outputs the divided clock signal to the phase comparator as a divided signal, using a CMOS logic circuit. A PLL circuit comprising the phase comparator using an ECL circuit comprising the frequency divider and mounting a bipolar transistor.   Included in the phase comparator that compares the phase of the reference signal and the divided signal and outputs a phase comparison signal indicating the phase difference between the reference signal and the divided signal, and the phase comparison signal output from the phase comparator A loop filter that removes and smoothes alternating current wave components and outputs a smoothed signal, and a voltage-controlled oscillator that oscillates a clock signal having a frequency corresponding to the smoothed signal output from the loop filter, A PLL circuit comprising a frequency divider that divides a clock signal oscillated by the voltage controlled oscillator and outputs the divided clock signal as a divided signal to the phase comparator. In the case of a stage-configured frequency divider, a CMOS logic circuit is used to form a subsequent-stage frequency divider, and an ECL circuit equipped with a bipolar transistor is used to form a previous-stage frequency divider and the phase comparator. PLL circuit, characterized by being configured.   2. The PLL circuit according to claim 1, wherein a phase comparator and a charge pump are configured by using a CML circuit having a MOS transistor instead of an ECL circuit having a bipolar transistor.   The frequency divider, the phase comparator, and the charge pump of the previous stage are configured using a CML circuit having a MOS transistor instead of an ECL circuit having a bipolar transistor. The PLL circuit according to 2.   4. The PLL circuit according to claim 3, wherein a phase comparator is configured using a CML circuit having a MOS transistor mounted therein instead of an ECL circuit having a bipolar transistor mounted thereon.   5. The frequency divider and the phase comparator of the previous stage are configured by using a CML circuit mounting a MOS transistor instead of an ECL circuit mounting a bipolar transistor. PLL circuit.

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