JP2017169109A - Clock generation circuit and clock generation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock generator circuit which is arranged so as to cover a wide band width while factoring in EMI, and which is capable of suppressing jitter because of small noise influence thereon and adequate responsiveness.SOLUTION: A clock generator circuit comprises: a spread-spectrum clock generator which performs frequency modulation on a reference clock generated by an oscillator; and a PLL circuit which generates an output clock according to the reference clock subjected to the frequency modulation and outputs the clock. In the clock generator circuit, the PLL circuit includes an oscillating frequency control part which controls an oscillating frequency of the output clock according to a value of a driving current input thereto; and the value of the driving current to the oscillating frequency control part is changed based on a predetermined count signal to perform the frequency modulation on the reference clock.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a clock generation technique, and more particularly to a clock generation circuit adapted for a spread spectrum function and a clock generation method using the same.

  The clock generation circuit is a circuit that generates a clock signal (hereinafter referred to as “clock”) necessary for the operation of an electronic device including a logic circuit such as a microprocessor. Typically, a PLL (Phase Locked Loop) circuit is used as the clock generation circuit. Consists of.

  A PLL circuit typically generates and outputs an output clock multiplied based on a clock having a reference frequency (reference clock), and the phase of the clock (feedback clock) that feeds back the output clock is The frequency negative feedback circuit generates the output clock so as to be synchronized with the phase of the reference clock. The PLL circuit typically includes a phase detection circuit, a charge pump, a loop filter, and a voltage controlled oscillator (VCO). In such a PLL circuit, the capacitor of the loop filter is charged / discharged by the output signal (current signal or voltage signal) from the charge pump, and the oscillation frequency of the output clock generated by the VCO is determined according to the change in the integrated value. Is done.

  As an improvement of such a conventional PLL circuit, a PLL circuit that includes two charge pumps and determines the oscillation frequency of the output clock by controlling the output of each charge pump according to different operating characteristics is known.

  For example, Patent Document 1 below discloses a PLL circuit in which a charge pump unit is divided into two parts, an integration unit and a phase control unit. Specifically, the PLL circuit of Patent Document 1 includes a phase frequency comparator that compares the phase and frequency of an external input signal and a feedback signal, and the output signal in accordance with the comparison result from the phase frequency comparator. An integrator for generating a current for controlling the oscillation frequency, and a phase for controlling the phase of the output signal in accordance with a comparison result from the phase frequency comparator so that a phase difference from the input signal is reduced. A phase control unit, a current control oscillator that generates the output signal that oscillates at a frequency corresponding to a current value obtained by adding the current generated by the phase control unit to the current generated by the integration unit, and the current control And a feedback frequency divider that divides the output signal from the oscillator and feeds back as a feedback signal to the phase frequency comparator.

  By the way, the higher frequency of the clock based on the demand for speeding up of the electronic device has an influence of electromagnetic interference (EMI) on the LSI itself, its peripheral circuits, other electronic devices, etc. SSCG (Spread Spectrum Clock Generator) technology for effectively reducing the above can be applied to the PLL circuit.

  The SSCG technology is a clock generation technology to which a spread spectrum function is added. Specifically, the SSCG technology modulates the clock frequency so that the spectrum of EMI energy radiated by an electronic device or the like is not concentrated in a specific frequency band, and thereby the EMI energy is set to a predetermined frequency band. Disperse and suppress its peak value. The spread spectrum function is realized by a digital circuit using a delay circuit, for example.

JP 2001-119296 A

  In general, in a PLL circuit, if the bandwidth of the loop filter is selected to be narrow in consideration of jitter suppression on the output clock, the response of the VCO becomes slower with respect to the phase detector and the charge pump, and the phase There is a problem that the follow-up performance to synchronization is lowered. On the other hand, if a loop filter having a wide bandwidth is selected in consideration of the responsiveness of the VCO, it is not possible to suppress jitter. Instead, there is a problem that it is expensive to use a reference clock with high frequency accuracy. In particular, in order to cover a wide bandwidth (for example, 1 to 4 GHz or more), it is necessary to increase the gain of the VCO, but this causes the VCO to change the oscillation frequency even with a slight noise. Therefore, it is necessary to consider the problem of jitter more.

  In such a situation, the PLL circuit disclosed in Patent Document 1 described above is configured to input the outputs of the two charge pumps to separate loop filters, but the bandwidth of the loop filter is not considered at all. It was not intended to improve jitter.

  In addition, when the spread spectrum function is applied to the PLL circuit in consideration of EMI, the frequency of the reference clock changes sequentially, so that the VCO is required to have high responsiveness. Therefore, a loop filter with a wide bandwidth is required. As a result, the jitter cannot be suppressed as described above.

  Therefore, there is a demand for a PLL circuit or a clock generation circuit that covers a wide bandwidth, considers EMI, has low noise influence, has good response, and can suppress jitter.

  Accordingly, an object of the present invention is to provide a clock generation circuit and a clock generation method that can cover a wide bandwidth, have low noise influence, have good responsiveness, and can suppress jitter while considering EMI. .

  More specifically, an object of the present invention is to provide a clock generation circuit and a clock generation method capable of separating and controlling the bandwidth and gain in a PLL circuit in a balanced manner while adapting the spread spectrum function.

  Further, the present invention suppresses the phase shift between the reference clock and the feedback clock that occurs when the spread spectrum function is applied to such a separable control clock generation circuit, thereby generating a clock that can suppress jitter. An object is to provide a circuit and a clock generation method.

  The present invention for solving the above-described problems is configured to include the following invention specific items or technical features.

  That is, an invention according to a certain aspect includes a spread spectrum clock oscillator that performs frequency modulation on a standard clock generated by an oscillator and generates a reference clock, and a PLL circuit that generates and outputs an output clock according to the reference clock. This is a clock generation circuit. In this clock generation circuit, the PLL circuit includes an oscillation frequency control unit that controls the oscillation frequency of the output clock according to the value of the input drive current. The drive current includes the reference clock and the output clock. The first output current is controlled based on the accumulation of the current output from the first charge pump driven by a signal based on the phase difference from the feedback clock obtained by dividing the feedback clock, and is driven in the same manner as the first charge pump. A second output current obtained by subtracting a current output from the second charge pump from an offset current that changes based on a predetermined count signal for frequency modulation with respect to the standard clock.

  Here, the offset current may increase as the frequency of the reference clock increases, and may decrease as the frequency decreases.

  Further, the offset current generating unit that generates the offset current, the offset current generating unit, a current mirror unit including a multi-stage current mirror circuit including a plurality of mirror transistors, and according to the count signal, A decoding circuit that determines a mirror ratio of a multi-stage current mirror circuit and changes a value of the offset current.

  The PLL circuit may include the first charge pump and include an integration unit that generates the first output current, and a proportional unit that includes the second charge pump and generates the second output current. .

  The offset current generation unit includes a calibration unit that calibrates the output of the current mirror unit, and the calibration unit receives the reference clock and the feedback when the PLL circuit receives the reference clock. In accordance with a signal based on a phase difference from a clock, a change coefficient that is the number of the mirror transistors whose operation is changed every time the value of the count signal changes by the decode circuit can be determined.

  The PLL circuit outputs an up signal when the phase of the feedback clock is delayed with respect to the reference clock, and outputs a down signal when the phase of the feedback clock is advanced with respect to the reference clock. A phase detection circuit that outputs the initial value of the change coefficient until the number of the down signals exceeds the number of the up signals when the PLL circuit receives the reference clock. After increasing the number of down signals by more than a predetermined value from the value and subtracting the predetermined value from the current value of the change coefficient after the number of down signals exceeds the number of up signals, the final value of the change coefficient Can be determined.

  The PLL circuit outputs an up signal when the phase of the feedback clock is delayed with respect to the reference clock, and outputs a down signal when the phase of the feedback clock is advanced with respect to the reference clock. A phase detection circuit that outputs the initial value of the change coefficient until the number of the down signals exceeds the number of the up signals when the PLL circuit receives the reference clock. By increasing the value by a predetermined value and after the number of the down signals exceeds the number of the up signals, by using a predetermined method, calculating a value after the decimal point from the current value of the change coefficient, The final value of the change factor can be determined.

  An invention according to a certain aspect includes a spread spectrum clock oscillator that performs frequency modulation on a standard clock generated by an oscillator and generates a reference clock, and a PLL circuit that generates and outputs an output clock according to the reference clock. This is the clock generation method used. In this clock generation method, the drive current is controlled based on the accumulation of the current output from the first charge pump driven by the signal based on the phase difference between the reference clock and the feedback clock obtained by dividing the reference clock. From an offset current that changes a first output current and a current output from a second charge pump driven in the same manner as the first charge pump based on a predetermined count signal for frequency modulation with respect to the standard clock Generating by the reduced second output current, and inputting the drive current to an oscillation frequency control unit that is provided in the PLL and controls the oscillation frequency of the output clock according to the input current value. ,including.

  According to the present invention, while considering EMI, a wide bandwidth is covered, the influence of noise is low, responsiveness is good, and jitter can be suppressed.

It is a block diagram for demonstrating a split tune type PLL circuit. It is a block diagram for demonstrating the clock generation circuit which applied SSCG to a split tune type PLL circuit. It is a block diagram which shows an example of a structure of SSCG which concerns on one Embodiment of this invention. 6 is a timing chart of various signals in a PPL circuit of a clock generation circuit in which SSCG is applied to a split tune type PLL circuit. It is a block diagram for demonstrating the clock generation circuit which concerns on one Embodiment of this invention. 4 is a block diagram for explaining an offset current generation unit of the clock generation circuit according to the embodiment of the present invention. 6 is a flowchart showing a calibration method of the decoding circuit by the calibration unit in the clock generation circuit according to the embodiment of the present invention. It is a figure which shows an example of the relationship between the reference clock at the time of calibration of the decoding circuit in the clock generation circuit which concerns on one Embodiment of this invention, and a feedback clock. It is a figure which shows an example of the relationship between the count signal in the clock generation circuit which concerns on one Embodiment of this invention, and the frequency of a reference | standard clock. It is a figure which shows an example of the relationship between the count signal in the clock generation circuit which concerns on one Embodiment of this invention, and the number of the auxiliary | assistant mirror transistors to operate. It is a table explaining an example of the selection signal SEL which the decoding circuit in the clock generation circuit concerning one embodiment of the present invention generates. 5 is a flowchart illustrating a clock generation method according to an embodiment of the present invention. 4 is a timing chart of various signals in the clock generation circuit according to the embodiment of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude various modifications and technical applications that are not explicitly described below. The present invention can be implemented with various modifications (for example, by combining the embodiments) without departing from the spirit of the present invention. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. The drawings are schematic and do not necessarily match actual dimensions and ratios. In some cases, the dimensional relationships and ratios may be different between the drawings.

  First, the basic principle of a split tune type PLL circuit (hereinafter referred to as an ST type PLL circuit) used in the clock generation circuit according to the present invention will be described. FIG. 1 is a block diagram for explaining an example of the configuration of an ST-type PLL circuit. An ST-type PLL circuit is generally a PLL circuit that includes two charge pumps and determines the oscillation frequency of an output clock by controlling the output of each charge pump according to different operating characteristics. Hereinafter, the ST-type PLL circuit is simply referred to as a PLL circuit unless particularly distinguished.

  That is, as shown in the figure, the PLL circuit 20 includes, for example, a phase detection circuit (PFD) 21, an integration unit 22, a proportional unit 23, an offset current generation unit 24, an oscillation frequency control unit 25, and a buffer. 26 and a frequency divider 27. The PLL circuit 20 is supplied with a reference clock REFCLK having a reference frequency from an oscillation source (not shown).

  The phase detection circuit 21 compares the reference clock REFCLK supplied from a predetermined oscillator (not shown) and the feedback clock FBCLK supplied from the frequency divider 27 to detect the phase difference, and the phase difference corresponding to the phase difference is detected. Output a signal. Specifically, when the phase of the feedback clock FBCLK is delayed with respect to the reference clock REFCLK, the phase detection circuit 21 generates an up signal UP having a pulse width corresponding to the phase difference. On the other hand, when the phase of the feedback clock FBCLK is advanced with respect to the reference clock REFCLK, the phase detection circuit 21 generates a down signal DN having a pulse width corresponding to the phase difference. The generated up signal UP or down signal DN is supplied to the first charge pump 221 of the integrating unit 22 and the second charge pump 231 of the proportional unit 23, respectively.

The integration unit 22 includes, for example, a first charge pump 221, a loop filter 222, and a transistor 223. The integration unit 22 generates a charge pump current based on either the up signal UP or the down signal DN from the phase detection circuit 21, and the first output current I _INT controlled based on the accumulated value of the charge pump current. Is output to the oscillation frequency control unit 25.

The first charge pump 221 outputs a current corresponding to the up signal UP and the down signal DN supplied from the phase detection circuit 21. Specifically, when the up signal UP is supplied from the phase detection circuit 21, the first charge pump 221 outputs a first charge pump current I _{cp —} I having a value larger by a unit current value, while the phase detection circuit 21. When the down signal DN is supplied, the first charge pump current _{Icp_I} having a value smaller by the unit current value is output.

The loop filter 222 is a low-pass filter circuit that stabilizes the operation of the PLL circuit 20 and determines its loop bandwidth, and includes a capacitor 222a, for example. For example, one terminal of the capacitor 222a is connected to the charge pump, and the other terminal is grounded. As a result, the capacitor 222a is supplied with the first charge pump current I _{cp_I} output from the first charge pump 221. Therefore, the output voltage of the capacitor 222a changes according to the increase / decrease of the first charge pump current I _{cp_I.} Will be.

The transistor 223 is, for example, a P-channel MOSFET, its gate terminal is connected to the output terminal of the loop filter 222, its drain terminal is connected to the power supply, and its source terminal is connected to the oscillation frequency control unit 25. Accordingly, the transistor 223 outputs the first output current I _INT corresponding to the output voltage of the capacitor 222a.

The proportional unit 23 includes, for example, a second charge pump 231, a transistor 232, and a transistor 233. The proportional unit 23 outputs a second output current corresponding to the difference between the constant offset current I _OFFSET generated by the offset current generating unit 24 and the second charge pump current I _{cp — p} corresponding to the phase difference signal from the phase detection circuit 21. and outputs the I _P. That is, the proportional unit 23 outputs the second output current I _P based on the second charge pump current I _{cp — p} proportional to the phase difference signal only when the second charge pump 231 is operated by the phase difference signal from the phase detection circuit 21. Is output to the oscillation frequency control unit 25.

Similar to the first charge pump 221, the second charge pump 231 outputs a current corresponding to either the up signal UP or the down signal DN supplied from the phase detection circuit 21. Specifically, when the up signal UP is supplied from the phase detection circuit 21, the second charge pump 231 outputs the second charge pump current I _{cp — p} having a value larger by the unit current value, while the phase detection circuit 21. Is supplied with the down signal DN, the second charge pump current _{Icp_p} having a value smaller by the unit current value is output.

The transistor 232 is, for example, a P-channel MOSFET, its gate terminal is connected to the second charge pump 231, its drain terminal is connected to the power supply, and its source terminal is the offset current generator 24 (that is, the drain terminal of the transistor 243). ). Further, the gate terminal and the source terminal of the transistor 232 are connected. Therefore, a differential current between the offset current I _OFFSET drawn by the offset current generation unit 24 and the second charge pump current I _{cp_p} flows through the source terminal of the transistor 232.

The transistor 233 is, for example, a P-channel MOSFET, and has a gate terminal connected to the gate terminal of the transistor 232, a drain terminal connected to the power supply, and a source terminal connected to the oscillation frequency control unit 25. The gate terminal of the transistor 233 is connected to the gate terminal of the transistor 232. That is, the transistor 233 functions as a current mirror circuit in combination with the transistor 232. Thus, the transistor 233 outputs the second output current _{I P} corresponding to the differential current flowing through the transistor 232.

The offset current generator 24 includes, for example, a current mirror circuit that includes a current source 241, a transistor 242, and a transistor 243. That is, the offset current generator 24 operates to draw the mirror current of the current I _REF supplied from the current source 241 from the proportional unit 23 as the offset current I _OFFSET . The transistors 242 and 243 are, for example, N-channel MOSFETs.

The oscillation frequency control unit 25 is a circuit that controls the oscillation frequency of the output signal in accordance with the input current. In this example, the oscillation frequency control unit 25 is a ring oscillator in which a plurality of stages of inverter elements are connected in a ring shape, but is not limited thereto. That is, the oscillation frequency control unit 25, based on the value of the combined current of the second output current I _P which is output from the first output current I _INT proportional portion 23 which is output from the integrating unit 22, the oscillation of the output signal Control the frequency. For example, the oscillation frequency control unit 25 is designed so that the oscillation frequency increases as the input current value increases. The oscillation frequency control unit 25 outputs a signal whose oscillation frequency is controlled, for example, to the buffer 26.

  The buffer 26 is a buffer circuit provided at the output stage of the oscillation frequency control unit 25, for example, from the viewpoint of circuit operation stability. An output signal output from the oscillation frequency control unit 25 is output to the outside and output to the frequency divider 27 as an output clock CLK via the buffer 26.

  The frequency divider 27 is a frequency dividing circuit that divides the frequency of the output clock CLK by a predetermined dividing ratio N. That is, the frequency divider 27 outputs the output clock divided by a predetermined frequency division ratio N to the phase detection circuit 21 as the feedback clock FBCLK. Thereby, the PLL circuit 20 can function as a frequency synthesizer. The frequency divider 27 may be configured so that the predetermined frequency division ratio N can be set to an arbitrary value.

  In the ST-type PLL circuit 20 as described above, the integrating unit 22 can be set so that the gain of the PLL circuit 20 is large and the bandwidth thereof is small, while the proportional unit 23 is small in gain. Since the bandwidth can be set to be large, the gain and the bandwidth can be controlled separately, and an improvement in jitter is expected as compared with a normal PLL circuit.

  FIG. 2 is a block diagram showing an example of the configuration of a clock generation circuit in which a spread spectrum clock oscillator is applied to the PLL circuit described above. That is, as shown in the figure, a spread spectrum clock oscillator (hereinafter referred to as “SSCG”) 10 that outputs the reference clock REFCLK while performing frequency modulation for spread spectrum is provided in the preceding stage of the PLL circuit 20. .

  FIG. 3 is a block diagram showing an example of the configuration of the SSCG according to an embodiment of the present invention. As shown in the figure, the SSCG 10 includes, for example, an oscillator 11, a counter 12, and a variable delay control circuit 13. The SSCG 10 of the present embodiment is configured to perform frequency modulation in accordance with, for example, a triangular wave shaped modulation profile.

  The oscillator 11 is a reference oscillation circuit including a crystal resonator, for example, and generates a standard clock SCLK having a fixed reference oscillation frequency. For example, the counter 12 counts rising edges due to alternating of the standard clock SCLK supplied from the oscillator 11, generates a selection signal corresponding to the count value, and outputs the selection signal to the variable delay control circuit 13. The variable delay control circuit 13 includes, for example, a plurality of stages of delay elements 131 and a selector 132 connected in series. The delay element 131 delays the input standard clock SCLK by, for example, 1/2 clock. The selector 132 receives the output of the delay element 131 at each stage as an input, selects one input according to the selection signal output from the counter 12, and outputs it as the reference clock REFCLK. That is, the counter 12 generates a selection signal for selecting the number of delay elements according to the count value according to the modulation profile, and the variable delay control circuit generates the standard clock SCLK to which a predetermined delay time is given according to the selection signal. Is output as the reference clock REFCLK. Here, the period of the standard clock SCLK given the delay time by the delay element 131 in the center stage is set as the reference period T.

  With the configuration as described above, the SSCG 10 performs frequency modulation (periodic modulation) of the output reference clock REFCLK by giving a predetermined delay amount corresponding to the number of alternating times of the standard clock SCLK to the generated standard clock SCLK. Realize.

  FIG. 4 is a timing chart of various signals in the PLL circuit 20 of the clock generation circuit shown in FIG. More specifically, this figure shows jitter generated in the PLL circuit 20 that operates based on the reference clock REFCLK in which frequency modulation for spread spectrum is performed. As shown in the figure, at a certain time point t0, the reference clock REFCLK, which is the reference period T, is frequency-modulated so as to become longer by the delay time D for each period.

In the case of the clock generation circuit shown in FIG. 2, in the PLL circuit 20, the integration unit 22 can hardly follow the frequency modulation of the reference clock REFCLK due to the narrow bandwidth of the integration unit 22. On the other hand, the proportional unit 23 having a wide bandwidth operates so as to follow the frequency modulation of the reference clock REFCLK. In Such oscillation frequency control unit 25 is to control the oscillation frequency based on the value of the second output current I _P according to the proportional unit 23, after all, following for frequency modulation of the reference clock REFCLK is not sufficient, the reference clock A phase shift (phase advance in this example) occurs between REFCLK and the feedback clock FBCLK.

Such a phase shift between the reference clock REFCLK and the feedback clock FBCLK is detected by the phase detection circuit 21, and a down signal DN is output from the phase detection circuit 21. As described above, the proportional unit 23 outputs the second charge pump current I _{cp_p} only during the period when the phase difference signal is output from the phase detection circuit 21, and thereby the second charge pump current I _{cp_p} is supplied to the oscillation frequency control unit 25. the magnitude of the second output current I _P is determined. Furthermore, the oscillation frequency control unit 25, and generates an output clock CLK according to the value of such a second output current I _P. That is, during the period in which the down signal DN is output from the phase detection circuit 21, the oscillation frequency control unit 25 adjusts the output clock CLK to delay the phase by a time ΔT with respect to one cycle of the reference clock REFCLK. Try to. Such a phase shift corresponding to the time ΔT due to the follow-up operation of the proportional unit 23 eventually appears as jitter that cannot be ignored with respect to the output clock CLK.

  As described above, the clock generation circuit in which the SSCG 10 is simply applied to the preceding stage of the PLL circuit 20 faces a problem that jitter that cannot be ignored is superimposed on the output clock CLK.

  Therefore, in the following embodiments, a clock generation circuit and a clock generation method are proposed in which SSCG is applied to the previous stage of the ST-type PLL circuit, which can reduce jitter superimposed on the output clock CLK.

  That is, according to the present embodiment, in the clock generation circuit in which SSCG is applied to the previous stage of the ST type PLL circuit, the offset current in the proportional part of the ST type PLL circuit is dynamically controlled in accordance with the frequency modulation with respect to the reference clock REFCLK. A clock generation circuit and a clock generation method configured as described above are disclosed.

  FIG. 5 is a block diagram for explaining a clock generation circuit according to an embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same component as the component mentioned above in the figure.

  As shown in the figure, the clock generation circuit 500 includes an SSCG 10 and a PLL circuit 510.

  SSCG 10 may have the same configuration as that shown in FIG. 3 except that count signal COUNT indicating the count value of counter 12 is output to PLL circuit 510. Note that the count signal COUNT is counted up by one per clock of the standard clock SCLK, for example, and reset to 0 when it reaches 4n.

  The PLL circuit 510 is a split-tune type PLL circuit. For example, the phase detection circuit 21, the integration unit 22, the proportional unit 23, the offset current generation unit 512, the oscillation frequency control unit 25, the buffer 26, And a frequency divider 27. The components of the PLL circuit 510 are the same as those of the PLL circuit 20 described above except for the offset current generation unit 512, and thus the description thereof is omitted.

The offset current generator 512 includes a reference clock REFCLK output from the SSCG 10, a count signal COUNT output from the counter 12 of the SSCG 10, and a phase difference signal (that is, an up signal UP or a down signal DN) from the phase detection circuit 21. Based on the above, an offset current I _OFFSET (n) is generated. Further, the offset current generation unit 512 supplies the generated offset current I _OFFSET (n) to the proportional unit 23 (that is, the source terminal of the transistor 232), and the proportional unit 23 receives the second current from the offset current I _OFFSET (n). The second output current I _{P obtained} by subtracting the charge pump current I _{cp — p} is output. Details of the offset current generator 512 will be described later.

  FIG. 6 is a block diagram for explaining an offset current generation unit of the clock generation circuit according to the embodiment of the present invention. As shown in the figure, the offset current generation unit 512 includes, for example, a flip-flop circuit 5121, a decode circuit 5122, a current mirror unit 5123, and a calibration unit 5124.

  The flip-flop circuit 5121 is a so-called D-type flip-flop, and latches and outputs the count signal COUNT in accordance with the reference clock REFCLK.

  The decode circuit 5122 decodes the count signal COUNT output from the flip-flop circuit 5121, thereby generating and outputting a predetermined selection signal SEL for controlling on / off of the switch 605 of the current mirror unit 5123. .

The current mirror unit 5123 is, for example, a multistage current mirror circuit that includes a current source 601, a transistor 602, a main mirror transistor 603, a plurality of auxiliary mirror transistors 604, and a plurality of switches 605. That is, the current mirror unit 5123 uses a mirror current determined by the total number of the main mirror transistor 603 and the operating auxiliary mirror transistor 604 with respect to the current I _REF supplied from the current source 601 as an offset current I _OFFSET (n). , Operates so as to be pulled in from the proportional portion 23. The transistor 602, the main mirror transistor 603, and the auxiliary mirror transistor 604 are, for example, N-channel MOSFETs. Each switch 605 is disposed between the gate terminal of the transistor 602 and the gate terminal of each auxiliary mirror transistor 604.

  The calibration unit 5124 obtains a calibration value for calibrating the current mirror unit 5123 at the time of the first operation, for example. Specifically, the calibration unit 5124 generates a calibration signal CAL based on, for example, the count signal COUNT, the reference clock REFCLK, the up signal UP, and the down signal DN output from the flip-flop circuit 5121. The data is output to the decode circuit 5122.

FIG. 7A is a flowchart illustrating a decoding circuit calibration method by the calibration unit in the clock generation circuit according to an embodiment of the present invention. Note that the calibration of the decoding circuit 5122 by the calibration unit 5124 is performed, for example, for the initial operation of the clock generation circuit 500 in order to set the offset current I _OFFSET (n) generated in the offset current generation unit 512 to an appropriate value. It is executed at times.

  As shown in the figure, the calibration unit 5124 generates a calibration signal CAL that sets the value of the change coefficient α in the decoding circuit 5122 to an initial value (eg, “1”), and outputs it to the decoding circuit 5122 (S701). ). Here, the change coefficient α indicates the number of auxiliary mirror transistors 604 whose operation state is changed by the decode circuit 5122 per one value of the count signal COUNT (that is, per one clock of the reference clock REFCLK). That is, when the value of the change coefficient α is 1, the decoding circuit 5122 outputs the selection signal SEL so that the number of the auxiliary mirror transistors 604 that are operated changes by one when the value of the count signal COUNT changes by one. And the current mirror unit 5123 is operated. Note that the decode circuit 5122 decreases the number of auxiliary mirror transistors 604 that operate each time the value of the count signal COUNT changes by the value of the change coefficient α as the cycle of the reference clock REFCLK increases. Further, the decode circuit 5122 increases the number of auxiliary mirror transistors 604 that are operated each time the value of the count signal COUNT changes by the value of the change coefficient α when the cycle of the reference clock REFCLK is shortened.

  Subsequently, the SSCG 10 creates a reference clock REFCLK and supplies it to the PLL circuit 510 (S702). At the time of executing this calibration, the SSCG 10 creates the reference clock REFCLK so as to be longer from the reference period T by the time D every period. For example, the number of reference clocks REFCLK created by the SSCG 10 is five as shown in FIG. This corresponds to a period in which the value of the count signal COUNT shown in FIG. 8A is 2n to 2n + 4.

  Returning to FIG. 7, the calibration unit 5124 counts the number of each of the up signal UP and the down signal DN while the PLL circuit 510 is operated by the reference clock REFCLK (S703).

The calibration unit 5124 compares the numbers of the counted up signal UP and down signal DN (S704). When the number of down signals DN is larger than the up signal UP (Yes in S704), the calibration unit 5124 creates a calibration signal CAL that increases the value of the change coefficient α in the decoding circuit 5122 by one, and sends the calibration signal CAL to the decoding circuit 5122. It outputs (S705). As a result, when the value of the count signal COUNT signal changes by one, the decode circuit 5122 generates the selection signal SEL so that the number of auxiliary mirror transistors 604 that operate is changed by one more than before, and the current mirror The unit 5123 is operated. Here, the fact that the number of the down signals DN is larger than the up signal UP means that the cycle of the feedback clock FBCLK is shorter than the reference clock REFCLK. This state is, for example, when the change coefficient α shown in FIG. 7B is set to 1, and as shown in the figure, the period of the feedback clock FBCLK is significantly shorter than that of the reference clock REFCLK. In order to eliminate this state, the calibration unit 5124 increases the value of the change coefficient α in the decoding circuit 5122 by one as described above. Thus, every time the value of the count signal COUNT changes, the decode circuit 5122 changes the operating state of the auxiliary mirror transistor 604 by one more than before, so that the value of the count signal COUNT changes by one. Each time the offset current I _OFFSET (n) is increased, the period of the feedback clock FBCLK can be lengthened. FIG. 7B is a graph showing an example of the period of the reference clock REFCLK supplied to the PLL circuit 510 in S702 of FIG. 7A and the period of the feedback clock FBCLK at that time.

  Returning to FIG. 7A, the calibration unit 5124 returns to S <b> 702 in order to continue calibration after performing the processing of S <b> 705 described above.

  On the other hand, when the number of the down signals DN is smaller than the up signal UP (No in S704), the calibration unit 5124 creates a calibration signal CAL that decreases the value of the change coefficient α in the decoding circuit 5122 by one, and generates the decoding circuit. It outputs to 5122 (S706). As a result, when the value of the count signal COUNT signal changes by one, the decode circuit 5122 generates the selection signal SEL so that the number of auxiliary mirror transistors 604 to operate changes by one less than before, and the current mirror The unit 5123 is operated. Here, the reason why the calibration unit 5124 performs such an operation is that when the number of down signals DN is smaller than the up signal UP, the value of the change coefficient α shown in FIG. The period of the feedback clock FBCLK is longer than that of the clock REFCLK. That is, the value of the change coefficient α has been increased too much, and the calibration unit 5124 performs the above-described operation to eliminate it. Note that the calibration unit 5124 performs the process of S706, so that the period of the feedback clock FBCLK is slightly shorter than the reference clock REFCLK. However, the clock generation circuit 500 is more likely to be in this state. It becomes easier to stabilize during operation. Thus, the calibration of the decoding circuit 5122 by the calibration unit 5124 is completed.

  FIG. 8A is a diagram for explaining frequency modulation by SSCG of the clock generation circuit according to one embodiment of the present invention, and specifically, an example of the relationship between the value of the count signal COUNT and the frequency of the reference clock REFCLK. Is shown. In the figure, the vertical axis indicates the frequency of the reference clock REFCLK, and the horizontal axis indicates the value of the count signal COUNT.

  As shown in the figure, the frequency of the reference clock REFCLK changes by a predetermined frequency Δf each time the value of the count signal COUNT is incremented by one. In other words, the value of the count signal COUNT changes from 0 to n in response to the increase of the reference clock REFCLK from 0Δf (reference frequency) to nΔf. Further, the value of the count signal COUNT changes from n to 2n corresponding to the decrease of the reference clock REFCLK from nΔf to 0Δf.

  Further, the value of the count signal COUNT changes from 2n to 3n corresponding to the decrease of the reference clock REFCLK from 0Δf to −nΔf. Further, the value of the count signal COUNT changes from 3n to 4n in response to the increase of the reference clock REFCLK from −nΔf to 0Δf. That is, the frequency of the reference clock REFCLK and the value of the count signal COUNT have a correspondence relationship. Note that the value of the count signal COUNT is reset to 0 when it reaches 4n.

  FIG. 8B is a diagram showing a relationship between the value of the count signal COUNT and the number of auxiliary mirror transistors 604 to be operated in the clock generation circuit according to the embodiment of the present invention. In the figure, the vertical axis represents the number of auxiliary mirror transistors 604 to be operated, and the horizontal axis represents the value of the count signal COUNT. In the following description, it is assumed that 2m auxiliary mirror transistors 604 and switches 605 in the current mirror unit 5123 are provided.

  As shown in the figure, the number of auxiliary mirror transistors 604 to be operated changes according to the value of the count signal COUNT, centering on m transistors at the reference frequency of the reference clock REFCLK. Specifically, the number of auxiliary mirror transistors 604 to be operated increases sequentially from m to m + nα between 0 and n in the count signal COUNT, and between n and 2n in the count signal COUNT. , M + nα to m.

  Furthermore, the number of auxiliary mirror transistors 604 to be operated decreases sequentially from m to m−nα between 2n and 3n in the count signal COUNT, and between 3n and 4n in the count signal COUNT. Sequentially increases from m-nα to m. Here, as described above, the change coefficient α indicates the number of auxiliary mirror transistors 604 whose decoding state is changed by the decode circuit 5122 per one value of the count signal COUNT, and is a value of m / n or less. .

  Based on FIGS. 8A and 8B described above, the number of auxiliary mirror transistors 604 to be operated can be increased or decreased by referring to the count signal COUNT in accordance with the increase or decrease of the frequency of the reference clock REFCLK.

  The decode circuit 5122 decodes the count signal COUNT, determines the number of auxiliary mirror transistors 604 to be operated, generates a corresponding selection signal SEL, and outputs this to the switch 605. The selection signal SEL is composed of, for example, a 2m bit string ([2m: 1]).

  FIG. 9 is a table for explaining an example of the selection signal SEL generated by the decoding circuit in the clock generation circuit according to the embodiment of the present invention, where the change coefficient α is 1, and n and m are the same value. Shows the case. As shown in the figure, the number of auxiliary mirror transistors 604 to be operated is indicated by the number of enabled bits of the selection signal SEL. For example, at the reference frequency of the reference clock REFCLK, the selection signal SEL in which all the lower m bits are “1” is generated so that the m auxiliary mirror transistors 604 operate. The switch 605 corresponding to each bit of the selection signal SEL performs an on or off operation according to the value, and thereby the operation of the auxiliary mirror transistor 604 is controlled. Hereinafter, the m-th auxiliary mirror transistor 604 may be represented as an auxiliary mirror transistor 604 [m], and the m-th switch 605 may be represented as a switch 605 [m].

  For example, as shown in FIG. 8B, when the value of the count signal COUNT is n, since the number of auxiliary mirror transistors 604 to be operated is m + nα, the decode circuit 5122 includes auxiliary mirror transistors 604 [1] to 604. In order to operate [m + nα], a selection signal SEL with the bit [m + nα: 1] set to “1” is generated. Accordingly, the switches 605 [1] to 605 [m + nα] are turned on, and the auxiliary mirror transistors 604 [1] to 604 [m + nα] are operated.

  For example, when the value of the count signal COUNT is 2n + 2, since the number of auxiliary mirror transistors 604 to be operated is m−2α, the decode circuit 5122 includes the auxiliary mirror transistors 604 [1] to 604 [m− In order to operate 2α], the selection signal SEL with the bit [m−2α: 1] set to “1” is generated. As a result, the switches 605 [1] to 605 [m-2α] are turned on, and the auxiliary mirror transistors 604 [1] to 604 [m-2α] operate.

As described above, in the clock generation circuit 500, in the offset current generation unit 512, the decoding circuit 5122 decodes the count signal COUNT signal indicating the frequency modulation of the reference clock REFCLK generated by the SSCG 10, and corresponds to the frequency of the reference clock REFCLK. The selection signal SEL for controlling on / off of the switch 605 is generated according to the number of auxiliary mirror transistors 604 that need to be operated. Thereby, in the clock generation circuit 500, the mirror ratio in the current mirror unit 5123 of the offset current generation unit 512 changes, and the offset current I _OFFSET (n) having a value corresponding to the frequency of the reference clock REFCLK can be generated.

In the clock generation circuit 500, the second output current _{I P} to be output from the proportional unit 23 to the oscillation frequency control unit 25, by subtracting the second charge pump current Icp_p from the generated offset current _{I OFFSET} (n) as described above since the second output current _{I P,} it is possible to output the output clock CLK which follows the frequency modulation of the reference clock REFCLK.

  FIG. 10 is a flowchart illustrating a clock generation method according to an embodiment of the present invention. Such a clock generation method is a process executed in the clock generation circuit 500.

  As shown in the figure, the SSCG 10 generates a reference clock REFCLK, outputs it to the phase detection circuit 21 and the offset current generator 512, and generates a count signal COUNT and outputs it to the offset current generator 512 (S1001). . Subsequently, the offset current generator 512 generates a selection signal SEL signal based on the value of the count signal COUNT in the decode circuit 5122 (S1002).

Then, the decode circuit 5122 sends the generated selection signal SEL to the switch 605 of the current mirror unit 5123, thereby controlling the on / off of the switch 605. As a result, the mirror ratio of the current mirror unit 5123 changes, and an offset current I _OFFSET (n) having a value corresponding to the frequency of the reference clock REFCLK is generated (S1003).

Subsequently, the proportional part 23 draws the generated offset current _{I OFFSET} (n), a first which generates a second output current _{I P} by subtracting the second charge pump currents _{I Cp_p,} the integral unit 22 generates The output current I _INT is output to the oscillation frequency control unit 25 and the oscillation frequency control unit 25 generates the output clock CLK via the buffer 26 (S1004). The output clock CLK generated by the oscillation frequency control unit 25 follows the frequency modulation of the reference clock REFCLK.

  Subsequently, when the generation of the reference clock REFCLK and the count signal COUNT by the SSCG 10 is finished (Yes in S1005), the clock generation by the clock generation circuit 500 is finished. On the other hand, if the generation of the reference clock REFCLK and the count signal COUNT by the SSCG 10 has not been completed (No in S1005), the process returns to S1002 and continues.

  FIG. 11 is a timing chart of various signals in the clock generation circuit according to the embodiment of the present invention. More specifically, this figure shows jitter that may occur in the clock generation circuit 500.

  As shown in the figure, at a certain time point t0, the reference clock REFCLK, which is the reference period T, is frequency-modulated so as to become longer by the time D for each period.

  Since the clock generation circuit 500 can generate the output clock CLK following the frequency modulation of the reference clock REFCLK as described above, no phase shift occurs between the reference clock REFCLK and the feedback clock FBCLK. Therefore, the down signal DN signal is not output from the phase detection circuit 21. In the clock generation circuit 500, the period of the output clock CLK changes following the frequency modulation of the reference clock REFCLK, and this change amount becomes jitter. This jitter is much smaller than the large jitter shown in FIG. That is, the clock generation circuit 500 can realize a significant reduction in jitter.

  Each of the above embodiments is an example for explaining the present invention, and is not intended to limit the present invention only to these embodiments. The present invention can be implemented in various forms without departing from the gist thereof.

  For example, in the method disclosed herein, steps, operations, or functions may be performed in parallel or in a different order, as long as the results do not conflict. The steps, operations, and functions described are provided as examples only, and some of the steps, operations, and functions may be omitted and combined with each other without departing from the spirit of the invention. There may be one, and other steps, operations or functions may be added.

  Further, although various embodiments are disclosed in this specification, specific features (technical matters) in one embodiment are added to other embodiments while appropriately improving the other features, or other Specific features in the embodiments can be replaced, and such forms are also included in the gist of the present invention.

  For example, in the above-described embodiment, when the number of down signals DN is smaller than the up signal UP in the calibration of the decoding circuit 5122 in the calibration unit 5124 (No in S704 in FIG. 7), the calibration unit 5124 The calibration signal CAL for reducing the value of the change coefficient α in 5122 by 1 is generated and output to the decoding circuit 5122. However, the value after the decimal point of the change coefficient α is calculated using a technique such as binary search. A calibration signal CAL may be generated and output to the decoding circuit 5122. In this way, the calibration unit 5124 can calibrate the decoding circuit 5122 with higher accuracy.

  For example, if the value of the change coefficient α in the decode circuit 5122 is set to 3.5 as a result of the operation of the calibration unit 5124 as described above, the decode circuit 5122 sets the value of the change coefficient α to 4, 3, The operation is performed while changing the average value to 4, 3,...

  The present invention can be widely used in the field of electronic devices including a clock generation circuit.

10 ... SSCG
DESCRIPTION OF SYMBOLS 11 ... Oscillator 12 ... Counter 13 ... Variable delay control circuit 131 ... Delay element 132 ... Selector 20 ... PLL circuit 21 ... Phase detection circuit 22 ... Integration part 221 ... First charge pump 222 ... Loop filter 222a ... Capacitor 223 ... Transistor 23 ... Proportional unit 231 ... second charge pump 232 ... transistor 233 ... transistor 24 ... offset current generation unit 241 ... current source 242 ... transistor 243 ... transistor 25 ... oscillation frequency control unit 26 ... buffer 27 ... frequency divider 500 ... clock generation circuit 510 ... PLL circuit 512 ... Offset current generation unit 5121 ... Flip-flop circuit 5122 ... Decode circuit 5123 ... Current mirror unit 601 ... Current source 602 ... Transistor 603 ... Main mirror transistor 604 ... Auxiliary Error transistor 605 ... switch 5124 ... calibration unit

Claims (8)

A spread spectrum clock oscillator that performs frequency modulation on a standard clock generated by an oscillator and generates a reference clock;
A PLL circuit that generates and outputs an output clock according to the reference clock,
The PLL circuit includes an oscillation frequency control unit that controls an oscillation frequency of the output clock according to a value of an input drive current,
The drive current is
A first output current controlled based on a cumulative current output from a first charge pump driven by a signal based on a phase difference between the reference clock and a feedback clock obtained by dividing the output clock;
The second output current obtained by subtracting the current output from the second charge pump driven in the same manner as the first charge pump from the offset current that changes based on a predetermined count signal for frequency modulation with respect to the standard clock. When,
including,
Clock generation circuit.   The clock generation circuit according to claim 1, wherein the offset current increases with an increase in frequency of the reference clock and decreases with a decrease. An offset current generator for generating the offset current,
The offset current generator is
A current mirror unit including a multi-stage current mirror circuit including a plurality of mirror transistors;
The clock generation circuit according to claim 2, further comprising: a decoding circuit that determines a mirror ratio of the multistage current mirror circuit according to the count signal and changes a value of the offset current. The PLL circuit includes:
An integrator that includes the first charge pump and generates the first output current;
A proportional unit that includes the second charge pump and generates the second output current;
The clock generation circuit according to claim 1. The offset current generator is
A calibration unit for calibrating the output of the current mirror unit,
The calibration unit changes the value of the count signal by one according to a signal based on a phase difference between the reference clock and the feedback clock when the PLL circuit receives the reference clock. A change coefficient that is the number of the mirror transistors whose operation is changed every time is determined.
The clock generation circuit according to claim 3. The PLL circuit includes:
A phase detection circuit that outputs an up signal when the phase of the feedback clock is delayed with respect to the reference clock and outputs a down signal when the phase of the feedback clock is advanced with respect to the reference clock; Including
The calibration unit increases the value of the change coefficient by a predetermined value from an initial value until the number of the down signals when the PLL circuit receives the reference clock exceeds the number of the up signals, After the number of the down signals exceeds the number of the up signals, the final value of the change coefficient is determined by subtracting the predetermined value from the current value of the change coefficient.
The clock generation circuit according to claim 5. The PLL circuit includes:
A phase detection circuit that outputs an up signal when the phase of the feedback clock is delayed with respect to the reference clock and outputs a down signal when the phase of the feedback clock is advanced with respect to the reference clock; Including
The calibration unit increases the value of the change coefficient by a predetermined value from an initial value until the number of the down signals when the PLL circuit receives the reference clock exceeds the number of the up signals, After the number of the down signals exceeds the number of the up signals, the final value of the change coefficient is calculated by calculating a value after the decimal point from the current value of the change coefficient using a predetermined method. Define
The clock generation circuit according to claim 5. A clock generation method using a spread spectrum clock oscillator that performs frequency modulation on a standard clock generated by an oscillator and generates a reference clock, and a PLL circuit that generates and outputs an output clock according to the reference clock. ,
A first output current controlled based on a cumulative current output from a first charge pump driven by a signal based on a phase difference between the reference clock and a feedback clock obtained by dividing the reference clock; The second output current obtained by subtracting the current output from the second charge pump driven in the same manner as the first charge pump from the offset current that changes based on a predetermined count signal for frequency modulation with respect to the standard clock. And generating with
Inputting the drive current to an oscillation frequency control unit that is provided in the PLL and controls the oscillation frequency of the output clock according to the input current value;
Clock generation method including: