JP2010015656A - Address decoder check circuit and its check method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an address decoder check circuit and its check method capable of making a detailed check with less check steps without preparing expected values for the test memory data. <P>SOLUTION: An address decoder check circuit for checking the functions of a plurality of address decoders includes: a multiplexer to select and output a negative logic signal of the address signal and a negative logic signal set up independently of the negative logic signal when checking for a part of the plurality of address decoders; a first switching element to cut off the connection between the output terminals and the power source terminals of each address decoder when checking; a common wiring connected to each of the output terminals of the plurality of address decoders through the relay wiring; and a second switching element provided on this relay wiring to electrically connect each output terminal and the common wiring when testing. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an inspection circuit for an address decoder that inspects a plurality of address decoders that output a result of decoding an address signal input to select a memory cell, and an inspection method thereof.

  First, the NOR type address decoder will be described. For example, a 3-bit NOR type address decoder includes three N-channel MOS transistors arranged in parallel between a ground terminal and an output terminal, and three Ps arranged in series between a power supply terminal and an output terminal. Each of the gate electrodes is connected to an input terminal. When any one of the three N-channel MOS transistors is driven by the address signal, the ground terminal and the output terminal are connected, and the output terminal becomes the ground potential. On the other hand, when all of the three P-channel MOS transistors are driven, the power supply terminal and the output terminal are connected, and the output terminal becomes the power supply potential.

  In the case of a decoder circuit composed of the above-described three-bit NOR type address decoders, three positive logic signals (input signals) in the address signal are inverted at each input terminal of the NOR type address decoder by a NOT gate. These three negative logic signals are appropriately connected. Therefore, when an address pattern of one positive logic signal is input, a negative logic signal is uniquely determined, and only one address decoder is selected.

  On the other hand, the inspection circuit of the address decoder disclosed in Patent Document 1 includes a multiplexer that selects and outputs a negative logic signal that is set independently of the negative logic signal at the time of inspection (at the time of test). I have. If all the address signals (signals that do not pass through the multiplexer) that are directly input are positive logic signal groups and all the negative logic signals that are set independently at the time of testing are negative logic signal groups, the positive logic signal group at the time of testing. And only one bit of the negative logic signal group is set to “1” (for example, the positive logic signal group is set to [000] and the negative logic signal group is set to [001]). Multiple selection is performed (see FIG. 2A of Patent Document 1). After executing the above-described multiple selection step for performing multiple selection, only one bit of the signal group that has not been set to “1” is set to “1” (for example, the positive logic signal group is [001]), a non-selection step is performed to confirm that the multiple-selected address decoder is not selected (see FIG. 2B of Patent Document 1). In this way, by confirming whether one N-channel MOS transistor in the multi-selected address decoder is normally turned on (whether it is in a non-selected state) or not, it is possible to check the N-channel MOS transistor. Inspect the transistor.

Thereafter, the multiple selection step and the all non-selection step described above are executed alternately, and the bit for setting “1” in the all non-selection step is sequentially changed (for example, the positive logic signal group is changed from [001] to [010]. And the corresponding step is executed for all bits of the signal group (for example, positive logic signal group). As a result, all the N-channel MOS transistors in the address decoder selected in the multiple selection step are inspected. Next, a signal group (for example, a negative logic signal group) in which any one bit is set to “1” in the multiple selection step described above, and any one bit is set to “1” in all the non-selection steps described above. By exchanging signal groups (for example, positive logic signal groups) with each other, the remaining address decoders not selected in the multiple selection step described above are selected, and the multiple selection step and all non-selection steps are executed in the same manner. The inspection of the N channel type MOS transistors in all the address decoders is completed.
JP 2007-193877 A

  By the way, in the address decoder inspection method disclosed in Patent Document 1, in order to inspect one N-channel MOS transistor in the selected address decoder, two steps of a multiple selection step and an all non-selection step are executed. There is a concern that there will be many inspection steps. For example, in the case of a decoder circuit composed of the above-mentioned eight 3-bit NOR type address decoders, twelve inspection steps are required at the shortest.

  Also, whether or not the N-channel MOS transistor of the multi-selected address decoder is normally turned on (whether or not it is in a non-selected state) is confirmed not by the output signals but by the multi-selected memory data. Therefore, depending on the selection of the address decoder, the memory data may be duplicated. For this reason, it is necessary to prepare the expected value of the test memory data that is expected to be detected by the output signal of the multiple-selected address decoder at the time of the test, and there is a concern that it takes time and effort. The

  Furthermore, for example, the contact resistance between the source side terminal and the ground terminal is high, the wiring connected to the source or drain side terminal is damaged, or a sufficient voltage is not applied to the gate electrode, resulting in high on-resistance. In the case of the so-called high impedance state, since the inspection is performed not based on the strength of the output signal to be output, but based on the two values (0 or 1) of the memory data, There is also a problem that it is difficult to detect defects inherent in the address decoder.

  Therefore, in view of the above problems, the present invention provides an inspection circuit for an address decoder and an inspection method thereof that can have a smaller number of inspection steps, do not need to provide an expected value of memory data for testing, and can perform inspection in detail. The purpose is to provide.

  In order to achieve the above object, an invention according to claim 1 is directed to an address decoder test for testing a function of a plurality of address decoders for outputting a result obtained by decoding an address signal inputted to select a memory cell. A multiplexer that selectively outputs a negative logic signal of an address signal and a negative logic signal that is set independently of the negative logic signal at the time of inspection to a part of a plurality of address decoders; A first switching element that cuts off an electrical connection between an output terminal of each address decoder and a power supply terminal at the time of inspection; a common wiring connected to each of the output terminals of the plurality of address decoders via a relay wiring; And a second switching element that is provided in each of the relay wirings and electrically connects each output terminal and the common wiring at the time of inspection. .

  As described above, the inspection circuit of the address decoder according to the present invention (hereinafter simply referred to as the inspection circuit) has a part of a plurality of address decoders for decoding n (n is a natural number of 2 or more) bit addresses. A multiplexer is provided that selects and outputs a negative logic signal of the address signal and a negative logic signal that is set independently of the negative logic signal at the time of inspection (test). Therefore, at the time of a test, multiple selections for selecting a plurality of address decoders can be performed by inputting a negative logic signal uniquely set via the multiplexer to the address decoder.

  The inspection circuit has a common wiring connected to each of the output terminals of the plurality of address decoders via a relay wiring. As a result, output signals output from a plurality of address decoders flow through the common wiring. In other words, the address decoder can be inspected by detecting the current value of the output signal flowing through the common wiring.

  The inspection circuit also includes a first switching element that cuts off the connection between the output terminal and the power supply terminal in the address decoder during the test. This suppresses the output signal from being output from the multiple-selected address decoder (when the address decoder is a NOR type, an address decoder in which “0” is input to all the bits of the address signal) during the test, The output signal is output to the common line only from the address decoder that is not selected multiple (if the address decoder is a NOR type, an address decoder in which “1” is input to one of the bits of the address signal). Therefore, by detecting the current value of the output signal output to the common wiring, it is possible to inspect the address decoder that has not been multiple-selected. In this manner, since the address decoder is not inspected with the memory data as in the conventional case, the address decoder can be inspected with fewer inspection steps than in the prior art.

  In addition, since the address decoder is inspected by a continuous value (analog value) called an output signal, the address decoder is inspected in more detail than the conventional method of inspecting by two values (digital values) of memory data. Can be done. In addition, since the inspection is performed using the output signal, it is not necessary to prepare in advance the expected value of the test memory data that is expected to be output by multiple selection.

  The inspection circuit includes a second switching element that is provided in each of the relay wirings and electrically connects each output terminal and the common wiring based on the test signal. That is, during the normal operation (outputting the decoded result to the memory cell), the electrical connection between each output terminal and the common wiring can be interrupted by the second switching element. As a result, during normal operation, an output signal output from one selected address decoder is output to a memory cell connected to an output terminal of another address decoder via the relay wiring and the common wiring. The occurrence of defects is suppressed.

  According to a second aspect of the present invention, there is preferably provided a register for writing an independently set truth signal and outputting it to the multiplexer. According to this, it is not necessary to provide an external connection terminal for giving an independently set negative logic signal.

  According to a third aspect of the present invention, a configuration in which an external connection terminal for connection to an external power source is connected to the common wiring can be employed. According to this, a voltage higher than the power supply voltage provided in the inspection circuit can be applied to the address decoder. Thereby, the current value of the output signal output to the common wiring can be increased, and the detection accuracy can be improved.

  According to a fourth aspect of the present invention, it is possible to employ a configuration including an inspection unit that inspects the address decoder based on the current value of the current flowing through the common wiring. According to this, the inspection can be performed in the inspection circuit of the address decoder. Thereby, it is not necessary to provide an external connection terminal for connection to an external power source.

  A fifth aspect of the present invention is a method for inspecting an address decoder using the address decoder inspection circuit according to any one of the first to fourth aspects, wherein when the address decoder is a NOR type, direct input is performed. If all address signals to be performed are positive logic signal groups and all negative logic signals set independently at the time of inspection are negative logic signal groups, only one bit of the positive logic signal group and the negative logic signal group is used. By setting to “1”, the address decoder is selected multiple times, and a multiple selection step is performed in which an inspection is performed based on the value of the current flowing in the common wiring. In the multiple selection step, the bits for setting “1” are sequentially changed. Thus, the multiple selection step is executed for all the bits of the signal group.

  As described above, according to the present invention, since the inspection is performed based on the value of the current flowing in the common wiring, the value of the memory data can be obtained by executing the all non-selection step after executing the multiple selection step as in the prior art. The inspection can be performed only by the multiple selection step, instead of performing the inspection by detecting. Thereby, it can test | inspect in a half inspection step. That is, the inspection can be performed by the same number of inspection steps as the total number of bits of the positive logic signal group and the negative logic signal group.

  For example, in the case of a decoder circuit composed of eight 3-bit NOR type address decoders, the total number of bits of the positive logic signal group and the negative logic signal group is 6, so that the inspection can be performed in a minimum of 6 inspection steps. it can.

  As described above, the address decoder inspection circuit and the inspection method described above have fewer inspection steps, do not require the expected value of the memory data for testing, and can perform the inspection in detail. This is an inspection circuit and an inspection method thereof.

  In addition, since the effect of the invention of Claim 6 is the same as the effect of the invention of Claim 5, the description is abbreviate | omitted.

Hereinafter, an embodiment in which the present invention is applied to a 3-bit NOR type address decoder for selecting a memory cell in a memory such as a ROM will be described with reference to the drawings. Further, in the following description, a signal with a high voltage (Hi level) is described as positive logic, and a signal with a low voltage (Low level) is considered as “0”.
(First embodiment)
FIG. 1 is a circuit diagram showing an inspection circuit of the address decoder according to the first embodiment at the time of inspection. FIG. 2 is a circuit diagram showing a configuration of a NOR gate constituting the address decoder. FIG. 3 is a diagram for explaining an operation in which multiple selection of the decoder is performed. FIG. 4 is a diagram showing a test address pattern. In FIG. 1, the power supply terminal 23 is omitted for convenience.

  As shown in FIG. 1, an address decoder test circuit 100 (hereinafter simply referred to as test circuit 100) receives address decoders 10 to 17 (NOR000 to NOR111) and input signals [A0 to A2] (positive logic signals). Inverted and outputs inverted signals [A0N to A2N] (negative logic signals) to address decoders 11 to 17 (NOR001 to NOR111), inverted signals [A0N to A2N], and inverted signals [A0N to Multiplexers 50 to 52 that select independent inverted signals [B0N to B2N] (negative logic signals) set independently of A2N], and a register 53 that outputs independent inverted signals [B0N to B2N] to the multiplexers 50 to 52 Relay lines 60 to 67 connected to the output terminals 18 of the address decoders 10 to 17 and the relay lines 60 to 67, respectively. The second switching elements 70 to 77 and the NOT gate 80 that inverts the test signal (TEST) and outputs the inverted test signal (TESTN) to the second switching elements 70 to 77 and the relay wirings 60 to 67. And a common line 90 connected to each output terminal 18 of the address decoders 10 to 17.

  As shown in FIG. 2, the address decoders 10 to 17 include three N-channel MOS transistors 20 to 22 arranged in parallel with each other between the output terminal 18 and the ground terminal 19, the output terminal 18, and the power supply terminal 23. And three P-channel MOS transistors 24 to 26 arranged in series with each other, and input terminals 27 to 29 for inputting an address signal are connected to corresponding gate electrodes. The first input terminal 27 is connected to the gate electrodes of the transistors 20 and 24, and any one of address signals A0, A0N, and B0N is input to the gate electrodes. The second input terminal 28 is connected to the gate electrodes of the transistors 21 and 25, and any one of the address signals A1, A1N, and B1N is input thereto. The third input terminal 29 is connected to the gate electrodes of the transistors 22 and 26 so that any one of the address signals A2, A2N, and B2N is input.

  When even one of the address signals input from the input terminals 27 to 29 has a Hi level signal “1”, any one of the three N-channel MOS transistors 20 to 22 is driven, and the ground terminal 19 and the output terminal 18 is connected, and the output terminal 18 becomes the ground potential. As a result, a signal “0” is output. On the other hand, when the normal operation (test signal (TEST) is at the low level) and all of the address signals input from the input terminals 27 to 29 are the low level signal “0”, the three P-channel types are used. All of the MOS transistors 24 to 26 are driven, the power supply terminal 23 and the output terminal 18 are connected, and the output terminal 18 becomes the power supply potential. As a result, the signal “1” is output.

  The address decoders 10 to 17 according to the present embodiment include a P-channel MOS transistor 24 disposed farthest from the power supply terminal 23 and a connection point 30 that connects the power supply terminal 23 and the output terminal 18. A first switching element 31 that controls connection between the power supply terminal 23 and the output terminal 18 is provided. The first switching element 31 according to the present embodiment is a P-channel MOS transistor, and a test wiring 32 is connected to the gate electrode thereof. A high-level test signal (TEST) is input to the gate electrode via the test wiring 32 during testing. As a result, the first switching element 31 is turned off during the test, the connection between the power supply terminal 23 and the output terminal 18 is cut off, and the signal “1” is not output. In the above example, the first switching element 31 is disposed between the P-channel MOS transistor 24 and the connection point 30. However, the arrangement position of the first switching element 31 is limited to the above example as long as the arrangement position controls the connection between the power supply terminal 23 and the output terminal 18 and does not hinder the connection between the output terminal 18 and the ground terminal 19. Not. For example, the first switching element 31 may be disposed between the P-channel MOS transistor 26 disposed closest to the power supply terminal 23 and the power supply terminal 23. Also by this, the connection between the power supply terminal 23 and the output terminal 18 can be controlled.

  NOT gates 40 to 42 invert input signals [A0 to A2] (positive logic signals) and output inverted signals [A0N to A2N] (negative logic signals) to address decoders 11 to 17 (NOR001 to NOR111). It is. Only the input signals [A0 to A2] are input to the address decoder 10 (NOR000). When one input signal [A0 to A2] (for example, [001]) is input to the NOT gates 40 to 42, the inverted signal [A0N to A2N] (for example, [110]) is uniquely determined. Thereby, only one address decoder (for example, address decoder 14 (NOR100)) is selected during normal operation. Thus, the NOT gates 40 to 42 and the address decoders 10 to 17 constitute a decoder circuit that outputs the result of decoding the input address signal (input signal).

  The multiplexers 50 to 52 include the inverted signals [A0N to A2N] output from the NOT gates 40 to 42 and the independent inverted signals [B0N to B2N] set independently of the inverted signals [A0N to A2N] during the test. (Negative logic signal) is selected. As shown in FIG. 1, each of the multiplexers 50 to 52 includes an inverted signal [A0N to A2N] output from the NOT gates 40 to 42, a test signal (TEST), and an independent inverted signal [ B0N to B2N] are input. When the test signal (TEST) is inactive (Low level), the multiplexers 50 to 52 output the inversion signals [A0N to A2N] output from the NOT gates 40 to 42 to the address decoders 11 to 17, respectively. When TEST) is active (Hi level), the independent inversion signals [B0N to B2N] output from the register 53 are output to the corresponding address decoders 11 to 17. As described above, when the test signal (TEST) is active, the independent inversion signals [B0N to B2N] are selected, and the plurality of address decoders can be selected by outputting the signals to the address decoders 11 to 17. It has a possible configuration. The register 53 temporarily stores the independent inversion signal [B0N to B2N], and can be written when the test signal (TEST) is active.

  The relay wirings 60 to 67 electrically connect (relay) the output terminals 18 of the address decoders 10 to 17 and the common wiring 90. In the middle of each of the relay wirings 60 to 67, second switching elements 70 to 77 for controlling the connection between the output terminal 18 and the common wiring 90 are provided, one end of which is connected to the output terminal 18 and the other end is connected. The common wiring 90 is connected. The second switching elements 70 to 77 according to the present embodiment are P-channel MOS transistors, and an inverted test signal (TESTN) obtained by inverting the test signal (TEST) by the NOT gate 80 is input to the gate electrode thereof. It has become so. Thereby, a low level inversion test signal (TESTN) is applied to the gate electrodes of the second switching elements 70 to 77 during the test, the second switching elements 70 to 77 are turned on, and the output terminal 18 and the common wiring 90 are connected. Connected. In the above example, the second switching elements 70 to 77 are P-channel MOS transistors. However, as the second switching elements 70 to 77, N-channel type MOS transistors can be employed. In this case, the NOT gate 80 may not be provided.

  The common wiring 90 is connected to the output terminals 18 of the plurality of address decoders 10 to 17 via the relay wirings 60 to 67 during the test. In the present embodiment, an external connection terminal 91 is provided in the common wiring 90, and the common wiring 90 and the external power supply 110 are connected via the external connection terminal 91. Therefore, by applying a voltage higher than the internal power supply voltage to the common wiring 90 by the external power supply 110, the value of the current flowing through the common wiring 90 can be increased and the detection accuracy can be improved. In this embodiment, by applying a tester to the external connection terminal 91, the current flowing through the common wiring 90 is detected, and the detected current value and a predetermined current value measured in advance (when the address decoder operates normally) Are compared with the current value expected to be detected by the common wiring 90). In the above example, the example in which the test is performed by applying the tester to the external connection terminal 91 is shown. However, the inspection may be performed by providing an inspection unit (not shown) in the inspection circuit 100. As a result, the inspection can be performed in the inspection circuit 100, so that it is not necessary to provide an external connection terminal. As the above-described inspection unit, for example, a unit composed of a resistor, a comparator, or the like can be adopted. When a comparator is used, function determination can be performed.

  Next, the operation of the inspection circuit 100 in the case where the test signal (TEST) is inactive (Low level), that is, in the normal operation will be described. When the test signal (TEST) is inactive, the multiplexers 50 to 52 select the inverted signals [A0N to A2N] output from the NOT gates 40 to 42. Accordingly, the input signals [A0 to A2] and the inverted signals [A0N to A2N] are appropriately input to the address decoders 10 to 17 (NOR000 to NOR111), and only one address decoder is selected. In this case, since the first switching element 31 is turned on, the output terminal 18 of the selected address decoder and the power supply terminal 23 are connected, and the output terminal 18 becomes the power supply potential. As a result, the signal “1” is output to the memory cell (not shown). Further, since the test signal is at the low level, the inverted test signal (TESTN) inverted by the NOT gate 80 becomes the Hi level, and the second switching elements 70 to 77 are turned off. As a result, the connection between the output terminal 18 and the common line 90 is cut off, and the output terminal of the selected address decoder is connected to another unselected address decoder via the relay line and the common line 90. Problems such as the output of the signal “1” to the memory cell are prevented.

  Next, the operation of the inspection circuit 100 when the test signal (TEST) is active (Hi level), that is, during the test will be described. When the test signal is active, the multiplexers 50 to 52 select the independent inverted signals [B0N to B2N] output from the register 53. Accordingly, the input signals [A0 to A2] and the independent inversion signals [B0N to B2N] are appropriately input to the address decoders 10 to 17 (NOR000 to NOR111), so that a plurality of address decoders can be selected. .

  For example, by inputting an address pattern [A0 to B2N] = [100000], which is a combination of the input signal [A0 to A2] and the independent inverted signal [B0N to B2N] as shown in FIG. Multiple address decoders can be selected. A portion surrounded by a thick frame in FIG. 3 indicates an address signal input to each of the address decoders 10 to 17 (NOR000 to NOR111). When the above address pattern is input, the address signal [000] is input to the address decoders 11, 13, 15, and 17 (NOR001, NOR011, NOR101, and NOR111), and multiple selection (four-fold selection) for selecting them at once. Is executed. In the case of a normal decoder circuit, all of the P-channel MOS transistors 24-26 in the multiple-selected address decoders 11, 13, 15, 17 are turned on, so that the output terminal 18 and the power supply terminal 23 are connected. An output signal “1” is output. However, the address decoders 10 to 17 according to the present embodiment have the first switching element 31 that is a P-channel MOS transistor. When a Hi level test signal (TEST) is input to the gate electrode of the first switching element 31, the first switching element 31 is turned off, and the connection between the output terminal 18 of the address decoders 10 to 17 and the power supply terminal 23 is established. Blocked. Therefore, the output terminal 18 of the selected address decoder 11, 13, 15, 17 does not become the power supply potential, and the signal “1” is not output. Since the address signal [000] is input, the N-channel MOS transistors 20 to 22 are not turned on, and the output terminal 18 and the ground terminal 19 are not connected. That is, the output terminal 18 does not become the ground potential, and the signal “0” is not output. Therefore, no output signal is output from the multiple-selected address decoders 11, 13, 15, and 17, and the current flowing from these output terminals 18 to the common wiring 90 is almost zero. On the other hand, address decoders 10, 12, 14, 16 (NOR00, NOR010, NOR100, NOR110) in which “1” is input to address signal A0 and “0” is input to other address signals are address signal A0. When each N-channel MOS transistor 20 to which is inputted normally is turned on, it is in a non-selected state. That is, when the N-channel MOS transistor 20 is normally turned on, the output terminal 18 and the ground terminal 19 are connected, and the output terminal 18 becomes the ground potential. As a result, the signal “0” is output to the memory cell (not shown).

  A low level inversion test signal (TESTN) inverted by the NOT gate 80 is inputted to the gate electrodes of the second switching elements 70 to 77, whereby the second switching elements 70 to 77 are turned on, and each address decoder is turned on. 10 to 17 output terminals 18 and the common wiring 90 are electrically connected. Therefore, the output signals of the address decoders 10 to 17 flow into the common wiring 90. Since the external power supply 110 is connected to the common wiring 90 via the external connection terminal 91, the potential of the external power supply 110 is connected to each N-channel MOS transistor 20 of the address decoder 10, 12, 14, 16. And a voltage based on the external power supply voltage (voltage dropped by the second switching element and the wiring resistance), which is the difference between the voltage and the ground potential, is applied. When each N-channel MOS transistor 20 is normally turned on, the output signal i determined by the on-resistance of the N-channel MOS transistor 20 and the voltage based on the external power supply voltage is supplied to each address decoder 10, 12, 14, 16 Output from the output terminal 18. These output signals i are output to the common wiring 90 via the common wirings 60, 62, 64, 66 and the second switching elements 70, 72, 74, 76. That is, a current 4i that is a sum of four output signals i (hereinafter, a sum of output signals output to the common wiring 90 is referred to as a total current) is output to the common wiring 90. However, for example, when an open failure occurs in the N-channel MOS transistor 20 of the address decoder 10 or when a wire connected to the terminal of the N-channel MOS transistor 20 is disconnected, the output signal i from the address decoder 10 Is not output, and a total current 3 i that is the sum of the output signals i output from the three address decoders 12, 14, and 16 is output to the common wiring 90. As described above, when a malfunction occurs in the N-channel MOS transistor 20, the total current that is expected to be detected when each N-channel MOS transistor 20 is normally turned on, and the total current that is detected at the time of inspection. Therefore, by comparing these values, it can be determined whether or not the N-channel MOS transistor 20 has a problem. In the above example, the case where there is no contribution of the output signal output from one N-channel MOS transistor is shown. However, for example, even when the N-channel MOS transistor is in a high impedance state, the high impedance state can be determined because the inspection is performed based on the current value of the output signal (total current). Thereby, non-defective product determination can be performed. Further, as described above, since the inspection is performed based on the current value of the output signal, it is not necessary to prepare the expected value of the test memory data that is expected to be output by the multiple selection in advance as in the prior art.

  The principle of testing one N-channel MOS transistor in four (half) address decoders by inputting one address pattern has been described. Hereinafter, a method of inspecting the N-channel MOS transistors 20 to 22 in all the address decoders 10 to 17 (NOR000 to NOR111) by sequentially changing the bits of the address signal for inputting the signal “1” in the address pattern. Outline. A diagram showing all the address patterns is shown in FIG.

  First, as shown in (1) of FIG. 4, by inputting an address pattern [A0 to B2N] = [100000], N of the address decoders 10, 12, 14, 16 (NOR000, NOR010, NOR100, NOR110) The channel type MOS transistor 20 is inspected. This is the inspection method described above. If the current value of the total current detected at this time is equal to the current value 4i that is expected to be detected, it indicates that each N-channel MOS transistor 20 has been turned on normally and that it is not in a high impedance state. ing. The above is one multiple selection step.

  Next, as shown in (2) of FIG. 4, by inputting an address pattern [A0 to B2N] = [010000] in which the bit for inputting “1” is changed from A0 to A1, the address decoders 10, 11 14, 15 (NOR000, NOR001, NOR100, NOR101) N-channel MOS transistors 21 are inspected. When the current value of the total current detected at this time is equal to the current value 4i expected to be detected, it indicates that each N-channel MOS transistor 21 is normally turned on, indicating that it is not in a high impedance state. ing.

  Next, as shown in (3) of FIG. 4, by inputting an address pattern [A0 to B2N] = [001000] in which the bit for inputting “1” is changed from A1 to A2, the address decoders 10, 11 , 12, 13 (NOR000, NOR001, NOR010, NOR011), the N-channel MOS transistor 22 is inspected. If the current value of the total current detected at this time is equal to the current value 4i expected to be detected, it indicates that each N-channel MOS transistor 22 is normally turned on, indicating that it is not in a high impedance state. ing.

  Next, as shown in (4) of FIG. 4, by inputting an address pattern [A0-B2N] = [000100] in which the bit for inputting “1” is changed from A2 to B0N, the address decoders 11, 13 , 15, 17 (NOR001, NOR011, NOR101, NOR111) are inspected. If the current value of the total current detected at this time is equal to the current value 4i that is expected to be detected, it indicates that each N-channel MOS transistor 20 has been turned on normally and that it is not in a high impedance state. ing.

  Next, as shown in (5) of FIG. 4, by inputting an address pattern [A0-B2N] = [000010] in which the bit for inputting “1” is changed from B0N to B1N, the address decoders 12, 13 , 16, 17 (NOR010, NOR011, NOR110, NOR111) N-channel MOS transistors 21 are inspected. When the current value of the total current detected at this time is equal to the current value 4i expected to be detected, it indicates that each N-channel MOS transistor 21 is normally turned on, indicating that it is not in a high impedance state. ing.

  Finally, as shown in (6) of FIG. 4, by inputting an address pattern [A0 to B2N] = [000001] in which the bit for inputting “1” is changed from B1N to B2N, address decoders 14 and 15 16, 17 (NOR100, NOR101, NOR110, NOR111) N-channel MOS transistors 22 are inspected. If the current value of the total current detected at this time is equal to the current value 4i expected to be detected, it indicates that each N-channel MOS transistor 22 is normally turned on, indicating that it is not in a high impedance state. ing.

  As described above, the inspection of the N channel type MOS transistors 20 to 22 in all the address decoders 10 to 17 (NOR000 to NOR111) is completed by the multiple selection step of six times. Thus, in the case of a 3-bit address decoder, the required inspection steps are six (same as the number of bits of the address pattern), and the test can be performed in half the inspection steps as compared with the conventional twelve.

  As described above, the inspection circuit 100 and the inspection method shown in the present embodiment have fewer inspection steps, do not need to provide the expected value of the memory data for testing, and can perform the inspection in detail. And its inspection method.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  In the present embodiment, an example in which the present invention is applied to a NOR type address decoder is shown. However, the present invention is not limited to the above example, and can be applied to a NAND type address decoder. In this case, “0” is input to any one bit (for example, A0) in the address pattern, and the multiple selection step is executed by inputting the other bits to “1”, and the signal “0” in the address pattern is input. By sequentially changing the bits to be performed, it is possible to perform the same inspection as the inspection shown in the present embodiment.

  In this embodiment, an example in which the present invention is applied to a 3-bit address decoder is shown. However, the present invention is not limited to the above example, and can be applied to an address decoder other than 3 bits. In the case of an n-bit address decoder, the number of bits of the address pattern is 2n, so that the inspection can be performed in the shortest 2n inspection steps.

  In the present embodiment, an example is shown in which the inspection is performed by comparing the detected current value of the total current with the current value expected to be detected. However, the inspection method is not limited to the above example. For example, in the case of the above-described 3-bit address decoder, since six kinds of inspection steps are executed in total, it is possible to obtain six total current values. An inspection may be performed based on the current values of these six total currents. As a result, noise such as manufacturing variation generated in the manufacturing process can be removed. Further, it is not necessary to prepare in advance a current value expected to be detected.

FIG. 3 is a circuit diagram showing an inspection circuit of the address decoder according to the first embodiment at the time of inspection. It is a circuit diagram which shows the circuit structure of the NOR gate which comprises the address decoder. It is a figure explaining the effect | action with which multiple selection of a decoder is performed. It is a figure which shows the address pattern for a test.

Explanation of symbols

10 to 17 Address decoder 31 First switching element 31
50 to 52, multiplexers 60 to 67, relay wiring 70 to 77, second switching element 90, common wiring 100, address decoder inspection circuit 110, external power source

Claims (6)

A test circuit for an address decoder that tests the functions of a plurality of address decoders that outputs a result obtained by decoding an address signal input to select a memory cell,
A multiplexer that selects and outputs a negative logic signal of the address signal and a negative logic signal that is set independently of the negative logic signal at the time of inspection for a part of the plurality of address decoders;
A first switching element that cuts off an electrical connection between an output terminal and a power supply terminal of each address decoder at the time of inspection;
A common line connected to each of the output terminals of the plurality of address decoders via a relay line;
An inspection circuit for an address decoder, comprising: a second switching element provided in each of the relay wirings and electrically connecting each output terminal and the common wiring at the time of inspection.   2. The address decoder inspection circuit according to claim 1, further comprising a register for writing the negative logic signal set independently and outputting the negative logic signal to the multiplexer.   3. The inspection circuit for an address decoder according to claim 1, wherein an external connection terminal for connecting to an external power source is provided in the common wiring.   3. The address decoder inspection circuit according to claim 1, further comprising: an inspection unit configured to inspect the address decoder based on a current value of a current flowing through the common wiring. A method for inspecting an address decoder using the address decoder inspection circuit according to claim 1, comprising:
When the address decoder is NOR type,
If all address signals that are directly input are positive logic signal groups, and all negative logic signals that are set independently at the time of inspection are negative logic signal groups,
Multiplexing is performed by selecting only one of the positive logic signal group and the negative logic signal group to “1” to multiple-select the address decoder and inspect based on the value of the current flowing through the common wiring. Perform the selection step,
In the multiple selection step, the bit for setting “1” is sequentially changed, and the multiple selection step is executed for all the bits of the signal group. A method for inspecting an address decoder using the address decoder inspection circuit according to claim 1, comprising:
When the address decoder is a NAND type,
If all address signals that are directly input are positive logic signal groups, and all negative logic signals that are set independently at the time of inspection are negative logic signal groups,
Multiplexing is performed by selecting only one of the positive logic signal group and the negative logic signal group to “0”, thereby selecting the address decoder in multiple, and performing inspection based on the value of the current flowing in the common wiring. Perform the selection step,
In the multiple selection step, the bit for setting “0” is sequentially changed, and the multiple selection step is executed for all the bits of the signal group.

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