JP2006078289A - Semiconductor memory device and test method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test a static random access memory (SRAM), in which a malfunctioning memory cell is non-destructive and the electrical characteristics of individual transistors in the cell are measured.
According to an SRAM testing method of the present invention, a circuit for switching each control circuit of a word line, a bit line, a ground line, and a power supply line of a selected memory cell to a corresponding external control circuit is provided, and a transfer gate is used. The electrical characteristics of individual devices are measured by passing a test current through either the load device or the drive device in the memory cell.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor memory device, and more particularly to a static random access memory (SRAM) test method and an SRAM incorporating a circuit therefor.

In general, four NMOS transistors and two PMOS transistors are used in a memory cell of a CMOS type SRAM intended for low power consumption. Accordingly, since the area occupied by a single memory cell is larger than that of a DRAM memory cell using one NMOS transistor, the frequency of occurrence of various defects increases accordingly. Needless to say, in order for each memory cell to function normally, it is necessary that all the six transistors in each memory cell operate normally. If an operational abnormality is found in a particular memory cell, analyzing the defective bit is important for producing a better product. Conventionally, the major analysis methods for defective bits are laboratory analysis for analysis of external abnormalities such as foreign matter and disconnection, observation method using an optical / electron microscope, etc., and analysis of electrical characteristics. In general, a method of measuring individual transistor characteristics by exposing a wiring of a defective bit, electrically isolating a transistor, and contacting a probe to the exposed wiring portion. As a method for quickly analyzing the electrical characteristics of defective bits on the production line, a pair of bit lines (BL / BLx) of defective memory cells are disconnected from the precharge circuit, connected to the measurement terminals, and further connected to the word line ( WL) is enabled, a test voltage is applied between the power line (Vss) or ground line (GND) connected to the memory cell, and the bit line, and the leakage current is measured, whereby the electrical characteristics of the defective memory cell There has been proposed a method for performing the analysis (for example, Patent Document 1). However, in this method, the two transfer gates constituting the memory cell are not subject to measurement, and the leakage current value flowing in the abnormal current path of the memory cell that should not flow originally is measured. The electrical characteristics of the individual MOSFETs constituting the memory cell cannot be obtained.
Published Patent Publication (A) Japanese Patent Laid-Open No. 5-304266 (page 7, FIG. 1)

  An object of the present invention is to provide an SRAM testing method for analyzing the electrical characteristics of defective bits by measuring the characteristics of individual transistors in a selected memory cell of the SRAM in a non-destructive manner.

  Static having first and second CMOS inverter circuits in which inputs and outputs connected to the first and second bit lines are cross-connected to each other via first and second transfer gates each having a gate connected to a common word line In the random access memory cell, the step of bringing the first transfer gate into a conducting state and the NMOS driving device or the PMOS load device of the first CMOS inverter are brought into a conducting state simultaneously with the first transfer gate. Applying a test voltage between one of a ground line or a power supply line connected to the conducting state of the NMOS drive device or the PMOS load device and the first bit; and Depending on a test voltage, the first transfer gate and the conductive NMOS driving device or Via one of the PMOS load devices, a method of testing a semiconductor memory device characterized by a step of measuring a test current flowing between the terminals of the test voltage.

  A memory cell array in which a word line, a bit line, a power line and a ground line are connected to each memory cell; means for disconnecting the word line from the word line control circuit; means for connecting the word line to an external word terminal; Means for disconnecting the line from the bit line control circuit, means for connecting the bit line to the external bit terminal, means for disconnecting the ground line from the ground line control circuit, means for connecting the ground line to the external ground terminal, A semiconductor memory device comprising: means for disconnecting the power supply line from the power supply line control circuit; and means for connecting the power supply line to an external power supply terminal.

  As an effect of the present invention, by measuring the test current flowing in the original current path of each memory cell circuit, not only the abnormal transistors among the six transistors constituting the memory cell are identified, but also Analysis of electrical characteristics is also possible.

  1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention. FIG. 1 shows a cell array, a main DEC, a CPG, a Col sw / SA, and an I / O, each of a CMOS memory cell array, a main decoder, a clock pulse generator, a column selection switch, a sense amplifier, and an input / output circuit. 1 shows a block diagram of a normal SRAM circuit, and CPG has terminals such as an external clock CK, address signals A0... A7, and Col sw / SA and I / O blocks have input / output terminals such as Din and Dout. Have However, a region 1 surrounded by a dotted line indicates an additional portion according to the present invention, and blocks 2, 3 and 4 included in the region 1 are WL sw, Vss variable sw and BL / BLx variable sw, Vdd variable sw and WL variable. Each circuit block of sw is shown in detail in FIG. 2 below.

  FIG. 2 shows specific contents of each block diagram, and WL sw is an ON / OFF switch (sw) for separating the left word line (WL) and the right cell array, and Vss variable sw and BL / BLx variable. Each of the sw, Vdd variable sw and WL variable sw is a circuit for supplying a variable input signal voltage to the ground line (Vss), the pair of bit lines (BL / BLx), the power supply line (Vdd) and the word line (WL). The figure is shown. Here, the variable sw (switch) is assumed not only to give a specified H (1) pulse or L (0) pulse voltage to the input and turn it on / off, but also to give an intermediate voltage. . Further, with respect to the ground line (Vss) and the power supply line (Vdd), in order to apply a back gate bias to each of the PMOSFET and the NMOSFET, the ground line (Vss) or the power supply line (Vdd) is connected to L (0) or H (1) It is also possible to apply a deeper voltage. It can be expected that more information can be obtained by applying various voltages to the MOSFET to be measured.

  FIG. 3 is a flowchart showing an example of the procedure of the method for analyzing the electrical characteristics of defective bits using the circuit of FIG. First, for example, “0” is written to all memory cells, “0” is read sequentially from the lowest address, “1” is written to the highest address, and then “1” is read sequentially from the highest address to “0”. Perform normal function measurements, such as performing up to the lowest address of writing. As a result, if a defective memory cell exists, the address of the defective memory cell is stored, the bit line output waveform is observed by monitor measurement of the defective memory cell, and due to a fatal defect such as disconnection or short circuit in the memory cell. Tests that flow through either the NMOS drive device or the PMOS load device of the CMOS inverter, which is a feature of the present invention, and the transfer gate connected to them, except for those incapable of operating memory cells The process of “measurement modes 1 and 2” (described later) for measuring current is performed. Further, normal memory cells in the vicinity of the malfunctioning memory cell are monitored and measured, and “measurement modes 1 and 2” are performed to measure the current flowing in each of the PMOSFET and NMOSFET of the malfunctioning memory cell, and the normal memory. The characteristics of the malfunctioning memory cell can be determined by comparing the characteristics of the cells. In selecting normal memory cells around a malfunctioning memory cell, a normal memory cell connected to the same word line or bit line as the malfunctioning memory cell to be measured is desirable in order to avoid the influence of decoder characteristics and column characteristics.

  FIG. 4 shows an example of a time chart for monitor measurement of the memory cell. In a write operation (write of “0”) to a memory cell at a specific address, H (1) pulse and L (0) are respectively applied to WL, BL, BLx and the column selection switch with reference to the clock pulse (CK). ) Pulse, H (1) and H (1) pulses are applied and L (0) is written. Next, in the Read operation (reading “0”), H (1) pulse and H (1) pulse are given to WL and the column selection switch based on the clock pulse (CK), and each of BL and BLx Monitor the output waveform. If the memory cell is normal, an L (0) level should be observed in BL and, conversely, an H (1) level should be observed in BLx, as indicated by the solid line. On the other hand, in the case of a malfunctioning memory cell, as indicated by the dotted line, the H (1) level may be maintained in BL, whereas the L (0) level may be observed in BLx.

  FIG. 5 is an explanatory diagram of a test current path of the CMOS memory cell according to the second embodiment of the present invention. The second embodiment shows the path of the test current I in “measurement mode 1” for measuring the current flowing through the NMOS drive device T2 of the CMOS inverter and the transfer gate T1 connected thereto. The test current I flows from the BL variable sw to the ground line (Vss) via the node N1, the transfer gates T1, N2, the NMOS driving device T2, and the node N3. In order to realize the above-described path of the test current I, the measurement conditions shown in “Tr. (Cell) monitor mode 1” in FIG.

  FIG. 6 shows a monitor mode of the test method of the second embodiment. First, according to the memory cell monitor measurement time chart shown in FIG. 4, “0” is written in advance to the node N2, WLsw is turned off, the circuit WL is shut off, and the WL variable sw is turned on. , Connect to external WL. Furthermore, the BL variable sw is turned on, a test voltage is applied to the external BL, the Vss variable sw is turned on, the test current I is made measurable at the Vss terminal, the Vdd variable sw is turned on, and Vdd is set. For example, a power supply voltage is applied. Under such a state, when the voltage level of the external WL is changed from L (0) to H (1) in a step function form, both transfer gates T1 and T6 are turned ON in the circuit diagram of FIG. As for the CMOS inverter on the left side, the NMOS drive device T2 is turned on and the PMOS load device is turned off, so that a test current I flows between the external BL and Vss terminals via the transfer gate T1. On the other hand, with respect to the right CMOS inverter, the CMOS memory cell forms a flip-flop circuit. Therefore, when “0” is written to the node N2, the PMOS load device T4 is turned on and the NMOS drive device T5 is turned off. Therefore, the power supply voltage of Vdd appears on the external BLx via T4 and T6. Therefore, if the BLx variable sw is turned on, the BLx is cut off, and an arbitrary test voltage is applied between the Vdd and the external BLx instead of the power supply voltage, the PMOS load device T4 is transferred via the transfer gate T6. You can know the electrical characteristics. A test method for knowing the electrical characteristics of a PMOS load device is described in Example 3 below.

  FIG. 7 is an explanatory diagram of a test current path of the CMOS memory cell according to the third embodiment. As in the case of FIG. 5, the CMOS inverter on the left side of the memory cell will be described. When “1” is written in advance in the node N2, the PMOS load device T3 is turned on and the NMOS drive device T2 is turned off. If an arbitrary test voltage is applied between BL, the test current II flows from the Vdd terminal to the external BL terminal via the nodes N5 and N4, the PMOS load device T3, and the transfer gate T1. In order to realize the above-described path of the test current II, measurement conditions shown in “Tr. (Cell) monitor mode 2” in FIG.

  FIG. 8 shows a monitor mode of the test method of the third embodiment. First, according to the memory cell monitor measurement time chart shown in FIG. 7, “1” is written in advance to the node N2, the WLsw is turned off, the circuit WL is shut off, and the WL variable sw is turned on. , Connect to external WL. Furthermore, the BL variable sw is turned ON, a test voltage is applied between the external BL terminal and the Vdd terminal, the Vss variable sw is turned ON, and the test current II can be measured at the external BL terminal, and the Vdd variable sw is set. It is turned on and Vss is set to the ground potential, for example. Under such a state, when the voltage level of the external WL is changed from L (0) to H (1) in a step function form, both transfer gates T1 and T6 are turned ON in the circuit diagram of FIG. As for the CMOS inverter on the left side, the PMOS load device T3 is turned on and the NMOS drive device T2 is turned off, so that the test current II flows between the external BL and Vdd terminals via the transfer gate T1.

  Although the measurement methods of the test currents I and II flowing through the transfer gate T1 in each of the PMOS load device T3 and the NMOS drive device T2 have been described separately in the second and third embodiments, as described above, In the state where the test current I is supplied to the NMOS drive device T2 via the transfer gate T1, the test current III is simultaneously supplied to the PMOS load device T4 via the transfer gate T6. In a state where a test current is passed to the PMOS load device T3 via T1, a test current IV is simultaneously passed to the NMOS drive device T5 via the transfer gate T6. Therefore, as shown in FIGS. 5 and 7, it is possible to measure a combination of test currents I and III and II and IV under the same test conditions. In that case, naturally, BLx is shut off and external BLx is turned ON.

  In the static random access memory (SRAM) test method of the present invention, the test current flowing through each of the PMOS load device and the NMOS drive device constituting the memory cell can be individually measured via the transfer gate. It is possible to know the electrical characteristics of each MOSFET in the cell.

1 is a block diagram of a semiconductor memory device according to a first embodiment of the invention. Circuit diagram of main part of semiconductor memory device according to embodiment 1 Flow chart of test method for defective memory cell Timing chart of write / read operation of “LoWLLevel (0)” to the memory cell Explanatory drawing of the test current path of the CMOS memory cell by Example 2 Monitor mode of the test method of Example 2 Explanatory drawing of the test current path of the CMOS memory cell by Example 3 Monitor mode of the test method of Example 3

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Additional area of semiconductor memory device 2 WL switch area 3 Vss variable switch area and BL / BLx variable switch area 4 Vdd variable switch area and WL variable switch areas T1, T2, T5, T5, T6, N-channel MOSFET
T3, T4, P-channel MOSFET
N1-N5, nodes

Claims (5)

  Static having first and second CMOS inverter circuits in which inputs and outputs connected to the first and second bit lines are cross-connected to each other via first and second transfer gates each having a gate connected to a common word line In the random access memory cell, the step of bringing the first transfer gate into a conducting state and the NMOS driving device or the PMOS load device of the first CMOS inverter are brought into a conducting state simultaneously with the first transfer gate. Applying a test voltage between one of a ground line or a power supply line connected to the conducting state of the NMOS drive device or the PMOS load device and the first bit; and Depending on a test voltage, the first transfer gate and the conductive NMOS driving device or Via one of the PMOS load devices, a method of testing a semiconductor memory device characterized by a step of measuring a test current flowing between the terminals of the test voltage.   In the static random access memory cell, after performing the function test of all the memory cells and storing the address of the malfunctioning memory cell, the test current is measured for the malfunctioning memory cell. The method of testing a semiconductor memory device according to claim 1.   Measuring a test current for a normal memory cell sharing a word line or a bit line with the malfunctioning memory cell; a measurement result of the test current; and a measurement result of the test current for the malfunctioning memory cell. 2. The method of testing a semiconductor memory device according to claim 1, further comprising a step of comparing.   Simultaneously with the step of measuring a first test current flowing through either the NMOS drive device or the PMOS load device of the first CMOS inverter circuit through the first transfer gate, the second transfer gate, and the second 2. A test method for a semiconductor memory device according to claim 1, further comprising a step of measuring a second test current flowing in either the PMOS load device or the NMOS drive device of the CMOS inverter circuit.   A memory cell array in which a word line, a bit line, a power line and a ground line are connected to each memory cell; means for disconnecting the word line from the word line control circuit; means for connecting the word line to an external word terminal; Means for disconnecting the line from the bit line control circuit, means for connecting the bit line to the external bit terminal, means for disconnecting the ground line from the ground line control circuit, means for connecting the ground line to the external ground terminal, A semiconductor memory device comprising: means for disconnecting the power supply line from the power supply line control circuit; and means for connecting the power supply line to an external power supply terminal.

Images