JP2010010264A - Semiconductor device - Google Patents

Abstract

The present invention suppresses occurrence of a displacement current that charges and discharges a parasitic capacitance due to a dv / dt surge, and prevents malfunction of a circuit.
A high breakdown voltage diode is formed by a PN junction formed by an electric field relaxation layer and a p-type portion of a support substrate. As a result, a depletion layer is formed at the PN junction constituting the high voltage diode, and each depot and each of the support bases 31a and 31b can be fixed to independent potentials by this depletion layer. For this reason, it becomes possible to suppress generation | occurrence | production of the displacement current by a dv / dt surge. Even if a displacement current is generated, the displacement current is pulled through the support base 31a. For this reason, it is possible to prevent the displacement current from flowing into the low potential reference circuit unit LV, and it is possible to prevent the circuit from malfunctioning due to the displacement current.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device used for an inverter control element or the like for driving a device such as a motor.

  As a semiconductor device used for an inverter control element or the like for driving a load such as a motor, there is an HVIC (High Voltage Integrated Circuit). The HVIC controls the power device provided in the inverter for driving the load.

  Conventionally, as shown in FIG. 10, the inverter is driven by a high-voltage reference gate drive circuit 103 corresponding to a high-voltage reference circuit that drives the high-side IGBT 102a of the inverter circuit 101 that drives the motor 100, and the low-side side. An HVIC 107 having a low potential reference gate drive circuit 104 corresponding to a low voltage reference circuit for driving the IGBT 102b and having level shift circuits 105a and 105b and a dead time generation circuit 106 therebetween is used. In the HVIC 107, the level shift of the reference voltage in the high potential reference circuit and the low voltage reference circuit is performed by transmitting a signal through the level shift circuits 105a and 105b. In such HVIC 107, in order to reduce the size of the inverter, one chip (HVIC) is being promoted, and the HVIC 107 shown in FIG. 10 is also configured by one chip.

However, in the HVIC 107 that is made into one chip in this way, there is a problem that potential interference occurs between the high potential reference circuit and the low potential reference circuit, causing the circuit to malfunction. For this reason, conventionally, element isolation is performed by a JI isolation structure, a dielectric isolation structure, a trench isolation structure using an SOI (Silicon on insulator) substrate (see, for example, Patent Document 1), and the like. However, since the potential of the output section for driving the IGBT 102a of the high potential reference circuit needs to be set to a virtual GND potential for use as a reference on the high voltage side, in any of the above element isolation structures, the level shift is low. When switching from a potential (for example, 0 V) to a high potential (for example, 750 V), a high voltage (for example, a voltage exceeding 1200 V) is generated at a fast rising speed of several tens of kV / μsec, and a large potential amplitude is generated. It is difficult to handle this high voltage surge with a fast rise (hereinafter referred to as dv / dt surge because of a high voltage rise with respect to the rise time) without malfunctioning of the circuit.
JP 2006-93229 A

  Among the element isolation structures described above, the trench isolation structure using an SOI substrate is considered to be the most resistant to noise and has the highest potential for element isolation. However, when a level shift element with a high breakdown voltage has been developed using this structure, even in an HVIC having a trench isolation structure using an SOI substrate, the potential interferes via the support substrate when a dv / dt surge is applied. In addition, a displacement current that charges and discharges a parasitic capacitance formed by a buried oxide film (BOX) disposed between the support substrate and the active layer (SOI layer) is generated, causing the circuit to malfunction. The problem of end. FIG. 11 is a cross-sectional view of the HVIC showing how the displacement current is generated. As shown in this figure, for example, the high potential reference circuit unit HV formed in the SOI layer 111 has flowed to the support substrate 112 through the embedded layer 113 composed of BOX from the portion to be the virtual GND potential. After that, a displacement current is generated along a route that flows again through the buried layer 113 into a portion of the low potential reference circuit portion LV that is set to the GND potential.

  Such a problem can be suppressed by reducing the parasitic capacitance by increasing the BOX film thickness, or by reducing the impurity concentration on the support substrate 112 side to increase the resistance and reducing the propagation of displacement current. When an amplifier circuit with an amplification factor is integrated, even a slight displacement current causes a malfunction, and a complete countermeasure is difficult.

  In view of the above points, the present invention provides a displacement for charging / discharging parasitic capacitance by a dv / dt surge when a semiconductor device including a low potential reference circuit, a high potential reference circuit, and a level shift element is formed by a trench isolation structure. An object of the present invention is to suppress the occurrence of current and prevent malfunction of the circuit.

  In order to achieve the above object, according to the first aspect of the present invention, the low potential reference circuit portion (LV) is disposed at a position corresponding to the low potential reference circuit portion (LV) with the support substrate (2) interposed therebetween. The first conductor member (30a, 31a) having the same potential as the portion to which the first potential is applied and the support substrate (2) are disposed at positions corresponding to the high potential reference circuit portion (HV). And a second conductor member (30b, 31b) having the same potential as a portion to which the second potential is applied in the high potential reference circuit section (HV), and the support substrate (2) The position corresponding to the low potential reference circuit part (LV) is a p-type semiconductor (2a, 2e, 2f), and the position corresponding to the high potential reference circuit part (HV) is an n-type semiconductor (2b, 2c, 2d), and these p-type semiconductors (2a, 2e, 2 ) And n-type semiconductor (2b, 2c, a high-voltage diode is characterized in that it is constituted by a PN junction formed by 2d).

  In this way, a high breakdown voltage diode is constituted by a PN junction constituted by p-type semiconductors (2a, 2e, 2f) and n-type semiconductors (2b, 2c, 2d). Therefore, when a potential difference occurs between the position corresponding to the high potential reference circuit portion (HV) and the position corresponding to the low potential reference circuit portion (LV) in the support substrate (2), the high breakdown voltage diode is A depletion layer is formed in the PN junction part which comprises, and it becomes possible to fix each site | part and 1st, 2nd conductor member (30a, 30b, 31a, 31b) to the independent electric potential by this depletion layer. For this reason, it becomes possible to suppress generation | occurrence | production of the displacement current by a dv / dt surge.

  In this case, as described in claim 2, the portion of the p-type semiconductor (2a, 2e, 2f) in contact with the first conductor member (30a, 31a) includes the first conductor member (30a, 31a) and A contact region (2a) in ohmic contact is provided, and a portion of the n-type semiconductor (2b, 2c, 2d) in contact with the second conductor member (30b, 31b) is provided with the second conductor member (30b, 31b). A configuration provided with a contact region (2b) in ohmic contact is preferable.

  In this way, the contact resistance between the p-type semiconductor (2a, 2e, 2f) and the first conductor member (30a, 31a) can be reduced, and the n-type semiconductor (2b, 2c, 2d) and the second conductor member are reduced. Contact resistance with (30b, 31b) can be reduced. Since the contact resistance between the p-type semiconductor (2a, 2e, 2f) and the first conductor member (30a, 31a) can be reduced, even if a displacement current is generated, it corresponds to the low potential reference circuit portion (LV). Since the first conductor member (30a, 31a) arranged at the position to be fixed to the first potential in the low potential reference circuit portion (LV), the displacement current is transmitted through the first conductor member (30a, 31a). Pull out. For this reason, it becomes possible to prevent the displacement current from flowing into the low potential reference circuit portion (LV), and it is possible to prevent the circuit from malfunctioning due to the displacement current.

  In the invention described in claim 3, the portion constituting the PN junction of the n-type semiconductor (2b, 2c, 2d) is the contact region (2b) provided in the n-type semiconductor (2b, 2c, 2d). It is characterized by being an electric field relaxation layer (2d) having a lower concentration.

  Thus, by providing the low concentration electric field relaxation layer (2d), it is possible to obtain an electric field relaxation effect.

  In this case, for example, as described in claim 4, the n-type semiconductor (2b, 2c, 2d) is covered with the contact region (2b) provided in the n-type semiconductor (2b, 2c, 2d). The n-type diffusion layer (2c) having a lower concentration than the contact region (2b) and a higher concentration than the electric field relaxation layer (2d) can be provided.

  Further, as described in claim 5, the n-type semiconductor (2b, 2c, 2d) is provided in the n-type semiconductor (2b, 2c, 2d) at an intermediate position in the thickness direction of the support substrate (2). The n-type diffusion layer (2c) having a lower concentration than the contact region (2b) and a higher concentration than the electric field relaxation layer (2d) may also be provided.

  Furthermore, as described in claim 6, the electric field relaxation layer (2 d) provided in the n-type semiconductor (2 b, 2 c, 2 d) is provided on the surface side that becomes the buried insulating film (3) side in the support substrate (2). And the support substrate (2) can be configured to be provided on the back surface side which is the second conductor member (30b, 31b) side.

  According to the seventh aspect of the present invention, the first conductor members (30a, 31a) have not only the position corresponding to the low potential reference circuit portion (LV) across the support substrate (2) but also the level shift element forming portion (LS). ) And the corresponding position.

  Thus, it can be set as the structure which has arrange | positioned the 1st conductor member (30a, 31a) also in the position corresponding to a level shift element formation part (LS).

  In the invention according to claim 8, the semiconductor layer (1) includes a chip on which the low potential reference circuit portion (LV) is formed, a chip on which the level shift element formation portion (LS) is formed, and a high potential reference circuit. It is characterized by being divided into chips formed with a portion (HV).

  As described above, the invention described in each of the above claims is also applied to a structure in which the low potential reference circuit portion (LV), the level shift element forming portion (LS), and the high potential reference circuit portion (HV) are formed as separate chips. Can be applied.

  In the invention according to claim 9, the first conductor member (30a, 31a) is divided at portions corresponding to the analog circuit, the digital circuit, and the gate drive circuit provided in the low potential reference circuit section (LV). The second conductor members (30b, 31b) are divided at portions corresponding to the analog circuit, digital circuit, and gate drive circuit provided in the high potential reference circuit section (HV). This is characterized in that the potential is fixed independently.

  As described above, the first conductor members (30a, 31a) and the first conductor members (30a, 31a) and the second circuit are respectively associated with the analog circuit, the digital circuit, and the gate drive circuit provided in the low potential reference circuit unit (LV) and the high potential reference circuit unit (HV). The two-conductor member (30b, 31b) may be divided so that the potential is independently fixed.

  In the invention according to claim 10, at least a part of the periphery of the high potential reference circuit portion (HV) is surrounded by the low potential reference circuit portion (LV), and the PN junction is low in the support substrate (2). It is characterized in that it is formed in the entire region between a position corresponding to the potential reference circuit portion (LV) and a position corresponding to the high potential reference circuit portion (HV).

  With such a structure, the PN junction formed in the entire region between the position corresponding to the low potential reference circuit portion (LV) and the position corresponding to the high potential reference circuit portion (HV) in the support substrate (2). The area becomes wider. For this reason, it becomes possible to improve the electric field relaxation effect more.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view of a semiconductor device (HVIC) according to the present embodiment. FIG. 2 is a layout diagram when the semiconductor device shown in FIG. 1 is viewed from the upper surface side. FIG. 1 is a diagram corresponding to a cross-sectional view taken along the line AA in FIG.

  Hereinafter, the configuration of the semiconductor device of this embodiment will be described with reference to these drawings. In the following description, the upper side in FIG. 1 is described as the front side of the semiconductor device, and the lower side in FIG. 1 is described as the back side of the semiconductor device.

  As shown in FIG. 1, the semiconductor device of this embodiment includes an SOI substrate 4 in which an SOI layer 1 made of, for example, n-type silicon and a support substrate 2 are joined via a buried oxide film 3. It is formed using as.

  The SOI layer 1 is disposed on the surface side of the semiconductor device, and is configured by grinding a silicon substrate to a predetermined film thickness. The SOI layer 1 is element-isolated by a plurality of trench isolation parts 5. Each trench isolation portion 5 is configured by a trench 6 reaching the buried oxide film 3 from the surface of the SOI layer 1 and an insulating film 7 disposed in the trench 6, for example, having an equal width.

  The plurality of trench isolation portions 5 have a multi-ring structure, and a region formed between the outermost trench isolation portion 5 and the innermost trench isolation portion 5 (that is, the region on the left side in FIG. 1 and FIG. 2). The low potential reference circuit portion LV, and the region in the innermost trench isolation portion 5 (that is, the region on the right side of the drawing) is formed between the high potential reference circuit portion HV and the low potential reference circuit portion LV and the high potential reference circuit portion HV. The region to be formed is a level shift element forming portion LS.

The low potential reference circuit unit LV in the SOI layer 1 includes a signal processing circuit such as an analog circuit or a digital circuit driven with a small potential, and these operate with 0 V (first potential) as a reference potential. To do. The low potential reference circuit part LV is isolated from other parts of the semiconductor device by the trench isolation part 5. The low potential reference circuit unit LV includes various elements that constitute a signal processing circuit including a gate driving circuit such as a CMOS 10. Specifically, the SOI layer 1 is element-isolated by an element isolation insulating film 11 such as STI (Shallow Trench Isolation) or LOCOS oxide film, and each element-isolated region is divided into an n-well layer 12a or p The well layer 12b is formed. A p ⁺ type source region 13a and a p ⁺ type drain region 14a are formed in the n well layer 12a, and an n ⁺ type source region 13b and an n ⁺ type drain region 14b are formed in the p well layer 12b. The surface of the n well layer 12a located between the p ⁺ type source region 13a and the p ⁺ type drain region 14a and the p well layer located between the n ⁺ type source region 13b and the n ⁺ type drain region 14b. Gate electrodes 16a and 16b are formed on the surface of 12b via gate insulating films 15a and 15b. Thus, a CMOS 10 composed of an n-channel MOSFET and a p-channel MOSFET is configured.

  Incidentally, on the surface side of the SOI layer 1, gate electrodes 16a and 16b constituting the CMOS 10, wiring portions electrically connected to the source regions 13a and 13b or the drain regions 14a and 14b, an interlayer insulating film, and the like are formed. However, the illustration is omitted here. In addition to the CMOS 10, a bipolar transistor, a diffused resistor, and a memory are also provided. Since these structures are well known, only the CMOS 10 is shown here as a representative. Further, instead of the CMOS 10, another element such as an IGBT or a power MOS transistor may be provided.

  The high potential reference circuit unit HV in the SOI layer 1 includes a signal processing circuit such as an analog circuit or a digital circuit driven at a high potential. These operate using a potential (second potential) higher than the reference potential of the low potential reference circuit portion LV as a reference potential. The high potential reference circuit portion HV is isolated from other portions of the semiconductor device by the trench isolation portion 5. The high potential reference circuit portion HV is also provided with a CMOS 10 having the same structure as that of the low potential reference circuit portion LV, and is also provided with a bipolar transistor, a diffused resistor, and a memory (not shown).

In the level shift element forming portion LS in the SOI layer 1, a high breakdown voltage LDMOS 20 is formed as a level shift element. The high breakdown voltage LDMOS 20 includes an n-type drain region 21, a p-type channel region 22, and an n ⁺ -type source region 23 that are located on the surface layer of the SOI layer 1. An n ⁺ -type contact layer 24 is formed on the surface layer of the n-type drain region 21, and a p ⁺ -type contact layer 25 is formed on the surface layer of the p-type channel region 22. The n-type drain region 21 and the p-type channel region 22 are separated by a so-called LOCOS oxide film 26. A gate electrode 28 is disposed on the p-type channel region 22 via a gate insulating film 27. Thereby, a high breakdown voltage LDMOS 20 is configured.

Note that, on the surface side of the SOI layer 1, the gate electrode 28, the n ⁺ -type source region 23 and the p ⁺ -type contact layer 25, or the wiring portion or interlayer insulating film electrically connected to the n ⁺ -type contact layer 24 However, the illustration is omitted here.

  The high breakdown voltage LDMOS 20 having such a structure is formed with a plurality of cells, and a plurality of cells are arranged between the low potential reference circuit portion LV and the high potential reference circuit portion HV, and each cell is separated by the trench isolation portion 5. It is separated.

On the other hand, the support substrate 2 is composed of a p-type silicon substrate doped with p-type impurities, and has a structure in which n-type or p-type impurities are implanted into each part. Specifically, a p ⁺ -type contact region 2 a formed by implanting p-type impurities from the back surface of the support substrate 2 is formed at a location corresponding to the low potential reference circuit portion LV in the support substrate 2. An n ⁺ -type contact region 2b formed by implanting an n-type impurity is formed on the back surface of the support substrate at a position corresponding to the high potential reference circuit portion HV in the support substrate 2. n ⁺ -type contact than n ⁺ -type contact region 2b so as to surround the region 2b n-type diffusion layer 2c which is a low concentration is formed, further n-type diffusion layer 2c so as to surround the n-type diffusion layer 2c An n− type electric field relaxation layer 2d having a lower concentration than that is formed. The n ⁺ -type contact region 2b, the n-type diffusion layer 2c, and the electric field relaxation layer 2d are formed such that, for example, n-type impurities are ion-implanted from the back surface of the support substrate 1 so that the vicinity of the back surface of the support substrate 2 has a peak concentration It is formed by thermally diffusing the implanted n-type impurity.

The p ⁺ -type contact region 2a and the n ⁺ -type contact region 2b have a high impurity concentration to reduce contact resistance, for example, 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ . The electric field relaxation layer 2d has a low concentration so as not to generate a breakdown voltage at a PN junction constituted by the electric field relaxation layer 2d and the p-type portion 2e in the support substrate 2, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ^-3 .

  Further, support tables 31a and 31b are provided on the back surface of the support substrate 2 via back surface electrodes 30a and 30b. Among these, the back electrode 30a and the support base 31a correspond to the first conductor member, and the back electrode 30b and the support base 31b correspond to the second conductor member.

  FIG. 3 is a layout diagram showing the relationship between each part formed in the SOI layer 1, the back electrodes 30a and 30b, and the support bases 31a and 31b. As shown in this figure, the back electrodes 30a, 30b and the support bases 31a, 31b are located at positions corresponding to the low potential reference circuit portion LV and positions corresponding to the high potential reference circuit portion HV on the back surface of the support substrate 2. Each is formed.

The back electrodes 30 a and 30 b are ohmically connected to the p ⁺ type contact region 2 a and the n ⁺ type contact region 2 b formed on the back surface of the support substrate 2, so that the support bases 31 a and 31 b and the support substrate 2 can be connected. The contact resistance is set to a value (for example, 10Ω or less) sufficiently smaller than the device resistance (˜1000Ω) in the low potential reference circuit portion LV. For example, the back electrodes 30a and 30b are made of Al, Au, Ni, Ti, alloys thereof, or the like. The material of the support bases 31a and 31b is composed of, for example, the same material as that of the back electrodes 30a and 30b. However, any material may be used as long as bonding strength with the back electrodes 30a and 30b can be obtained. Absent.

  Further, the back electrode 30a and the support base 31a formed at the position corresponding to the low potential reference circuit portion LV are set to the same potential as the reference potential (for example, GND in the circuit) in the low potential reference circuit portion LV. For example, the back electrode 30a or the support base 31a is electrically connected to a line (not shown) for applying a reference potential (for example, GND in the circuit) in the low potential reference circuit unit LV through a bonding wire (not shown). . Further, the back electrode 30b and the support base 31b formed at positions corresponding to the high potential reference circuit unit HV are set to the same potential as the reference potential (for example, GND in the circuit) in the high potential reference circuit unit HV. For example, the back electrode 30b or the support base 31b is electrically connected to a line (not shown) for applying a reference potential (for example, GND in the circuit) in the high potential reference circuit unit HV through a bonding wire (not shown). . For this reason, the back electrode 30a and the support base 31a formed at a position corresponding to the low potential reference circuit portion LV and the back electrode 30b and the support base 31b formed at a position corresponding to the high potential reference circuit portion HV are independent. Fixed to potential.

  An insulating film 32 formed of an oxide film or the like is formed on the back surface of the support substrate 2 between the back electrodes 30a and 30b, and the back electrodes 30a and 30b are insulated and separated by the insulating film 32. ing.

  In the semiconductor device configured as described above, a high breakdown voltage diode is configured by a PN junction formed by the electric field relaxation layer 2d and the p-type portion 2e of the support substrate 2. For this reason, when a potential difference occurs between the position corresponding to the high potential reference circuit unit HV and the position corresponding to the low potential reference circuit unit LV in the support substrate 2, the PN junction constituting the high breakdown voltage diode A depletion layer is formed, and it becomes possible to fix each site | part and each support stand 31a, 31b to the independent electric potential by this depletion layer. For this reason, it becomes possible to suppress generation | occurrence | production of the displacement current by a dv / dt surge.

  Even if a displacement current is generated, the back electrode 30a and the support base 31a arranged at positions corresponding to the low potential reference circuit unit LV are fixed to the reference potential (for example, GND potential) in the low potential reference circuit unit LV. Therefore, the displacement current is drawn through the support base 31a. For this reason, it is possible to prevent the displacement current from flowing into the low potential reference circuit unit LV, and it is possible to prevent the circuit from malfunctioning due to the displacement current.

  When the displacement current is pulled out in this way, when packaging the semiconductor device, the layout is such that the support base 31a to be pulled out is evenly arranged with respect to the low potential reference circuit portion LV. For this purpose, a dedicated GND pin is preferable.

(Second Embodiment)
A second embodiment of the present invention will be described. This embodiment is different from the first embodiment in the configuration of the n-type diffusion layer 2c and the electric field relaxation layer 2d formed in the support substrate 1, and is otherwise the same as the first embodiment. Only different parts will be described.

FIG. 4 is a cross-sectional view of the semiconductor device (HVIC) according to the present embodiment. As shown in this figure, in the semiconductor device according to the present embodiment, p ⁺ -type contact regions 2a, n ⁺ are applied to the support substrate 2 formed of a p-type silicon substrate, as in the first embodiment. Type contact region 2b, n-type diffusion layer 2c and electric field relaxation layer 2d are formed, but n-type diffusion layer 2c is not formed so as to cover n ⁺ -type contact region 2b, and the supporting substrate 2, the electric field relaxation layer 2 d surrounds the periphery thereof and is in contact with the n ⁺ -type contact region 2 b. The n-type diffusion layer 2c and the electric field relaxation layer 2d are doped with n-type impurities from the back surface of the support substrate 2 by, for example, high acceleration ion implantation so that the intermediate position of the thickness of the support substrate 2 has a peak concentration. It is formed by thermally diffusing it.

  As described above, the n-type diffusion layer 2c is formed at an intermediate position of the thickness of the support substrate 2, and the same effect as in the first embodiment can be obtained. With such a structure, since the electric field relaxation layer 2d is formed over a wider range, it is possible to obtain a further electric field relaxation effect.

(Third embodiment)
A third embodiment of the present invention will be described. In the present embodiment, the configuration of the electric field relaxation layer 2d formed in the support substrate 1 is changed with respect to the first embodiment, and the others are the same as those in the first embodiment, and therefore only different portions will be described. To do.

  FIG. 5 is a cross-sectional view of the semiconductor device (HVIC) according to the present embodiment. As shown in this figure, in the semiconductor device according to the present embodiment, the electric field relaxation layer 2d is not only from the back surface side of the support substrate 2 but also from the front surface side with respect to the support substrate 2 configured by a p-type silicon substrate. That is, the structure is formed also from the buried oxide film 3 side. In addition, the p-type diffusion layer 2 f is formed on the surface side of the support substrate 2.

  The electric field relaxation layer 2d and the p-type diffusion layer 2f on the surface side of the support substrate 2 are formed on the support substrate 2 in advance before the support substrate 2 is bonded to the SOI layer 1 through the buried oxide film 3, for example. On the other hand, it is formed by ion-implanting n-type impurities or p-type impurities.

  As described above, even in the structure in which the electric field relaxation layer 2d and the p-type diffusion layer 2f are formed not only on the back surface side but also on the front surface side, the same effect as in the first embodiment can be obtained.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. In this embodiment, the configurations of the back surface electrodes 30a and 30b and the support bases 31a and 31b are changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment, and therefore only different portions will be described. To do.

  FIG. 6 is a layout diagram showing the relationship between each part of the semiconductor device according to the fourth embodiment of the present invention, the back electrodes 30a and 30b, and the support bases 31a and 31b. As shown in this figure, a back electrode 30a and a support base 31a are arranged at positions corresponding to the low potential reference circuit portion LV and the level shift element forming portion LS on the back surface of the support substrate 2. Thus, the back electrode 30a and the support base 31a can be arranged not only at the low potential reference circuit part LV but also at a position corresponding to the level shift element forming part LS. Even with such a structure, the same effect as in the first embodiment can be obtained.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. In this embodiment, the configurations of the back surface electrodes 30a and 30b and the support bases 31a and 31b are changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment, and therefore only different portions will be described. To do.

  FIG. 7 is a diagram showing a layout when the low potential reference circuit unit LV and the high potential reference circuit unit HV of the semiconductor device according to the present embodiment are configured by a composite IC. Since the layout corresponding to each of the low potential reference circuit unit LV and the high potential reference circuit unit HV is the same, the low potential reference circuit unit LV is illustrated here.

  As shown in FIG. 7, when the low potential reference circuit portion LV is configured to include an analog circuit, a digital circuit, and a gate drive circuit such as a power MOS transistor or IGBT, each of these has a back electrode 30a (30b). Further, the support base 31a (31b) is divided. This makes it possible to fix the potential independently in each of the analog circuit, the digital circuit, and the gate drive circuit. As described above, the low potential reference circuit unit LV and the high potential reference circuit unit HV are not fixed to the same potential by the same back electrodes 30a and 30b and the support bases 31a and 31b. You may make it fix to the electric potential independent for every circuit in the reference | standard circuit part HV.

  Here, the case where the potential is independently fixed in each of the analog circuit, the digital circuit, and the gate drive circuit has been described. However, the analog circuit and the digital circuit may include a single back electrode 30a and a support base 31a. good.

(Sixth embodiment)
A sixth embodiment of the present invention will be described. In the present embodiment, the low potential reference circuit unit LV, the high potential reference circuit unit HV, and the level shift element forming unit LS are configured on separate chips, respectively, with respect to the first to fifth embodiments. Since it is the same as that of 1st-5th Embodiment, only a different part is demonstrated.

  FIG. 8 is a layout diagram showing the relationship between each part of the semiconductor device according to the present embodiment, the back surface electrodes 30a and 30b, and the support bases 31a and 31b. As shown in this figure, the low potential reference circuit unit LV, the high potential reference circuit unit HV, and the level shift element forming unit LS are configured by separate chips. Although not shown, each chip is mounted on the support substrate 2 via an insulating film, and the support substrate 2 has the structure shown in the first to third embodiments. In such a structure, as in the fourth embodiment, the back surface is located at a position corresponding to the chip on which the low potential reference circuit unit LV is formed and the chip on which the level shift element forming unit LS is formed on the back surface of the support substrate 2. An electrode 30a and a support base 31a are arranged.

  As described above, the low potential reference circuit unit LV, the high potential reference circuit unit HV, and the level shift element formation unit LS can be configured by separate chips. Thereby, the effect similar to 1st-5th embodiment can be acquired. Here, the case where the back electrodes 30a, 30b and the support bases 31a, 31b are configured as in the fourth embodiment for the chip on which each circuit is formed has been described. It can also be configured as a form.

(Seventh embodiment)
A seventh embodiment of the present invention will be described. In the present embodiment, the configuration of the low-potential reference circuit unit LV is changed with respect to the first embodiment. The other aspects are the same as those in the first to fifth embodiments, and only different portions will be described.

  FIG. 9 is a layout diagram showing the relationship between each part of the semiconductor device according to the present embodiment, the back electrodes 30a and 30b, and the support bases 31a and 31b. As shown in this figure, the low potential reference circuit unit LV is set to a level within the high potential reference circuit unit HV so that at least a part of the periphery of the high potential reference circuit unit HV is surrounded by the low potential reference circuit unit LV. The structure extends to the side opposite to the shift element forming portion LS. With such a structure, the area of the PN junction formed in the entire region between the position corresponding to the low potential reference circuit portion LV and the position corresponding to the high potential reference circuit portion HV in the support substrate 2 becomes wider. For this reason, it becomes possible to improve the electric field relaxation effect more.

(Other embodiments)
In each of the above-described embodiments, an example of the elements configuring the low potential reference circuit unit LV, the high potential reference circuit unit HV, and the level shift element forming unit LS is described. However, the types of the elements configuring these are appropriately changed. Is possible. Further, the layout of the low potential reference circuit unit LV, the high potential reference circuit unit HV, and the level shift element formation unit LS can be appropriately changed.

In each of the above-described embodiments, the case where the support substrate 2 is configured as a p-type has been described, but the present invention can be similarly applied even when the support substrate 2 is configured as an n-type. In that case, a p-type impurity layer having a concentration lower than that of the p ⁺ -type contact region 2 a is disposed so as to surround the p ⁺ -type contact region 2 a with respect to the support substrate 2, and the electric field relaxation layer is formed by the n-type portion of the support substrate 2. What is necessary is just to comprise 2d.

  Further, in the above-described embodiment, the example in which the SOI substrate 4 is used as the semiconductor substrate has been described. However, the present invention is not limited to the SOI substrate 4. For example, as for the circuit in which each circuit is configured as a separate chip as in the sixth embodiment, a semiconductor that configures each chip via a buried insulating film on a support substrate 2 configured by a semiconductor. A configuration in which layers are mounted may be used. As for the buried oxide film 3, another buried insulating film such as a nitride film or an ONO film may be used.

1 is a cross-sectional view of a semiconductor device (HVIC) according to a first embodiment of the present invention. FIG. 2 is a layout diagram when the semiconductor device shown in FIG. 1 is viewed from the upper surface side. FIG. 3 is a layout diagram showing the relationship between each part formed in the SOI layer 1 and back electrodes 30a and 30b and support bases 31a and 31b. It is sectional drawing of the semiconductor device (HVIC) concerning 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device (HVIC) concerning 3rd Embodiment of this invention. It is the layout figure which showed the relationship between each part of the semiconductor device concerning 4th Embodiment of this invention, back surface electrode 30a, 30b, and support stand 31a, 31b. It is the figure which showed the layout in case the low potential reference circuit part LV and the high potential reference circuit part HV of the semiconductor device concerning 5th Embodiment of this invention are comprised by composite IC. It is the layout figure which showed the relationship between each part of the semiconductor device concerning 6th Embodiment of this invention, back electrode 30a, 30b, and the support bases 31a, 31b. It is the layout figure which showed the relationship between each part of the semiconductor device concerning 7th Embodiment of this invention, back surface electrode 30a, 30b, and support stand 31a, 31b. It is the figure which showed the circuit structure for driving the inverter circuit which drives a motor. It is sectional drawing of HVIC which showed a mode that a displacement current generate | occur | produced.

Explanation of symbols

1 SOI layer 2 Support substrate 2a p ⁺ type contact region 2b n ⁺ type contact region 2c n type diffusion layer 2d electric field relaxation layer 2e p type part 2f n type diffusion layer 3 buried oxide film 4 SOI substrate 5 trench isolation part 10 CMOS
20 LDMOS
30a, 30b Back electrode 31a, 31b Support base LS Level shift element forming part LV Low potential reference circuit part HV High potential reference circuit part

Claims (10)

A semiconductor substrate (4) in which a semiconductor layer (1) and a support substrate (2) made of a semiconductor are bonded via a buried insulating film (3);
The semiconductor layer (1) in the semiconductor substrate (4) has a low potential reference circuit portion (LV) that operates using the first potential as a reference potential, and a second potential that is higher than the first potential. A high potential reference circuit section (HV) that operates as a reference potential, and a level shift for performing a level shift of the reference potential between the low potential reference circuit section (LV) and the high potential reference circuit section (HV) In a semiconductor device in which a level shift element forming portion (LS) provided with an element (20) is formed,
The portion of the low potential reference circuit portion (LV) to which the first potential is applied is disposed at a position corresponding to the low potential reference circuit portion (LV) with the support substrate (2) interposed therebetween. First conductor members (30a, 31a) having the same potential;
A part of the high potential reference circuit unit (HV) to which the second potential is applied is disposed at a position corresponding to the high potential reference circuit unit (HV) across the support substrate (2). A second conductor member (30b, 31b) having the same potential,
The support substrate (2) has p-type semiconductors (2a, 2e, 2f) at positions corresponding to the low potential reference circuit portion (LV) and also corresponds to the high potential reference circuit portion (HV). The position is an n-type semiconductor (2b, 2c, 2d), and a high voltage diode is formed by a PN junction composed of the p-type semiconductor (2a, 2e, 2f) and the n-type semiconductor (2b, 2c, 2d). A semiconductor device characterized by being configured. A contact region (2a) in ohmic contact with the first conductor member (30a, 31a) is formed in a portion of the p-type semiconductor (2a, 2e, 2f) that is in contact with the first conductor member (30a, 31a). Provided,
A contact region (2b) in ohmic contact with the second conductor member (30b, 31b) is formed in a portion of the n-type semiconductor (2b, 2c, 2d) that is in contact with the second conductor member (30b, 31b). The semiconductor device according to claim 1, wherein the semiconductor device is provided.   The portion of the n-type semiconductor (2b, 2c, 2d) that forms the PN junction has a lower concentration than the contact region (2b) provided in the n-type semiconductor (2b, 2c, 2d). 3. The semiconductor device according to claim 2, wherein the semiconductor device is an electric field relaxation layer (2d).   The n-type semiconductor (2b, 2c, 2d) has a lower concentration than the contact region (2b) so as to cover the contact region (2b) provided in the n-type semiconductor (2b, 2c, 2d). 4. The semiconductor device according to claim 3, further comprising an n-type diffusion layer (2c) having a higher concentration than the electric field relaxation layer (2d).   In the n-type semiconductor (2b, 2c, 2d), the contact region (2b) provided in the n-type semiconductor (2b, 2c, 2d) is provided at an intermediate position in the thickness direction of the support substrate (2). The semiconductor device according to claim 3, further comprising an n-type diffusion layer (2 c) having a low concentration and a higher concentration than the electric field relaxation layer (2 d).   The electric field relaxation layer (2d) provided in the n-type semiconductor (2b, 2c, 2d) includes a surface side which is the buried insulating film (3) side of the support substrate (2) and the support substrate (2). 4. The semiconductor device according to claim 3, wherein the semiconductor device is provided on a back surface side which is the second conductor member (30 b, 31 b) side.   The first conductor members (30a, 31a) are positioned not only at positions corresponding to the low potential reference circuit portion (LV) across the support substrate (2) but also at positions corresponding to the level shift element forming portion (LS). The semiconductor device according to claim 1, further comprising:   The semiconductor layer (1) includes a chip on which the low potential reference circuit unit (LV) is formed, a chip on which the level shift element formation unit (LS) is formed, and the high potential reference circuit unit (HV). 8. The semiconductor device according to claim 1, wherein the semiconductor device is divided into formed chips. The first conductor members (30a, 31a) are independently fixed in potential by being divided at portions corresponding to the analog circuit, digital circuit, and gate driving circuit provided in the low potential reference circuit portion (LV). And
The second conductor members (30b, 31b) are independently fixed in potential by being divided at portions corresponding to the analog circuit, digital circuit, and gate driving circuit provided in the high potential reference circuit portion (HV). The semiconductor device according to claim 1, wherein the semiconductor device is provided.   The low potential reference circuit unit (LV) surrounds at least a part of the periphery of the high potential reference circuit unit (HV), and the PN junction is the low potential reference circuit unit of the support substrate (2). 10. The semiconductor device according to claim 1, wherein the semiconductor device is formed in a whole area between a position corresponding to (LV) and a position corresponding to the high potential reference circuit portion (HV). .

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