JP2009266934A - Semiconductor device - Google Patents

Abstract

A malfunction of a circuit is prevented by suppressing potential interference through a support substrate and suppressing a displacement current caused by a parasitic capacitance caused by a buried oxide film from flowing.
The impurity concentration of the support substrate is set to 1 × 10 ¹⁴ cm ⁻³ or less, and the potential of the support substrate is set to GND. Thereby, on the high potential reference circuit portion HV side, the depletion layer capacity is increased by lowering the impurity concentration of the support substrate 2 so that the depletion layer spreads, and the combined capacity with the buried oxide film 3 is decreased. Thus, the displacement current can be suppressed. Further, on the low potential reference circuit portion LV side, the voltage applied to the buried oxide film 3 can be suppressed by fixing the potential of the support substrate 2 to GND. Therefore, it is possible to suppress the displacement current in both the low potential reference circuit unit LV and the high potential reference circuit unit HV. As a result, malfunction of the circuit can be prevented.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device used for an inverter control element or the like for driving a device such as a motor.

  As a semiconductor device used for an inverter control element or the like for driving a load such as a motor, there is an HVIC (High Voltage Integrated Circuit). The HVIC controls the power device provided in the inverter for driving the load.

  Conventionally, for driving the inverter, as shown in FIG. 9, a high potential reference gate drive circuit corresponding to a high potential reference circuit for driving the IGBT 102a on the high side of the inverter circuit 101 that drives the motor 100 is formed. An element 104 in which a low-potential reference gate drive circuit corresponding to a low-potential reference circuit for driving the element 103 and the low-side IGBT 102b is formed in a separate chip, and photocouplers 105a and 105b and a control circuit are provided between these two chips. A circuit with 106 was used. In this circuit, the level shift of the reference voltage in the high potential reference circuit and the low potential reference circuit is performed by transmitting a signal through the photocouplers 105a and 105b.

  In recent years, in order to reduce the size of the inverter, one-chip (HVIC) has been promoted. As shown in FIG. 10, a high potential for controlling the IGBTs 202 a and 202 b provided in the inverter circuit 201 that drives the motor 200. In addition to the reference circuit 203 and the low potential reference circuit 204, a semiconductor device (HVIC) 206 provided with a high voltage level shift element 205 (for example, LDMOS) is used.

  However, in the semiconductor device 206 that is made into one chip in this way, there is a problem that potential interference occurs between the high potential reference circuit 203 and the low potential reference circuit 204, causing the circuit to malfunction. For this reason, conventionally, element isolation is performed by a JI isolation structure, a dielectric isolation structure, a trench isolation structure using an SOI (Silicon on insulator) substrate (see, for example, Patent Document 1), and all of them are level shifted. When switching from a low potential (for example, 0 V) to a high potential (for example, 750 V), a high voltage (for example, a voltage exceeding 1200 V) is generated at a fast rising speed of several tens of kV / μsec. Hereinafter, it is difficult to handle (without dv / dt surge) without malfunction of the circuit because the voltage rise with respect to the rise time is high. In particular, when a circuit including an analog element sensitive to noise is used, a malfunction occurs more remarkably than a logic circuit, which causes a problem.

  Among the element isolation methods described above, the trench isolation structure using the SOI substrate is considered to be the most resistant to noise, and has the highest potential for element isolation. However, when a high voltage level shift element has been developed using this structure, even in a trench isolation structure HVIC using an SOI substrate, the potential interferes with the support substrate when a dv / dt surge is applied. In addition, a displacement current that charges and discharges a parasitic capacitance formed by a buried oxide film (BOX) disposed between the support substrate and the active layer (SOI layer) is generated, causing the circuit to malfunction. The problem of end.

  Here, as a conventional technique for suppressing potential interference in a high-breakdown-voltage element that does not have a plurality of reference potentials, there is a method for suppressing potential interference through a support substrate, which is disclosed in Patent Document 2. Specifically, when the internal resistance of the support substrate is low (specific resistance <1.5 Ωcm), the potential of the support substrate is fixed (grounded) to GND, and when the internal resistance of the support substrate is high (specific resistance> 15 Ωcm) This is a method of floating the potential of the support substrate.

The former is a method of eliminating the potential difference between the active layer side and the support substrate by securely fixing the potential of the support substrate to the GND potential and invalidating the parasitic capacitance due to the buried oxide film. This is a technique of suppressing the propagation of surge by increasing the value. If such a method is applied to a semiconductor device including an HVIC, the potential interference can be suppressed even in the semiconductor device including the HVIC.
JP 2006-93229 A JP 2002-343947 A

  However, in the case of an element having a plurality of reference potentials such as HVIC, in the former method, the support substrate becomes GND, so that a high voltage is applied to the buried oxide film on the high potential reference circuit side, and buried oxide Displacement current due to the parasitic capacitance caused by the film is generated. In the latter method, since the potential of the support substrate becomes an intermediate potential between the low potential reference circuit and the high potential reference circuit, a high voltage is applied to the buried oxide films on the low potential and high potential sides, and the buried substrate is buried. Displacement current due to parasitic capacitance due to the oxide film is generated. Furthermore, since the conventional high voltage IC is several hundreds V at most, the HVIC handles a high voltage of 600 to 1200 V, so that the influence of potential interference through the support substrate is further increased.

  In view of the above points, the present invention suppresses potential interference through a support substrate in a semiconductor device including an HVIC, and suppresses displacement current caused by parasitic capacitance due to a buried oxide film from flowing. The purpose is to prevent malfunction.

In order to achieve the above object, according to the present invention, the active layer (1) and the support substrate (2) have an SOI substrate (4) bonded with a buried insulating film (3). The active layer (1) in the SOI substrate (4) has a low potential reference circuit portion (LV) that operates using the first potential as a reference potential, and a second potential that is higher than the first potential as a reference potential. And a level shift element (20) for performing a level shift of the reference potential between the low potential reference circuit unit (LV) and the high potential reference circuit unit (HV). In the semiconductor device formed with the level shift element forming portion (LS) provided with the above, the support substrate (2) is set to an impurity concentration of 1 × 10 ¹⁴ cm ⁻³ or less and grounded. Yes.

Thus, by setting the impurity concentration of the support substrate (2) to a low concentration, specifically 1 × 10 ¹⁴ cm ⁻³ or less, and setting the potential of the support substrate (2) to ground, the low potential reference circuit The displacement current can be suppressed in both the portion (LV) and the high potential reference circuit portion (HV). As a result, malfunction of the circuit can be prevented.

  According to the second aspect of the present invention, the surface of the support substrate (2) corresponding to the low potential reference circuit portion (LV) on the side of the buried insulating film (3) has the same conductivity as the support substrate (2). An impurity layer (31) which is a mold and has a higher impurity concentration than the support substrate (2) is formed.

  Thus, by disposing the impurity layer (31) for reducing the internal resistance of the support substrate (2) on the surface portion of the support substrate (2), the buried insulating film (3) in the low potential reference circuit portion (LV). Can be grounded more reliably. As a result, the voltage applied to the buried insulating film (3) can be further reduced, and the displacement current on the low potential reference circuit portion (LV) side can be suppressed.

  In the invention according to claim 3, a trench (34) that penetrates the active layer (1) and the buried insulating film (3) on the low potential reference circuit portion (LV) side and reaches the impurity layer (31), An inner wall insulating film (35) formed so as to cover the inner wall of the trench (34), and a through electrode embedded in the inner wall insulating film (35) and embedded in the trench (34) and electrically connected to the impurity layer (31) (33), and the through electrode (33) is electrically connected to a ground wiring provided in the low potential reference circuit portion (LV).

  According to such a configuration, the potential of the impurity layer (31) can be more reliably grounded through the through electrode (33). For this reason, the voltage applied to the buried insulating film (3) can be further reduced, and the displacement current on the low potential reference circuit portion (LV) side can be further suppressed.

  According to the fourth aspect of the present invention, a portion of the back surface of the support substrate (2) opposite to the buried insulating film (3) that corresponds to the low potential reference circuit portion (LV) is provided on the support substrate (2 ) And an impurity layer (32) having a higher impurity concentration than that of the support substrate (2).

  Thus, by providing the impurity layer (32) on the back surface portion on the low potential reference circuit portion (LV) side of the support substrate (2), it is possible to further reduce the voltage applied to the buried insulating film (3). Thus, the displacement current on the low potential reference circuit part (LV) side can be further suppressed.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view of a semiconductor device (HVIC) according to the present embodiment. FIG. 2 is a layout diagram when the semiconductor device shown in FIG. 1 is viewed from the upper surface side. FIG. 1 is a diagram corresponding to a cross-sectional view taken along the line AA in FIG.

  Hereinafter, the configuration of the semiconductor device of this embodiment will be described with reference to these drawings. In the following description, the upper side in FIG. 1 is described as the front side of the semiconductor device, and the lower side in FIG. 1 is described as the back side of the semiconductor device.

  As shown in FIG. 1, the semiconductor device of this embodiment uses an SOI substrate 4 in which an SOI layer 1 made of, for example, n-type silicon and a support substrate 2 are bonded via a buried oxide film 3. Is formed.

  The SOI layer 1 is disposed on the surface side of the semiconductor device, and is configured by grinding a silicon substrate to a predetermined film thickness. The SOI layer 1 is element-isolated by a plurality of trench isolation parts 5. Each trench isolation portion 5 is configured by a trench 6 reaching the buried oxide film 3 from the surface of the SOI layer 1 and an insulating film 7 disposed in the trench 6, for example, having an equal width.

  The plurality of trench isolation portions 5 have a multi-ring structure, and a region formed between the outermost trench isolation portion 5 and the innermost trench isolation portion 5 (that is, the region on the left side in FIG. 1 and FIG. 2). The low potential reference circuit portion LV, and the region in the innermost trench isolation portion 5 (that is, the region on the right side of the drawing) is formed between the high potential reference circuit portion HV and the low potential reference circuit portion LV and the high potential reference circuit portion HV. The region to be formed is a level shift element forming portion LS.

The low potential reference circuit portion LV in the SOI layer 1 includes a signal processing circuit such as a logic circuit driven at a small potential, and these operate with 0 V (first potential) as a reference potential. The low potential reference circuit part LV is isolated from other parts of the semiconductor device by the trench isolation part 5. The low potential reference circuit unit LV includes various elements that constitute a signal processing circuit such as the CMOS 10. Specifically, the SOI layer 1 is element-isolated by an element isolation insulating film 11 such as STI (Shallow Trench Isolation) or LOCOS oxide film, and each element-isolated region is divided into an n-well layer 12a or p The well layer 12b is formed. A p ⁺ type source region 13a and a p ⁺ type drain region 14a are formed in the n well layer 12a, and an n ⁺ type source region 13b and an n ⁺ type drain region 14b are formed in the p well layer 12b. The surface of the n well layer 12a located between the p ⁺ type source region 13a and the p ⁺ type drain region 14a and the p well layer located between the n ⁺ type source region 13b and the n ⁺ type drain region 14b. Gate electrodes 16a and 16b are formed on the surface of 12b via gate insulating films 15a and 15b. Thus, a CMOS 10 composed of an n-channel MOSFET and a p-channel MOSFET is configured.

  Incidentally, on the surface side of the SOI layer 1, gate electrodes 16a and 16b constituting the CMOS 10, wiring portions electrically connected to the source regions 13a and 13b or the drain regions 14a and 14b, an interlayer insulating film, and the like are formed. However, the illustration is omitted here. In addition to the CMOS 10, a bipolar transistor, a diffused resistor, and a memory are also provided. Since these structures are well known, only the CMOS 10 is shown here as a representative.

  The high potential reference circuit portion HV in the SOI layer 1 is configured with a signal processing circuit such as a logic circuit driven at a high potential. These operate using a potential (second potential) higher than the reference potential of the low potential reference circuit portion LV as a reference potential. The high potential reference circuit portion HV is isolated from other portions of the semiconductor device by the trench isolation portion 5. The high potential reference circuit portion HV is also provided with a CMOS 10 having a structure similar to that of the low potential reference circuit portion LV, and is also provided with a bipolar transistor, a diffused resistor, and a memory (not shown).

In the level shift element forming portion LS in the SOI layer 1, a high breakdown voltage LDMOS 20 is formed as a level shift element. The high breakdown voltage LDMOS 20 includes an n-type drain region 21, a p-type channel region 22, and an n ⁺ -type source region 23 that are located on the surface layer of the SOI layer 1. An n ⁺ -type contact layer 24 is formed on the surface layer of the n-type drain region 21, and a p ⁺ -type contact layer 25 is formed on the surface layer of the p-type channel region 22. The n-type drain region 21 and the p-type channel region 22 are separated by a so-called LOCOS oxide film 26. A gate electrode 28 is disposed on the p-type channel region 22 via a gate insulating film 27. Thereby, a high breakdown voltage LDMOS 20 is configured.

Note that, on the surface side of the SOI layer 1, the gate electrode 28, the n ⁺ -type source region 23 and the p ⁺ -type contact layer 25, or the wiring portion or interlayer insulating film electrically connected to the n ⁺ -type contact layer 24 However, the illustration is omitted here.

  The high breakdown voltage LDMOS 20 having such a structure is formed with a plurality of cells, and a plurality of cells are arranged between the low potential reference circuit portion LV and the high potential reference circuit portion HV, and each cell is separated by the trench isolation portion 5. It is separated.

On the other hand, the support substrate 2 is composed of a p ⁻ type silicon substrate doped with p type impurities. In the support substrate 2, the impurity concentration of the p-type impurity is set to 1 × 10 ¹⁴ cm ⁻³ or less. For this reason, the internal resistance of the support substrate 2 is high resistance (specific resistance is 100 Ωcm or more).

  Further, as shown in FIG. 1, the back electrode 30 is disposed on the entire back surface of the support substrate 2 so as to include the low potential reference circuit portion LV to the high potential reference circuit portion HV. The back electrode 30 is connected (grounded) to GND. For this reason, the potential of the support substrate 2 is set to GND in the entire region from the low potential reference circuit unit LV to the high potential reference circuit unit HV.

  In the semiconductor device configured as described above, the potential of the support substrate 2 is fixed (grounded) to GND while the support substrate 2 has a high resistance (specific resistance of 100 Ωcm or more). For this reason, the following effects can be acquired. This will be described with reference to FIGS.

FIG. 3 is a graph showing the results of examining the dependence of the displacement current on the support substrate concentration by simulation for each of the low potential reference circuit unit LV side and the high potential reference circuit unit HV side. Specifically, with respect to how the displacement current flowing when the dv / dt surge is applied changes when the impurity concentration of the support substrate 2 is changed, the potential of the support substrate 2 is changed as in this embodiment. Was examined for each of the case of fixing to GND and the case of floating. As a result, as shown in FIG. 3, in the low potential reference circuit portion LV, when the potential of the support substrate 2 is fixed to GND, the entire displacement is caused even if the impurity concentration is changed as compared with the case of floating. Although the current can be reduced, in the high potential reference circuit portion HV, when the potential of the support substrate 2 is fixed to GND, the impurity concentration should be 1 × 10 ¹⁴ cm ⁻³ or less as compared with the case of floating. It was confirmed that the displacement current is almost the same, but the displacement current increases when the impurity concentration is 1 × 10 ¹⁴ cm ⁻³ or more. Therefore, both the low potential reference circuit unit LV and the high potential reference circuit unit HV are obtained by setting the impurity concentration of the support substrate 2 to 1 × 10 ¹⁴ cm ⁻³ or less and setting the potential of the support substrate 2 to GND. The displacement current can be suppressed.

4 and 5 show a case where the potential of the support substrate 2 is fixed to GND when the impurity concentration of the support substrate 2 is 4.4 × 10 ¹⁴ cm ⁻³ and 2 × 10 ¹³ cm ^−3. It is the figure which showed the result of having investigated by simulation the potential distribution when the dv / dt surge (10 kV / μsec, 1300 V) in each case was applied when floating and how the depletion layer spreads.

  When a dv / dt surge is applied, a depletion layer spreads in a place corresponding to the high potential reference circuit portion HV in the support substrate 2. At this time, the surge voltage is applied to the combined capacitance of the parasitic capacitance due to the buried oxide film 3 and the capacitance due to the depletion layer in the support substrate 2 (hereinafter referred to as depletion layer capacitance). At this time, the larger the depletion layer capacitance, the smaller the voltage applied to the parasitic capacitance due to the buried oxide film 3, and the displacement current can be suppressed. That is, when the applied surge voltage is the same, the depletion layer spreads more greatly when the support substrate 2 has a lower concentration, so that the voltage applied to the buried oxide film 3 becomes smaller and the displacement current can be suppressed.

When the impurity concentration of the support substrate 2 is as high as 4.4 × 10 ¹⁴ cm ⁻³ , the specific resistance ρ is about 30 Ωcm.
At this time, when the reference potential of the low potential reference circuit unit LV is 0 V and the reference potential of the high potential reference circuit unit HV is dv / dt surge of 1300 V, the potential of the support substrate 2 is fixed to GND as shown in FIG. As described above, the potential of the location corresponding to the low potential reference circuit portion LV in the support substrate 2 is 0 V on both the front surface side (the buried oxide film 3 side) and the back surface side of the support substrate 2, but the high potential reference circuit portion. The potential at a location corresponding to HV is 400 V on the front surface side of the support substrate 2 and 0 V on the back surface side. That is, almost no voltage is applied to the buried oxide film 3 on the low potential reference circuit portion LV side, but on the high potential reference circuit portion HV side, since the depletion layer capacitance is small, most of the surge voltage (1300-400V). Is applied to the buried oxide film 3.

  On the other hand, if the potential of the support substrate 2 is made floating, the potential of the support substrate 2 becomes higher than when the potential of the support substrate 2 is fixed to GND, so that a high potential reference circuit is applied when a dv / dt surge is applied. Although the voltage (1300-1004V) applied to the buried oxide film 3 on the portion HV side is reduced, a high voltage (588V) is also applied to the buried oxide film 3 on the low potential reference circuit portion LV side.

When the impurity concentration of the support substrate 2 is as low as 2 × 10 ¹³ cm ⁻³ , the specific resistance ρ is about 700 Ωcm.

At this time, when the reference potential of the low potential reference circuit unit LV is 0 V and the reference potential of the high potential reference circuit unit HV is 1300 V dv / dt surge, the impurity concentration of the support substrate 2 is 4.4 × 10 ¹⁴ cm ^−. Compared with the case of ³ , the depletion layer expands greatly, so the depletion layer capacity increases. For this reason, when the potential of the support substrate 2 is fixed to GND, as shown in FIG. 5, the potential at the location corresponding to the low potential reference circuit portion LV is the surface side (the buried oxide film 3 side) and the back surface of the support substrate 2. Both sides are almost 0 V, and the potential of the location corresponding to the high potential reference circuit portion HV is 1171 V on the front surface side of the support substrate 2 and 0 V on the back surface side. That is, almost no voltage is applied to the buried oxide film 3 on the low potential reference circuit portion LV side, and the voltage (1300-1171 V) applied to the buried oxide film 3 on the high potential reference circuit portion HV side is also on the support substrate 2. Compared with the case where the concentration is 4.4 × 10 ¹⁴ cm ⁻³ , the concentration can be significantly reduced.

On the other hand, when the potential of the support substrate 2 is made floating, the voltage (1300-1211V) applied to the buried oxide film 3 is greatly increased on the high potential reference circuit portion HV side as in the case where the support substrate 2 is set to GND. However, on the low potential reference circuit portion LV side, a high voltage (559 V) is applied to the buried oxide film 3 as in the case where the impurity concentration of the support substrate 2 is 4.4 × 10 ¹⁴ cm ^−3. Will be applied.

  Therefore, on the high potential reference circuit portion HV side, the depletion layer capacitance is increased by lowering the impurity concentration of the support substrate 2 so that the depletion layer expands, and the voltage applied to the parasitic capacitance due to the buried oxide film is decreased. It can be said that the displacement current can be suppressed. On the low potential reference circuit portion LV side, it can be said that the voltage applied to the buried oxide film 3 can be suppressed by fixing the potential of the support substrate 2 to GND.

Thus, by setting the impurity concentration of the support substrate 2 to a low concentration, specifically 1 × 10 ¹⁴ cm ⁻³ or less, and setting the potential of the support substrate 2 to GND, the low potential reference circuit portion LV and the high potential reference circuit portion LV are increased. It is possible to suppress the displacement current in both of the potential reference circuit units HV.

As described above, in the present embodiment, the impurity concentration of the support substrate 2 is set to 1 × 10 ¹⁴ cm ⁻³ or less, and the potential of the support substrate 2 is set to GND. As a result, the displacement current can be suppressed in both the low potential reference circuit unit LV and the high potential reference circuit unit HV. As a result, malfunction of the circuit can be prevented.

(Second Embodiment)
A second embodiment of the present invention will be described. The semiconductor device of the present embodiment is obtained by changing the configuration of the support substrate 2 on the low potential reference circuit unit LV side with respect to the first embodiment, and is otherwise the same as the first embodiment. Only portions different from the embodiment will be described.

FIG. 6 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in this figure, in this embodiment, a p-type impurity layer 31 is provided on the surface portion of the support substrate 2 on the low potential reference circuit portion LV side. The p-type impurity layer 31 is formed over the entire portion of the support substrate 2 corresponding to the low potential reference circuit portion LV, and has a higher p-type impurity concentration than the p ⁻ -type silicon substrate constituting the support substrate 2. Yes.

  As described above, on the low potential reference circuit portion LV side, the voltage applied to the buried oxide film 3 can be suppressed by fixing the potential of the support substrate 2 to GND. Therefore, in the low potential reference circuit portion LV, the p-type impurity layer 31 that lowers the internal resistance of the support substrate 2 is disposed in order to make the potential immediately below the buried oxide film 3 more reliably GND. As a result, the voltage applied to the buried oxide film 3 can be further reduced, and the displacement current on the low potential reference circuit portion LV side can be further suppressed.

(Third embodiment)
A third embodiment of the present invention will be described. The semiconductor device of the present embodiment is obtained by further changing the configuration of the support substrate 2 on the low potential reference circuit unit LV side with respect to the second embodiment, and is otherwise the same as the first embodiment. Only parts different from the first embodiment will be described.

FIG. 7 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in this figure, in this embodiment, in addition to the p-type impurity layer 31 shown in the second embodiment, a p-type impurity layer is further formed on the back surface of the support substrate 2 on the low potential reference circuit portion LV side. 32. This p-type impurity layer 32 is also formed over the entire portion of the support substrate 2 corresponding to the low potential reference circuit portion LV, and has a higher p-type impurity concentration than the p ⁻ -type silicon substrate constituting the support substrate 2. Yes.

  In order to make the low potential reference circuit portion LV side of the support substrate 2 more reliably GND, it is only necessary to increase the concentration of the p-type impurity in the entire portion of the support substrate 2 corresponding to the low potential reference circuit portion LV. . However, since it is difficult to perform ion implantation with a depth corresponding to the thickness of the support substrate 2, it is not easy to implant p-type impurities throughout the portion of the support substrate 2 corresponding to the low potential reference circuit portion LV. Absent. Therefore, as in the present embodiment, by providing the p-type impurity layer 32 on the back surface portion of the support substrate 2 on the low potential reference circuit portion LV side, it is possible to further reduce the voltage applied to the buried oxide film 3. Further, it is possible to further suppress the displacement current on the low potential reference circuit unit LV side.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. The semiconductor device of this embodiment has a structure in which the potential of the p-type impurity layer 31 can be more reliably set to GND than that of the second embodiment, and is otherwise the same as that of the first embodiment. Only parts different from the first embodiment will be described.

  FIG. 8 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in this figure, in this embodiment, in addition to the p-type impurity layer 31 shown in the second embodiment, the low potential reference circuit section is included in the SOI layer 1 on the low potential reference circuit section LV side. A through electrode 33 that is electrically connected to the GND wiring (ground wiring) in the LV is formed. Specifically, a trench 34 that penetrates the SOI layer 1 and the buried oxide film 3 and reaches the p-type impurity layer 31 is formed on the low potential reference circuit portion LV side, and thermal oxidation is performed on the inner wall of the trench 34. An inner wall insulating film 35 formed of, for example, is provided, and a through electrode 33 is formed therein.

  According to such a configuration, the potential of the p-type impurity layer 31 can be more reliably set to GND through the through electrode 33. Therefore, the voltage applied to the buried oxide film 3 can be further reduced, and the displacement current on the low potential reference circuit portion LV side can be further suppressed.

(Other embodiments)
In the first to fourth embodiments, an example of elements constituting the low potential reference circuit unit LV, the high potential reference circuit unit HV, and the level shift element forming unit LS is described. Can be changed as appropriate. Further, the layout of the low potential reference circuit unit LV, the high potential reference circuit unit HV, and the level shift element formation unit LS can be appropriately changed.

  Further, the third embodiment and the fourth embodiment can be combined, that is, the p-type impurity layer 32 shown in the third embodiment can be applied to a structure including the through electrode 33 as in the fourth embodiment. It is. Furthermore, it can also be set as the structure provided only with the p-type impurity layer 32 among the p-type impurity layers 31 and 32 shown in 3rd Embodiment.

  In addition, although the case where the support substrate 2 is configured as a p-type has been described here, the present invention can be similarly applied even when the support substrate 2 is configured as an n-type. In that case, when the structures of the second to fourth embodiments are applied, the support substrate 2 is provided with an n-type impurity layer having the same conductivity type as the support substrate 2 instead of the p-type impurity layers 31 and 32. What is necessary is just to form.

1 is a cross-sectional view of a semiconductor device (HVIC) according to a first embodiment of the present invention. FIG. 2 is a layout diagram when the semiconductor device shown in FIG. 1 is viewed from the upper surface side. It is the graph which showed the result of having investigated the dependence of the displacement current on the support substrate concentration by simulation. When the impurity concentration of the support substrate 2 is 4.4 × 10 ¹⁴ cm ⁻³ , when the potential of the support substrate 2 is fixed to GND and when the dv / dt surge is applied in each case floating It is the figure which showed how the electric potential distribution and the depletion layer spread. When the impurity concentration of the support substrate 2 is 2 × 10 ¹³ cm ⁻³ , the potential when the dv / dt surge is applied in the case where the potential of the support substrate 2 is fixed to GND and in the case where the potential is floating. It is the figure which showed how the distribution and the depletion layer spread. It is sectional drawing of the semiconductor device (HVIC) concerning 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device (HVIC) concerning 3rd Embodiment of this invention. It is sectional drawing of the semiconductor device (HVIC) concerning 4th Embodiment of this invention. It is the figure which showed the circuit structure for driving the inverter circuit which drives the conventional motor. It is the figure which showed the circuit structure for driving the inverter circuit which drives the conventional motor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 SOI layer 2 Support substrate 3 Buried oxide film 4 SOI substrate 5 Trench isolation part 10 CMOS
20 LDMOS
30 Back electrode 31 p-type impurity layer 32 p-type impurity layer 33 through electrode 34 trench 35 inner wall insulating film LS level shift element forming part LV low potential reference circuit part HV high potential reference circuit part

Claims (4)

An SOI substrate (4) in which an active layer (1) and a supporting substrate (2) are bonded together through a buried insulating film (3);
The active layer (1) of the SOI substrate (4) has a low potential reference circuit portion (LV) that operates using the first potential as a reference potential, and a second potential that is higher than the first potential. A high potential reference circuit section (HV) that operates as a reference potential, and a level shift for performing a level shift of the reference potential between the low potential reference circuit section (LV) and the high potential reference circuit section (HV) In a semiconductor device in which a level shift element forming portion (LS) provided with an element (20) is formed,
The semiconductor device, wherein the support substrate (2) has an impurity concentration set to 1 × 10 ¹⁴ cm ⁻³ or less and is grounded.   The surface portion on the buried insulating film (3) side of the portion corresponding to the low potential reference circuit portion (LV) in the support substrate (2) has the same conductivity type as the support substrate (2), and 2. The semiconductor device according to claim 1, wherein an impurity layer (31) having an impurity concentration higher than that of the support substrate (2) is formed. A trench (34) reaching the impurity layer (31) through the active layer (1) and the buried insulating film (3) on the low potential reference circuit part (LV) side; and the trench (34) An inner wall insulating film (35) formed so as to cover the inner wall of the inner wall insulating film, and a through electrode (in which the trench (34) is embedded in the inner wall insulating film (35) and electrically connected to the impurity layer (31)) 33)
3. The semiconductor device according to claim 2, wherein the through electrode (33) is electrically connected to a ground wiring provided in the low potential reference circuit portion (LV).   Of the back surface portion of the support substrate (2) opposite to the buried insulating film (3), the portion corresponding to the low potential reference circuit portion (LV) has the same conductivity type as the support substrate (2). The semiconductor device according to claim 1, wherein an impurity layer (32) having a higher impurity concentration than that of the support substrate (2) is formed.

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