JP2010003914A - Method for manufacturing solder bump - Google Patents

Abstract

A solder bump manufacturing method capable of improving the accuracy of the weight ratio of Cu and Sn.
A resist layer having an opening is provided on a UBM layer formed on a semiconductor element, and a Cu plating layer having a thickness of approximately 0 on the inner surface of the opening is formed by electroplating. After forming the Sn plating layer 12 in the opening 41, the resist layer 40 is removed, the UBM layer 30 is etched, and the Cu plating layer 11 and the Sn plating layer 12 are reflowed to produce Sn-0. .7Cu solder bumps are formed.
[Selection] Figure 1

Description

  The present invention relates to a method for manufacturing a Sn-Cu solder bump connected to a semiconductor element, and more particularly to a method capable of improving the accuracy of the weight ratio of Sn and Cu.

  Currently, various types of semiconductor devices are used in home electronic devices and the like. Such a semiconductor device is formed, for example, on a substrate called an interposer (or substrate) by connecting an IC (hereinafter, “semiconductor element”) such as an LSI (Large Scale Integration) by solder bumps or the like.

  These semiconductor devices are mounted by connecting the interposer and the printed board by solder or the like via solder balls or terminals.

  Conventionally, solder mainly composed of lead such as Pb-5Sn has been used for solder bumps used to connect an interposer and a semiconductor element of a semiconductor device. However, lead has various problems such as adversely affecting the human body, and currently, lead-free solder that does not use lead is used. As such lead-free solder, for example, solder using Sn-Cu is used for solder bumps (see, for example, cited document 1).

  In this solder bump manufacturing method, for example, a UBM (Under Bump Metal) layer (metal layer) in which Ti, Ni, and Pd are sequentially stacked on a semiconductor element by sputtering or the like is formed. Next, a resist layer having openings at positions where solder bumps are provided on the UBM layer is formed.

  Next, a Cu plating layer and a Sn plating layer having a predetermined volume and a constant film thickness are sequentially formed on the UBM layer exposed from the opening of the resist layer. When these Cu plating layer and Sn plating layer are formed, the resist layer is removed (peeled). After removing the resist layer, an unnecessary UBM layer is removed by etching, and the semiconductor element is reflowed to form Sn-Cu solder bumps on the UBM layer.

In such a solder bump, generally, the weight ratio of Sn and Cu is Sn-0.7Cu (Cu is 0.7% of the total weight of the solder bump), which is the weight ratio at which the melting point of the solder bump is the lowest. It has been adjusted back and forth. However, there is a problem that the melting point of the solder bump increases as the Cu weight ratio is different from 0.7%.
JP 2004-207685 A

  The solder bumps described above have the following problems. That is, when the UBM layer is removed by etching, the Ni layer and the Pd layer are etched using an acid-based etchant. However, when the acid-based etching solution comes into contact with the Cu plating layer, the Cu plating layer is also etched.

  Here, the Cu plating layer is configured such that when the resist layer is removed, a Cu plating layer and an Sn plating layer that are stacked in two stages in the shape of the opening are provided on the UBM layer. That is, the side surface of the Cu plating layer is exposed to the outside.

  In this state, when the Ni layer and the Pd layer are etched with an acid-based etching solution, the side surface of the Cu plating layer is exposed to the outside, so the Cu plating layer is also etched from the side surface, so-called side etching. It becomes.

  When the Cu plating layer is side-etched, the weight ratio of the Cu plating layer to the weight of the Cu plating layer and the Sn plating layer (the weight of the solder bump) also differs. Since the solder bump has a Cu weight ratio of less than about 0.7% and a different Cu weight ratio (out of about 0.7%) with respect to the weight of the solder bump, the Sn-Cu solder bump The melting point may be high.

  In particular, since it is a solder bump for connecting the semiconductor element and the interposer, the volume of the solder bump itself is extremely small, and the volume of the Cu plating layer, which is 0.7% of the weight of the solder bump, is further minimal. For this reason, even if it is a short time, if a Cu plating layer is side-etched, a weight ratio will collapse | crumble rapidly. Further, since the Cu plating layer has a small weight ratio to the solder bump and its volume is extremely small, for example, the Cu plating layer is formed by increasing the volume (thickening the layer thickness) on the Cu plating layer. Countermeasures for side etching are also conceivable. However, in this way, with the measure for forming the Cu plating layer thick, it is not easy to manage the ratio of the Cu plating layer, and there is a high possibility that the Cu plating layer greatly deviates from a predetermined weight ratio.

  When the melting point of the solder bump is increased, there is a possibility that the semiconductor chip or the like may be adversely affected due to unconnection due to insufficient heating temperature in the soldering (connection) between the interposer and the solder bump or an increase in the heating temperature.

  Accordingly, an object of the present invention is to provide a method for manufacturing a solder bump that can improve the accuracy of the weight ratio of Cu and Sn.

  In order to solve the above-described problems and achieve the object, the method for manufacturing solder bumps of the present invention is configured as follows.

  In one embodiment of the present invention, a step of forming a metal layer by sequentially laminating a Ti layer, a Ni layer, and a Pd layer on at least an electrode provided in a semiconductor element, and forming the metal layer on the surface of the metal layer The ratio of the copper sulfate and the inhibitor of the plating solution for Cu having the step of forming a resist layer having an opening exposing the layer, copper sulfate, and the inhibitor adsorbed on the metal layer by an electric field And the electroplating process is performed on the surface of the metal layer exposed from the opening using the plating solution, and the thickness is thicker at the center of the opening than the inner side of the opening. A step of forming a Cu plating layer, a step of forming an Sn plating layer on the surface of the metal layer and the surface of the Cu plating layer exposed from the opening, a step of removing the resist layer, Etching is performed on the metal layer, and at least the Pd layer in contact with the Cu plating layer and the Ti layer and a part of the Ni layer located between the Sn plating layer of the metal layer and the semiconductor element remain. And a step of reflowing the Cu plating layer and the Sn plating layer. A method of manufacturing a solder bump is provided.

  According to the present invention, it is possible to improve the accuracy of the weight ratio of Cu and Sn even in the manufacturing method of the Sn—Cu solder bump in which the UBM layer is etched after forming the Cu plating layer and the Sn plating layer. .

  1 is a cross-sectional view showing a configuration of a solder bump 10 according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a process of forming the solder bump 10, and FIG. 3 is a cross-section showing a process of forming the solder bump 10. 4 is a cross-sectional view showing the formation process of the solder bump 10, FIG. 5 is a cross-sectional view showing the formation process of the solder bump 10, and FIG. 6 is a cross-sectional view showing the formation process of the solder bump 10.

  As shown in FIG. 1, the solder bumps 10 are formed on, for example, a semiconductor element such as an LSI, a wafer, or the like (hereinafter referred to as “semiconductor element”). That is, the solder bump 10 is formed on the UBM layer (metal layer) 30 formed on the electrode of the semiconductor element 20 or the like. Such a semiconductor element 20 forms a semiconductor device by soldering the formed solder bump 10 to an interposer or the like.

  In the UBM layer 30, a Ti layer 31, a Ni layer 32, and a Pd layer 33 are sequentially formed from the semiconductor element 20 side. The Ti layer 31, Ni layer 32, and Pd layer 33 are formed by sputtering or the like.

  The solder bump 10 is made of Sn—Cu. Here, the solder bump 10 has Sn—Cu having the lowest melting point, for example, Sn-0 having a Cu weight of 0.7% with respect to the weight of the solder bump 10 (Sn—Cu). .7Cu is used. Here, the weight ratio of Cu may be a weight ratio having a relatively low melting point from the viewpoint of accuracy in forming the solder bumps 10, and as an example, the ratio of the Cu melting point is relatively low. The weight may be in the range of 0.5% to 3% with respect to the weight of the solder bump 10. The weight ratio of Cu is not limited to 0.7% depending on the use conditions of the solder bumps 10, and the weight ratio can be set as appropriate.

A method for manufacturing such a solder bump 10 will be described with reference to FIGS.
As shown in FIG. 2, first, as a first step, a Ti (titanium) layer 31 is formed on the surface of the surface having the electrodes of the semiconductor element 20 by sputtering or the like. Next, a Ni (nickel) layer 32 is formed on the Ti layer 31, and a Pd (palladium) layer 33 is formed on the Ni layer 32 by sputtering or the like. In this manner, the UBM layer 30 is formed by sequentially forming and stacking the Ti layer 31, the Ni layer 32, and the Pd layer 33.

  In addition, the Ti layer 31 and the Ni layer 32 are provided to improve the adhesion between the semiconductor element 20 and the solder bump 10 while being hardly dissolved in the solder bump 10. The Pd layer 33 is provided for preventing oxidation of the surface of the Ni layer 32.

  As shown in FIG. 3, as a second step, a resist layer 40 is formed on the UBM layer 30 formed in the first step. The resist layer 40 has openings 41 that are patterns for forming solder bumps 10 to be described later. The opening 41 exposes the UBM layer 30.

  Next, as shown in FIG. 4, as a third step, the Cu plating layer 11 is formed on the surface of the UBM layer 30 exposed from the opening 41 and on the inner side of the inner surface of the opening 41 by electroplating. Form. As shown in FIG. 4, the Cu plating layer 11 has an end portion of the Cu plating layer 11 located at a ridge where the inner side surface of the opening 41 and the surface of the UBM layer 30 intersect, and the opening 41 from the ridge. It is formed so that its thickness gradually increases and changes to at least a certain distance toward the center side of the.

  That is, the Cu plating layer 11 has a thickness (height) of approximately 0 μm on the inner surface of the opening 41 and is hardly formed. As the distance from the inner surface of the opening 41 increases, the thickness increases, and a substantially flat cross-sectional shape is obtained from a certain distance. In addition, the thickness of the Cu plating layer 11 is hardly formed on the inner surface of the opening 41, and the volume ratio of the Cu plating layer 11 to the volume of the solder bump 10 is such that the weight ratio of the Cu plating layer 11 to the solder bump 10 is 0. The volume may be 5% to 3%, and the cross-sectional shape may be an arc shape.

Details of the method of forming the Cu plating layer 11 will be described below.
First, the plating solution used for the electroplating method is adjusted. This plating solution is, for example, a copper sulfate solution, and the copper sulfate solution contains, for example, copper sulfate and a solute that is an inhibitor of two kinds of organic substances (organic compounds). These inhibitors are two, a suppressor (hereinafter “first inhibitor”) as a leveler (for smoothing) and an inhibitor (hereinafter “second inhibitor”) as a surfactant.

  For example, an organic substance such as polyamine is used as the first inhibitor as the leveler. The first inhibitor has a property of being attracted and adsorbed to the plating surface when the strength of the electric field is strong. The first inhibitor also has a leveler, that is, a function of smoothing the plating surface. In addition, this 1st inhibitor is an organic agent and has the effect which makes Cu hard to precipitate on the surface.

  That is, this first inhibitor is adsorbed on the surface of the Cu plating layer 11 and / or the UBM layer 30 (Pd layer 33) having a strong electric field during electroplating, and is adsorbed. Cu plating layer 11 becomes difficult to deposit on the surface. Thereby, formation of Cu plating layer 11 will be controlled. In addition, this 1st inhibitor may be another organic substance etc. instead of polyamine, as long as it has an equivalent property.

  For example, an organic substance such as polyethylene glycol is used as the second inhibitor as the surfactant. The second inhibitor is adsorbed on the surface of the Cu inhibitor when contacting with the Cu plating layer 11 and / or the UBM layer 30. Thus, it has the effect that Cu plating layer 11 becomes difficult to precipitate because this inhibitor adsorbs.

  For adjusting the ratio between the two inhibitors in the plating solution and copper sulfate, the thickness of the inner surface of the opening 41 is approximately 0 as appropriate, as in the Cu plating layer 11 described above. Adjust so that That is, the conditions such as the deposition of the Cu plating layer 11 and the adsorption of the inhibitor vary depending on the nature of each inhibitor, the strength of the electric field of electroplating, the immersion time, and the like. For this reason, since the formation state of the Cu plating layer 11 is also different, the plating solution is appropriately adjusted. Specifically, the ratio is adjusted by forming the Cu plating layer 11 with a plating solution having an inhibitor of each ratio, measuring and confirming the formed Cu plating layer 11, and having a predetermined shape, that is, at least an opening. What is necessary is just to determine the ratio from which thickness becomes substantially 0 by the inner surface of 41.

  Next, at least the UBM layer 30, the opening 41, and the resist layer 40 are immersed in a plating solution, and a predetermined current is applied for a predetermined time. The predetermined current and the predetermined time vary depending on the relationship between the thickness of the Cu plating layer 11, the properties of the plating solution, and the plating conditions (current, time, etc.). Details thereof are omitted.

  When the UBM layer 30 comes into contact with the plating solution, first, the second inhibitor in the plating solution starts to be adsorbed on the UBM layer 30. Next, when an electric current is applied, copper ions move to the surface of the UBM layer 30 and begin to be attached (reduced), and the first inhibitor also starts to be adsorbed (attached) to the UBM plating layer.

  When a current is applied to the UBM layer 30, the electric field at the ridge (the bottom inner side of the opening 41) between the inner surface of the opening 41 and the UBM layer 30 is strong, and gradually increases toward the center of the opening 41. It becomes weak and becomes constant from a certain distance. That is, the electric field becomes stronger from the point at a certain distance from the center side of the opening 41 toward the inner surface of the opening 41.

  That is, the first inhibitor is adsorbed more on the inner surface side of the opening 41, and the adsorbed first inhibitor decreases toward the center side of the opening 41, and the center side of the opening 41. The first inhibitor adsorbed from a certain distance is constant.

  For this reason, when a current is started to be applied, first, the second inhibitor continues to be adsorbed on the entire UBM layer 30 exposed from the opening 41, and the first inhibitor is adsorbed on the entire exposed surface of the UBM layer 30. . In particular, a large amount of the first inhibitor is adsorbed on the inner surface side of the opening 41.

  Further, copper ions adhere to the surface of the UBM layer 30 including the first inhibitor and the second inhibitor exposed from the opening 41, and the Cu plating layer 11 is formed. At this time, adhesion (reduction) of copper ions is suppressed by the first inhibitor and the second inhibitor. Further, the first inhibitor and the second inhibitor are also adsorbed on the surface of the Cu plating layer 11 formed by adhering to the upper part of the UBM layer 30.

  As described above, the first inhibitor and the second inhibitor are further adsorbed on the surface of the UBM layer 30 and the Cu plating layer 11 being formed, and the formation of the Cu plating layer 11 is suppressed. In particular, there is little adsorption of each inhibitor from the inner surface side to the center side of the opening 41 of the UBM layer 30. Therefore, the thickness of the Cu plating layer 11 becomes substantially zero on the inner surface side of the opening 41 of the UBM layer 30, and the thickness gradually increases toward the center of the opening 41. The thickness is formed flat from the center side that is a fixed distance away from the side surface. When the Cu plating layer 11 is thus formed for a predetermined time by electroplating, the plating solution is washed to form the Cu plating layer 11 in a volume (film thickness) having a predetermined weight ratio.

  Next, when the Cu plating layer 11 is formed in the third step, Sn plating is performed on the surfaces of the Cu plating layer 11 and the UBM layer 30 and in the opening 41 as the fourth step, thereby forming the Sn plating layer 12. In addition, the Sn plating layer 12 may use an electroplating method, and may also use a vapor deposition plating method. At this time, the thickness of the Sn plating layer 12 is formed so that the weight ratio of the Cu plating layer 11 to the solder bump 10 is 0.7%.

  Note that the volume of the Sn plating layer 12 is set to a predetermined volume by determining the thickness of the plating film thickness of the Sn plating layer 12 according to the processing time of the plating process in consideration of the Cu plating layer 11 to be formed. To do. Here, the processing time of the plating process for determining the thickness of the plating film thickness is set by adjusting in advance according to the plating solution to be used, the conditions of the plating process, and the like.

  After the Sn plating layer 12 is formed, next, as a fifth step, the resist layer 40 is removed using a resist stripping solution or the like. In this state, as shown in FIG. 5, the Cu plating layer 11 and the Sn plating layer 12 are laminated on the UBM layer 30.

  Next, as shown in FIG. 6, the UBM layer 30 is etched as a sixth step. First, the Ni layer 32 and the Pd layer 33 are etched with an acid-based etchant. At this time, the Ni layer 32 is etched so as to have an area equivalent to the bottom surface shape of the Sn plating layer 12 or smaller than the bottom area (or shape) of the Sn plating layer 12.

  In addition, the Pd layer 33 is etched substantially the same as the bottom shape of the Sn plating layer 12. That is, by performing etching equivalent to the bottom shape of the Sn plating layer 12 on the Pd layer 33, it is possible to prevent the surfaces where the Pd layer 33 and the Sn plating layer 12 are in contact with each other from being exposed to the outside. This prevents the Cu plating layer 11 from being exposed to the outside.

  Next, the Ti layer 31 is etched. The Ti layer 31 may be etched using anisotropic etching or other etching. Further, the Ti layer 31 may have substantially the same shape and area as the Ni layer 32, for example.

  Next, as a seventh step, the etched UBM layer 30, Cu plating layer 11 and Sn plating layer 12 are reflowed at the melting temperature of the Cu plating layer 11 and Sn plating layer 12. By this reflow, the Cu plating layer 11 and the Sn plating layer 12 are melted, the melted Cu plating layer 11 and the Sn plating layer 12 are mixed, and the circular Sn—Cu solder shown in FIG. Bumps 10 are formed.

  In the solder bump 10 thus configured, even if the Ni layer 32 and the Pd layer 33 are plated with an acid-based etching solution after the Cu plating layer 11 and the Sn plating layer 12 are formed, the Cu plating layer 11 is exposed. Therefore, it is not etched with the etching solution. As a result, the weight ratio of the Cu plating layer 11 to the solder bump 10 is not lost, and the accuracy of the weight ratio can be improved.

Details will be described below.
In general, since the etching solution is acidic, when the etching solution touches the Cu plating layer 11, the Cu plating layer 11 is also etched.

  However, in the present embodiment, as described above, the Cu plating layer 11 having the thickness at the position of the inner surface of the opening 41 is substantially zero is formed by the first inhibitor, and the Sn plating layer 12 and the Pd are formed. By covering the Cu plating layer 11 with the layer 33, the Cu plating layer 11 is not exposed to the outside. Further, when the Ni layer 32 and the Pd layer 33 are etched, the etching of the Pd layer 33 is substantially the same as the opening area of the opening 41, so that the Cu plating layer 11 is etched due to excessive etching of the Pd layer 33. It is also possible to prevent exposure from between the Pd layer 33 and the Sn plating layer 12.

  For this reason, even if the Ni layer 32 and the Pd layer 33 are etched, the Cu plating layer 11 is not etched, and the predetermined volume of the Cu plating layer 11 can be maintained. As a result, the weight ratio between the solder bump 10 and Cu can be managed within a predetermined weight ratio (here, 0.5% to 3%), and the solder bump 10 having a low melting point temperature can be obtained. It becomes possible.

  Further, the Cu plating layer 11 in which the thickness of the position of the inner side surface of the opening 41 is approximately 0 μm may be simply electroplated with a plating solution having a first inhibitor. It can be formed easily. Furthermore, once the plating solution capable of forming the Cu plating layer 11 in a predetermined shape is adjusted, the Cu plating layer 11 can be formed under the same electroplating conditions. That is, manufacturing management such as the thickness of the Cu plating layer 11 becomes easy. Further, electroplating may be performed using the adjusted plating solution under predetermined conditions, and no special process is required, so that the manufacturing cost of the semiconductor device is not increased.

  Here, the thickness of the Cu plating layer 11 positioned on the inner surface of the opening 41 is approximately 0 μm. However, actually, the Cu plating layer 11 having a very thin thickness is formed around the opening 41. Sometimes formed. However, even in this case, the Cu plating layer 11 exposed to the outside is extremely small, and even when side etching is performed when the UBM layer 30 is etched, only a very small amount of the Cu plating layer 11 is etched. That's it. For this reason, the volume of the Cu plating layer 11 hardly changes.

  As described above, the Cu plating layer 11 is exposed to the outside by the Sn plating layer 12 and the Pd layer 33 by forming the Cu plating layer 11 using a plating solution containing an inhibitor whose adsorption is different depending on the strength of the electric field. There is no longer to do. Thereby, even if the UBM layer 30 is etched, the Cu plating layer 11 can be prevented from being etched, and a predetermined volume of the Cu plating layer 11 can be maintained.

  This also makes it possible to maintain the weight ratio of Cu with respect to the weight of the solder bump 10 at a predetermined ratio, improving the accuracy of the weight ratio of Cu (Cu plating layer 11), and reducing the solder bump 10 having a low melting point. It becomes possible to form.

  Modifications other than the above-described embodiments will be described. For example, in the above-described example, the UBM layer 30 includes the Ti layer 31, the Ni layer 32, and the Pd layer 33 from the semiconductor element 20 side. However, the UBM layer 30 is not limited to these configurations. As long as it is possible to improve the close contact between the semiconductor element 20 and the solder bumps 10, other materials may be used, or a configuration without any of them may be used.

  In addition, the cross-sectional shape of the Cu plating layer 11 is thicker as it is separated from the inner surface of the opening 41, and is a substantially flat cross-sectional shape from a certain distance, but as described above, An arc-shaped cross section may be used. Moreover, the cross section may be rectangular. That is, any shape can be applied as long as the Cu plating layer 11 is not exposed to the outside and the weight ratio with the solder bump 10 is within a predetermined range.

  In FIG. 4, the above-described Cu plating layer 11 is approximately 0 μm at the position of the inner surface of the opening 41, and the Cu plating layer 11 is formed without being substantially separated from the inner surface of the opening 41. However, the Cu plating layer 11 may be formed from the point where the end of the Cu plating layer 11 is further away from the inner side than that shown in FIG. That is, the outer end portion of the Cu plating layer 11 may not be in contact with the opening 41 (not exposed to the outside) or may have a thickness of approximately 0 μm at the inner surface position of the opening 41. Further, even if the Cu plating layer 11 has a certain thickness at the inner side surface position of the opening 41, the thickness (area) exposed to the outside is smaller than the thickest film thickness of the Cu plating layer 11. If the weight ratio of Cu after etching is within a predetermined range, a part of the Cu plating layer 11 may be exposed to the outside.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

Sectional drawing which shows the solder bump which concerns on one embodiment of this invention. Sectional drawing which shows one of the formation process of the solder bump. Sectional drawing which shows one of the formation process of the solder bump. Sectional drawing which shows one of the formation process of the solder bump. Sectional drawing which shows one of the formation process of the solder bump. Sectional drawing which shows one of the formation process of the solder bump.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Solder bump, 11 ... Cu plating layer, 12 ... Sn plating layer, 20 ... Semiconductor element, 30 ... UBM layer, 31 ... Ti layer, 32 ... Ni layer, 33 ... Pd layer, 40 ... Resist layer, 41 ... Opening Department.

Claims (5)

Forming a metal layer by sequentially laminating a Ti layer, a Ni layer and a Pd layer by sputtering on at least an electrode provided in a semiconductor element;
Forming a resist layer having an opening exposing the metal layer on a surface of the metal layer;
A step of adjusting the ratio of the copper sulfate and the inhibitor in the plating solution for Cu having copper sulfate and an inhibitor adsorbed on the metal layer by an electric field;
An electroplating process is performed on the surface of the metal layer exposed from the opening using the plating solution, and a thick Cu plating layer is formed on the inner side of the opening on the center side of the opening. Process,
Forming a Sn plating layer on the surface of the metal layer and the Cu plating layer exposed from the opening;
Removing the resist layer;
Etching is performed on the metal layer, and at least the Ti layer and part of the Ni layer located between the Sn plating layer of the metal layer and the semiconductor element, and the Pd layer in contact with the Cu plating layer are at least A process of remaining;
A process of reflowing the Cu plating layer and the Sn plating layer.   2. The solder bump manufacturing method according to claim 1, wherein the Cu plating layer is formed in a weight ratio of 0.5% to 3% with respect to a total weight of the Cu plating layer and the Sn plating layer. Method.   The Cu plating layer has an end portion of the Cu plating layer located at a ridge where the inner side surface of the opening and the surface of the metal layer intersect, and is at least constant from the ridge toward the center of the opening. The method of manufacturing a solder bump according to claim 1, wherein the thickness gradually increases to a distance.   2. The method of manufacturing a solder bump according to claim 1, wherein the Cu plating layer is formed to be separated from an inner surface of the opening to a center side of the opening.   2. The method of manufacturing a solder bump according to claim 1, wherein the Cu plating layer is formed to be thinnest at a position of an inner surface of the opening.

Images