JP2010093118A - Light-receiving element and light-receiving apparatus - Google Patents

Abstract

A light receiving element capable of generating a large photocurrent while minimizing an increase in parasitic capacitance and a light receiving device including the light receiving element are provided.
In a light receiving element 10, a semiconductor layer 14 having a p-type semiconductor region 14A and an n-type semiconductor region 14B facing each other in an in-plane direction is provided. Both the facing portion 18A of the p-type semiconductor region 14A facing the n-type semiconductor region 14B and the facing portion 18B of the n-type semiconductor region 14B facing the p-type semiconductor region 14A are alternately uneven.
[Selection] Figure 2

Description

  The present invention relates to a light receiving element that generates an electric charge according to the amount of received light and a light receiving device including the same.

  2. Description of the Related Art Conventionally, techniques for detecting the position of an object that is in contact with or close to a display surface of a display device are known. Among them, a representative and widely used technique is a display device provided with a touch panel. There are various types of touch panels, but a type that detects a capacitance is one of the most popular touch panels. This type of device detects changes in the surface charge of the panel by touching the touch panel with a finger, and detects the position of the object. Therefore, the user can operate intuitively by using such a touch panel.

  Recently, various technologies have been proposed that can detect the position of an object without separately providing such a touch panel on the display surface. For example, in an organic EL (Electro-Luminescence) display or a liquid crystal display, a technique for periodically operating a light receiving element disposed on a display surface has been proposed. By using such a display device, it is possible to detect the position of an object based on the captured video. Therefore, by using such a display device, it is possible to detect the position of an object with a simple configuration without separately providing components such as a touch panel on the display surface.

  FIG. 8 illustrates an example of a circuit configuration of the light receiving device in the display device capable of position detection described above. The light receiving device 100 shown in FIG. 8 includes a light receiving element 110, a capacitive element 111, and two transistors 112 and 113. The light receiving element 110 generates an electric charge according to the amount of received light, and includes, for example, a photodiode, a phototransistor, or the like. FIG. 8 illustrates the case where the light receiving element 110 is made of a photodiode. Each of the transistors 112 and 113 is configured by, for example, a thin film transistor (TFT).

  In the light receiving device 100, for example, the cathode of the light receiving element 110 is connected to the power supply voltage line VDD, the anode of the light receiving element 110 is the drain of the resetting transistor 112, one end of the capacitive element 111, and the amplifying transistor 113. Connected to the gate. The gate of the transistor 112 is connected to the reset signal line RST, and the source of the transistor 112 is connected to the reference voltage line VSS. The other end of the capacitor 111 is connected to the reference voltage line VSS, and the source of the transistor 113 is connected to the power supply voltage line VDD. The drain of the transistor 113 is connected to the signal output line OUT.

For example, Patent Document 1 discloses a transistor in which the pn junction surface is uneven and the area of the pn junction surface is enlarged for the purpose of improving static characteristics.
JP 56-4274 A

  Incidentally, in the light receiving device 100 described above, the voltage Vs of the signal output line OUT is Ip × t / Cs. Here, Ip is a photocurrent output from the light receiving element 110, t is a light irradiation time, and Cs is a capacitance of the light receiving element 110. From the above relational expression, in order to increase the sensitivity of the light receiving device 100, (1) the sensitivity of the light receiving element 110, that is, the photocurrent generated from the light receiving element 110 is increased, or (2) the time for light detection is increased. Or (3) reducing the capacitance of the capacitive element 111. However, since the time required for detection cannot be increased so much, it is necessary to practice the above (1) or (3) in order to increase the sensitivity of the light receiving device 100.

  However, in an actual circuit, the storage capacitor C ′ for accumulating charges generated from the light receiving element 110 is Cs + Cp. Here, Cp is a parasitic capacitance of the light receiving element 110. Therefore, in order to increase sensitivity in an actual circuit, it is necessary to practice the above (1) or practice to reduce the parasitic capacitance Cp.

  However, when the size of the light receiving element 110 is increased in order to practice the above (1), there is a problem that the parasitic capacitance Cp becomes enormous.

  The present invention has been made in view of such problems, and an object thereof is to provide a light receiving element capable of generating a large photocurrent while minimizing an increase in parasitic capacitance, and a light receiving device including the light receiving element. There is to do.

  The first light receiving element of the present invention includes a semiconductor layer having a p-type semiconductor region and an n-type semiconductor region facing each other in the in-plane direction. The first light receiving element is provided with electrodes that are in separate contact with the p-type semiconductor region and the n-type semiconductor region. In addition, a gate insulating film and a gate electrode are provided in a facing region between a portion of the p-type semiconductor region facing the n-type semiconductor region and a portion of the n-type semiconductor region including a portion facing the p-type semiconductor region. It has been. In addition, at least one of a portion facing the n-type semiconductor region in the p-type semiconductor region and a portion facing the p-type semiconductor region in the n-type semiconductor region has an uneven shape.

  The first light receiving device of the present invention takes out the light receiving element that generates a charge according to the amount of received light, a capacitive element that accumulates the charge generated from the light receiving element, and takes out the charge accumulated in the capacitive element as a photocurrent. An output element and an emission element that discharges the charge remaining in the capacitor element after the charge is taken out by the output element are provided.

  In the first light receiving element and the first light receiving device of the present invention, in the semiconductor layer, a portion of the p-type semiconductor region that faces the n-type semiconductor region and a portion of the n-type semiconductor region that faces the p-type semiconductor region. At least one is uneven. Accordingly, the facing area between the p-type semiconductor region and the n-type semiconductor region can be increased without increasing the size of the light receiving element.

  The second light receiving element of the present invention has a second conductivity type provided in a gap between a pair of first conductivity type semiconductor regions and a pair of first conductivity type semiconductor regions facing each other with a predetermined gap in an in-plane direction. A semiconductor layer having a semiconductor region is provided. The second light receiving element is provided with electrodes that are in separate contact with the pair of first conductive semiconductor regions and the second conductive semiconductor regions. In addition, the opposing region between the first conductive type semiconductor region and the second conductive type semiconductor region facing part and the second conductive type semiconductor region facing part including the first conductive type semiconductor region, A gate insulating film and a gate electrode are provided. And at least one of the opposing part with the 2nd conductivity type semiconductor area among the 1st conductivity type semiconductor area and the opposing part with the 1st conductivity type semiconductor area among the 2nd conductivity type semiconductor areas is uneven.

  The second light receiving device of the present invention takes out the light receiving element that generates a charge corresponding to the amount of received light, a capacitive element that accumulates the charge generated from the light receiving element, and takes out the charge accumulated in the capacitive element as a photocurrent. An output element and an emission element that discharges the charge remaining in the capacitor element after the charge is taken out by the output element are provided.

  In the second light receiving element and the second light receiving device of the present invention, in the semiconductor layer, a portion of the first conductive type semiconductor region facing the second conductive type semiconductor region and a first conductive type among the second conductive type semiconductor regions. At least one of the portions facing the type semiconductor region has an uneven shape. Thereby, even if it does not enlarge the size of a light receiving element, the opposing area of a 1st conductivity type semiconductor region and a 2nd conductivity type semiconductor region can be enlarged.

  According to the first light receiving element and the first light receiving device of the present invention, in the semiconductor layer, the p-type semiconductor region is opposed to the n-type semiconductor region and the n-type semiconductor region is opposed to the p-type semiconductor region. Since at least one of the portions has a concavo-convex shape, a large photocurrent can be generated from the light receiving element while minimizing an increase in parasitic capacitance of the light receiving element.

  According to the second light receiving element and the second light receiving device of the present invention, in the semiconductor layer, the first conductive type semiconductor region, the portion facing the second conductive type semiconductor region, and the second conductive type semiconductor region of the first conductive type semiconductor region. Since at least one of the portions facing the one-conductivity-type semiconductor region has a concavo-convex shape, a large photocurrent can be generated from the light receiving element while minimizing an increase in parasitic capacitance of the light receiving element.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First embodiment]
FIG. 1 shows an example of a circuit configuration of the light receiving device 1 according to the first embodiment of the present invention. The light receiving device 1 of the present embodiment is formed with an organic EL element and a liquid crystal element on an insulating substrate such as a plastic film substrate or a glass substrate, although not shown.

  The light receiving device 1 according to the present embodiment includes, for example, a light receiving element 10, a capacitive element 20, and two transistors 30 and 40. The light receiving element 10 generates electric charge according to the amount of received light, and is constituted by a photodiode. The capacitive element 20 accumulates charges generated from the light receiving element 10 and is constituted by a capacitor. The transistor 40 (output element) extracts the charge accumulated in the capacitor element 20 as a photocurrent, and the transistor 30 (emission element) remains in the capacitor element 20 after the charge is extracted by the transistor 40. It releases electric charge. Each of these transistors 30 and 40 is constituted by, for example, a thin film transistor (TFT).

  In the light receiving device 1, for example, the cathode of the light receiving element 10 is connected to the power supply voltage line VDD, and the anode of the light receiving element 10 is connected to the drain of the transistor 30, one end of the capacitive element 20, and the gate of the transistor 40. . The gate of the transistor 30 is connected to the reset signal line RST, and the source of the transistor 30 is connected to the reference voltage line VSS. The other end of the capacitive element 20 is connected to the reference voltage line VSS, and the source of the transistor 40 is connected to the power supply voltage line VDD. The drain of the transistor 40 is connected to the signal output line OUT.

  FIG. 2A shows an example of a cross-sectional configuration of the light receiving element 10 of FIG. The light receiving element 10 is, for example, a bottom gate type photodiode in which a gate electrode 12, a gate insulating film 13, a semiconductor layer 14, and electrodes 15 and 16 are sequentially provided on a substrate 11 from the substrate 11 side. .

  The substrate 11 is an insulating substrate such as a plastic film substrate or a glass substrate. The gate electrode 12 is made of, for example, Al. The gate electrode 12 is formed in a region facing a portion including a junction interface 14C described later, and has a rectangular shape, for example. Thereby, the gate electrode 12 is a low-resistance electrode, and functions as a light shielding film that blocks light incident from the substrate 11 side from entering the bonding interface 14C. Specifically, the portion including the junction interface 14C refers to a portion 18A (described later) of the p-type semiconductor region 14A facing the n-type semiconductor region 14B and a p-type semiconductor region 14A of the n-type semiconductor region 14B. And a portion including a facing portion 18B (described later).

The gate insulating film 13 includes, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiN) as a main component. The gate insulating film 13 is formed in a region facing at least a portion including the bonding interface 14C, and is formed to cover the gate electrode 12, for example. FIG. 2A illustrates the case where the gate insulating film 13 is formed over the entire surface of the substrate 11 including the gate electrode 12.

The semiconductor layer 14 is formed so as to cross a region facing the gate electrode 12 and extends in a direction facing the electrodes 15 and 16 (described later). The upper surface of the semiconductor layer 14 is covered with a protective film 17 except for the contact portions with the electrodes 15 and 16. A region facing the portion including the bonding interface 14 </ b> C on the upper surface of the protective film 17 serves as a light incident surface on which light from the outside is incident. The protective film 17 is made of a material that is transparent to incident light, and includes, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), or the like as a main component.

  For example, as shown in FIGS. 2A and 2B, the semiconductor layer 14 includes a p-type semiconductor region 14A and an n-type semiconductor region 14B that face each other in the in-plane direction. Note that FIG. 2B illustrates a planar configuration when the semiconductor layer 14 is viewed from the light incident side. The p-type semiconductor region 14A is made of, for example, a silicon thin film containing p-type impurities, and the n-type semiconductor region 14B is made of, for example, a silicon thin film containing n-type impurities.

  At least one of the facing portion 18A of the p-type semiconductor region 14A facing the n-type semiconductor region 14B and the facing portion 18B of the n-type semiconductor region 14B facing the p-type semiconductor region 14A has an uneven shape. In the present embodiment, the facing portions 18A and 18B are in direct contact with each other, and a bonding interface 14C is formed between the facing portion 18A and the facing portion 18B. Therefore, uneven shapes are alternately formed in both of the facing portions 18A and 18B, and the joining interface 14C is wavyly zigzag in a crank shape.

  Here, the area S of the bonding interface 14C is defined such that the width of the semiconductor layer 14 (the length in the extending direction of the bonding interface 14C) is W, the amplitude of the waviness of the bonding interface 14C is d, and the number of waviness is n. When the thickness of the semiconductor layer 14 is h, the area S is approximately (W + 2nd) h. That is, it is approximately 2ndh larger than the area (Wh) when the bonding interface 14C is a flat surface. As illustrated in FIG. 2B, when the undulation of the bonding interface 14C is rectangular and the number n of undulations is 2, the area S is approximately 4 dh. It is getting bigger.

  The electrodes 15 and 16 are made of, for example, Al. The electrodes 15 and 16 are formed in the opening formed in the protective film 17, and the upper surfaces thereof are exposed from the protective film 17. Here, the electrode 15 is electrically connected to the p-type semiconductor region 14A, and the electrode 16 is electrically connected to the n-type semiconductor region 14B.

  In the light receiving device 1 of the present embodiment, when light is incident on the light receiving element 10 from outside while the IV characteristic of the light receiving element 10 is controlled by the gate electrode 12, the photocurrent Ip is generated from the light receiving element 10. appear. The generated photocurrent Ip flows into the capacitive element 20, charges are accumulated in the capacitive element 20, and when the gate potential of the transistor 40 is displaced, a current corresponding to the amount of displacement flows between the source and drain of the transistor 40, thereby outputting a signal output. Output to line OUT.

  Meanwhile, in the light receiving device 1, the voltage Vs of the signal output line OUT is Ip × t / Cs. Here, Ip is a photocurrent output from the light receiving element 10, t is a light irradiation time, and Cs is a capacitance of the light receiving element 10. From the above relational expression, in order to increase the sensitivity of the light receiving device 1, (1) the sensitivity of the light receiving element 10, that is, the photocurrent Ip generated from the light receiving element 10 is increased, or (2) the time for light detection is increased. (3) It is conceivable to reduce the capacitance of the capacitive element 20. However, since the time required for detection cannot be increased so much, in order to increase the sensitivity of the light receiving device 1, it is necessary to practice the above (1) or (3).

  However, in an actual circuit, the storage capacitor C ′ for accumulating charges generated from the light receiving element 10 is Cs + Cp. Here, Cp is a parasitic capacitance of the light receiving element 10. Therefore, in order to increase sensitivity in an actual circuit, it is necessary to practice the above (1) or practice to reduce the parasitic capacitance Cp. However, if the size of the light receiving element 10 is increased in order to practice the above (1), the parasitic capacitance Cp becomes enormous.

  On the other hand, in the present embodiment, in the semiconductor layer 14, both the facing portion 18A of the p-type semiconductor region 14A facing the n-type semiconductor region 14B and the facing portion 18B of the n-type semiconductor region 14B facing the p-type semiconductor region 14A. Are alternately uneven. Thereby, even if the size of the light receiving element 10 is not increased, the facing area (area of the bonding interface 14C) between the p-type semiconductor region 14A and the n-type semiconductor region 14B can be increased. As a result, it is possible to generate a large photocurrent Ip from the light receiving element 10 while minimizing an increase in the parasitic capacitance Cp of the light receiving element 10.

[Modification]
In the above embodiment, the p-type semiconductor region 14A and the n-type semiconductor region 14B are in direct contact with each other. For example, as shown in FIGS. An intrinsic semiconductor region 14D may be provided between the type semiconductor region 14B. In this case, the opposing portion 18A and the opposing portion 18B are not in direct contact with each other, and are disposed via the intrinsic semiconductor region 14D. Therefore, in this case, although not shown, it is possible to provide a concavo-convex shape only in one of the facing portion 18A and the facing portion 18B. In addition, as shown in FIG. 3B, it is of course possible to provide uneven shapes alternately in both the facing portion 18A and the facing portion 18B.

  As shown in FIG. 3B, when uneven portions are alternately provided in both the facing portion 18A and the facing portion 18B, the facing portion 52A and the p-type semiconductor region 14A among the intrinsic semiconductor regions 14D are provided. And the facing portion 18C are in direct contact with each other, and a bonding interface 14E is formed between the facing portion 18A and the facing portion 18C. Therefore, uneven portions are alternately formed in both of the facing portions 18A and 18C, and the joining interface 14E is wavyly zigzag in a crank shape. Furthermore, the facing portion 18B and the facing portion 18D of the intrinsic semiconductor region 14D facing the n-type semiconductor region 14B are in direct contact with each other, and a bonding interface 14F is formed between the facing portion 18B and the facing portion 18D. Yes. For this reason, uneven portions are alternately formed in both of the facing portions 18B and 18D, and the joining interface 14F is zigzag in a crank shape.

  Here, the area S1 of the bonding interface 14E is approximately (W + 2 × n1 × d1) h where the amplitude of the undulation of the bonding interface 14E is d1 and the number of undulations is n1. That is, it is approximately 2 × n1 × d1 × h larger than the area (Wh) when the bonding interface 14E is a flat surface. On the other hand, regarding the area S2 of the bonding interface 14F, if the amplitude of the undulation of the bonding interface 14F is d2, and the number of undulations is n2, the area S2 is approximately (W + 2 × n2 × d2) h. That is, it is approximately 2 × n2 × d2 × h larger than the area (Wh) when the bonding interface 14F is a flat surface. As a result, as in the above embodiment, a large photocurrent Ip can be generated from the light receiving element 10 while minimizing an increase in the parasitic capacitance Cp of the light receiving element 10.

  In the modified example, a region having a p-type impurity concentration lower than the p-type impurity concentration of the p-type semiconductor region 14A is provided instead of the intrinsic semiconductor region 14D, or the n-type impurity concentration of the n-type semiconductor region 14B is lower than that of the intrinsic semiconductor region 14D. A region having a low n-type impurity concentration may be provided.

  In the above embodiment, the case where the light receiving element 10 is a bottom gate type photodiode has been described. However, the light receiving element 10 is formed on the substrate 11 with the light shielding film 21 as shown in FIG. Alternatively, a top gate photodiode including a buffer insulating film 22, a semiconductor layer 14, a gate insulating film 23, and a gate electrode 24 in this order from the substrate 11 side may be used.

In the above description, the light shielding film 21 is formed in a region facing the portion including the bonding interface 14C as in the gate electrode 12 of the above-described embodiment, and has, for example, a rectangular shape. Thus, the light shielding film 21 has a function of blocking light incident from the substrate 11 side from entering the bonding interface 14C. In addition, the buffer insulating film 22 includes, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), or the like as a main component, like the gate insulating film 13 of the above embodiment. The buffer insulating film 22 is formed over the entire surface of the substrate 11 including the gate electrode 12 and has a role of a planarizing film.

[Second Embodiment]
FIG. 5 shows an example of a circuit configuration of the light receiving device 2 according to the second embodiment of the present invention. The light receiving device 2 of the present embodiment is formed together with an organic EL element and a liquid crystal element on an insulating substrate such as a plastic film substrate and a glass substrate, although not shown, for example, as in the above embodiment. .

  The light receiving device 2 of the present embodiment is different from the configuration of the light receiving device 1 of the above embodiment in that a light receiving element 50 is provided instead of the light receiving element 10. Therefore, hereinafter, differences from the above embodiment will be mainly described, and common points with the above embodiment will be omitted as appropriate.

  6A illustrates an example of a cross-sectional configuration of the light receiving element 50 in FIG. The light receiving element 50 is, for example, a bottom gate type photodiode in which a gate electrode 12, a gate insulating film 13, a semiconductor layer 51, and electrodes 15 and 16 are sequentially provided on the substrate 11 from the substrate 11 side. .

  The semiconductor layer 51 is formed so as to cross a region facing the gate electrode 12, and is formed so as to extend in a direction facing the electrodes 15 and 16 (described later). The upper surface of the semiconductor layer 51 is covered with the protective film 17 except for the contact portions with the electrodes 15 and 16.

  For example, as shown in FIGS. 6A and 6B, the semiconductor layer 51 described above includes a pair of n-type semiconductor regions 51A and 51B (first conductive layers) facing each other with a predetermined gap in the in-plane direction. And a p-type semiconductor region 51C (second conductivity type semiconductor region) in the gap between the pair of n-type semiconductor regions 51A and 51B. FIG. 6B shows a planar configuration when the semiconductor layer 51 is viewed from the light incident side. The p-type semiconductor region 51C is made of, for example, a silicon thin film containing p-type impurities, and the n-type semiconductor regions 51A and 51B are made of, for example, a silicon thin film containing n-type impurities.

  A portion 52A of the n-type semiconductor region 51A facing the p-type semiconductor region 51C, a portion 52B of the p-type semiconductor region 51C facing the n-type semiconductor region 51A, and a portion of the p-type semiconductor region 51C facing the n-type semiconductor region 51B. At least one of the facing portion 52C and the facing portion 52D of the n-type semiconductor region 51B facing the p-type semiconductor region 51C has an uneven shape. In the present embodiment, the facing portions 52A and 52B are in direct contact with each other, and a bonding interface 51D is formed between the facing portion 52A and the facing portion 52B. Therefore, uneven portions are alternately formed in both of the facing portions 52A and 52B, and the joining interface 51D is wavyly zigzag in a crank shape. Further, the facing portions 52C and 52D are in direct contact with each other, and a bonding interface 51E is formed between the facing portion 52C and the facing portion 52D. For this reason, uneven portions are alternately formed in both of the facing portions 52C and 52D, and the joining interface 51E is undulating in a crank shape.

  Here, the area S3 of the bonding interface 51D is approximately (W + 2 × n3 × d3) h where the amplitude of the undulation of the bonding interface 51D is d3 and the number of undulations is n3. That is, it is approximately 2 × n3 × d3 × h larger than the area (Wh) when the bonding interface 51D is a flat surface. On the other hand, regarding the area S4 of the bonding interface 51E, if the amplitude of the undulation of the bonding interface 51E is d4 and the number of undulations is n4, the area S4 is approximately (W + 2 × n4 × d4) h. That is, it is approximately 2 × n4 × d4 × h larger than the area (Wh) when the bonding interface 51E is a flat surface. Accordingly, as in the above embodiment, a large photocurrent Ip can be generated from the light receiving element 50 while minimizing an increase in the parasitic capacitance Cp of the light receiving element 50.

  In the light receiving device 2 of the present embodiment, when light is incident on the light receiving element 50 from the outside in a state where the IV characteristic of the light receiving element 50 is controlled by the gate electrode 12, the photocurrent Ip is generated from the light receiving element 50. appear. The generated photocurrent Ip flows into the capacitive element 20, charges are accumulated in the capacitive element 20, and when the gate potential of the transistor 40 is displaced, a current corresponding to the amount of displacement flows between the source and drain of the transistor 40, thereby outputting a signal output. Output to line OUT.

  In the present embodiment, in the semiconductor layer 51, both of the facing portions 52A and 52B are alternately uneven, and both of the facing portions 52C and 52D are alternately uneven. Thus, even if the size of the light receiving element 50 is not increased, the opposing area (area of the junction interface 51D) between the n-type semiconductor region 51A and the p-type semiconductor region 51C, the n-type semiconductor region 51B, and the p-type semiconductor region 51C. Can be increased (the area of the bonding interface 51E). As a result, a large photocurrent Ip can be generated from the light receiving element 50 while minimizing an increase in the parasitic capacitance Cp of the light receiving element 50.

[Modification]
Although the case where the light receiving element 50 is a bottom gate type photodiode has been described in the second embodiment, the light receiving element 50 is formed on the substrate 11 on the light shielding film 21 as shown in FIG. Alternatively, a top-gate photodiode including the buffer insulating film 22, the semiconductor layer 51, the gate insulating film 23, and the gate electrode 24 in this order from the substrate 11 side may be used.

  In the second embodiment, the semiconductor layer 51 has an npn structure in which the p-type semiconductor region 51B is formed in the gap between the pair of n-type semiconductor regions 51A and 51B. However, the semiconductor layer 51 has a pnp structure. Also good.

  In the second embodiment, a region having a p-type impurity concentration lower than the p-type impurity concentration of the p-type semiconductor region 51C is provided between the n-type semiconductor region 51A and the p-type semiconductor region 51C. A region having an n-type impurity concentration lower than the n-type impurity concentration of the n-type semiconductor region 51A may be provided. Further, a region having a p-type impurity concentration lower than the p-type impurity concentration of the p-type semiconductor region 51C is provided between the n-type semiconductor region 51B and the p-type semiconductor region 51C, or the n-type impurity of the n-type semiconductor region 51B. A region having an n-type impurity concentration lower than the concentration may be provided.

  As described above, the light receiving element and the light receiving device of the present invention have been described with reference to the embodiment and modifications thereof. However, the present invention is not limited to the above embodiments and the like, and the light receiving element and the light receiving device of the present invention. The configuration can be freely modified as long as the same effects as those of the above-described embodiments and the like can be obtained.

  For example, in each of the embodiments described above, the light receiving elements 10 and 50 have a TFT structure. However, for example, although not shown, the light receiving elements 10 and 50 may have a FinFET structure. In the light receiving elements 10 and 50, an SOI substrate can be used as the substrate 11 instead of a glass substrate or the like.

1 is a circuit diagram of a light receiving device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the light receiving element in FIG. 1 and a top view of a semiconductor layer in the light receiving element. FIG. 2 is a cross-sectional view of a modification of the light receiving element in FIG. 1 and a top view of a semiconductor layer in the light receiving element. It is sectional drawing of the other modification of the light receiving element of FIG. It is a circuit diagram of the light-receiving device which concerns on 2nd embodiment of this invention. FIG. 6 is a cross-sectional view of the light receiving element of FIG. 5 and a top view of a semiconductor layer in the light receiving element. It is sectional drawing of the modification of the light receiving element of FIG. It is a circuit diagram of the conventional light receiving device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Light receiving device, 10, 50 ... Light receiving element, 11 ... Substrate, 12, 24 ... Gate electrode, 13, 23 ... Gate insulating film, 14, 51 ... Semiconductor layer, 14A, 51C ... P-type semiconductor region, 14B, 51A , 51B ... n-type semiconductor region, 14C, 14E, 14F, 51D, 51E ... junction interface, 14D ... intrinsic semiconductor region, 15, 16 ... electrode, 17 ... protective film, 18A, 18B, 18C, 18D, 52A, 52B, 52C, 52D ... opposing portion, 20 ... capacitive element, 21 ... light shielding film, 22 ... buffer insulation film, 30, 40 ... transistor, Cs ... parasitic capacitance, Ip ... current, OUT ... signal output line, RST ... reset signal line, Vs ... voltage, VDD ... power supply voltage line, VSS ... reference voltage line.

Claims (5)

A semiconductor layer having a p-type semiconductor region and an n-type semiconductor region facing each other in the in-plane direction;
Electrodes that are in separate contact with the p-type semiconductor region and the n-type semiconductor region;
A gate insulating film and a gate formed in a facing region between a portion of the p-type semiconductor region facing the n-type semiconductor region and a portion of the n-type semiconductor region including a portion facing the p-type semiconductor region An electrode and
A light receiving element in which at least one of a portion facing the n-type semiconductor region in the p-type semiconductor region and at least one portion facing the p-type semiconductor region in the n-type semiconductor region has an uneven shape.   The light receiving element according to claim 1, wherein the semiconductor layer includes an intrinsic semiconductor region between the p-type semiconductor region and the n-type semiconductor region. A semiconductor layer having a pair of first conductivity type semiconductor regions facing each other with a predetermined gap in the in-plane direction and a second conductivity type semiconductor region provided in a gap between the pair of first conductivity type semiconductor regions;
Electrodes that are in separate contact with the pair of first conductive semiconductor regions and the second conductive semiconductor regions;
In a facing region between a portion of the first conductivity type semiconductor region facing the second conductivity type semiconductor region and a portion of the second conductivity type semiconductor region including a portion facing the first conductivity type semiconductor region. A formed gate insulating film and a gate electrode,
At least one of the first conductive type semiconductor region facing the second conductive type semiconductor region and at least one of the second conductive type semiconductor region facing the first conductive type semiconductor region has an uneven shape. Light receiving element. A light receiving element that generates an electric charge according to the amount of received light;
A capacitive element for accumulating charges generated from the light receiving element;
An output element for taking out the electric charge accumulated in the capacitive element as a photocurrent;
A discharge element that discharges the charge remaining in the capacitive element after the charge is taken out by the output element;
The light receiving element is
A semiconductor layer having a p-type semiconductor region and an n-type semiconductor region facing each other in the in-plane direction;
Electrodes that are in separate contact with the p-type semiconductor region and the n-type semiconductor region;
A gate insulating film and a gate formed in a facing region between a portion of the p-type semiconductor region facing the n-type semiconductor region and a portion of the n-type semiconductor region including a portion facing the p-type semiconductor region An electrode and
A light receiving device in which at least one of a portion of the p-type semiconductor region facing the n-type semiconductor region and a portion of the n-type semiconductor region facing the p-type semiconductor region has an uneven shape. A light receiving element that generates an electric charge according to the amount of received light;
A capacitive element for accumulating charges generated from the light receiving element;
An output element for taking out the electric charge accumulated in the capacitive element as a photocurrent;
A discharge element that discharges the charge remaining in the capacitive element after the charge is taken out by the output element;
The light receiving element is
A semiconductor layer having a pair of first conductivity type semiconductor regions facing each other with a predetermined gap in the in-plane direction and a second conductivity type semiconductor region provided in a gap between the pair of first conductivity type semiconductor regions;
Electrodes that are in separate contact with the pair of first conductive semiconductor regions and the second conductive semiconductor regions;
In a facing region between a portion of the first conductivity type semiconductor region facing the second conductivity type semiconductor region and a portion of the second conductivity type semiconductor region including a portion facing the first conductivity type semiconductor region. A formed gate insulating film and a gate electrode,
At least one of the first conductive type semiconductor region facing the second conductive type semiconductor region and at least one of the second conductive type semiconductor region facing the first conductive type semiconductor region has an uneven shape. Light receiving device.

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