JP2010080340A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which has excelling display quality and of which the manufacturing cost can be reduced by the improvement of the manufacturing yield. <P>SOLUTION: The display device is provided with: a first color pixel and a second color pixel having mutually different colors, and has a first electrode 60, which is respectively arranged in the first color pixel and the second color pixel; a barrier rib 70, which is arranged along the periphery of the respective first electrodes so as to separate the first color pixel and the second color pixel and of which on the upper face 70T, and a recess C is formed; an organic active layer 62, which is respectively arranged on the first electrode of the first color pixel and the second color pixel and includes a luminous layer made of a low-molecule-based material, and a second electrode 64, which is arranged on the organic active layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly, to a display device having a self-luminous display element formed through a vapor deposition process through a vapor deposition mask having a predetermined opening pattern.

  In recent years, organic electroluminescence (EL) display devices have attracted attention as flat display devices. Since this organic EL display device is provided with an organic EL element that is a self-luminous element, the viewing angle is wide, it can be reduced in thickness and weight without the need for a backlight, power consumption is reduced, and The response speed is fast. Because of these characteristics, organic EL display devices are attracting attention as potential candidates for next-generation flat display devices that can replace liquid crystal display devices.

  The organic EL display device includes an organic EL element that holds an organic active layer containing an organic compound having a light emitting function between an anode and a cathode. As such an organic EL display device, a bottom emission method in which EL light generated in the organic EL element is extracted from the array substrate side, and EL light generated in the organic EL element from the sealing substrate side are used. There is a top emission method that takes out to the outside.

In such an organic EL element, in the step of forming an organic active layer made of a low molecular weight organic compound, a vapor deposition method of vapor-depositing a material source scattered from a vapor deposition source can be applied (for example, Patent Document 1 and Patent Document 2).
JP 2004-323888 A JP 2008-103173 A

  As a typical method for realizing an organic EL display device capable of color display, for example, a method of arranging a plurality of types of color pixels that emit light in red (R), green (G), and blue (B), respectively. It is done. As a method for forming the organic active layer (especially, the light emitting layer) disposed in each of these color pixels, a mask vapor deposition method in which a low molecular weight organic compound is vapor-deposited through a vapor deposition mask (fine mask) having an opening pattern is applied. Is possible.

  In such a mask vapor deposition method, when a process of depositing a vapor deposition mask on the upper surface of a partition wall that separates color pixels and applying a material source, the following problems may occur.

  That is, if foreign matter is sandwiched between the vapor deposition mask and the upper surface of the partition wall, an unnecessary gap is formed between the vapor deposition mask and the vapor deposition surface (mask floating). Normally, the area where the material source is deposited is approximately the same size as the opening pattern of the deposition mask, but as the distance from the deposition surface to the deposition mask increases, the material source that has passed through the deposition mask diffuses. Therefore, the area is wider than the opening pattern (deposition blur). That is, if the area where the material source is deposited is enlarged more than necessary, and further reaches another adjacent color pixel, color mixing failure occurs.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a display device that has good display quality and can reduce manufacturing costs by improving manufacturing yield. .

A display device according to an aspect of the present invention includes:
A display device including a first color pixel and a second color pixel of different colors in an active area,
A first electrode disposed in each of the first color pixel and the second color pixel;
A partition wall that is disposed along the periphery of each of the first electrodes so as to separate the first color pixel and the second color pixel, and that has a recess recessed from an upper surface thereof.
An organic active layer that is disposed on the first electrode of the first color pixel and the second color pixel and includes a light emitting layer made of a low molecular material;
A second electrode disposed on the organic active layer;
It is provided with.

  According to the present invention, it is possible to provide a display device that has good display quality and can reduce manufacturing costs by improving manufacturing yield.

  Hereinafter, a display device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings. In this embodiment, a self-luminous display device, for example, an organic EL (electroluminescence) display device will be described as an example of the display device.

  As shown in FIG. 1, the organic EL display device 1 includes an array substrate (first substrate) 100 having an active area 102 for displaying an image. The active area 102 is composed of a plurality of pixels PX arranged in a matrix. Further, FIG. 1 shows a color display type organic EL display device 1 as an example, and the active area 102 includes a plurality of types of color pixels, for example, a red pixel PXR, a green pixel PXG, and a blue color corresponding to three primary colors. A pixel PXB is used.

  At least the active area 102 of the array substrate 100 is sealed with a sealing substrate (second substrate) 200. The inner surface of the sealing substrate 200 facing the array substrate 100 may be formed flat, or at least the surface facing the active area 102 may be recessed and thinner than the peripheral edge.

  For example, the array substrate 100 and the sealing substrate 200 are bonded to each other by a seal member 300 arranged in a frame shape so that each peripheral portion surrounds the active area 102. The seal member 300 is made of frit glass (low melting point glass), a resin material (for example, an ultraviolet curable resin or a thermosetting resin), or the like.

  Each pixel PX (R, G, B) includes a pixel circuit 10 and a display element 40 that is driven and controlled by the pixel circuit 10. The pixel circuit 10 shown in FIG. 1 is an example, and it goes without saying that a pixel circuit having another configuration may be applied.

  In the example illustrated in FIG. 1, the pixel circuit 10 includes a driving transistor DRT, various switches (first switch SW1, second switch SW2, third switch SW3), a storage capacitor element Cs, and the like. The drive transistor DRT has a function of controlling the amount of current supplied to the display element 40. The first switch SW1 and the second switch SW2 function as a sample / hold switch. The third switch SW3 has a function of controlling the supply of drive current from the drive transistor DRT to the display element 40, that is, the on / off of the display element 40. The storage capacitor element Cs has a function of holding the gate-source potential of the drive transistor DRT.

  The drive transistor DRT is connected between the high potential power supply line P1 and the third switch SW3. The display element 40 is connected between the third switch SW3 and the low potential power line P2. The gate electrodes of the first switch SW1 and the second switch SW2 are connected to the first gate line GL1. The gate electrode of the third switch SW3 is connected to the second gate line GL2. The source electrode of the first switch SW1 is connected to the video signal line SL.

  The drive transistor DRT, the first switch SW1, the second switch SW2, and the third switch SW3 are configured by, for example, a thin film transistor (TFT), and the semiconductor layer can be formed by amorphous silicon, polysilicon, or the like. Here, it is formed of polysilicon.

  In the case of such a circuit configuration, the first switch SW1 and the second switch SW2 are turned on based on the ON signal supplied from the first gate line GL1, and the high potential is set according to the amount of current flowing through the video signal line SL. A current flows from the power supply line P1 to the drive transistor DRT, and the storage capacitor element CS is charged according to the current flowing through the drive transistor DRT. As a result, the drive transistor DRT can supply the same amount of current as that supplied from the video signal line SL to the display element 40 from the high potential power supply line P1.

  Then, the third switch SW3 is turned on based on the ON signal supplied from the second gate line GL2, and the driving transistor DRT is connected to the first potential from the high potential power supply line P1 according to the capacitance held in the storage capacitor element CS. A predetermined amount of current corresponding to a predetermined luminance is supplied to the display element 40 via the three switch SW3. Thereby, the display element 40 emits light with a predetermined luminance.

  The display element 40 includes an organic EL element 40 (R, G, B) that is a self-luminous display element. That is, the red pixel PXR includes an organic EL element 40R that mainly emits light corresponding to the red wavelength. The green pixel PXG includes an organic EL element 40G that mainly emits light corresponding to the green wavelength. The blue pixel PXB includes an organic EL element 40B that mainly emits light corresponding to the blue wavelength.

  The various organic EL elements 40 (R, G, B) have basically the same configuration, and are disposed on the wiring substrate 120 as shown in FIG. The wiring board 120 includes an insulating layer such as an undercoat layer 111, a gate insulating film 112, an interlayer insulating film 113, and a protective film 114 on an insulating support substrate 101 such as a glass substrate. , Driving transistor DRT, storage capacitor element Cs, various wirings (gate line, video signal line, power supply line, etc.) and the like. The undercoat layer 111, the gate insulating film 112, and the interlayer insulating film 113 are made of an inorganic material such as silicon nitride (SiN) or silicon oxide (SiO).

  The protective film 114 may be formed of an organic material or an inorganic material such as silicon nitride. In the case where the protective film 114 is formed of an organic material, the protective film 114 is formed by a technique such as coating the material, so that the influence of unevenness in the lower layer can be reduced and the surface thereof can be planarized.

  That is, in the example shown in FIG. 2, on the undercoat layer 111, the semiconductor layer 21 of a transistor element (corresponding to the third switch SW3 in the circuit configuration shown in FIG. 1) 20 such as a switch or a drive transistor. Is arranged. The semiconductor layer 21 is covered with the gate insulating film 112.

  On the gate insulating film 112, a gate electrode 20G of the transistor element 20, a gate line (not shown), and the like are disposed. The gate electrode 20G and the gate line are covered with an interlayer insulating film 113. On the interlayer insulating film 113, a source electrode 20S and a drain electrode 20D of the transistor element 20, a signal line (not shown), and the like are arranged.

  The source electrode 20S and the drain electrode 20D are in contact with the semiconductor layer 21 through contact holes that penetrate the gate insulating film 112 and the interlayer insulating film 113 to the semiconductor layer 21, respectively. The source electrode 20S, the drain electrode 20D, and the signal line are covered with a protective film 114.

  In this embodiment, the organic EL element 40 is disposed on the protective film 114. The organic EL element 40 has a configuration in which an organic active layer 62 is held between a first electrode 60 and a second electrode 64, and a detailed structure will be described below.

  That is, the first electrode 60 is arranged in an island shape independent of each pixel PX on the protective film 114 and functions as an anode. The first electrode 60 is in contact with the drain electrode 20D through a contact hole that penetrates the protective film 114 to the drain electrode 20D.

  Such a first electrode 60 is made of indium tin oxide (ITO) or indium oxide on a reflective layer formed using a light reflective conductive material such as aluminum (Al) or silver (Ag). It may have a structure in which a transmission layer formed using a light-transmitting conductive material such as zinc oxide (IZO) is laminated, or may be configured as a reflection layer single layer or a transmission layer single layer. good. In the case of the top emission method, it is desirable that the first electrode 60 includes a reflective layer.

  The organic active layer 62 is disposed on the first electrode 60 and includes at least the light emitting layer 62A. The organic active layer 62 can include functional layers other than the light emitting layer, and includes, for example, functional layers such as a hole injection layer, a hole transport layer, a blocking layer, an electron transport layer, an electron injection layer, and a buffer layer. it can. Such an organic active layer 62 may be composed of a single layer in which a plurality of functional layers are combined, or may have a multilayer structure in which the functional layers are laminated. In the organic active layer 62, the light emitting layer 62A may be an organic material, and layers other than the light emitting layer may be an inorganic material or an organic material. In the organic active layer 62, the functional layer other than the light emitting layer may be a common layer.

  The light emitting layer 62A is formed of an organic compound having a light emitting function that emits red, green, or blue light, and is individually disposed in each color pixel. The organic active layer 62, particularly the light emitting layer 62A, is formed of a low molecular material. A thin film made of such a low molecular material is formed by a mask vapor deposition method.

  The second electrode 64 is common to the plurality of pixels PX, is disposed on the organic active layer 62 of each pixel PX, and functions as a cathode. The second electrode 64 is formed by laminating a semi-transmissive layer made of a mixture of silver (Ag) and magnesium (Mg), and a transmissive layer formed using a light-transmitting conductive material such as ITO. The structure may be such that it may be configured as a single semi-transmissive layer or a single transmissive layer. In the case of the top emission method, it is desirable that the second electrode 64 includes a semi-transmissive layer.

  In addition, the array substrate 100 includes a partition wall 70 that separates adjacent pixels, particularly pixels PX (R, G, B) of different colors in the active area 102. That is, the partition wall 70 is disposed along the periphery of each first electrode 60 and covers at least a part of the periphery of the first electrode 60. Such partition walls 70 are formed in a lattice shape in the active area 102. Thereby, the adjacent organic EL elements of different colors are insulated.

  Such a partition wall 70 is formed by applying a resin material such as acrylic resin or polyimide, and then patterning by a technique such as photolithography, and has a substantially trapezoidal cross-sectional shape. The bottom surface of the partition wall 70 is in contact with the first electrode 60 and the protective film 114. At least a part of the side surface of the partition wall 70 is covered with the organic active layer 62. The inner side surrounded by the side surface of the partition wall 70 emits light and becomes an effective portion that substantially contributes to display.

  Further, the upper surface 70T of the partition wall 70 corresponds to the highest apex from the main surface of the wiring substrate 120 (that is, the surface of the protective film 114) 120A. The upper surface 70 </ b> T may be partially covered with the organic active layer 62, but is covered with the second electrode 64 disposed on the organic active layer 62.

  In particular, in this embodiment, a recess is formed in the upper surface 70T of the partition wall 70. That is, the upper surface 70T of the partition wall 70 serves as a support surface that supports a vapor deposition mask for performing color pixel separation when a mask vapor deposition method for forming the light emitting layer 62A is applied. When supporting such a vapor deposition mask, there is a possibility that foreign matter may exist between the vapor deposition mask and the upper surface 70T, and undesired floating of the vapor deposition mask (that is, the vapor deposition mask is locally or entirely separated from the upper surface 70T). It is desired to suppress this).

  Therefore, by forming the concave portion on the upper surface 70T, the area where the vapor deposition mask is supported, that is, the area where the vapor deposition mask and the upper surface 70T come into contact with each other is reduced. It is possible to reduce the probability that foreign matter exists between the upper surface 70T and the upper surface 70T.

  Thereby, it becomes possible to suppress the evaporation mask from floating. Therefore, it is possible to provide an organic EL display device that suppresses vapor deposition blur caused by floating of the vapor deposition mask, suppresses color mixing failure, has a good display quality, and can reduce the manufacturing cost by improving the manufacturing yield. .

  A more specific configuration example will be described below.

<< First configuration example >>
In the first configuration example, the partition wall 70 is composed of a plurality of segments that partition the pixels PX having different colors from each other and are spaced apart from each other. That is, in the example shown in FIGS. 3 and 4, the red pixel PXR, the green pixel PXG, and the blue pixel PXB are arranged in this order. The partition wall 70 is disposed to partition the red pixel PXR, the first segment 70R disposed to partition the green pixel PXG, and the second segment 70G disposed to partition the blue pixel PXB. It is composed of three segments 70B.

  These segments 70 (R, G, B) are spaced apart from each other, and between the first segment 70R and the second segment 70G and between the second segment 70G and the third segment 70B, respectively. The main surface 120A of the wiring board 120, that is, the surface of the protective film 114 is exposed. The upper surface 70T of each segment 70 (R, G, B) is in the same horizontal plane and serves as a support surface. That is, the heights H from the main surface 120A of the wiring board 120 to the upper surface 70T of each segment 70 (R, G, B) are all the same.

  In the partition wall 70 having such a configuration, the recess C is formed in a groove shape between the segments 70 (R, G, B). That is, the concave portion C corresponds to a portion where the protective film 114 is exposed from the partition wall 70. In the example shown here, the recess C is formed between the first segment 70R and the second segment 70G, and between the second segment 70G and the third segment 70B, respectively. In other words, the recess C extends along the direction in which the pixels PX (R, G, B) are arranged, that is, the direction orthogonal to the row direction H, that is, the column direction V.

  Each segment 70 (R, G, B) is, for example, arranged so as to overlap the entire periphery of the first electrode 60. The organic active layer 62 is disposed on the inner side partitioned by the segments 70 (R, G, B). The 2nd electrode 64 is arrange | positioned so that the organic active layer 62, the upper surface 70T of each segment 70 (R, G, B), and the recessed part C may be covered. With such a configuration, the organic EL element 40 (R, G, B) disposed in each pixel PX (R, G, B) is partitioned.

  Note that the contact portion CP between the first electrode 60 and the drain electrode 20D of the transistor element 20 is short-circuited with the second electrode 64 when exposed from the recess C between the segments of the partition wall 70. Is important. For this reason, in the configuration described above, it is desirable that the contact portion CP be disposed between pixels adjacent in the column direction V. In other words, it is desirable that the recess C extends only along the column direction V and is not formed between pixels adjacent in the column direction V.

  The formation process of such an organic EL element 40 is as follows.

  First, the pixel circuit 10 such as a transistor element is formed on the support substrate 101 and covered with the protective film 114. Then, the first electrode 60 is formed on the protective film 114. Then, a resin material is applied on the protective film 114 on which the first electrode 60 is formed so as to have a desired thickness, and is patterned into a shape as shown in FIG. For example, a photolithography method can be applied to this patterning. Thereby, the partition 70 which consists of a some segment 70 (R, G, B) is formed.

  Subsequently, as illustrated in FIG. 5, a deposition mask M having an opening pattern OP corresponding to a pixel of a predetermined color, for example, a red pixel PXR, is placed on the upper surface 70 </ b> T of the partition wall 70. At this time, even if foreign matter adheres to the surface of the vapor deposition mask M (the surface facing the upper surface 70T), the entire surface of the upper surface 70T is in close contact with the vapor deposition mask M because the foreign matter has a high probability of being absorbed by the recess C. The vapor deposition mask M can be supported while maintaining a predetermined gap.

  Subsequently, a low molecular material containing an organic compound having a light emitting function is deposited on the first electrode 60 through the deposition mask M to form the organic active layer 62. Then, the vapor deposition mask M is removed, and the second electrode 64 is formed on the organic active layer 62. By such a process, the organic EL element 40 is formed.

  In the formation process described above, the partition wall 70 has the highest height on the wiring substrate 120 at the stage of forming the organic active layer 62, particularly the light emitting layer 62A, by mask deposition. That is, the upper surface 70T of the partition wall 70 protrudes most from the main surface 120A of the wiring board 120. Therefore, the partition wall 70 supports the vapor deposition mask M on its upper surface 70T.

  At this time, by dividing the partition wall 70 into a plurality of segments, the contact area with the vapor deposition mask M is reduced, and the probability that foreign matter exists between the upper surface 70T and the vapor deposition mask M can be reduced. For this reason, even if a foreign substance adheres to the surface of the vapor deposition mask M, the vapor deposition mask M is prevented from floating, and the vapor deposition mask M can be supported on the entire upper surface 70T. Therefore, vapor deposition blur and color mixing failure can be suppressed.

  Further, the height of the partition wall 70 from the main surface 120A to the upper surface 70T of the wiring board 120 is, for example, about 2 to 3 μm, and the depth of the recess C is equal to the height of the partition wall 70 (about 2 to 3 μm). In addition, even a foreign substance having a particle size of about 2 to 3 μm can be absorbed by the concave portion C.

<< Second configuration example >>
In the second configuration example, the partition wall 70 is integrally formed, but is formed in a shape recessed from the upper surface 70T so as to form a recess. That is, in the example shown in FIGS. 6 and 7, the red pixel PXR, the green pixel PXG, and the blue pixel PXB are arranged in this order. The partition wall 70 is disposed so as to partition the red pixel PXR, the green pixel PXG, and the blue pixel PXB.

  The partition wall 70 is formed on the red pixel PXR side and the green pixel RXG side so as to have a first film thickness T1 from the main surface 120A to the upper surface 70T of the wiring board 120, while the red pixel PXR of the partition wall 70 is formed. And the green pixel RXG so as to have a second film thickness T2 that is thinner than the first film thickness T1. Similarly, the partition wall 70 is formed on the green pixel PXG side and the blue pixel RXB side so as to have the first film thickness T1 from the main surface 120A to the upper surface 70T of the wiring substrate 120, respectively. The green pixel PXG and the blue pixel RXG are formed to have a second film thickness T2 that is thinner than the first film thickness T1.

  That is, the concave portion C corresponds to a portion having the second film thickness T2.

  In the partition wall 70 having such a configuration, the recess C is formed between the pixels PX (R, G, B). That is, in the example shown here, the concave portion C is formed between the red pixel PXR and the green pixel PXG and between the green pixel PXG and the blue pixel PXB, respectively. In other words, the recess C extends along the direction in which the pixels PX (R, G, B) are arranged, that is, the direction orthogonal to the row direction H, that is, the column direction V.

  In the second configuration example, the partition walls 70 are disposed so as to overlap the entire periphery of the first electrode 60 and cover the protective film 114 between the first electrodes 60. That is, the main surface 120 </ b> A of the wiring substrate 120, that is, the surface of the protective film 114 is not exposed from the partition wall 70. Therefore, the contact portion CP between the first electrode 60 and the drain electrode 20 </ b> D of the transistor element 20 is reliably covered with the partition wall 70.

  The organic active layer 62 is disposed on the inner side divided by the partition walls 70. The second electrode 64 is disposed so as to cover the organic active layer 62, the upper surface 70T of the partition wall 70, and the recess C. With such a configuration, the organic EL element 40 (R, G, B) disposed in each pixel PX (R, G, B) is partitioned.

  In such a configuration, the concave portion C can be formed between pixels adjacent in the column direction V regardless of the position of the contact portion CP. That is, when the concave portion C is formed to a depth that does not expose the contact portion CP (that is, the difference obtained by subtracting the second film thickness T2 from the first film thickness T1), the concave portion C defines each pixel PX. You may form in a grid | lattice form so that it may surround. Thereby, the contact area of upper surface 70T and a vapor deposition mask can further be reduced.

  The partition wall 70 having such a shape can be formed as follows, for example.

  First, after applying a resin material on the protective film 114 on which the first electrode 60 is formed to have a desired thickness, the portion where the first electrode 60 is exposed and the portion where the recess C is formed are different. Exposure under conditions. For example, when a positive photosensitive resin material is used, a multi-stage exposure method can be applied, and a portion where the recess C is formed is exposed for a shorter time than a portion where the first electrode 60 is exposed. Thereafter, by developing the photosensitive resin material, the depth of the recess C is shallower than the portion where the first electrode 60 is exposed, and the protective film 114 is exposed from the partition wall 70 between the first electrodes 60. There is no. Note that the method for forming such an uneven shape is not limited to the multistage exposure method, and a halftone exposure method may be employed.

  Thereby, the partition 70 which has the recessed part C is formed.

  Also in the configuration example including the partition wall 70 having such a structure, a deposition mask M having an opening pattern OP corresponding to a pixel of a predetermined color, for example, a red pixel PXR, is provided on the upper surface 70T of the partition wall 70 as shown in FIG. Place. At this time, even if foreign matter adheres to the surface of the vapor deposition mask M (the surface facing the upper surface 70T), the entire surface of the upper surface 70T is in close contact with the vapor deposition mask M because the foreign matter has a high probability of being absorbed by the recess C. The vapor deposition mask M can be supported while maintaining a predetermined gap. Therefore, vapor deposition blur and color mixing failure can be suppressed.

  Further, the height of the partition wall 70 from the main surface 120A to the upper surface 70T of the wiring substrate 120 is, for example, about 2 to 3 μm, and the film thickness of the partition wall 70 necessary to cover the contact portion CP is about 0.1 μm. Is sufficient, and the depth of the recess C can be about 1.5 μm or more. For this reason, even a foreign substance having a particle size of about 1.5 μm can be absorbed by the recess C.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the spirit of the invention in the stage of implementation. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

FIG. 1 is a diagram schematically showing a configuration of an organic EL display device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view schematically showing a structure when the organic EL display device shown in FIG. 1 is cut. FIG. 3 is a plan view schematically showing the structure of the active area in the organic EL display device of the first configuration example. FIG. 4 is a cross-sectional view schematically showing a structure when the pixel shown in FIG. 3 is cut along line AA. FIG. 5 is a diagram for explaining a process of forming an organic active layer in the organic EL display device of the first configuration example. FIG. 6 is a plan view schematically showing the structure of the active area in the organic EL display device of the second configuration example. FIG. 7 is a cross-sectional view schematically showing a structure when the pixel shown in FIG. 6 is cut along line BB. FIG. 8 is a diagram for explaining a process of forming an organic active layer in the organic EL display device of the second configuration example.

Explanation of symbols

PX (R, G, B) ... pixel 40 ... display element (organic EL element)
DESCRIPTION OF SYMBOLS 60 ... 1st electrode 62 ... Organic active layer 62A ... Light emitting layer 64 ... 2nd electrode CP ... Contact part 70 ... Partition 70T ... Upper surface 70 (R, G, B) ... Segment C ... Recess 100 ... Array substrate 120 ... Wiring substrate 120A ... Main surface 200 ... Sealing substrate 300 ... Sealing member M ... Deposition mask OP ... Opening pattern

Claims (6)

A display device including a first color pixel and a second color pixel of different colors in an active area,
A first electrode disposed in each of the first color pixel and the second color pixel;
A partition wall that is disposed along the periphery of each of the first electrodes so as to separate the first color pixel and the second color pixel, and that has a recess recessed from an upper surface thereof.
An organic active layer that is disposed on the first electrode of the first color pixel and the second color pixel and includes a light emitting layer made of a low molecular material;
A second electrode disposed on the organic active layer;
A display device comprising: The partition wall includes a first segment arranged so as to partition the first color pixel, and a second segment arranged so as to partition the second color pixel apart from the first segment. ,
The display device according to claim 1, wherein the recess is formed in a groove shape between the first segment and the second segment.   The display device according to claim 1, wherein the recess extends along a direction orthogonal to a direction in which the first color pixel and the second color pixel are arranged. The barrier ribs are formed on the first color pixel side and the second color pixel side so as to have a first film thickness up to the upper surface,
The said recessed part was formed so that it might have a 2nd film thickness thinner than a 1st film thickness between the said 1st color pixel and the said 2nd color pixel of the said partition. Display device.   The display device according to claim 1, wherein the recess is formed in a lattice shape so as to surround the first color pixel and the second color pixel. A transistor element electrically connected to the first electrode;
The display device according to claim 1, wherein the partition wall is arranged to cover a contact portion between the first electrode and the transistor element.

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