JP2010063264A - Voltage balance correcting circuit of serial storage cell - Google Patents

Abstract

In a power storage system such as a voltage sag / power failure compensation device, a railway power storage device, etc., cell voltage variation that gradually occurs during long-term charging can be easily and inexpensively connected in series. Compensates with high efficiency and high accuracy with a circuit that can easily cope with the increase or decrease in the number of connections.
In each of the two series cell portions C1 and C2 in the series cell, a resistance voltage dividing circuit that equally divides a voltage (E1 + E2) appearing at the two series terminals, and positive and negative operating power are supplied from the series terminals. An operational amplifier OP1 is installed, and the operational amplifier OP1 forms a negative feedback loop that makes the voltage between the differential input terminals zero, and is controlled so that its operating gain is 500 or less.
[Selection] Figure 1

Description

  The present invention relates to a voltage balance correction circuit for series storage cells, and more particularly to a technique that is effective when two or more storage cells such as secondary batteries and capacitors are connected in series.

  Power storage cells such as secondary batteries and capacitors are used in power storage systems such as an instantaneous voltage drop / power failure (instantaneous voltage drop / instantaneous power failure) compensation device, a railway power storage device, and the like. In such a power storage system, since a single power storage cell can be charged with only a few volts, a large number of power storage cells are connected in series.

  In a series storage cell, when the capacity | capacitance and a charging rate vary between cells, the voltage will concentrate on a specific cell and the problem that the lifetime of a cell will become short arises. For example, when charging / discharging a series storage cell, if any cell in the series storage cell is overcharged or overdischarged, the entire storage system is damaged due to abnormal heat generation or rupture. . The problem due to voltage variation between cells becomes more prominent as the number of series connections increases. Therefore, equalization of the voltage of each cell is an important issue when using the storage cells connected in series.

  Therefore, in the prior art, as shown in FIG. 8, an overcharge protection switch Suvp and an overdischarge protection switch Sovp are interposed in series between the series terminals of the series storage cells C1 to C4 and the external terminals (T1-T2). A cell protection circuit 20 is proposed in which the voltage of each of the cells C1 to C4 is individually monitored and the switch Suvp or Sovp is set from an on state to an off state when any one of the cell voltages is abnormal ( Patent Document 1).

  In addition, as another means for equalizing the voltages of the series-connected storage cells, a charging period is provided in which an inductor for current storage is provided between two series-connected cells, and the inductor current is charged from one cell to the inductor. And a voltage balance correction circuit for a series cell of a dynamic operation system in which the inductor current is alternately switched between a discharge period for discharging in the path for charging the other cell (Patent Document 2). reference).

  This dynamic operation type voltage balance correction circuit is employed in a power storage system in which charging and discharging are repeated at a high frequency, such as a power source for an electric vehicle or a power storage system for load leveling.

  As another means, as shown in FIG. 9, a resistance voltage dividing circuit (R11, R12) that equally divides the voltage (E1 + E2) appearing at the series terminals of the first cell C1 and the second cell C2 connected in series. ) And an operational amplifier OP1 to which positive and negative operating power supplies (+ V, −V) are supplied from the series terminal, and a divided voltage (appears at the intermediate voltage dividing point p1 of the resistance voltage dividing circuit (R11, R12)). Vp1) and an intermediate voltage (Vp2) appearing at the intermediate connection point p2 of the first cell C1 and the second cell C2 are input to the differential input terminal of the operational amplifier OP1, and the differential amplified output is input to the intermediate voltage By supplying the voltage to the connection point p2, a negative feedback loop is formed so that the voltage (Vp1-Vp2) between the differential input terminals becomes zero, and a voltage difference is generated between the first cell C1 and the second cell C2. When the voltage Voltage balance correction circuit for series-connected cells of static operation scheme so as to discharge had how cells have been proposed (see Patent Document 3).

In FIG. 9, (a) shows the voltage balance correction circuit 101 of the static operation system, and (b) and (c) show the operation characteristic graphs of the main parts thereof.
JP2003-189480 JP 2006-67742 A JP-A-8-55643

However, the conventional techniques described above have the following problems.
First, in the cell protection circuit 20 shown in FIG. 8, when four cells C <b> 1 to C <b> 4 each having a capacity of 2000 F and a working voltage range of 3.9 V to 2.0 V are connected in series, the voltage balance of each cell C <b> 1 to C <b> 4 is If so, the four series cells can be used in a voltage range of 15.6V to 8V, and become a capacitor module having a combined capacity of 500F as a whole.

  However, as shown in the figure, when the voltages of the cells C1 to C4 are not uniform and a variation from 2.001V to 3.899V occurs, the 4 series voltage is 13.7V within the normal voltage range. However, if charging (about 0.1V) proceeds from this state, cells (C1 to C3) exceeding the upper limit (> 3.9V) of the voltage range (3.9V to 2.0V) are generated. The overcharge protection switch Sovp is activated.

  On the other hand, even if the above 4 series voltage is 13.7V within the normal voltage range, if discharge (about 0.1V) progresses even slightly from this state, this time the voltage range (3.9V to 2.0V) ) Occurs below the lower limit (<2.0 V), and the overdischarge protection switch Suvp is activated. As a result, the 4-series cell cannot function as a capacitor module. Here, a balance correction circuit is required separately from the protection circuit.

  Next, the above-described voltage balance correction circuit of the series cell of the dynamic operation method is effective for a power storage system in which charging and discharging are repeated at a high frequency, but there is a problem that the circuit is complicated and expensive. It was.

  In a storage system where the state of charge continues for a long period of time, such as a voltage sag / power failure compensation device, when a high voltage cell occurs, only the high voltage cell is discharged to compensate for voltage variations between cells. The present inventors have found that the method (static operation method) is more advantageous for simplifying the circuit and reducing the cost.

  In addition, the above-described dynamic operation method is effective in the case where the voltage variation between cells is instantaneously performed, but in order to compensate for the voltage variation between cells which gradually occurs during long-term charging, There is a problem that the power consumption is excessive for the compensation operation as well as over-specification.

  However, even in the static balance method voltage balance correction circuit 101 shown in FIG. 9A, the operation characteristic graph is shown in FIG. 9B or FIG. Even when the generated voltage difference (E1-E2) is small, a problem arises in that excessive discharge current (Isat or Isat) is energized and power waste for compensation operation increases.

  Such excessive operation is caused by the gain of the operational amplifier OP1 being too large. The operational amplifier OP1 has an open gain that is substantially infinite, and if this is used without feedback, the output current Io for compensation operation is equal to the input voltage ( At the polarity switching point of Vp1-Vp2), it is overwhelmed to either the positive or negative saturation level Isat, and excessive operation that causes power waste is performed.

  The operational amplifier OP1 is normally controlled so as to have a constant amplification gain by a negative feedback resistance element (not shown) in order to stabilize its amplification operation. As shown in (c) of the figure, there is a problem that the output current Io for the compensation operation flows more than necessary, resulting in waste of power due to excessive operation.

  The present invention has been made in view of the technical background as described above. The purpose of the present invention is, for example, in a power storage system such as a voltage sag / power failure compensation device, a railway power storage device, etc. The voltage of the series storage cell that is suitable for compensating high-efficiency and high-accuracy with a circuit that can easily cope with the increase and decrease in the number of series connection of cells in a simple and low-cost manner. It is to provide a balance correction circuit.

  Other objects and configurations of the present invention will be clarified in the description of the present specification and the accompanying drawings.

The present invention provides the following solutions.
(1) A series battery cell voltage balance correction circuit for equalizing each voltage of a battery cell array in which two or more battery cells are connected in series,
(A) a resistance voltage dividing circuit for equally dividing a voltage appearing at a series terminal of the first cell and the second cell between the first cell and the second cell adjacent in series connection order; A discharge circuit unit with an operational amplifier to which positive and negative operating power is supplied from the terminal is installed,
(B) In each discharge circuit unit, the divided voltage appearing at the intermediate voltage dividing point of the resistance voltage dividing circuit and the intermediate voltage appearing at the intermediate connection point of the first cell and the second cell are the differential of the operational amplifier. The difference between the two voltages input to the input terminal is amplified, and the output current obtained by the amplification is supplied to the intermediate connection point, so that the voltage between the differential input terminals becomes zero. When a feedback loop is formed and a voltage difference occurs between the first cell and the second cell, the cell having the higher voltage is discharged,
(C) A current limiting resistor element is interposed in series at the output terminal of the operational amplifier, and a negative feedback resistor element is inserted between the output terminal and the inverting input terminal to control the voltage amplification gain to 500 times or less. As a result, the change in the output current with respect to the input voltage was linearized and sloped.
A voltage balance correction circuit for a series storage cell, wherein:

  (2) In the above means (1), the voltage of each cell is individually monitored, and when any cell voltage becomes equal to or lower than a predetermined overdischarge protection voltage, it is serially connected to the charge / discharge path of the series storage cell. A voltage balance correction circuit for a series storage cell, comprising a cell protection circuit for setting an intervening protection switch from an on state to an off state.

  (3) In the means (1) or (2), a buffer output circuit including a pair of complementary transistors is interposed between the output terminal of the operational amplifier and the intermediate connection point. Voltage balance correction circuit.

  (4) In any one of the above means (1) to (3), transistors are respectively connected between the series terminals of the first cell and the second cell and the operation power input terminals on the positive side and the negative side of the operational amplifier. A voltage balance correction circuit for a series storage cell, wherein the transistor is interposed in series and the transistor is turned on only when a voltage between the series terminals is equal to or higher than a predetermined voltage.

  For example, in a power storage system such as a voltage sag / blackout compensator, a railway power storage device, etc., the voltage variation between cells that gradually occurs during long-term charging can be reduced easily and at low cost. With a circuit that can easily cope with increase / decrease, compensation can be made with high efficiency and high accuracy.

  The operations / effects other than the above will be clarified in the description of the present specification and the accompanying drawings.

  FIG. 1 shows a voltage balance correction circuit for a series storage cell according to a first embodiment of the present invention. FIG. 2 shows a circuit and an operation characteristic graph focusing on a part of FIG.

  The voltage balance correction circuit shown in the figure is a voltage balance correction circuit for a series storage cell that equalizes each voltage of a storage cell array in which four storage cells C1 to C4 are connected in series, and has the following configuration Is provided.

  First, as shown in FIG. 1, in four cells C1 to C4 connected in series, the cells C1 and C2, C2 and C3, and C3 and C4 are the first and second cells adjacent in series connection order, respectively. A set of cells is formed. Each set of cells forms two series cell portions, and each of the two series cell portions includes a discharge circuit unit 10 including a resistance voltage dividing circuit (R11, R12), an operational amplifier OP1, and resistance elements R13 to R16. is set up.

  Here, as shown in FIG. 2A, when attention is paid to C1 and C2 as a set of the first cell and the second cell, the resistance voltage dividing circuit (R11, R12) includes the first cell C1. And the voltage (E1 + E2) appearing at the series terminal of the second cell C2 is equally divided. The operational amplifier OP1 is supplied with positive and negative operating power supplies (+ V, −V) from the series terminal and performs a differential amplification operation.

  Each discharge circuit unit 10 has a divided voltage (Vp1) appearing at an intermediate voltage dividing point p2 of the resistance voltage dividing circuit (R11, R12) and an intermediate connection point p2 between the first cell C1 and the second cell C2. The intermediate voltage (Vp2) that appears is input to the differential input terminal (+, −) of the operational amplifier OP1 to amplify the difference (Vp1−Vp2) between the two voltages, and the output current Io obtained by the amplification is By supplying the intermediate connection point p2, a negative feedback loop is formed so that the voltage between the differential input terminals becomes zero. And when the voltage difference (E1-E2) arises between the 1st cell C1 and the 2nd cell C2, it is comprised so that a cell with a higher voltage may be discharged.

  That is, in FIG. 2, when the voltage E1 of the first cell C1 becomes higher than the voltage E2 of the second cell C2 (E1> E2), the divided voltage Vp1 becomes higher than the intermediate voltage Vp2 (Vp1> Vp2). A current is discharged from the output of the operational amplifier OP1 to the intermediate connection point p2 via the resistance element R14. As a result, the discharge current path of the first cell C1 is formed, and the voltage difference between the cells C1 and C2 is corrected.

  Conversely, when the voltage E2 of the second cell C2 becomes higher than the voltage E1 of the first cell C1 (E2> E1), the intermediate voltage Vp2 becomes higher than the divided voltage Vp1 (Vp2> Vp1), and the intermediate connection A current flows from the point p2 to the output of the operational amplifier OP1 through the resistance element R14. As a result, the discharge current path of the second cell C2 is formed and the voltage difference between the cells C1 and C2 is corrected.

  As described above, when a voltage difference occurs between the first cell C1 and the second cell C2, the higher voltage cell is discharged through the operational amplifier OP1, thereby reducing the voltage difference. Operation is performed.

  In the illustrated embodiment, the resistance element R13 sets the input resistance (impedance) of the operational amplifier OP1 to a predetermined value. The resistor element R14 limits the output current of the operational amplifier OP1, thereby protecting the operational amplifier OP1 and limiting the discharge current during the compensation operation.

  Here, in the operational amplifier OP1, negative feedback resistance elements R15 and R16 for controlling the amplification gain are inserted between the output terminal and the inverting input terminal. The negative feedback resistance elements R15 and R16 are set so that the voltage amplification gain of the operational amplifier OP1 is 500 times or less (500> R15 / R16).

  As a result, in the discharge circuit unit 10, as shown in the operation characteristic graph of FIG. 2B, the change in the output current Io with respect to the input voltage (Vp1-Vp2) is linearized and sloped. That is, by setting the amplification gain to a finite value less than a predetermined value by negative feedback, particularly 500 or less, the current Io according to the magnitude of the voltage difference (E1-E2) between the cells C1 and C2 at about 2V to 5V, The voltage difference (E1-E2) can be corrected to about 10 μV. In this way, excessive compensation operation can be avoided, and voltage balance correction can always be performed with an appropriate compensation amount.

  FIG. 3 shows a second embodiment of the voltage balance correction circuit according to the present invention. In the figure, (a) shows the voltage balance correction circuit, and (b) shows the operation characteristics of the main part.

  In the voltage balance correction circuit shown in the figure, a constant input diode (Zener diode) Dz connected in series in the opposite direction is interposed at the input of the operational amplifier OP1, thereby providing a predetermined input threshold at the input of the operational amplifier OP1. A value Vz is provided.

  Thereby, when the voltage difference (E1-E2) between the cells C1 and C2 is equal to or less than a predetermined value and there is no need for voltage correction, unnecessary compensation operation can be avoided.

  In this embodiment, since the input threshold value Vz of the operational amplifier OP1 is set to be relatively high, the cells C1 and C2 that are subject to voltage balance correction are constituted by, for example, cell modules in which a plurality of cells are connected in series. Suitable for such cases.

  FIG. 4 shows a third embodiment of the voltage balance correction circuit according to the present invention. In the figure, (a) shows the voltage balance correction circuit, and (b) shows the operation characteristics of the main part.

  In the voltage balance correction circuit shown in the figure, similarly to the embodiment shown in FIG. 3, the voltage difference (E1−E2) between the cells C1 and C2 is provided by giving a predetermined input threshold value Vf to the input of the operational amplifier OP1. ) Is made to perform the compensation operation only when it exceeds a predetermined value.

  In this case, in this embodiment, in order to set the input threshold value Vf of the operational amplifier OP1, a diode Df connected in parallel so as to be forward in both directions is interposed at the input of the operational amplifier OP1. .

  As a result, an input threshold value Vf corresponding to the forward voltage (about Vf = 0.5 V) of the diode Df is set, and a voltage difference (E1-E2) exceeding the threshold value Vf is between the cells C1 and C2. The compensation operation is performed only when it occurs.

  As described above, for example, in a power storage system such as a voltage sag / blackout compensator, a railway power storage device, etc., cell voltage variation that gradually occurs during long-term charging can be easily and cost-effectively connected in series. With a circuit that can easily cope with an increase or decrease in the number of connections, high-efficiency and high-precision compensation can be performed.

  The voltage balance correction circuit of the present invention described above is particularly effective in combination with a conventional cell protection circuit 20 (see Patent Document 1) as shown in FIG.

  The cell protection circuit 20 individually monitors the voltages of the cells C1 to C4, and when any of the cell voltages becomes equal to or higher than a predetermined overcharge protection voltage or lower than a predetermined overdischarge protection voltage, the series storage cell By setting the protection switch Suvp or Sovp interposed in series in the charging / discharging path from the on state to the off state, it is possible to prevent each of the cells C1 to C4 from being overcharged or overdischarged.

  By combining the above-described voltage balance correction circuit of the present invention with this cell protection circuit 20, the voltage variation between the cells can be steadily corrected, so that the cell protection circuit 20 can be operated with little discharge or charge. It is possible to avoid the operation from occurring. As a result, the function as the capacitor of the entire series storage cells C1 to C4 is reliably maintained.

  In the 4 series cells C1 to C4 described above, between the first cell C1 and the second cell C2, between the second cell C2 and the third cell C3, and between the third cell C3 and the fourth cell C4. Each of the discharge circuit units 10 is installed, and the wiring connection for the installation can be performed at the same place as the wiring connection between the series cells C1 to C4 and the cell protection circuit 20, as shown in FIG. . Thereby, the expansion of the number of storage cells in series can be easily coped with by adding the circuit unit 10.

  FIG. 5 shows a typical internal equivalent circuit of the operational amplifier OP1. The operational amplifier OP1 shown in the figure is configured as a monolithic IC, and includes MOS transistors Q01 and 02, bipolar transistors Q03 to Q08, resistance elements R01 and R02, diodes D01 to D03, constant current circuits Ic1 and Ic2, and the like. Operation is performed with two power supplies + V and -V, and a differential amplification operation is performed using an intermediate potential between the power supplies + V and -V as an operation reference potential.

  In the figure, transistors Q01 to Q04, resistance elements R01 and R02, and a constant current circuit Ic1 form a differential input circuit. Transistors Q05 and Q06, diodes D01 to D03, and constant current circuit Ic2 form interstage buffer, phase division, and level shift circuit functions. The transistors Q05 and Q06 are complementary bipolar transistors of npn and pnp, and form a push-pull type output stage by being totem-pole connected between the power supplies + V and −V.

  FIG. 6 shows a fourth embodiment of the voltage balance correction circuit according to the present invention. In the voltage balance correction circuit shown in the figure, a buffer output circuit 11 including a pair of complementary transistors Q11 and Q12 is interposed between the output terminal of the operational amplifier OP1 and the intermediate connection point p2.

  The complementary transistors Q11 and Q12 are npn and pnp bipolar transistors, each emitter being connected to the intermediate connection point p2, and each collector being connected to the series terminal of the two series cells C1 and C2 via the resistance elements R18 and R19. It is connected. The bases are connected in common and then connected to the output terminal of the operational amplifier OP1 through the resistor element R14.

In this embodiment, when the voltage difference (E1-E2) between the cells C1 and C2 is detected by the operational amplifier OP1, the output of the operational amplifier OP1 energizes and drives one of the complementary transistors Q11 and Q12. Discharge the high voltage cell to correct the voltage balance.
This embodiment is particularly effective when the capacitance values of the cells C1 and C2 are large and when it is desired to speed up the voltage balance correction operation.

  FIG. 7 shows a fifth embodiment of the voltage balance correction circuit according to the present invention. In the voltage balance correction circuit shown in the figure, transistors Q13 and Q14 are connected in series between the series terminals of the two series cells C1 and C2 and the operating power input terminals (+ V, −V) on the positive and negative sides of the operational amplifier OP1, respectively. In addition, the transistors Q13 and Q14 are turned on only when the voltage (E1 + E2) between the series terminals is equal to or higher than a predetermined voltage.

  The transistors Q13 and Q14 are pnp and npn bipolar transistors. The pnp transistor Q13 is interposed between the positive side of the series terminal and the positive side operation power supply input terminal (+ V) of the operational amplifier OP1, and the voltage between the series terminals ( E1 + E2) is divided by the resistance elements R20 and R21 and applied to the base.

  The npn transistor Q14 is interposed between the negative side of the series terminal and the negative side operation power supply input terminal (−V) of the operational amplifier OP1, and the collector voltage of the pnp transistor Q13 is divided by the resistance elements R22 and R23 to become the base. It is to be applied. That is, the npn transistor Q14 is turned on / off following the pnp transistor Q13.

  In this embodiment, when the series voltage (E1 + E2) of the cells C1 and C2 is equal to or lower than a predetermined voltage, both the transistors Q13 and Q14 are turned off, so that the operation power supply of the operational amplifier OP1 is cut off and the consumption current is zero. become.

  The operating current of the operational amplifier OP1 is very small and can be almost ignored when the cells C1 and C2 are in use. However, when the operational amplifier OP1 and the series cells C1 and C2 are modularized to make a product, the module cells C1 and C2 are defined between shipment and use by the user or while remaining in the warehouse. There is a concern that the battery will be discharged below the final discharge voltage. In order to avoid this concern, it is necessary to manage the time from shipping to the start of use, which is actually difficult.

  However, according to the above-described embodiment, the operation power supply of the operational amplifier OP1 can be automatically shut off before the cells C1 and C2 are lowered to the specified end-of-discharge voltage. Can be made unnecessary.

  As described above, the present invention has been described based on the typical embodiments. However, the present invention can have various modes other than those described above. For example, the transistors Q11 to Q14 can be replaced with MOS transistors.

  For example, in a power storage system such as a voltage sag / blackout compensator, a railway power storage device, etc., the voltage variation between cells that gradually occurs during long-term charging can be reduced easily and at low cost. With a circuit that can easily cope with increase / decrease, compensation can be made with high efficiency and high accuracy.

It is a circuit diagram which shows the voltage balance correction circuit of the serial electrical storage cell which makes 1st Embodiment of this invention. FIG. 2 is a main part circuit diagram and a main part operation characteristic graph showing the voltage balance correction circuit of FIG. It is the circuit diagram and principal part characteristic view which show 2nd Embodiment of the voltage balance correction circuit by this invention. It is the circuit diagram and principal part characteristic diagram which show 3rd Embodiment of the voltage balance correction circuit by this invention. It is a circuit diagram which shows the typical internal equivalent circuit of the operational amplifier used by this invention. FIG. 6 is a main part circuit diagram and a main part characteristic diagram showing a fourth embodiment of a voltage balance correction circuit according to the present invention; FIG. 10 is a main part circuit diagram and a main part characteristic diagram showing a fifth embodiment of a voltage balance correction circuit according to the present invention; It is a circuit diagram which shows the cell protection circuit used with the conventional serial cell. It is the circuit diagram which shows the principal part of the voltage balance correction circuit used with the conventional series cell, and the operation characteristic graph of the principal part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Discharge circuit unit 11 Buffer output circuit 20 Cell protection circuit C1-C4 Power storage cell T1-T2 External terminal Suvp Overcharge protection switch Sovp Overdischarge protection switch R11, R12 Resistance element (resistance voltage dividing circuit)
OP1 Operational Amplifier + V Positive Operating Power Supply -V Negative Operating Power Supply p1 Intermediate Voltage Dividing Point of Resistance Divider Circuit (R11-R12) Vp1 Divided Voltage p2 Intermediate Connection Point of Cells C1 and C2 Vp2 Intermediate Voltage R14 to R23 Resistive element I1 Discharge current of the first cell C1 I2 Discharge current of the second cell C2 Vp1-Vp2 Input voltage of the operational amplifier OP1 Io Output current of the operational amplifier OP1 Vz Input threshold value of the operational amplifier OP1 Vf of the operational amplifier OP1 Input threshold Dz Constant voltage diode (Zener diode)
Df diode (forward diode)

Claims (4)

A voltage balance correction circuit for a series storage cell that equalizes each voltage of a storage cell array in which two or more storage cells are connected in series,
(A) a resistance voltage dividing circuit for equally dividing a voltage appearing at a series terminal of the first cell and the second cell between the first cell and the second cell adjacent in series connection order; A discharge circuit unit with an operational amplifier to which positive and negative operating power is supplied from the terminal is installed,
(B) In each discharge circuit unit, the divided voltage appearing at the intermediate voltage dividing point of the resistance voltage dividing circuit and the intermediate voltage appearing at the intermediate connection point of the first cell and the second cell are the differential of the operational amplifier. The difference between the two voltages input to the input terminal is amplified, and the output current obtained by the amplification is supplied to the intermediate connection point, so that the voltage between the differential input terminals becomes zero. When a feedback loop is formed and a voltage difference occurs between the first cell and the second cell, the cell having the higher voltage is discharged,
(C) A current limiting resistor element is interposed in series at the output terminal of the operational amplifier, and a negative feedback resistor element is inserted between the output terminal and the inverting input terminal to control the voltage amplification gain to 500 times or less. As a result, the change in the output current with respect to the input voltage was linearized and sloped.
A voltage balance correction circuit for a series storage cell, wherein:   In Claim 1, the voltage of each cell is monitored individually, and when any cell voltage becomes a predetermined overdischarge protection voltage or less, the protection switch interposed in series in the charge / discharge path of the series storage cell A voltage balance correction circuit for a series storage cell, wherein a cell protection circuit for setting an on state to an off state is provided.   3. The voltage balance correction circuit for a series storage cell according to claim 1, wherein a buffer output circuit comprising a pair of complementary transistors is interposed between the output terminal of the operational amplifier and the intermediate connection point.   The transistor according to any one of claims 1 to 3, wherein a transistor is interposed in series between the series terminal of the first cell and the second cell and the operating power input terminal on the positive side and the negative side of the operational amplifier, and A voltage balance correction circuit for a series storage cell, wherein the transistor is turned on only when a voltage between series terminals is equal to or higher than a predetermined voltage.

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