JP2010062860A - Switching element drive circuit - Google Patents

Description

  The present invention relates to a switching element drive circuit that drives a switching element that constitutes a power conversion circuit that performs power conversion.

  As a conventional switching element driving circuit, for example, in a driving circuit of a current sense IGBT having a function of outputting a detection current obtained by detecting a current flowing in its own main circuit, an excess of the main circuit is detected from the detection current. A current sensing IGBT comprising means for determining a current, and a variable voltage source for gradually decreasing the voltage applied to the gate of the IGBT over time while the determining means is operating. A drive circuit has been proposed (see, for example, Patent Document 1).

  In addition, the first switching element and the second switching element are connected in series between the power supply terminal and the reference potential terminal, and a voltage interrelated with the voltage at the connection point of the first switching element and the second switching element is output gate. A gate drive circuit that supplies a voltage to the drive switching element as a voltage, and when an overcurrent of the drive switching element is detected by the overcurrent detection circuit, a protection signal is supplied from the latch circuit and an external on / off input signal is input respectively. By supplying to the switch control circuit and the switch control circuit for turning off, when the overcurrent is detected by the overcurrent detection circuit while the first switching element is in the on state, the first switching element is turned off. There has also been proposed a gate drive circuit that controls the second switching element to be turned on. For example, see Patent Document 2). Here, the switch control circuit for off has a power supply buffer stage whose input reference voltage is changed, and includes a buffer stage whose driving state and non-driving state are controlled by the output of the power supply buffer stage. The output is connected to the gate of the second switching element.

Furthermore, it has a source driver and a sink driver connected in series between the DC power source and the ground, and has a configuration for supplying the gate voltage obtained at the connection point of both drivers to the gate of the IGBT to be driven. The IGBT's gate voltage is lowered by an overcurrent limiting circuit provided between the connection point of both drivers and ground for a relatively short time of overcurrent, and the overcurrent protection circuit is used for a relatively long time of overcurrent. First, an overcurrent protection transistor provided between both drivers and the ground causes the gate voltage to be lowered relatively slowly, and then the sink driver is turned on to rapidly lower the gate voltage to “0” due to current fluctuation. There has also been proposed a semiconductor switching element driving circuit that performs high-speed interruption of an IGBT while preventing a jumping voltage (for example, Patent Documents). Reference).
JP-A-4-79758 (FIG. 5) Japanese Patent Laying-Open No. 2006-229454 (FIGS. 1, 2, and 4) JP 2001-345688 A (FIGS. 1 and 2)

In the conventional examples described in the above Patent Documents 1 to 3, when an overcurrent of a switching element to be controlled is detected, the drive voltage applied to the control terminal of the switching element is reduced to reduce the overcurrent. The switching element is protected from current.
However, the control mode of the drive voltage when protecting the switching element from the overcurrent is, in the conventional example described in Patent Document 1, two switching elements that form the drive voltage by applying the drive voltage applied to the switching element to be driven. Uses another active element to lower the drive voltage, but in the conventional example described in Patent Document 2, the drive voltage applied to the switching element to be driven is driven out of the two switching elements that form the drive voltage. The switching element for turning off the voltage is controlled to lower the drive voltage. Further, the conventional example described in Patent Document 3 has both configurations of Patent Documents 1 and 2.

  By the way, in the case of the conventional example described in Patent Document 2, the switching element to be driven among the first switching element and the second switching element for forming the driving voltage applied to the switching element to be driven is selected. Since the second switching element that is controlled to be in the off state is used to control the drive voltage drop at the time of overcurrent, the configuration of the off switch control circuit for driving the second switching element is complicated. There is a problem of becoming.

Therefore, in order to easily drive the two switching elements that control the driving voltage of the switching element to be driven, an active element other than the two switching elements that drives the driving target switching element described in Patent Document 1 It is preferable to employ a method of reducing the drive voltage of the switching element to be driven at the time of overcurrent by using.
The basic operation in this case will be described with reference to FIG. 7 in the case of driving the IGBT of the inverter circuit.

  The inverter circuit 100 includes three switching arms SA1 to SA3 connected in parallel between the positive electrode line P and the negative electrode line N. The switching arm SA1 is configured by connecting two IGBTs 101 and 102 in series, and a connection point between the two IGBTs 101 and 102 is connected to a three-phase AC load. Similarly, the switching arm SA2 is also configured by connecting two IGBTs 103 and 104 in series, and a connection point between the IGBTs 103 and 104 is connected to a three-phase AC load. Furthermore, the switching arm SA3 is also configured by connecting two IGBTs 105 and 106 in series, and a connection point between the IGBTs 105 and 106 is connected to a three-phase AC load.

Each of the IGBTs 101 to 106 includes a current detection IGBT 107 as represented by the IGBT 101 of the switching arm SA1.
And the gate of each IGBT101-106 is driven by driver IC110 as a drive circuit. As representatively shown for the IGBT 101, the driver IC 110 includes a P-channel field effect between a control voltage input terminal tvcc to which a DC control power supply 120 is connected and a PGND terminal tpgnd to which a negative line N of the inverter circuit 100 is connected. Transistor 111 and N-channel field effect transistor 112 are connected in series, and the gates of these field effect transistors 111 and 112 are connected to each other and connected to a control signal input terminal tin. The connection point is connected to the gate of the IGBT 101 of the inverter circuit 100 through the output terminal tout.

  In the driver IC 110, voltage dividing resistors R1 and R2 are connected between a current input terminal toc connected to the emitter of the current detection IGBT 107 and a ground terminal tgnd connected to the ground, and these voltage dividing resistors R1 and R2 are connected. A voltage value Vi representing the current flowing through the IGBT 101 divided in step S is input to one input side of the comparator 113, and the first reference voltage source 114 is connected to the other input side of the comparator 113. The comparator 113 outputs a high-level comparison signal when the input voltage value Vi becomes equal to or higher than the first reference voltage Vb1 of the first reference power supply 114. The comparison signal output from the comparator 113 is supplied to the gate of the N-channel field effect transistor 115 connected in parallel with the N-channel field effect transistor 112 described above.

  According to this switching element driving circuit, a rectangular wave signal that takes a DC voltage Vc equal to the DC voltage VCC of the DC control power supply 120 and a ground voltage is input to the control signal input terminal tin of the driver IC 110. Here, when the rectangular wave signal input to the control signal input terminal tin is the ground voltage, the P-channel field effect transistor 111 is turned on and the N-channel field effect transistor 112 is turned off. As a result, the output voltage of the output terminal tout becomes the DC voltage VCC of the DC control power supply 120, and the IGBT 101 of the inverter circuit 100 becomes conductive.

Conversely, when the rectangular wave signal input to the control signal input terminal tin is the DC voltage Vc, the P-channel field effect transistor 111 is turned off and the N-channel field effect transistor 112 is turned on. As a result, the output voltage of the output terminal tout becomes the ground voltage, and the IGBT 101 of the inverter circuit 100 becomes nonconductive.
In this way, by driving the IGBTs 101 to 106 of the inverter circuit 100 with the individual driver ICs 110, the DC voltage between the positive line P and the negative line N can be supplied to the three-phase load as a three-phase AC voltage. it can.

By the way, for example, when the rectangular wave signal input to the control signal input terminal tin becomes the ground voltage, the P-channel field effect transistor 111 is turned on and the N-channel field effect transistor 112 is turned off as described above. . During this period, the voltage at the output terminal tout becomes the DC voltage VCC and becomes a high voltage, and the IGBT 101 becomes conductive.
During the period when the IGBT 101 is in a conductive state, the IGBT 102 of the upper arm is in a non-conductive state when in a normal state. A DC high voltage of 300 V or 400 V (voltage between the positive line P and the negative line N) is directly applied to the IGBT 101 between the collector and the emitter, and an excessive current flows through the collector of the IGBT 101.

Therefore, a current proportional to the collector current of the IGBT 101 flows through the IGBT 107 for detecting the collector current of the IGBT 101, and this current flows into the voltage dividing resistors R1 and R2 via the current input terminal toc, and the voltage dividing resistors R1 and R2 The voltage value Vi obtained from the connection point becomes higher.
When the voltage value Vi becomes equal to or higher than the first reference voltage Vb1 input to the comparator 113, the comparison output output from the comparator 113 is inverted from the ground voltage to the high voltage. Therefore, the N-channel field effect transistor 115 to which the comparison output is supplied to the gate is turned on, the voltage at the output terminal tout, that is, the gate voltage of the IGBT 101 is lowered, and the collector current of the IGBT 101 is suppressed, thereby suppressing the IGBT 101. Avoid device destruction.

As described above, when the IGBT 101 becomes an overcurrent state and the current limiting N-channel field effect transistor 115 becomes conductive, the P-channel field effect transistor 111 and the current limiting N-channel field effect transistor 115 become conductive at the same time. It becomes.
The output voltage of the output terminal tout during this overcurrent period is determined by the source-drain voltage vs. source current characteristics of the P-channel field effect transistor 111 and the current limiting N-channel field effect transistor 115. The output terminal voltage versus source current characteristics of the P-channel field effect transistor 111 and the current limiting N-channel field effect transistor 115 are shown in FIG.

  The characteristic of the N channel field effect transistor 115 for current control is a curve L1 that rises to the right, and the characteristic of the P channel field effect transistor 111 is a curve L2 that falls to the right. At the point PO where these two curves intersect, the collector current of the P-channel field effect transistor 111 and the current limiting N-channel field effect transistor 115 is the same, so that the current passing through the output terminal tout becomes zero, The terminal tout can be in a stable state with a constant voltage.

However, in the conventional example shown in FIG. 7, in order to verify the overcurrent limiting operation of the driver IC 110, it is necessary to configure the overcurrent test circuit shown in FIG. In this overcurrent test circuit, the input signal source 120 is connected to the control signal input terminal tin of the driver IC 110, and the DC voltage source 130 is connected between the collector and emitter of the IGBT 101.
FIG. 10 shows the gate voltage of the IGBT 101 when the step-down voltage is generated in the input signal source 120 in this overcurrent test circuit. In FIG. 10, the voltage when the size of the P-channel field effect transistor 111 is fixed and the size of the current limiting N-channel field effect transistor 115 is changed (a, b, c, d, e) is filled in.

  When the voltage VS of the input signal source 120 is stepped down at time t1, the collector current of the IGBT 101 increases, and the comparator 113 is inverted, so that the current limiting N-channel field effect transistor 115 becomes conductive, and the gate of the IGBT 101 The voltage VG is a constant voltage (curves a, b, c, and d) lower than the voltage VCC of the input signal source 120. These curves are obtained when the current limiting N-channel field effect transistor 115 is maintained in an overcurrent state.

Here, the curve e is the gate voltage VG of the IGBT 101 when the size of the current limiting N-channel field effect transistor 115 is increased and the overcurrent limitation is severe. This is a continuous vibration. This is caused by vibrations that occur when the current control N-channel field effect transistor repeats a conductive state and a non-conductive state in an overcurrent state.
Due to the step-down change of the control signal input terminal tin, the P-channel field effect transistor 111 becomes conductive, the N-channel field effect transistor 112 becomes non-conductive, the gate voltage of the IGBT 101 rises, and the IGBT 101 becomes conductive. An excessive current flows through the collector. When a current proportional to this current flows to the IGBT 107 and flows into the OC terminal toc, the voltage Vi divided by the resistors R1 and R2 rises and exceeds the voltage of the first reference voltage Vb1, the comparator The output of 113 is inverted from the ground voltage to the high voltage, and the current limiting N-channel field effect transistor 115 is turned on.

Since the size of the current limiting N-channel field effect transistor 115 is large, the gate voltage drop of the IGBT 101 also increases, and the collector current of the IGBT 101 decreases. When this current drop increases, the comparison output of the comparator 113 is inverted again, and the current limiting N-channel field effect transistor 115 becomes non-conductive.
The conduction state and the non-conduction state of the current limiting N-channel field effect transistor 115 are repeated to generate a continuous vibration of the curve e, and noise may be generated to cause a malfunction of the driver IC 110.

  In order to avoid this continuous vibration, an accurate simulation model of the P-channel field effect transistor 111, the current limiting N-channel field effect transistor 115, and the current detection IGBT 107 is required when designing the driver IC 110. It becomes very difficult. In order to put it into practical use, it is necessary to manufacture a driver IC 110 in which the sizes of the P-channel field-effect transistor 111 and the current-limiting N-channel field-effect transistor 115 are variously changed, and to confirm appropriate values through tests. Cost and time are required.

FIG. 11 shows the waveform of the gate voltage VG of the IGBT 101 during the short-circuit test when the DC control voltage VCC input to the control power supply voltage input terminal tvcc of the driver IC 110 is changed. When the magnitude of the DC control voltage VCC is changed, the steady voltage value of the gate voltage VG of the IGBT 101 at the time of overcurrent changes, so that the limit value of the collector current of the IGBT 101 is also affected by the magnitude of the DC control voltage VCC. There is also a problem.
Furthermore, the system having a large rated output current of the inverter circuit 100 has the following two problems.

  The first is an increase in manufacturing costs. From the viewpoint of efficiency, it is necessary to design the resistance of the IGBT 101 to be small, and the size of the IGBT 101 becomes large. In order to drive the IGBT 101 having a large size, it is necessary to increase the drive capability of the P-channel field effect transistor 111, so the size of the P-channel field effect transistor 111 is necessarily increased. When the size of the P-channel field effect transistor 111 is large, the size of the current limiting N-channel field effect transistor 115 needs to be increased in order to rapidly control the voltage at the output terminal tout during an overcurrent. There is an unsolved problem that the chip size increases and the manufacturing cost increases.

The second is a noise malfunction. As the current flowing through the IGBT 101 increases, the noise generated in the inverter circuit 100 also increases. Even in normal sound operation, this noise flows into the OC terminal toc of the driver IC 110, causing an unsolved problem that the current limiting N-channel field effect transistor 115 malfunctions.
Accordingly, the present invention has been made paying attention to the unsolved problems of the above-described conventional example, and an object thereof is to provide a switching element driving circuit that reduces the chip size and does not increase the manufacturing cost. . In addition to the above object, an object of the present invention is to provide a switching element drive circuit that can avoid malfunction due to noise.

  To achieve the above object, a switching element drive circuit according to claim 1 includes a power conversion circuit that has a switching element and performs power conversion, and the switching element of the power conversion circuit is in an operating state. A switching element drive circuit comprising: a drive circuit that supplies a source current to a control terminal of the switching element and supplies a sink current to the control terminal when the switching element is in a non-operating state; A current detection unit that detects a flowing current as a voltage value; and a voltage value detected by the current detection unit is compared with a first reference voltage to output an overcurrent detection signal when an overcurrent state is detected. An overcurrent state control unit for stopping supply of a source current to the control terminal of the switching element of the drive circuit, and a voltage detected by the current detection unit And the second reference voltage are input, the output is supplied to the output side of the drive circuit, and there is an operational amplifier that enters an operation state when an overcurrent detection signal is output from the overcurrent state control unit. And an output voltage controller that stabilizes the output voltage of the drive circuit in accordance with the second reference voltage when the operational amplifier is in an operating state.

  According to a second aspect of the present invention, there is provided the switching element driving circuit according to the first aspect, wherein the driving circuit is connected to a control power source to control the source current and the first switching element. A second switching element for controlling the sink current connected between the element and a negative electrode side of the DC power source, and a connection point of the first switching element and the second switching element is the power conversion It is characterized by being connected to the control terminal of the switching element of the circuit.

  Further, in the switching element drive circuit according to claim 3, in the invention according to claim 2, the overcurrent state detection unit compares the voltage value detected by the current detection unit with the first reference voltage. A comparison circuit that outputs a detection signal when the voltage value is equal to or higher than the first reference voltage, and a flip-flop circuit that is set by the detection signal output from the comparison circuit and outputs the overcurrent detection signal And an OR circuit in which a control signal is input to one input side, a positive output of the flip-flop circuit is input to the other input side, and an output is supplied to the control terminal of the first switching element. It is characterized by having.

Furthermore, the switching element drive circuit according to claim 4 is the invention according to claim 3, wherein the overcurrent control unit includes a noise removal circuit including a signal delay circuit between the comparison circuit and the flip-flop circuit. It is characterized by being inserted.
Still further, the switching element drive circuit according to claim 5 is the invention according to any one of claims 1 to 4, wherein the output voltage controller is configured to perform the calculation when the operational amplifier is in an operating state. Control is performed so that the second reference voltage input to the amplifier matches the voltage value detected by the current detection unit.

A switching element driving circuit according to a sixth aspect is the invention according to any one of the first to fifth aspects, wherein the operational amplifier uses the first reference of the overcurrent detection unit as the second reference voltage. It is characterized by voltage being input.
Furthermore, the switching element drive circuit according to claim 7 is the invention according to any one of claims 2 to 5, wherein the operational amplifier includes the second switching element of the drive circuit as the second reference voltage. The voltage dividing voltage of the voltage dividing resistor connected in parallel is inputted.
Furthermore, the switching element drive circuit according to claim 8 is characterized in that, in the invention according to any one of claims 1 to 7, the switching element of the inverter circuit is an IGBT.

According to the present invention, when the overcurrent state control unit detects an overcurrent state of the switching element to be driven, the supply of the source current to the switching element from which the drive is canceled from the drive circuit is stopped, and at the same time, the drive voltage In the control unit, the operational amplifier to which the voltage value detected by the current detection unit and the second reference voltage are input is operated, and the output voltage of the drive circuit is stabilized according to the second reference voltage. Unlike the conventional example, it is not necessary to provide a current limiting N-channel field effect transistor having the same size as that of the P-channel field effect transistor, and the calculation is performed without being affected by the DC control voltage supplied to the drive circuit. The amplifier can stabilize and control the output voltage of the drive circuit, and can suppress the increase in chip size and reduce the manufacturing cost. The effect is obtained that that.
Further, the overcurrent state control unit supplies the overcurrent detection signal of the overcurrent detection circuit to the flip-flop circuit via the noise removal circuit including the signal delay circuit, and sets the flip-flop circuit. Thus, the effect of removing the influence of noise can be obtained.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a first embodiment of the present invention, in which 1 is an inverter circuit as a power conversion circuit, and this inverter circuit 1 is connected to a DC voltage source (not shown). Between the positive electrode line P and the negative electrode line N, three switching arms SA1 to SA3 are connected in parallel. In the switching arm SA1, two IGBTs 11 and 12 as switching elements are connected in series between a negative electrode line N and a positive electrode line P, and an AC output terminal tu is derived from a connection point between the IGBTs 11 and IGBT12. In the switching arm SA2, two IGBTs 13 and 14 as switching elements are connected in series between the negative electrode line N and the positive electrode line P, and an AC output terminal tv is derived from a connection point between the IGBTs 13 and 14. Further, in the switching arm SA3, two IGBTs 15 and 16 as switching elements are connected in series between the negative electrode line N and the positive electrode line P, and an AC output terminal tw is derived from a connection point between the IGBTs 15 and 16. Then, a three-phase load such as a three-phase AC motor is connected to each AC output terminal tu to tw.

Moreover, each IGBT11-16 which comprises the inverter circuit 1 is equipped with IGBT17 for a current detection by which the collector was connected to the collector of IGBT11 and the gate was connected to the gate of IGBT11 so that it might represent by IGBT11.
And the gate voltage VG of each IGBT11-16 which comprises the inverter circuit 1 is controlled by driver IC20 as a drive circuit so that it may represent by IGBT11.

  The driver IC 20 includes a control signal input terminal tin to which an on / off control signal CS for on / off control of the IGBT 11 of the inverter circuit 1 is input, a DC control power supply terminal tvcc to which a DC voltage VCC from the DC control voltage source 30 is input, an inverter circuit Output terminal tout connected to the gate of one IGBT 11, ground terminal tpgnd connected to the negative electrode line N of the inverter circuit 1, detection current input terminal toc connected to the emitter of the current detection IGBT 17 of the inverter circuit 1, and ground A ground terminal tgnd to be connected is provided.

  A P-channel field effect transistor 21 as a first switching element that controls a source current between a DC control voltage terminal tvcc and a ground terminal tpgnd and an N-channel field effect type as a second switching element that controls a sink current. The transistor 22 is connected in series, and the field effect transistors 21 and 22 constitute a drive circuit 23. A connection point between the P-channel field effect transistor 21 and the N-channel field effect transistor 22 is connected to the output terminal tout.

  The driver IC 20 has voltage dividing resistors R1 and R2 connected in series between the current input terminal toc and the ground terminal tgnd, and the collector of the IGBT 11 of the inverter circuit 1 from the connection point of the voltage dividing resistors R1 and R2. A voltage value Vi corresponding to the value of the current flowing through is output. These voltage dividing resistors R1 and R2 and the current detection IGBT 17 constitute a current detection circuit 40.

  The driver IC 20 includes an overcurrent state control unit 50 to which the voltage value Vi detected by the current detection circuit 40 is input. In this overcurrent state control unit 50, the voltage value Vi input from the current detection circuit 40 is on the non-inverting input side, and the first reference voltage Vb1 from the DC power supply (first reference voltage source) 51 is on the inverting input side. And a comparator 52 that outputs a comparison signal Sc having a logic value “0” when Vi <Vb1 and a logic value “1” when Vi ≧ Vb1. In the overcurrent state control unit 50, the comparison signal Sc output from the comparator 52 is input to the set terminal S, and the control signal CS input to the control signal input terminal tin is input to the reset terminal R. A flip-flop circuit 53 is provided. Further, the overcurrent state control unit 50 receives the overcurrent detection signal Soc output from the positive output terminal Q of the flip-flop circuit 53 on one input side and the control signal input to the control signal input terminal tin on the other input side. An OR circuit 54 to which CS is input is provided. The output of the OR circuit 54 is supplied to the gate of the P-channel field effect transistor 21.

  Further, the driver IC 20 includes an output voltage control unit 60 to which the first reference voltage Vb1 described above is input as the second reference voltage Vb2 and the voltage value Vi detected by the current detection circuit 40 is input. This output voltage control unit 60 has an operational amplifier 61 in which the first reference voltage Vb2 is input to the non-inverting input side, the voltage value Vi is input to the inverting input side, and the operation state is controlled by an external signal. The output side of the operational amplifier 61 is connected between the connection point of the P-channel field effect transistor 21 and the N-channel field effect transistor 22 of the drive circuit 23 and the output terminal tout. The operational amplifier 61 receives the overcurrent detection signal Soc output from the flip-flop circuit 53 of the above-described overcurrent state control unit 50 as an external signal. Thus, when the overcurrent detection signal Soc is in the on state, the operation state is established.

Next, the operation of the first embodiment will be described.
Now, in a state where the inverter circuit 1 is normal, when the IGBTs 11, 13 and 15 constituting the lower arm are controlled to be in the ON state in the switching arms SA1 to SA3, the IGBTs 12, 14 and 16 constituting the upper arm are turned off. The IGBTs 11 to 16 are controlled to be in a state and are subjected to pulse width modulation control by individual driver ICs, thereby converting the DC power supplied to the positive line P and the negative line N into AC power and output from the output terminals tu to tw. Supply to a three-phase load.

When the inverter circuit 1 is in a normal state, the current value flowing through the current detection IGBT 17 provided in each of the IGBTs 11 to 16 is a relatively small value, and the voltage value Vi divided by the voltage dividing resistors R1 and R2 is also The value is smaller than the first reference voltage Vb1.
For this reason, the comparison signal Sc output from the comparator 52 also becomes a logical value “0”, and the flip-flop circuit 53 receives the ON state control signal CS that becomes the predetermined DC voltage Vc at the reset terminal R. The reset state is maintained, and the overcurrent detection signal Soc maintains the off state.

For this reason, the operational amplifier 61 of the output voltage control unit 60 maintains the non-driven state since the input overcurrent detection signal Soc is in the OFF state.
Therefore, in the drive circuit 23, when the control signal CS input to the control signal input terminal tin is in the off state, which is the ground voltage, the P-channel field effect transistor 21 is in a conductive state and the N-channel field effect transistor 22 is non-conductive. It becomes a conductive state. For this reason, a direct current from the direct current control voltage source 30 is supplied as a source current to the gate of the IGBT 11 of the inverter circuit 1, and the gate voltage VG becomes a high voltage so that the IGBT 11 is controlled to be conductive.

On the other hand, when the control signal CS input to the control signal input terminal tin is in the ON state where the predetermined DC voltage is applied, the P-channel field effect transistor 21 is turned off and the N-channel field effect transistor 22 is turned on. It becomes. For this reason, a sink current flows through the N-channel field effect transistor 22, the gate voltage VG of the IGBT 11 of the inverter circuit 1 is lowered, and the IGBT 11 becomes non-conductive.
As for the other IGBTs 12 to 16 of the inverter circuit 1, a three-phase alternating current is applied to the three-phase load from the alternating current output terminals tu to tw by controlling the conductive state and the nonconductive state at a predetermined timing by a driver IC (not shown). Is output.

  From the normal state of the inverter circuit 1, for example, the control signal CS in the off state is input to the driver IC 20, and the IGBT 11 of the switching arm SA 1 is controlled to be in a conductive state. When an arm short-circuit phenomenon occurs in which the emitters are short-circuited, a DC high voltage of 300 V or 400 V supplied between the positive electrode line P and the negative electrode line N is directly applied between the collector and emitter of the IGBT 11, An excessive current flows through the collector of the IGBT 11.

Therefore, a current proportional to the collector current of the IGBT 11 flows through the current detection IGBT 17, and this current flows to the voltage dividing resistors R1 and R2 via the current input terminal toc. Therefore, the connection point between these voltage dividing resistors R1 and R2 The voltage value Vi rises in comparison with the normal value and becomes equal to or higher than the first reference voltage Vb1.
As a result, the comparison signal Sc output from the comparator 52 is inverted from the logical value “0” to the logical value “1”, and accordingly, the flip-flop circuit 53 is set and turned on from the positive output terminal Q. The overcurrent detection signal Soc is output. For this reason, since the ON-state overcurrent detection signal is input to the gate of the P-channel field effect transistor 21 via the OR circuit 54, the P-channel field effect transistor 21 is controlled to be non-conductive. At this time, since the control signal CS input to the control signal input terminal tin is in the off state, the N-channel field effect transistor 22 continues to be in a non-conductive state.

Therefore, the gate voltage VG supplied to the gate of the IGBT 11 of the inverter circuit 1 is maintained in a high voltage state, but the overcurrent detection signal Soc output from the flip-flop circuit 53 is turned on. The operational amplifier 61 of the output voltage control unit 60 changes from the non-operating state to the operating state. Therefore, in the operational amplifier 61, the gate voltage VG is set so that the first reference voltage Vb1 supplied to the input side matches the voltage value Vi detected by the voltage dividing resistors R1 and R2 of the current detection circuit 40. Reduced and converged to a predetermined fixed voltage. At this time, since the P-channel field effect transistor 21 is controlled to be in a non-conductive state, the P-channel field effect transistor 21 is not affected by the DC control voltage VCC of the DC control voltage source 30 and is not affected by the P-channel electric field as in the conventional example described above. Since there is no need to provide a current limiting N-channel field effect transistor that matches the size of the effect transistor 21, the design is easy, and even when the size of the IGBT is increased, it is not affected and the manufacturing cost is reduced. Can be reduced. That is, since it is not necessary to provide an N channel field effect transistor for current control, the chip size of the driver IC 20 can be reduced, and the manufacturing cost can be reduced.
The waveform of the gate voltage VG of the IGBT 11 during the short-circuit test in the first embodiment is as shown in FIG. 2, and the constant voltage at which the voltage of the gate voltage VG converges is 15V and 20V as the DC control voltage VCC. Even when the two types were applied, there was no change and the waveforms were substantially the same.

Next, a second embodiment of the present invention will be described with reference to FIG.
In the second embodiment, the influence of noise generated in the inverter circuit 1 in the first embodiment is not affected.
That is, in the second embodiment, as shown in FIG. 3, the second embodiment is the same as the above except that a noise removal circuit 55 is interposed between the comparator 52 and the flip-flop circuit 53 of the overcurrent state control unit 50. 1 has the same configuration as those of the first embodiment, and the same reference numerals are given to corresponding parts to those in FIG.
Here, the specific configuration of the noise removal circuit 55 includes a signal delay circuit 56 that delays the comparison signal Sc output from the comparator 52 and a comparison signal Sc output from the comparator 52 as shown in FIG. The NAND circuit 57 includes a NAND circuit 57 to which the delay comparison signal Sc ′ delayed by the signal delay circuit 56 is input, and an inverter 58 that inverts the output of the NAND circuit 57.

  Here, the signal delay circuit 56 includes a C-MOS 56a to which the comparison signal Sc output from the comparator 52 is input, a C-MOS 56b connected to the C-MOS 56a via a resistor R3, and resistors R3 and C. The capacitor C1 is interposed between the MOS 56b and the ground. A NAND circuit 57 to which the comparison signal Sc and the output of the C-MOS 56 b are input and an inverter 58 connected to the output side of the NAND circuit 57 are configured. Therefore, in the signal delay circuit 56, the input comparison signal Sc is delayed by a delay time (for example, several hundreds nsec) corresponding to a time constant determined by the resistance value of the resistor R3 and the capacitance of the capacitor C1. The NAND circuit 57 calculates the logical product of the delayed comparison signal Sc ′ delayed by the signal delay circuit 56 and the comparison signal Sc input from the comparator 52, thereby generating a high-frequency signal generated in the inverter circuit 1. Even if the noise component is transmitted to the comparator 52 via the current detection IGBT 17, the noise component can be removed.

  According to the second embodiment, when a high frequency noise component generated in the inverter circuit 1 is transmitted to the driver IC 20 via the current detection IGBT 17 and the current input terminal toc, the noise component is separated. Since it is included in the voltage value Vi of the voltage resistors R1 and R2 and is input to the comparator 52, the comparison signal Sc output from the comparator 52 includes a noise component. However, the comparison signal Sc including the noise component is supplied to the noise removal circuit 55, and the logical product of the delay comparison signal Sc ′ delayed by the signal delay circuit 56 for a predetermined time and the comparison signal Sc is calculated by the NAND circuit 57. Therefore, the comparison signal Sc from which the noise component has been removed can be supplied to the set terminal S of the flip-flop circuit 53. Therefore, it is possible to reliably prevent the noise component from affecting the overcurrent detection signal Soc output from the flip-flop circuit 53, and to reliably prevent malfunction due to the noise component.

  In the first and second embodiments, the case where the first reference voltage Vb1 supplied to the comparator 52 as the second reference voltage Vb2 is supplied to the operational amplifier 61 of the output voltage control unit 60 has been described. However, the present invention is not limited to this, and a DC voltage source that generates a second reference voltage Vb2 different from the DC voltage source 51 may be provided. Further, as shown in FIGS. 5 and 6 corresponding to the first and second embodiments, the connection point between the P-channel field effect transistor 21 and the N-channel field effect transistor 22 of the drive circuit 23 and the negative line N Is connected to the N-channel field effect transistor 22 in parallel with the voltage dividing resistors R4 and R5, and a voltage proportional to the gate voltage VG obtained from the connection point of the voltage dividing resistors R4 and R5 is inverted by the operational amplifier 61. You may make it input into an input terminal.

Moreover, in the said 1st and 2nd embodiment, although the case where the inverter circuit 1 was applied as a power converter device was demonstrated, it is not limited to this, This invention can be applied to a converter circuit. In short, the present invention can be applied when the switching element is controlled to be conductive or non-conductive by the drive circuit.
Further, in the first and second embodiments, the case where the IGBT is applied as the switching element has been described. However, the present invention is not limited to this, and other switching elements such as a power MOS can be applied. .

1 is a circuit diagram showing a first embodiment of the present invention. It is a characteristic diagram which shows the gate voltage waveform at the time of the short circuit test in 1st Embodiment. It is a circuit diagram which shows the 2nd Embodiment of this invention. It is a circuit diagram which shows the specific example of the noise removal circuit in 2nd Embodiment. It is a circuit diagram which shows the modification of the 1st Embodiment of this invention. It is a circuit diagram which shows the modification of the 2nd Embodiment of this invention. It is a circuit diagram which shows a prior art example. It is a characteristic diagram which shows the output terminal voltage vs. source current characteristic of a prior art example. It is a circuit diagram which shows the overcurrent test circuit of a prior art example. It is a characteristic diagram which shows the IGBT gate voltage waveform at the time of the short circuit which used the size of the field effect transistor as a parameter. It is a characteristic diagram which shows the IGBT gate voltage waveform at the time of the short circuit which used DC control voltage VCC as a parameter.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Inverter circuit SA1-SA3 ... Switching arm 11-16 ... IGBT
17 ... IGBT for current detection
20 ... Driver IC
DESCRIPTION OF SYMBOLS 21 ... P channel field effect transistor 22 ... N channel field effect transistor 23 ... Drive circuit 30 ... DC control voltage source 40 ... Current detection circuit 50 ... Overcurrent control part 51 ... First reference voltage source 52 ... Comparator 53 Flip-flop circuit 54 OR circuit 55 Noise removal circuit 56 Signal delay circuit 57 NAND circuit 58 Inverter 60 Output voltage controller 61 Operational amplifier

Claims (8)

A power conversion circuit that has a switching element and performs power conversion, and when the switching element of the power conversion circuit is in an operating state, a source current is supplied to a control terminal of the switching element, and the switching element is in a non-operating state A switching element drive circuit comprising a drive circuit for supplying a sink current to the control terminal,
A current detector that detects a current flowing through the switching element as a voltage value;
When the overcurrent state is detected by comparing the voltage value detected by the current detection unit with the first reference voltage, an overcurrent detection signal is output and the source current for the control terminal of the switching element of the drive circuit is An overcurrent state control unit for stopping supply;
When the voltage value detected by the current detection unit and the second reference voltage are input, the output is supplied to the output side of the drive circuit, and the overcurrent detection signal is output from the overcurrent state control unit And a drive voltage control unit that stabilizes the output voltage of the drive circuit in accordance with the second reference voltage when the operational amplifier enters the operation state. A switching element driving circuit.   The drive circuit is connected to a control power source to control the source current, and controls the sink current connected between the first switching element and the negative side of the DC power source. 2. A connection point between the first switching element and the second switching element is connected to a control terminal of the switching element of the power conversion circuit. The switching element driving circuit described.   The overcurrent state detection unit compares the voltage value detected by the current detection unit with the first reference voltage, and outputs a detection signal when the voltage value becomes equal to or higher than the first reference voltage. And a flip-flop circuit that is set by a detection signal output from the comparison circuit and outputs the overcurrent detection signal, a control signal is input to one input side, and the flip-flop circuit is input to the other input side. The switching element drive circuit according to claim 2, further comprising an OR circuit that receives an affirmative output of the circuit and further supplies an output to a control terminal of the first switching element.   4. The switching element drive circuit according to claim 3, wherein the overcurrent control unit includes a noise elimination circuit including a signal delay circuit between the comparison circuit and the flip-flop circuit.   The output voltage control unit controls the second reference voltage input to the operational amplifier and the voltage value detected by the current detection unit when the operational amplifier is in an operating state. The switching element driving circuit according to claim 1, wherein:   6. The switching element drive circuit according to claim 1, wherein the operational amplifier receives a first reference voltage of the overcurrent detection unit as the second reference voltage. 7. .   7. The operational amplifier receives a divided voltage of a voltage dividing resistor connected in parallel with a second switching element of the drive circuit as the second reference voltage. The switching element driving circuit according to any one of the above.   The switching element drive circuit according to any one of claims 1 to 7, wherein the switching element of the inverter circuit is an IGBT.

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