JP2010060655A - Plasma display panel drive circuit and plasma display device - Google Patents

Abstract

There is provided a PDP driving circuit capable of achieving both improvement of power efficiency by a recovery circuit and ensuring of steepness of a sustain pulse edge.
A discharge sustain pulse generator 29 for applying a voltage to a display electrode pair from a sustain voltage power supply Es via sustain switch elements Q1 and Q2 in order to cause a sustain discharge in the display cell, a recovery capacitor C1, and a recovery inductor L1 And a recovery circuit 33 having a recovery switch element Q3 for controlling the connection between the recovery capacitor and the display electrode pair. Furthermore, a power supply circuit 34 for adjusting the voltage charged in the recovery capacitor is provided. At the rise of the sustain pulse voltage for causing the sustain discharge, the recovery switch element is turned off and the sustain switch element is turned on, and the sustain pulse voltage is applied to the display electrode from the discharge sustain pulse generator, and the sustain pulse voltage rises. At the time of falling, the recovery switch element is turned on and the sustain switch element is turned off, and the charge accumulated in the display electrode is recovered by the recovery capacitor.
[Selection] Figure 1

Description

  The present invention relates to a plasma display panel drive circuit and a plasma display device used for a wall-mounted television or a large monitor.

  FIG. 16 shows an example of the configuration of an AC surface discharge type plasma display panel (hereinafter abbreviated as “PDP”) representative of the AC type. In FIG. 16, the front plate 1 has a configuration in which display electrode pairs 5 including scan electrodes 3 and sustain electrodes 4 that perform surface discharge are arranged in parallel on the surface of a front glass substrate 2. Scan electrode 3 and sustain electrode 4 are each composed of transparent electrodes 3a, 4a formed on the surface of front glass substrate 2, and bus electrodes 3b, 4b formed thereon. The bus electrodes 3b and 4b are made of, for example, silver (Ag) and a glass frit material as a binding material thereof. A front-side dielectric layer 6 is formed so as to cover the display electrode pair 5, and a protective film 7 is formed thereon.

  The back plate 8 is formed on the surface of the back glass substrate 9 by arranging the address electrodes 10 in parallel, and the top is covered with the back side dielectric layer 11. A partition wall 12 is formed on the back side dielectric layer 11. The barrier ribs 12 have a cross beam shape formed by vertical barrier ribs 12a formed extending in a direction parallel to the address electrodes 10 and horizontal barrier ribs 12b formed in a direction orthogonal thereto. A red (R) phosphor layer 13r, a green (G) phosphor layer 13g, and a blue (B) phosphor layer 13b corresponding to the address electrodes 10 are provided on the side surface of the partition wall 12 and the surface of the back side dielectric layer 11. (Also collectively referred to as “phosphor layer 13”) is formed by coating.

  The front plate 1 and the back plate 8 are arranged so that the display electrode pair 5 and the address electrode 10 face each other so as to form a matrix. A discharge space 14 is formed in the gap between the front plate 1 and the back plate 8. And the outer peripheral part of the front board 1 and the back board 8 is sealed by sealing materials, such as glass frit (not shown), and the discharge gas which consists of mixed gas of neon (Ne) and xenon (Xe) is enclosed. ing. For example, a discharge gas having a Xe ratio of 10% is used, and the discharge gas is sealed at a pressure of about 450 Torr (about 60 kPa). Discharge cells 15 defined by the barrier ribs 12 are formed in the discharge space 14 where the display electrode pair 5 and the address electrode 10 intersect three-dimensionally. A black matrix (light absorption layer) 16 corresponding to the horizontal partition wall 12b is formed between the display electrode pair 5 of the front plate 1.

  FIG. 17 is an electrode array diagram of the PDP. In the row direction, n scan electrodes SCN1 to SCNn (scan electrode 3 in FIG. 16) and n sustain electrodes SUS1 to SUSn (sustain electrode 4 in FIG. 16) are alternately arranged, and m address electrodes in the column direction. DA1 to DAm (address electrodes 10 in FIG. 16) are arranged. A discharge cell Cij (discharge cell 15 in FIG. 16) is formed at a portion where a pair of scan electrode SCNi and sustain electrode SUSi (i = 1 to n) intersects with one address electrode DAj (j = 1 to m). And (m × n) discharge cells 15 are formed. In the following description, all scan electrodes are denoted by SCN, all sustain electrodes are denoted by SUS, and all address electrodes are denoted by DA.

  In the PDP having such a configuration, color display is performed by generating ultraviolet rays by gas discharge and exciting the phosphor layers 13 of R, G, and B colors with the ultraviolet rays to emit light. In this PDP, one field period is divided into a plurality of subfields, and gradation display is performed by a combination of subfields that emit light. Each subfield has a predetermined luminance weight. Each subfield has an initialization period, an address period, and a sustain period. In order to display image data, different signal waveforms are applied to each electrode in the initialization period, the address period, and the sustain period.

  FIG. 18 is a block diagram showing a circuit configuration of a plasma display device incorporating the above-described PDP 20. The plasma display device shown in FIG. 18 includes an AD converter 21, a video signal processing unit 22, a subfield processing unit 23, an address electrode driving unit 24, a scan electrode driving unit 25, a sustain electrode driving unit 26, and a PDP 20. .

  The AD converter 21 converts the input analog video signal into a digital video signal. The video signal processing unit 22 displays the input digital video signal on the PDP 20 by combining a plurality of subfields having different light emission period weights, and controls each subfield from the video signal of one field. Convert to data. The subfield processing unit 23 generates an address electrode driving unit control signal, a scan electrode driving unit control signal, and a sustain electrode driving unit control signal from the subfield data created by the video signal processing unit 22, and generates an address electrode. The data is output to the drive unit 24, the scan electrode drive unit 25, and the sustain electrode drive unit 26, respectively.

  The address electrode driver 24 drives each of the address electrodes DAj independently. Scan electrode driver 25 drives each of scan electrodes SCNi independently. The sustain electrode driver 26 can drive all the sustain electrodes SUSi of the PDP 20 together.

  FIG. 19 shows a specific circuit configuration of a plasma display panel (PDP) driving circuit for applying the driving voltage as described above. FIG. 19 is a diagram showing an equivalent circuit of scan electrode drive unit 25 and sustain electrode drive unit 26 of the conventional PDP drive circuit. Here, the equivalent circuit of the PDP 20 is represented only by the stray capacitance Cp (hereinafter referred to as the panel capacitance of the PDP 20) between the sustain electrode SUS and the scan electrode SCN, and the path of the current flowing through the PDP 20 during discharge in the discharge cell is omitted. Is done.

FIG. 20 shows drive voltage waveforms applied to the electrodes of the PDP 20 during the initialization period, address period, and sustain period of each subfield. In each subfield, almost the same operation is performed except that the number of sustain pulses in the sustain period is different in order to change the weight of the light emission period, and the operation principle in each subfield is also substantially the same. The operation will be described only for the field. FIG. 20 also shows control waveforms of the switches of the PDP drive circuit of FIG. Operations in the initialization period, the address period, and the discharge sustain period in the PDP driving circuit will be described with reference to FIGS.

  During the initialization period, in the scan electrode driver 25, the scan pulse generator 27 maintains the low-side scan switch element S2 in the ON state. The initialization pulse generator 28 applies an initialization pulse voltage to the scan electrode SCN through the low-side scan switch element S2. At the same time, in the sustain electrode driver 26, the second sustaining pulse generator 31 applies the initialization pulse voltage to the sustain electrode SUS. As a result, the potential of scan electrode SCN and sustain electrode SUS changes. On the other hand, the address electrode DA is maintained at the ground potential (≈0).

  According to the change of the initialization pulse voltage, the initialization period is divided into six modes I to VI as shown in FIG.

<Mode I>
In the scan electrode driving unit 25, the low side sustain switch element Q2, the separation switch elements QS1 and QS, and the low side scan switch element S2 are maintained in the ON state. In sustain electrode driver 26, low side sustain switch element Q2X is maintained in the ON state. The remaining switch elements are kept off. Thereby, both scan electrode SCN and sustain electrode SUS are maintained at the ground potential.

<Mode II>
In scan electrode driver 25, low-side sustain switch element Q2 is turned off and high-side sustain switch element Q1 is turned on. As a result, the potential of the scan electrode SCN rises to the potential Vs of the external power supply Es. In the sustain electrode driver 26, the on / off states of all the switch elements are maintained as they are. Thereby, sustain electrode SUS is maintained at the ground potential.

<Mode III>
In the scan electrode driving unit 25, the separation switch element QS is turned off, and the high side ramp waveform generating unit QR1 is turned on. Thereby, the potential of the scan electrode SCN rises from the potential Vs of the external power supply Es to the upper limit Vr of the initialization pulse voltage at a constant speed. In the sustain electrode driver 26, the on / off states of all the switch elements are maintained as they are. Thereby, sustain electrode SUS is maintained at the ground potential. Thus, the voltage applied to all the discharge cells of the PDP 20 increases uniformly to the upper limit Vr of the initialization pulse voltage. Thereby, uniform wall charges are accumulated in all the discharge cells of the PDP 20.

<Mode IV>
In scan electrode driver 25, high-side ramp waveform generator QR1 is turned off, and separation switch element QS is turned on. As a result, the potential of the scan electrode SCN drops to the potential Vs of the external power supply Es. In the sustain electrode driver 26, the on / off states of all the switch elements are maintained as they are. Thereby, sustain electrode SUS is maintained at the ground potential.

<Mode V>
In the scan electrode driver 25, the on / off states of all the switch elements are maintained as they are. Thereby, scan electrode SCN is maintained at potential Vs of external power supply Es. In sustain electrode driver 26, low side sustain switch element Q2X is turned off and high side sustain switch element Q1X is turned on. As a result, the potential of the sustain electrode SUS rises to the potential Vs of the external power supply Es.

<Mode VI>
In the scan electrode driver 25, the high-side sustain switch element Q1 and the separation switch element QS1 are turned off, and the low-side ramp waveform generator QR2 is turned on. As a result, the potential of the scan electrode SCN drops at a constant speed to the potential of the external negative voltage source En (voltage: −Vn <0). In the sustain electrode driver 26, the on / off states of all the switch elements are maintained as they are. Thereby, sustain electrode SUSi is maintained at potential Vs of external power supply Es. Therefore, a voltage having a polarity opposite to that applied in modes II to V is applied to the discharge cell of PDP 20. As a result, the wall charges are uniformly removed and made uniform in all the discharge cells.

  Next, the operation during the address period will be described. During the address period, in the sustain electrode driver 26, the high side sustain switch element Q1X is maintained in the ON state. The remaining switch elements are kept off. Thereby, sustain electrode SUS is maintained at potential Vs of external power supply Es. In the scan electrode driver 25, the low-side sustain switch element Q2, the low-side ramp waveform generator QR2, and the separation switch element QS are maintained in the ON state. Accordingly, one end of the series connection of the scan switch elements S1 and S2 is maintained at a potential Vp = V1-Vn (hereinafter referred to as an upper limit of the scan pulse voltage) higher than −Vn by the voltage V1 of the first constant voltage source E1. The end is maintained at -Vn.

  At the start of the address period, for all the scan electrodes SCN, the high side scan switch element S1 is maintained in the on state and the low side scan switch element S2 is maintained in the off state. Thereby, the potentials of all the scan electrodes SCN are uniformly maintained at the upper limit Vp of the scan pulse voltage.

  Subsequently, the scan electrode driver 25 changes the potential of the scan electrode SCNi as follows (see the scan pulse voltage SP shown in FIG. 20). When one of the scan electrodes SCNi is selected, the high side scan switch element S1 connected to the scan electrode SCNi is turned off and the low side scan switch element S2 is turned on. As a result, the potential of the scan electrode SCNi drops to the potential of −Vn. After the scan electrode SCNi is maintained at a potential of −Vn for a predetermined time, the low side scan switch element S2 connected to the scan electrode SCNi is turned off and the high side scan switch element S1 is turned on. As a result, the potential of the scan electrode SCNi rises to the upper limit Vp of the scan pulse voltage.

  In the scan electrode driver 25, the scan switch elements S1 and S2 connected to the scan electrodes sequentially perform the same switching operation as described above. Thus, the scan pulse voltage SP is sequentially applied to each scan electrode.

  During the address period, one of the address electrodes DAj is selected based on an externally input video signal, and the potential of the selected address electrode DAj rises to the upper limit Va of the signal pulse voltage for a predetermined time. For example, as shown in FIG. 20, when the scan pulse voltage SP is applied to one of the scan electrodes SCNi and the signal pulse voltage Va is applied to one of the address electrodes DAj, the scan electrode SCNi and the address electrode DAj Is higher than the voltage between the other electrodes. Therefore, discharge occurs in the discharge cell located at the intersection between the scan electrode SCNi and the address electrode DAj. Due to the discharge, new wall charges are accumulated on the surface of the discharge cell.

  Next, the operation during the discharge sustain period will be described. During the discharge sustain period, in the scan electrode driver 25, the scan pulse generator 27 maintains the low-side scan switch element S2 in the on state and maintains the separation switch elements QS1 and QS in the on state. The first sustaining pulse generator 29 turns on the two sustain switching elements Q1 and Q2 alternately. As a result, the potential of the scan electrode SCN is switched between the potential Vs of the external power supply Es and the ground potential. That is, the sustaining voltage pulse is applied to the scan electrode SCN through the separation switch elements QS1 and QS and the low-side scan switch element S2.

  At the same time, in the sustain electrode driver 26, the second sustaining pulse generator 31 turns on the two sustain switch elements Q1X and Q2X alternately. As a result, the potential of the scan electrode SCN is switched between the potential Vs of the external power supply Es and the ground potential. That is, the sustaining voltage pulse is applied to the sustaining electrode SUS.

  Since the two discharge sustain pulse generators 29 and 31 operate in opposite phases, the discharge sustain pulse voltage is alternately applied to the scan electrode SCN and the sustain electrode SUS. Thereby, in each discharge cell of PDP 20, an AC voltage is generated between scan electrode SCN and sustain electrode SUS. At that time, since discharge is maintained in the discharge cell in which wall charges are accumulated during the address period, light emission occurs.

  Each of the two recovery circuits 30 and 32 includes an inductor and a recovery capacitor (not shown). In the first recovery circuit 30, when the potential of the scan electrode SCN goes up and down, the inductor resonates with the panel capacitance Cp of the PDP 20. Similarly, in the second recovery circuit 32, when the potential of the sustain electrode SUS goes up and down, The inductor resonates with the panel capacitance Cp. In this manner, during the sustain period, the scan electrode SCN and the sustain electrode SUS are driven by LC resonance, so that the sustain switch elements Q1 and Q2 and the sustain switch elements Q1X and Q2X are turned on and off to fill the panel capacity of the PDP 20. Compared to the case of discharging, the effective value of the current flowing to the PDP 20 and the current flowing from the PDP 20 can be reduced.

As described above, by reducing the charge / discharge current due to the rise and fall of the panel voltage by the recovery circuit, loss can be reduced and power efficiency can be improved. (For example, see Patent Document 1)
Moreover, in the technique described in Patent Document 1, control is performed so as to generate a discharge during the collection operation in order to increase the light emission efficiency. That is, when the recovery circuit is operated and a current is supplied to the PDP by LC resonance, a discharge is generated. Since the LC resonance operation is being performed, the first inductor L1 acts to limit the discharge current. Therefore, the discharge becomes longer in time, and as a result, a plasma display device with high luminous efficiency and stable discharge can be obtained.
JP 2002-215084 A

  In recent years, PDPs with high luminous efficiency have been demanded from the viewpoint of promoting energy saving and reducing power consumption. For this purpose, PDPs with different discharge cell structures and discharge gas components have been developed. In the case of such a PDP that is different from the conventional one, there are cases where the conventional voltage and current supply methods cannot sufficiently exhibit the performance of the PDP, and as a result, the luminous efficiency is low.

  For example, in the case of a PDP in which the luminous efficiency is increased by increasing the xenon partial pressure in the discharge gas, the emission time tends to be shorter than that of a PDP having a low xenon partial pressure. In this case, if the discharge current is limited, the current required for light emission is insufficient. Therefore, in the case of such a PDP, the light emission efficiency of the PDP is not increased as a result of the approach as in Patent Document 1.

  In the PDP having the above-described configuration, it is known that the emission luminance increases as the sustain pulse voltage increases. However, in the configuration of the conventional example, since the sustain pulse voltage is raised using the recovery circuit, the rise of the sustain pulse voltage becomes gentle and the steepness of the leading edge of the pulse is impaired. That is, when the sustain pulse voltage is raised using the recovery circuit, a voltage is applied to the panel capacitance using LC resonance, so that the waveform applied to the panel capacitance shows a sine waveform when rising and falling. Therefore, the slope of the waveform applied to the panel capacitance decreases immediately before reaching the sustain pulse voltage value. As described above, the rise is gentle immediately before the sustain pulse voltage value is reached, and the discharge occurs before the discharge reaches the sustain pulse voltage. Therefore, it is difficult to increase the sustain pulse voltage.

  Further, since there is a circuit resistance loss in a general recovery circuit, it is actually impossible to recover 100% of the charge and reach the sustain pulse voltage value using the recovery circuit.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a plasma display panel driving circuit capable of achieving both improvement in power efficiency by using a recovery circuit and a high sustain pulse voltage during discharge.

  The plasma display panel driving circuit according to the present invention has a basic configuration in which a voltage is applied to each electrode of a plasma display panel having a plurality of display electrode pairs including scan electrodes and sustain electrodes, and address electrodes orthogonal to the display electrode pairs. The display electrode is configured to be applied and discharged in a display cell formed by the display electrode pair and the address electrode, and in order to cause a sustain discharge in the display cell, the display electrode is supplied from a sustain voltage power source via a sustain switch element. A sustaining pulse generator for applying a voltage to the pair, a recovery capacitor, a recovery inductor connected between the recovery capacitor and the display electrode pair, and a recovery for controlling the connection between the recovery capacitor and the display electrode pair A recovery circuit having a switch element.

  In order to solve the above-mentioned problem, in the plasma display panel driving circuit of the first configuration, the recovery circuit further includes a power supply circuit that adjusts a voltage charged in the recovery capacitor, and for causing the sustain discharge At the rise of the sustain pulse voltage, the recovery switch element is turned off, the sustain switch element is turned on, and the sustain pulse voltage is applied to the display electrode from the discharge sustain pulse generator, and the sustain pulse voltage rises. At the time of lowering, the recovery switch element is turned on, the sustain switch element is turned off, and control is performed so that the charge accumulated in the display electrode is recovered by the recovery capacitor.

  In the plasma display panel drive circuit of the second configuration, the recovery circuit further includes a power supply circuit that charges the recovery capacitor to a predetermined voltage, and when the sustain pulse voltage for causing the sustain discharge falls, the recovery circuit The switch element is turned off, the sustain switch element is turned on, and the sustain pulse voltage is applied to the display electrode from the discharge sustain pulse generator, and when the sustain pulse voltage rises, the recovery switch element is turned on, Control is performed such that the sustain switch element is turned off and the charge accumulated in the recovery capacitor is supplied to the display electrode.

  According to the first configuration, when only the sustain pulse voltage rises, only the discharge sustain pulse generator is operated to apply a steep rise pulse voltage to obtain high-luminance light emission. By making the recovery circuit function at the time of falling, power efficiency can be improved. In addition, an efficient recovery operation can be performed by reducing the voltage of the recovery capacitor by supplying the voltage charged in the recovery capacitor from the power supply circuit to other elements.

  Further, according to the second configuration, when the sustain pulse voltage rises, the voltage is supplied from the recovery circuit, thereby suppressing the loss and increasing the sustain pulse voltage to a predetermined voltage. When the sustain pulse voltage falls, By operating only the discharge sustain pulse generator, the sustain pulse falls steeply and high-luminance light emission is obtained.

  The PDP drive circuit of the present invention can take the following aspects based on the above configuration.

  That is, in the PDP driving circuit having the first configuration, when the voltage Va supplied from the voltage of the recovery capacitor through the power supply circuit has a relationship of Va> Vc with respect to the set voltage Vc of the recovery capacitor. The power supply circuit is constituted by a booster circuit, and when the relationship Va <Vc is satisfied, the power supply circuit can be constituted by a step-down circuit.

  In the PDP driving circuit having the second configuration, when the voltage Va supplied to the recovery capacitor via the power supply circuit is in a relationship of Va> Vc with respect to the set voltage Vc of the recovery capacitor, The power supply circuit is composed of a step-down circuit, and when the relationship Va <Vc is satisfied, the power supply circuit can be composed of a step-up circuit.

  In the PDP drive circuit having the first configuration, it is preferable that the set voltage Vc of the recovery capacitor is set to a relationship of Vc <Vsus / 2 with respect to the voltage value Vsus of the sustain voltage power supply.

  In the PDP drive circuit of the second configuration, it is preferable that the set voltage Vc of the recovery capacitor is set to a relationship of Vc> Vsus / 2 with respect to the voltage value Vsus of the sustain voltage power supply.

  The PDP drive circuit having the first or second configuration includes a voltage detection circuit that detects a voltage of the recovery capacitor, and a detection value by the voltage detection circuit is within a predetermined range with respect to a set voltage Vc of the recovery capacitor. In some cases, it is preferable to control the power supply circuit not to operate.

  The PDP driving circuit of the first configuration further includes an auxiliary power supply circuit connected to the recovery capacitor and receiving the supply of the voltage Vb from a constant voltage source, and the auxiliary power supply circuit includes the recovery capacitor when the plasma display panel is activated. However, it is preferable to perform control so as to perform charging for setting voltage Vc.

  In this case, the voltage Va supplied by the power supply circuit and the voltage Vb supplied by the auxiliary power supply circuit are the same, and the power supply circuit and the auxiliary power supply circuit are a power supply circuit combining a booster circuit and a step-down circuit. Configured so that when the plasma display panel is started, either the booster circuit or the step-down circuit is operated to charge the recovery capacitor, and when the plasma display panel is not started, the other is operated to supply power to the voltage Va. It can be set as the structure driven.

  In the PDP drive circuit of the first or second configuration, a drive circuit for driving the sustain switch element on the high side or the low side of the discharge sustain pulse generator is a short cycle drive circuit and a long cycle drive. A time for which the sustain switch element is turned on by the long-cycle driving circuit is set to be longer than a time for which the sustain switch element is turned on by the short-cycle driving circuit. It is preferable that the short cycle driving circuit and the long cycle driving circuit are switched and used based on the image data displayed by the above.

  The plasma display apparatus of the present invention has a display electrode pair composed of a scan electrode and a sustain electrode, and an address electrode orthogonal to the display electrode pair, and a display cell is formed at each intersection of the display electrode pair and the address electrode. And a plasma display panel driving circuit having any one of the above-described structures for driving the plasma display panel.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a circuit diagram showing the configuration of the recovery circuit 33 of the scan electrode driving unit, which is a main part of the PDP driving circuit in Embodiment 1, together with the sustaining pulse generating unit 29. Since the recovery circuit of the sustain electrode driver is configured in the same manner as the recovery circuit 33, the illustration is omitted. In the present embodiment, the configuration is the same as that shown in FIG. 20 except for the recovery circuit 33, and the same elements are denoted by the same reference numerals and the description thereof will not be repeated.

  The recovery circuit 33 includes an inductor L1, a recovery capacitor C1, a recovery switch element Q3, and a diode D1. Further, the recovery circuit 33 is provided with a power supply circuit 34 connected to the recovery capacitor C1. The power supply circuit 34 is configured to adjust the voltage charged in the recovery capacitor C1 and supply the constant voltage Va to other elements constituting the drive circuit.

  The operation of the PDP drive circuit including the recovery circuit 33 will be described with reference to FIGS. FIG. 2 shows waveforms of sustain pulses applied to the scan electrodes and the sustain electrodes (represented as SCN and SUS, respectively) during the sustain period of the circuit having the above configuration. According to the voltage waveform shown in FIG. 2, both the sustain pulse waveforms SCN and SUS generate a discharge immediately after the steep leading edge portion at the rising edge. In order to make the rise of the sustain pulse steep in this way, the high-side sustain switch element Q1 is turned on and the sustain voltage Vsus is supplied from the voltage source Es to the scan electrode without using the recovery circuit 33 at the time of rise. At the falling portion, the recovery circuit 33 is operated to recover the charge of the display electrode to the recovery capacitor C1, so that the voltage gradually drops at the trailing edge.

  FIG. 3 shows the voltage waveform SCN applied to the scan electrode and the on / off timing of each of the switch elements Q1, Q2, Q3 of the discharge sustain pulse generating unit 29 and the recovery circuit 33 in this operation. Regarding the state of each switch element, the shaded portion may be on, the portion marked with x may be either on or off, and the portion without a mark indicates off.

  In the period I, the high-side sustain switch element Q1 is turned on, and the recovery switch element Q3 and the low-side sustain switch element Q2 are turned off. By turning on the high-side sustain switch element Q1, the sustain voltage Vsus is supplied from the voltage source Es to the scan electrode SCNi, a steep rise is formed, and a discharge is generated.

  In period II, the high-side sustain switch element Q1 is turned off and the recovery switch element Q3 is turned on. By turning on the recovery switch element Q3, an LC resonance circuit is formed by the panel capacitance of the PDP and the inductor L1. Thereby, the voltage of scan electrode SCNi falls. Since the recovery diode D2 is connected in series, the direction of the current is reversed, and at the same time, the diode D2 blocks the reverse current, and the resonance operation stops.

  In the period III, the low-side sustain switch element Q2 is turned on. The recovery switch element Q3 may be either on or off. During this period, the same operation as in periods I and II is performed on the sustain electrode SUSi by the discharge sustain pulse generator 31 and the recovery circuit on the sustain electrode driver 26 side. Therefore, the voltage on the sustain electrode side rises and is clamped at the sustain voltage, and after the discharge current flows from the sustain electrode side to the scan electrode side, the voltage drops to near the ground potential.

  As described above, when the sustain pulse voltage rises, the recovery switch element Q3 is turned off, the high side sustain switch element Q1 of the discharge sustain pulse generator 29 is turned on, and the discharge sustain pulse generator 29 applies to the display electrode. It operates so that discharge power is supplied. Since the recovery circuit 33 does not operate, the rise of the sustain pulse is steep, and a sufficiently high sustain pulse voltage is applied when a discharge occurs, so that high brightness can be obtained. On the other hand, when the sustain pulse voltage falls, the recovery switch element Q3 is turned on, the high side sustain switch element Q1 of the discharge sustain pulse generator 29 is turned off, and the charge accumulated in the display electrode is recovered by the recovery capacitor C1. .

  Next, the operation of the power supply circuit 34 will be described. The reason why the power supply circuit 34 adjusts the voltage charged in the recovery capacitor C1 to supply power to other elements constituting the drive circuit is as follows.

  That is, in the recovery circuit 33, the recovery capacitor C1 settles to about half of the sustain voltage Vsus by the coexistence of the discharge at the rising edge of the sustain pulse and the charging operation at the falling edge. On the other hand, when the discharge from the recovery circuit 33 at the rising edge is removed as in the present embodiment, only the charging at the falling edge is obtained. All of the charge stored in the panel capacity of the PDP is stored in the recovery capacitor C1, but since there is no recovery switch element for discharging at the rising edge, the charge stored in the recovery capacitor C1 is not used. If the recovery capacitor C1 becomes one side that stores electric charge, the voltage of the recovery capacitor C1 exceeds half of the sustain voltage Vsus.

  In the recovery circuit 33, the recovery operation is performed by the resonance phenomenon using the potential difference between the recovery capacitor C1 and the PDP. However, when the voltage of the recovery capacitor C1 rises and the potential difference from the voltage of the PDP disappears, the recovery operation is performed. It becomes impossible. Thus, only the charging switch element does not operate efficiently as a recovery circuit. Therefore, a power supply circuit 34 is provided to control the voltage of the recovery capacitor C1, thereby enabling the recovery operation.

  The power supply circuit 34 is configured as follows according to the relationship between the voltage Va supplied as a constant voltage source and the set voltage Vc of the recovery capacitor. That is, when Va> Vc, the power supply circuit is a booster circuit (switching regulator). In this case, the constant voltage source is supplied to, for example, a sustain voltage source. When Va <Vc, the power supply circuit is a step-down circuit (switching regulator / linear regulator). In this case, the constant voltage source is supplied to, for example, an address voltage source. The supply destination of the constant voltage source needs to have a certain amount of power consumption. This is because the charge of the recovery capacitor C1 is moved by the power supply circuit 34, and if more charge moves than the consumption amount, stabilization of the voltage, which is the original purpose of the constant voltage source, is hindered. is there.

  As described above, the discharge is performed after the sustain pulse rises, and instead of the configuration in which the recovery is performed at the falling portion not involved in the discharge, the sustain discharge may be performed with the following sustain pulse, With a steep pulse voltage, it is possible to achieve both high-luminance light emission and improved power efficiency. FIG. 4 shows the configuration of the recovery circuit 35 in this case, together with the discharge sustain pulse generator 29. In the recovery circuit 35, the high-side recovery switch element Q4 and the diode D2 are connected to the inductor L1 and the recovery capacitor C1, and the voltage Va from the constant voltage source is supplied to the power supply circuit 34. The supply point is different from the recovery circuit 33 shown in FIG.

  FIG. 5 shows waveforms of sustain pulses applied to the scan electrodes and the sustain electrodes during the sustain period of the recovery circuit 35 (referred to as SCN and SUS, respectively). In the voltage waveform shown in FIG. 5, in both the sustain pulse waveforms SCN and SUS, when the sustain pulse rises, the voltage gradually rises due to voltage application from the recovery circuit 35. After the voltage applied to one electrode rises to Vsus, the trailing edge portion of the voltage applied to the other electrode falls sharply. Discharge occurs immediately after the steep trailing edge. In order to make the sustain pulse fall steep in this way, the low-side sustain switch element Q2 is turned on and the scan electrode is connected to the ground potential without using the recovery circuit 35.

  FIG. 6 shows the voltage waveform SCN applied to the scan electrodes and the on / off timings of the switch elements Q1, Q2, Q4 of the discharge sustain pulse generating unit 29 and the recovery circuit 35 in this operation. In the period I, the recovery switch element Q4 is turned on and the sustain switch elements Q1 and Q2 are turned off. By turning on the recovery switch element Q4, an LC resonance circuit is formed by the panel capacitance of the PDP and the inductor L1. Thereby, a voltage is applied from the recovery capacitor C1 to the PDP, and the voltage of the scan electrode SCNi gradually rises.

  In the period II, the high-side sustain switch element Q1 is turned on. The recovery switch element Q4 may be either on or off. By turning on the high side sustain switch element Q1, the scan electrode is clamped to the sustain voltage Vsus. In the period III, the low-side sustain switch element Q2 is turned on, and the recovery switch element Q4 and the high-side sustain switch element Q1 are turned off. By turning on the low side sustain switch element Q2, the scan electrode is connected to the ground potential, and the SCN falls sharply. In the period IV, the low-side sustain switch element Q2 is kept on and the scan electrode is clamped at the ground potential.

  As shown in FIG. 5, in the period II, the discharge sustain pulse generator 31 (see FIG. 20) on the sustain electrode driver 26 side and the recovery circuit perform the periods III, IV, and I for the sustain electrode. A similar operation is performed. In a state where the scan electrode is clamped to the sustain voltage Vsus, the sustain electrode voltage SUS falls sharply, whereby the sustain voltage Vsus is applied between the scan electrode and the sustain electrode, and a discharge is generated. A discharge current flows through the sustain electrode.

  As described above, when the sustain pulse voltage rises, the recovery switch element Q4 is turned on, the sustain switch elements Q1 and Q2 of the discharge sustain pulse generator 29 are off, and the voltage is supplied from the recovery capacitor C1 to the display electrode. By applying the sustain pulse voltage via the resonance circuit, the effective value of the current flowing through the panel is reduced, and the sustain pulse voltage is increased with less loss. On the other hand, when the sustain pulse voltage falls, the recovery switch element Q4 is turned off and the low-side sustain switch element Q2 of the discharge sustain pulse generator 29 is turned on to bring the scan electrode to the ground potential. Therefore, since the recovery circuit 35 does not operate, the sustain pulse falls steeply, and a high sustain pulse voltage is applied between the display electrodes to obtain high luminance.

  The power supply circuit 34 is configured as follows according to the relationship between the voltage Va that supplies a voltage to the recovery capacitor as a constant voltage source and the set voltage Vc of the recovery capacitor. That is, when Va> Vc, the power supply circuit is a step-down circuit (switching regulator / linear regulator). In this case, the constant voltage source is supplied to, for example, a sustain voltage source. When Va <Vc, the power supply circuit is a booster circuit (switching regulator). In this case, the constant voltage source is supplied to, for example, an address voltage source.

  Next, regarding the set voltage Vc of the recovery capacitor C1, it is desirable to consider the following. That is, at the normal recovery capacitor setting voltage Vsus / 2, there is a resistance loss of the circuit, etc., and therefore using the recovery circuit, the sustain pulse voltage can be reduced to GND or the pulse voltage can be increased to Vsus. Can not.

  Therefore, when the recovery circuit 33 is used at the time of falling as in the configuration of FIG. 1, the voltage Vc of the recovery capacitor C1 is made smaller than Vsus / 2. As a result, the recovery pulse 33 can be used to reduce the sustain pulse voltage to GND. Further, when the recovery circuit 35 is used at the time of rising as in the configuration of FIG. 4, the voltage Vc of the recovery capacitor C1 is made larger than Vsus / 2. Thereby, the sustain pulse voltage can be increased to Vsus using the recovery circuit 35. By setting in this way, recovery efficiency can be increased.

  Next, a specific configuration example of the power supply circuit 34 constituting the recovery circuit 33 or the recovery circuit 35 in the case of FIG. 1 will be described.

  The power supply circuit 34a shown in FIG. 7 is a booster circuit, and is configured by a switching regulator. It is connected to a constant voltage source (a constant voltage source is a constant voltage Va) through a series circuit of an inductor L2 and a diode D3 connected to the positive terminal of the recovery capacitor C1. A transistor Tr1 is connected between the inductor L2 and the diode D3 and between the ground potential, and a control circuit 36a is connected to the base thereof. The control circuit 36a is also connected to the positive terminal of the recovery capacitor C1, and detects the voltage of the recovery capacitor C1. Based on the detected voltage, the switching of the transistor Tr1 is controlled so that the voltage of the recovery capacitor C1 becomes the set voltage Vc.

  The power supply circuit 34b shown in FIG. 8 is a step-down circuit and is constituted by a linear regulator. It is connected to a constant voltage source via a transistor Tr2 connected to the positive terminal of the recovery capacitor C1. A control circuit 36b is connected to the base of the transistor Tr2. The control circuit 36b is also connected to the positive terminal of the recovery capacitor C1, and detects the voltage of the recovery capacitor C1. Based on the detected voltage, the transistor Tr2 is controlled by analog control so that the voltage of the recovery capacitor C1 becomes the set voltage Vc.

  The power supply circuit 34c shown in FIG. 9 is a step-down circuit, and is configured by a switching regulator. It is connected to a constant voltage source through a series circuit of a transistor Tr3 and an inductor L3 connected to the positive terminal of the recovery capacitor C1. A diode D4 is connected between the transistor Tr3 and the inductor L3 and between the ground potential. A control circuit 36c is connected to the base of the transistor Tr3. The control circuit 36c is also connected to the positive terminal of the recovery capacitor C1, and detects the voltage of the recovery capacitor C1. Based on the detected voltage, the switching of the transistor Tr3 is controlled so that the voltage of the recovery capacitor C1 becomes the set voltage Vc.

(Embodiment 2)
FIG. 10A is a circuit diagram showing a main part of the PDP drive circuit in the second exemplary embodiment. The PDP drive circuit of the present embodiment includes any of the power supply circuits 34a, 34b, and 34c shown in FIGS. 7, 8, and 9 mounted on the recovery circuit of FIG. The circuit in FIG. 10A is a voltage detection circuit for detecting the voltage Vz of the recovery capacitor C1, which is a part of the control circuits 36a, 36b, and 36c included in the power supply circuits 34a, 34b, and 34c.

  This voltage detection circuit is constituted by a hysteresis comparator, and resistors R1 and R2 for dividing the voltage Vz of the recovery capacitor C1, a resistor R3 for inputting the divided voltage to the operational amplifier 37, and a feedback resistor R4. And a reference voltage Vref. The operational amplifier 37 compares the voltage Vz divided by the resistors R1 and R2 with the reference voltage Vref, and outputs a binary output OUT according to the result, for example, by the power supply circuit 34a. A boosting operation is performed.

  The output OUT from the operational amplifier 37 is set as shown in FIG. 10B by appropriately selecting the values of Vref and resistors R1 to R4. In the case of the drive circuit of FIG. 1, if the power supply circuit is not operated, the charge of the PDP is accumulated in the recovery capacitor, so that the voltage Vz of the recovery capacitor increases. When the output OUT is 0, the power supply circuit is stopped, and when the voltage Vz of the recovery capacitor C1 rises and the voltage Vz becomes Vc + α, the output OUT is inverted to 1 to put the power supply circuit into an operating state.

  On the other hand, in the case of the drive circuit of FIG. 4, if the power supply circuit is not operated, a voltage is applied to the PDP, so the voltage Vz of the recovery capacitor drops. When the output OUT is 1, the power supply circuit is stopped, and when the voltage Vz drops and the capacitor voltage Vz becomes lower than Vc, the output OUT is inverted to 0 and the power supply circuit is put into an operating state.

  As described above, in the case of the drive circuit as shown in FIG. 1, the power supply circuit is controlled not to operate in a range where the capacitor voltage Vz does not reach Vc + α. The reason for such control is to operate the power supply circuit only during the discharge sustain period. In the case of a PDP, there are an initialization period, an address period, and a discharge sustaining period. During the discharge sustaining period, the recovery circuit is used to recover the panel voltage, but the recovery circuit basically does not operate during other periods. . Therefore, the voltage of the recovery capacitor C1 does not change, and it is not necessary to operate the power supply circuits 34a, 34b, and 34c. This concept can also be applied to the drive circuit having the configuration shown in FIG.

  As described above, according to the configuration of the present embodiment, since it is not necessary to always operate the power supply circuit, the power used for the operation of the power supply circuit can be reduced, and the power consumption can be suppressed.

(Embodiment 3)
FIG. 11 is a circuit diagram showing a main part of the PDP drive circuit according to the third embodiment. The PDP drive circuit of the present embodiment is obtained by changing the recovery circuit 33 shown in FIG. 1, for example. That is, in addition to the power supply circuit 34, an auxiliary power supply circuit 38 is connected to the recovery capacitor C1. The function of the auxiliary power circuit 38 is as follows.

  Since the voltage of the recovery capacitor C1 is 0 V when the PDP is activated, the recovery efficiency is deteriorated for a while after the activation. Therefore, an auxiliary power supply circuit 38 for setting the recovery capacitor C1 to the set voltage Vc at the time of startup is provided. Since the auxiliary power supply circuit 38 operates by receiving supply of the voltage Vb from another constant voltage source, the type of the auxiliary power supply circuit 38 is determined by the relationship between the voltage Vb of the constant voltage source and the set voltage Vc.

  In the case of Vb> Vc, the auxiliary power supply circuit 38 uses a step-down circuit such as a switching regulator or a linear regulator as described above. Such a voltage source of the voltage Vb is, for example, a sustain voltage source.

  When Vb <Vc, the auxiliary power supply circuit 38 uses a booster circuit such as the switching regulator as described above. Such a voltage source of the voltage Vb is, for example, a write voltage source.

  When Va = Vb, that is, when the voltage Va of the constant voltage source to which the power supply circuit 34 supplies the voltage and the voltage Vb of the constant voltage source to which the auxiliary power supply circuit 38 is supplied with the voltage are the same, As described above, the power supply circuit 34 and the auxiliary power supply circuit 38 can be integrated using a bidirectional converter in which a booster circuit and a step-down circuit are combined.

  FIG. 12A shows a configuration example of a bidirectional converter when Va = Vb> Vc. This circuit is connected between a series circuit of a Pch transistor Tr4 and an inductor L4 connected between a constant voltage source (voltage Va) and a recovery capacitor C1, and a connection node between the Pch transistor Tr4 and the inductor L4 and a ground potential. Nch transistor Tr5. The control circuit 39 controls the switching operation of both transistors based on the detected value of the voltage of the recovery capacitor C1 and the start signal. The operation is shown in FIG. 12B.

  A case where a start signal is supplied at the time of start is indicated by 1, and a case where a start signal is not supplied is indicated by 0. At the time of start-up, the transistor Tr4 is switched and the transistor Tr5 is always OFF, and operates as a step-down circuit via the body diode or parallel diode of the transistor Tr5 to charge the recovery capacitor C1.

  The transistor Tr4 is always OFF, the transistor Tr5 is switched, and operates as a booster circuit through the body diode or parallel diode of the transistor Tr4 except for the start-up, and power is supplied from the recovery capacitor C1 to the constant voltage source. Is called.

  FIG. 13A shows a configuration example of a bidirectional converter when Va = Vb <Vc. In this circuit, a series circuit of an inductor L5 and a Pch transistor Tr6 connected between a constant voltage source (voltage Va) and a recovery capacitor C1, and a connection node between the inductor L5 and the Pch transistor Tr6 and a ground potential are connected. Nch transistor Tr7. The control circuit 40 controls the switching operation of both transistors based on the detected value of the voltage of the recovery capacitor C1 and the start signal. The operation is shown in FIG. 13B.

  At start-up, the transistor Tr7 switches and the transistor Tr6 is always OFF, and operates as a booster circuit via the body diode or parallel diode of the transistor Tr6 to charge the recovery capacitor C1.

  The transistor Tr7 is always OFF and the transistor Tr6 is switched except when starting up, and operates as a step-down circuit via the body diode or parallel diode of the transistor Tr7, and power is supplied from the recovery capacitor C1 to the constant voltage source. Is called.

  Note that, instead of the above configuration, a synchronous rectification operation is performed, and at the time of start-up, one transistor is switched and the other transistor is switched so as to perform a synchronous rectification. The other transistor may be configured to switch.

(Embodiment 4)
FIG. 14 is a circuit diagram showing a main part of the PDP drive circuit according to the fourth embodiment. This circuit shows a discharge sustain pulse generator 29 and a recovery circuit 33 similar to FIG. 1A. The feature of this embodiment is that there are two types of gate drive circuits for the high-side sustain switch element Q1, that is, a short-cycle gate drive circuit 41 and a long-cycle gate drive circuit.

  When the sustain pulse period is increased, the interval between discharges is increased, and the priming particles are attenuated. As a result, the discharge delay is increased, and the discharge is performed after the sustain voltage Vsus is reached without relatively shortening the rise time of the pulse.

  Therefore, as shown in FIG. 14, two types of gate drive circuits for the high-side sustain switch element Q1 are provided. The short cycle gate drive circuit 41 supplies a sustain pulse having a short cycle To and drives the gate of the high side sustain switch element Q1 through the gate resistor Ro. The long-cycle gate drive circuit 42 supplies a sustain pulse having a long cycle Tg, and drives the gate of the high-side sustain switch element Q1 through the gate resistor Rg.

  FIG. 15A shows a sustain waveform in the case of driving by the short cycle gate drive circuit 41, and FIG. 15B shows a sustain waveform in the case of driving by the long cycle gate drive circuit. Since Ro <Rg, the time tg when the high-side sustain switch element Q1 is turned on by the long-cycle gate drive circuit 42 is longer than the time to when the high-side sustain switch element Q1 is turned on by the short-cycle gate drive circuit 41. Become.

  When the sustain pulse period is lengthened and the rise time is lengthened, the current flowing through the panel capacitance is reduced, so that power consumption is reduced. Even if the amount of charge required to move the charge to the panel is the same, if the charge is moved in a short time, the effective current increases. Since the loss is proportional to the square of the effective current, the loss increases when the charge is moved in a short time.

  However, if the sustain pulse period is simply lengthened, the number of subfields that can be set decreases, and the number of display gradations decreases. Therefore, when there is a subfield in which the sustain pulse period may be increased based on the image data, the gate drive circuit 42 may be operated with the configuration of the present embodiment. In addition, two types of gate drive circuits for the low-side sustain switch element Q2 of the discharge sustain pulse generator of FIG. 4 shown in the first embodiment may be provided. Thereby, it is possible to obtain the same effect as the configuration shown in the fourth embodiment.

  According to the present invention, it is possible to achieve both improvement in power efficiency by using a recovery circuit and securing steepness of a sustain pulse edge involved in discharge, and drive of a PDP used in a wall-mounted television or a large monitor. Useful for.

FIG. 3 is a circuit diagram showing a recovery circuit and a discharge sustain pulse generator included in the PDP drive circuit in the first embodiment Waveform diagram showing sustain pulses applied to scan electrodes and sustain electrodes in the sustain period of the PDP drive circuit The figure which shows the voltage waveform applied to a display electrode in the sustain period of the PDP drive circuit, and the ON / OFF timing of each switch element of the discharge sustain pulse generator and recovery circuit The circuit diagram which shows the collection | recovery circuit and discharge sustain pulse generation part of the other structure contained in the PDP drive circuit in Embodiment Waveform diagram showing sustain pulses applied to scan electrodes and sustain electrodes in the sustain period of the PDP drive circuit The figure which shows the voltage waveform applied to a display electrode in the sustain period of the PDP drive circuit, and the ON / OFF timing of each switch element of the discharge sustain pulse generator and recovery circuit A circuit diagram showing a power supply circuit included in the recovery circuit of FIG. 1 or FIG. Circuit diagram showing another configuration of the power supply circuit Circuit diagram showing still another configuration of the power supply circuit A circuit diagram showing a voltage detection circuit which is a main part of a PDP drive circuit in a second embodiment Table showing the operation of the same voltage detection circuit FIG. 5 is a circuit diagram showing a configuration in which an auxiliary power supply circuit, which is a main part of a PDP drive circuit in Embodiment 3, is provided. The circuit diagram which shows the structure of the power supply circuit which integrated the power supply circuit and the auxiliary power supply circuit in the embodiment Table showing the operation of the power supply circuit Circuit diagram showing another configuration of the power supply circuit integrating the power supply circuit and the auxiliary power supply circuit Table showing the operation of the power supply circuit FIG. 6 is a circuit diagram showing a discharge sustaining pulse generation unit that is a main part of the PDP drive circuit in the fourth embodiment. Waveform diagram showing the operation of the sustaining pulse generator The perspective view which shows the structure of PDP of a prior art example. The figure which shows the electrode arrangement | sequence of the same PDP Block diagram showing the configuration of the plasma display device incorporating the PDP for each functional block Circuit diagram showing scan electrode driver and sustain electrode driver in a conventional PDP driver circuit Waveform diagram showing voltage waveforms applied to each electrode of the PDP during one subfield period

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Front plate 2 Front glass substrate 3 Scan electrode 3a, 4a Transparent electrode 3b, 4b Bus electrode 4 Sustain electrode 5 Display electrode pair 6 Front side dielectric layer 7 Protective film 8 Back plate 9 Back glass substrate 10 Address electrode 11 Back side dielectric Body layer 12, 20 Partition 12a Vertical partition 12b Horizontal partition 13 Phosphor layer 13r Red (R) phosphor layer 13g Green (G) phosphor layer 13b Blue (B) phosphor layer 14 Discharge space 15 Discharge cell 16 Black matrix 20 PDP
21 A / D converter 22 Video signal processor 23 Subfield processor 24 Address electrode driver 25 Scan electrode driver 26 Sustain electrode driver 27 Scan pulse generator 28 Initialization pulse generator 29 First discharge sustain pulse generator 30, 32, 33, 35 Recovery circuit 31 Second sustaining pulse generators 34, 34a, 34b, 34c Power supply circuit 36a, 36b, 36c, 39, 40 Control circuit 37 Operational amplifier 38 Auxiliary power supply circuit 41 Short cycle gate Drive circuit 42 Long-period gate drive circuit C1 Recovery capacitors D1, D2 Recovery diodes D3, D4 Diode IC1 Scan drivers L1-L5 Inductors Q1, Q1X High-side sustain switch elements Q2, Q2X Low-side sustain switch elements Q3, Q4 Recovery switch elements QR1 High side ramp waveform generation QR2 low side ramp wave generating unit QS1, QS separation switching device R1 to R4, Ro, Rg resistor S1 high side scan switching elements S2 low side scan switching element Tr1~Tr7 transistor

Claims (12)

A voltage is applied to each electrode of the plasma display panel having a plurality of display electrode pairs each including a scan electrode and a sustain electrode and an address electrode orthogonal to the display electrode pair, and is formed by the display electrode pair and the address electrode. Configured to cause the display cell to discharge,
A discharge sustain pulse generator for applying a voltage to the display electrode pair from a sustain voltage power source via a sustain switch element in order to cause a sustain discharge in the display cell;
A plasma display panel comprising a recovery capacitor, a recovery inductor connected between the recovery capacitor and the display electrode pair, and a recovery circuit having a recovery switch element for controlling the connection between the recovery capacitor and the display electrode pair In the drive circuit,
The recovery circuit further comprises a power supply circuit for adjusting a voltage charged in the recovery capacitor;
At the rise of the sustain pulse voltage for causing the sustain discharge, the recovery switch element is turned off, the sustain switch element is turned on, and the sustain pulse voltage is applied to the display electrode from the discharge sustain pulse generator. ,
When the sustain pulse voltage falls, the recovery switch element is turned on, the sustain switch element is turned off, and the charge accumulated in the display electrode is controlled to be recovered by the recovery capacitor. Plasma display panel drive circuit. A voltage is applied to each electrode of the plasma display panel having a plurality of display electrode pairs each including a scan electrode and a sustain electrode and an address electrode orthogonal to the display electrode pair, and is formed by the display electrode pair and the address electrode. Configured to cause the display cell to discharge,
A discharge sustain pulse generator for applying a voltage to the display electrode pair from a sustain voltage power source via a sustain switch element in order to cause a sustain discharge in the display cell;
A plasma display panel comprising a recovery capacitor, a recovery inductor connected between the recovery capacitor and the display electrode pair, and a recovery circuit having a recovery switch element for controlling the connection between the recovery capacitor and the display electrode pair In the drive circuit,
The recovery circuit further comprises a power circuit for charging the recovery capacitor to a predetermined voltage;
At the fall of the sustain pulse voltage for causing the sustain discharge, the recovery switch element is turned off, the sustain switch element is turned on, and the sustain pulse voltage is applied to the display electrode from the discharge sustain pulse generator And
The plasma is controlled such that when the sustain pulse voltage rises, the recovery switch element is turned on, the sustain switch element is turned off, and the charge accumulated in the recovery capacitor is supplied to the display electrode. Display panel drive circuit.   When the voltage Va supplied from the voltage of the recovery capacitor through the power supply circuit has a relationship Va> Vc with respect to the set voltage Vc of the recovery capacitor, the power supply circuit is configured by a booster circuit, Va 2. The plasma display panel driving circuit according to claim 1, wherein when the relationship is <Vc, the power supply circuit is constituted by a step-down circuit.   When the voltage Va supplied to the recovery capacitor via the power supply circuit has a relationship Va> Vc with respect to the set voltage Vc of the recovery capacitor, the power supply circuit is constituted by a step-down circuit, and Va <Vc 3. The plasma display panel driving circuit according to claim 2, wherein when the relationship is satisfied, the power supply circuit is constituted by a booster circuit.   2. The plasma display panel driving circuit according to claim 1, wherein the set voltage Vc of the recovery capacitor is set to a relationship of Vc <Vsus / 2 with respect to a voltage value Vsus of the sustain voltage power source.   The plasma display panel driving circuit according to claim 2, wherein the set voltage Vc of the recovery capacitor is set to a relationship of Vc> Vsus / 2 with respect to the voltage value Vsus of the sustain voltage power source.   A voltage detection circuit for detecting the voltage of the recovery capacitor is provided, and the power supply circuit is controlled not to operate when the detection value by the voltage detection circuit is within a predetermined range with respect to the set voltage Vc of the recovery capacitor. The plasma display panel drive circuit according to claim 1 or 2. An auxiliary power supply circuit connected to the recovery capacitor and receiving a voltage Vb from a constant voltage source;
2. The plasma display panel drive circuit according to claim 1, wherein the auxiliary power supply circuit is controlled to charge the recovery capacitor to a set voltage Vc when the plasma display panel is activated. 3. The voltage Va supplied by the power supply circuit and the voltage Vb supplied by the auxiliary power supply circuit are the same,
The power supply circuit and the auxiliary power supply circuit are configured as a power supply circuit combining a booster circuit and a step-down circuit,
When the plasma display panel is started, either the booster circuit or the step-down circuit is operated to charge the recovery capacitor, and the other is operated so as to supply power to the voltage Va except for the startup. Item 9. The plasma display panel drive circuit according to Item 8. The drive circuit for driving the sustain switch element on the high side of the discharge sustain pulse generator includes a short cycle drive circuit and a long cycle drive circuit,
The time for which the sustain switch element is turned on by the long cycle drive circuit is set to be longer than the time for which the sustain switch element is turned on by the short period drive circuit,
2. The plasma display panel drive circuit according to claim 1, wherein the short cycle drive circuit and the long cycle drive circuit are switched and used based on image data displayed by the plasma display panel. A drive circuit for driving the sustain switch element on the low side of the discharge sustain pulse generator includes a short cycle drive circuit and a long cycle drive circuit,
The time for which the sustain switch element is turned on by the long cycle drive circuit is set to be longer than the time for which the sustain switch element is turned on by the short period drive circuit,
3. The plasma display panel drive circuit according to claim 2, wherein the short cycle drive circuit and the long cycle drive circuit are switched and used based on image data displayed by the plasma display panel. A plasma display panel having a display electrode pair composed of a scan electrode and a sustain electrode and an address electrode orthogonal to the display electrode pair, wherein a display cell is formed at each intersection of the display electrode pair and the address electrode;
The plasma display apparatus provided with the plasma display panel drive circuit of any one of Claims 1-11 for driving the said plasma display panel.

Images