JP2010057230A - Voltage generation circuit and operation control method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein conventional voltage generating circuit could not fully suppress the ripples of the output voltage. <P>SOLUTION: The voltage generating circuit comprises: a plurality of booster circuits 10 to 13 outputting an output voltage with respect to an output terminal OUT; a voltage detection part 30a monitoring the output voltage and detecting the output voltage, exceeding a predetermined voltage range and outputs a detection signal DN; and a control circuit 20a, including a register storing the number of the booster circuits to be activated, updating the value held in the register, corresponding to the detection signal DN that provides activation instruction to the number of booster circuits corresponding to the value held in the register. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The voltage generation circuit according to the present invention relates to a booster circuit that has a plurality of booster circuits and changes the current supply capability according to the number of booster circuits to be activated.

  2. Description of the Related Art In recent years, many semiconductor memory devices incorporating a nonvolatile memory circuit have been adopted in various fields such as in-vehicle and portable applications. In such a semiconductor memory device, low power consumption and high reliability are desired. A nonvolatile memory circuit has a memory cell structure that requires a high voltage and a large current for data writing, reading, and erasing. For this reason, the nonvolatile memory circuit employs a configuration in which a charge pump circuit capable of supplying a high voltage and a large current to the internal cells is built in and can be operated from a low power supply voltage.

  Here, the charge pump circuit used in such applications secures the current capability required even under worst conditions (power supply voltage = minimum, transistor threshold voltage = maximum) where the current required in the cell is maximum. Designed to be able to. However, the charge pump circuit designed to meet the worst conditions is required for the current capability required under the best conditions (power supply voltage = maximum, transistor threshold voltage = minimum) where the current required in the cell is minimum. With excessive current capability. Therefore, under the best conditions, there arises a problem that a large potential fluctuation (hereinafter, this potential fluctuation is referred to as a ripple) occurs in the output voltage output from the charge pump circuit. When the ripple is large, a large voltage is intermittently applied to the transistors arranged in the path from the memory cell and the charge pump circuit to the memory cell, which causes a problem that the reliability of the memory cell and the transistor is lowered. In addition, the charge pump circuit having excessive current capability leads to wasteful consumption of large power.

  Therefore, Patent Document 1 discloses an example of a technique for reducing ripple in a charge pump circuit. FIG. 18 is a block diagram of the charge pump circuit 100 disclosed in Patent Document 1. The charge pump circuit 100 includes charge pump units Pump0 to Pump3, a regulator 110, a control circuit 120, and a control mode signal generation circuit 130.

  The charge pump units Pump0 to Pump3 are respectively connected in parallel. Then, the charge pump voltage VPUMP boosted by the charge pump units Pump0 to Pump3 is output. The regulator 110 generates a program voltage VPROG that is supplied to the memory cell using the charge pump voltage VPUMP as a power source. At this time, the program voltage VPROG is a value obtained by amplifying the reference voltage VREF with a voltage division ratio determined by the capacitors C1 and C2.

  The control circuit 120 includes comparators 101 and 102, AND gates 122 and 124, an OR gate 126, and a charge pump activation control circuit 111. With these circuits, the control circuit 120 increases the number of activation states of the charge pump unit when the charge pump voltage VPUMP changes to be lower than the first target voltage TL1, and the charge pump voltage VPUMP becomes the first target voltage. The number of activation states of the charge pump unit is reduced when the voltage changes to become higher than the second target voltage TL2 lower than the voltage TL1. The first target voltage TL1 is set based on the first reference voltage VREF1, and the second target voltage TL2 is set based on the second reference voltage VREF2.

  The charge pump circuit 100 includes a control mode signal generation circuit 130 that generates the mode signals EN1 and EN2. The control mode signal generation circuit 130 outputs mode signals EN1 and EN2 according to the voltage level of the charge pump voltage VPUMP detected by the comparators 101 and 102. Then, the control circuit 120 switches the mode whether the control circuit 120 increases or decreases the number of activation states of the charge pump unit according to the mode signals EN1 and EN2. Here, a timing chart showing the operation of the charge pump circuit 100 is shown in FIG.

That is, the charge pump circuit 100 gives the hysteresis characteristic to the control of the control circuit 120 that controls the activation states of the plurality of charge pump units, and the hysteresis characteristic has an upper limit (TL1 in FIG. 19) and a lower limit (TL2 in FIG. 19). ) To control switching of the active state and inactive state of the charge pump unit. In addition, the charge pump circuit 100 is configured to sequentially activate and deactivate the charge pump unit by the control circuit 120 (PUMP-EN (0) to PUMP-EN (3) in FIG. 19). It is possible to control the number of charge pump units to be activated according to the state. With such a configuration, the charge pump circuit 100 can keep the amplitude of the charge pump voltage VPUMP low. Further, the level of the generated charge pump voltage can be brought close to the minimum required level. Furthermore, since the charge pump circuit 100 controls the number of charge pump units activated in accordance with the load state, an excessive boosting operation is avoided, and power consumption can be saved.
JP 2004-248475 A

  However, in the charge pump circuit 100, the charge pump unit is switched between the active state and the inactive state based on the hysteresis characteristic, and the charge pump voltage VPUMP has a range exceeding the upper limit and the lower limit of the hysteresis characteristic. For this reason, the charge pump circuit 100 cannot guarantee that the ripple of the charge pump voltage VPUMP is within a range determined by the upper limit and the lower limit of the hysteresis characteristic. That is, the charge pump circuit 100 has a problem that the ripple of the charge pump voltage VPUMP cannot be sufficiently suppressed.

  One aspect of the voltage generation circuit according to the present invention includes a plurality of booster circuits that output an output voltage to an output terminal, and monitors the output voltage to detect the output voltage that exceeds a predetermined voltage range. A voltage detection unit that outputs a detection signal; and a register that stores the number of the booster circuits to be activated. The value held in the register is updated in accordance with the detection signal, and the value held in the register is updated. And a control circuit for giving an activation instruction to a corresponding number of the booster circuits.

  The voltage generation circuit according to the present invention monitors the output voltage, and updates the value of the register when the output voltage exceeds a predetermined voltage range. If the output voltage fluctuation range is within a predetermined voltage range, the number of booster circuits indicated by the value held in the register is activated. That is, the voltage generation circuit according to the present embodiment can keep the magnitude of the ripple noise of the output voltage within a preset voltage range.

  According to the voltage generation circuit of the present invention, the magnitude of the ripple of the output voltage can be suppressed.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the voltage generation circuit 1 according to the first embodiment. As shown in FIG. 1, the voltage generation circuit 1 includes a plurality of booster circuits (for example, charge pump circuits 10 to 13), a charge pump control circuit 20a, and a voltage detection unit 30a.

  Each of the charge pump circuits 10 to 13 operates based on a power supply voltage (not shown) input from the outside, and outputs an output voltage obtained by boosting the power supply voltage. The outputs of the charge pump circuits 10 to 13 are each connected to one output terminal OUT. The activation states of the charge pump circuits 10 to 13 are controlled by the activation control signal S output from the charge pump control circuit 20a.

  The charge pump control circuit 20a includes a register that stores the number of charge pump circuits to be activated, updates the value held in the register according to the detection signal output from the voltage detection unit 30a, and holds the value held in the register An activation instruction is given to the number of charge pump circuits corresponding to. Details of the charge pump control circuit 20a will be described later.

  The voltage detector 30a monitors the output voltage, detects an output voltage exceeding a preset first voltage range, and outputs a detection signal. The voltage detection unit 30 a includes a resistance voltage dividing unit 31 a and comparators 32 and 33. The resistance voltage divider 31a includes resistors R11 to R13. The resistors R11 to R3 are connected in series between the output terminal OUT and the ground terminal. Here, one end of the resistor R11 is connected to the output terminal, and the other end of the resistor R13 is connected to the ground terminal. The first monitor voltage VC11 is output from the connection node between the resistor R11 and the resistor R12. The second monitor voltage VC12 is output from the connection node between the resistor R12 and the resistor R13.

  In the comparator 101, the first monitor voltage VC11 is input to the negative input terminal, and the reference voltage Vref is input to the positive input terminal. The comparator 101 compares the two input voltages and outputs a monitor signal LVM. The monitor signal LVM indicates whether the output voltage is higher or lower than the ideal voltage value (ideal voltage) of the output voltage. In the comparator 102, the second monitor voltage VC12 is input to the negative input terminal, and the reference voltage Vref is input to the positive input terminal. The comparator 101 compares the two input voltages and outputs a first detection signal DN. The first detection signal DN gives an instruction to reduce the value held in the register in the charge pump control circuit 20a when the output voltage exceeds the upper limit of the first voltage range.

  Here, the relationship between the first voltage range, the resistors R11 to R13, and the reference voltage Vref will be described. In the present embodiment, a voltage range in which only an upper limit is set is set as the first voltage range. In the following description, 5.3 V is set as the upper limit voltage value VH of the first power supply range. Moreover, 5.0V is set as an ideal voltage. In such a setting, the reference voltage Vref is set to 1.0 V in the present embodiment. The first monitor voltage VC11 needs to be the same voltage as the reference voltage Vref when the output voltage is 5.0V, and the second monitor voltage VC12 is the reference voltage when the output voltage is 5.3V. The voltage needs to be the same as Vref. Therefore, the resistance values of the resistors R11 to R13 are set such that the first monitor voltage VC11 and the second monitor voltage VC12 satisfy the above conditions.

  Next, details of the charge pump control circuit 20a will be described. A block diagram of the charge pump control circuit 20a is shown in FIG. As shown in FIG. 2, the charge pump control circuit 20a includes a register 21a and a gating circuit 22a. In the present embodiment, a shift register is used as the register 21a. Note that the number of D flip-flops constituting the shift register is four according to the number of charge pump circuits. Therefore, reference numerals 210 to 213 are given to the D flip-flops used in the register 21a.

  The D flip-flops 210 to 213 are connected in series. Further, the D flip-flop 213 is arranged at the first stage, and the D flip-flop 210 is arranged at the final stage. The input terminal D of the D flip-flop 213 is connected to the power supply terminal VDD. On the other hand, the output terminal Q of the D flip-flop 210 is not connected to other D flip-flops. Each of the D flip-flops 210 to 213 performs a latch operation in synchronization with the falling edge of the first detection signal DN. The D flip-flops 210 to 213 are reset by a reset signal RST output from another circuit (not shown).

  The register 21a sets the outputs of all D flip-flops to 0 in the reset state. The register 21a increases the number of outputs that become 1 each time the falling edge of the first detection signal DN is input. In this embodiment, the operation setting value held by the register 21a is the number of D flip-flops whose output is 0. Then, the register 21a performs an operation of reducing the operation setting value held every time the falling edge of the first detection signal DN is input.

  The gating circuit 22a controls a period during which the charge pump circuit is activated according to the monitor signal LVM. At this time, the gating circuit 22a refers to the value of the register 21a and sets the number of charge pump circuits to be activated according to the number of operation setting values held in the register 21a. In the present embodiment, the gating circuit 22a has four AND gates according to the number of charge pump circuits. In the present embodiment, reference numerals 220 to 223 are assigned to the AND gate.

  In the AND gates 220 to 223, the monitor signal LVM is input to one input terminal, and the output signal of the D flip-flop corresponding to the other input terminal (F10 to F13 in this embodiment) is input. The other input terminal of the AND gates 220 to 223 is an inverting input terminal, and the inverting logic of the input signal is used as an operation target. That is, the AND gates 220 to 223 output the logical OR operation result of the inverted logic of the output signal of the D flip-flop and the monitor signal as the activation control signal S. That is, when the output signal of the D flip-flop indicates 0, the AND gates 220 to 223 set the activation control signal S to 0 (for example, low level) regardless of the value of the monitor signal LVM, and the output signal of the D flip-flop is 1 , The activation control signal S having the same logic as that of the monitor signal LVM is output. In the present embodiment, if the activation control signal S is 1 (for example, high level), the charge pump circuit is activated, and if the activation control signal S is low level, the charge pump circuit is deactivated. Become. In addition, since the activation control signal S is handled as a bus signal, in the following description, a number indicating what bit of the bus signal the signal corresponds to in [] after S.

  Next, a timing chart showing the operation of the voltage generation circuit 1 is shown in FIG. The operation of the voltage generation circuit 1 will be described with reference to FIG. First, the voltage generation circuit 1 starts the operation with the operation setting value held in the register 21a as 4. Therefore, the activation control signals S [3: 0] are all at a high level at the time of operation disclosure. Then, the voltage generation circuit 1 performs a boost operation using four charge pump circuits.

  When the output signal exceeds the ideal voltage value VT at timing t1, the first monitor voltage VC11 exceeds 1.0 V, so that the monitor signal LVM switches from the high level to the low level. Further, the activation control signal S [3: 0] also falls in response to the fall of the monitor signal LVM. However, actually, after the output voltage exceeds the ideal voltage value VT, the activation control signal S changes, and further, the delay time is delayed due to the delay of the comparator 101 etc. until the charge pump circuits 10 to 13 are stopped. appear. Therefore, a ripple occurs in the output voltage.

  At time t2, the output voltage exceeds the upper limit voltage value VH. Therefore, the second monitor voltage VC12 exceeds 1.0V, and the first detection signal DN falls. Then, since the output F13 of the register 21a rises in response to the fall of the first detection signal DN, the operation set value decreases from 4 to 3. The output voltage starts to decrease thereafter and falls below the upper limit voltage value VH at timing t3. Therefore, at the timing t3, the second monitor voltage VC12 falls below 1.0V, and the first detection signal DN rises.

  When the output signal falls below the ideal voltage value VT at timing t4, the first monitor voltage VC11 falls below 1.0V, so that the monitor signal LVM switches from the low level to the high level. The activation control signal S [2: 0] also rises in response to the rise of the monitor signal LVM. At this time, since the operation setting value held in the register 21a is 3, the activation control signal S [3] maintains the low level. Therefore, three charge pump circuits are activated after timing t4. Also at this timing t4, actually, after the output voltage falls below the ideal voltage value VT, the activation control signal S changes, and further, the comparator until the charge pump circuits 10-13 start operating. A delay time occurs due to a delay of 101 or the like. Therefore, a ripple occurs in the output voltage.

  When the charge pump circuit is activated, the output voltage starts to rise. When the output signal exceeds the ideal voltage value VT at timing t5, the first monitor voltage VC11 exceeds 1.0 V, so that the monitor signal LVM is switched from the high level to the low level. Then, the activation control signal S [2: 0] also falls in response to the fall of the monitor signal LVM. However, actually, after the output voltage exceeds the ideal voltage value VT, the activation control signal S changes, and further, the delay time is delayed due to the delay of the comparator 101 etc. until the charge pump circuits 10 to 13 are stopped. appear. Therefore, a ripple occurs in the output voltage.

  At time t6, the output voltage exceeds the upper limit voltage value VH. Therefore, the second monitor voltage VC12 exceeds 1.0V, and the first detection signal DN falls. Then, the output F12 of the register 21a rises in response to the fall of the first detection signal DN, so that the operation set value decreases from 3 to 2. The output voltage starts to decrease thereafter and falls below the upper limit voltage value VH at timing t7. Therefore, at the timing t7, the second monitor voltage VC12 falls below 1.0V, and the first detection signal DN rises.

  When the output signal falls below the ideal voltage value VT at timing t8, the first monitor voltage VC11 falls below 1.0V, so that the monitor signal LVM switches from the low level to the high level. In response to the rise of the monitor signal LVM, the activation control signal S [1: 0] also rises. At this time, since the operation setting value held in the register 21a is 2, the activation control signal S [3: 2] maintains the low level. Therefore, two charge pump circuits are activated after timing t6. Also at this timing t8, actually, after the output voltage falls below the ideal voltage value VT, the activation control signal S changes, and further, the comparator until the charge pump circuits 10-13 start operating. A delay time occurs due to a delay of 101 or the like. Therefore, a ripple occurs in the output voltage.

  When the charge pump circuit is activated, the output voltage starts to rise. When the output signal exceeds the ideal voltage value VT at timing t9, the first monitor voltage VC11 exceeds 1.0 V, so that the monitor signal LVM is switched from the high level to the low level. Then, the activation control signal S [1: 0] also falls in response to the fall of the monitor signal LVM. However, actually, after the output voltage exceeds the ideal voltage value VT, the activation control signal S changes, and further, the delay time is delayed due to the delay of the comparator 101 etc. until the charge pump circuits 10 to 13 are stopped. appear. Therefore, a ripple occurs in the output voltage. However, the magnitude of the ripple generated after timing t6 is small because the number of activated charge pump circuits is smaller than the period before timing t6. Specifically, after the timing t6, if the amount of current consumed in the load circuit connected to the output terminal OUT does not decrease, the output voltage does not exceed the upper limit voltage value VH due to ripple.

  Therefore, after timing t6, the output voltage fluctuates back and forth above and below the ideal voltage value VT while maintaining the upper limit voltage value VH or less. Further, the monitor signal LVM switches the signal level in accordance with such a change in the output voltage. The charge pump control circuit gives an instruction to switch the active state and the inactive state to the charge pump circuits 10 and 11 in response to the switching of the signal level of the monitor signal LVM (timing t9 to t12).

  From the above description, the voltage generation circuit 1 according to the present embodiment sets the number of charge pump circuits to be activated based on the operation setting value stored in the register 21a. Further, the voltage generation circuit 1 updates the operation setting value based on the detection signal generated by the voltage detection unit 30a that monitors the output voltage, and the output voltage falls within a range not exceeding the predetermined first voltage range. The operation set value is determined as follows. When the voltage generation circuit 1 operates according to the number of charge pump circuits activated based on the operation setting value thus determined, the ripple amount of the output voltage is the first voltage range unless the load current varies. Fits in. The voltage generation circuit 1 switches between the active state and the inactive state of the charge pump circuit based on whether or not the output voltage exceeds the ideal voltage value VT. Therefore, the voltage generation circuit 1 does not need to refer to the upper limit voltage value VH of the first voltage range for switching between the active state and the inactive state of the charge pump circuit. That is, according to the voltage generation circuit 1, it is possible to ensure that the ripple amount of the output voltage is within the first voltage range. Further, the voltage generation circuit 1 can reduce the ripple amount as compared with the conventional charge pump circuit.

  Further, in the voltage generation circuit 1, since the number of charge pump circuits to be activated is based on the operation setting value stored in the register 21a, circuit characteristics such as a comparator are determined after the optimum operation setting value is determined. Regardless of this, the ripple amount can be set to be equal to or less than the first voltage range.

  Further, the voltage generation circuit 1 switches between the active state and the inactive state of the charge pump circuit based on the switching of the voltage relationship between the output voltage and the ideal voltage value VT. Thereby, in the voltage generation circuit 1, the active state and inactive state of the charge pump circuit can be switched earlier than the conventional example. Further, the ripple of the output voltage can be reduced by switching the active state and the inactive state of the charge pump circuit at an early stage.

  In addition, according to the voltage generation circuit 1 according to the present embodiment, the number of charge pump circuits to be activated is determined so as to reduce the ripple amount, and therefore the charge pump circuit to be activated more than the conventional charge pump circuit. The number of can be reduced. That is, the voltage generation circuit 1 can reduce the current consumed in the charge pump circuit and realize low power consumption.

  Further, according to the voltage generation circuit 1 according to the present embodiment, when the fluctuation amount of the load current is small and the output voltage does not exceed the first voltage range, the operation voltage value determined so far is continued. Use. For this reason, the voltage generation circuit 1 can efficiently reduce the ripple of the output voltage if the fluctuation of the load current is small.

Embodiment 2
FIG. 4 is a block diagram of the voltage generation circuit 2 according to the second embodiment. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof is omitted.

  As shown in FIG. 4, the voltage generation circuit 2 is obtained by replacing the charge pump control circuit 20a in the voltage generation circuit 1 with a charge pump control circuit 20b. The charge pump control circuit 20b operates in response to the same control signals (for example, the reset signal RST, the monitor signal LVM, the first detection signal DN) as the charge pump control circuit 20a, but the waveform of the activation control signal S to be output. Is different.

  Here, a block diagram of the charge pump control circuit 20b is shown in FIG. As shown in FIG. 5, the charge pump control circuit 20b is obtained by adding a sequential control circuit 23 to the charge pump control circuit 20a. The sequential control circuit 23 receives the monitor signal LVM and outputs sequential signals SQ [0] to SQ [3]. The sequential signal SQ [0] is input to one terminal of the AND gate 220, the sequential signal SQ [1] is input to one terminal of the AND gate 221, and the sequential signal SQ [2] is one terminal of the AND gate 222. The sequential signal SQ [3] is input to one terminal of the AND gate 223. Further, the sequential signals SQ [0] to SQ [3] sequentially fall in the order of the sequential signal SQ [3] to the sequential signal SQ [0] according to the fall of the monitor signal LVM. On the other hand, when the monitor signal LVM rises, it sequentially rises in the order of the sequential signal SQ [3] to the sequential signal SQ [0] in response to the rise.

  The activation control signal S output from the charge pump control circuit 20b sequentially falls in the order of the activation control signal S [3] to the activation control signal S [0] according to the rise of the monitor signal LVM, and the monitor signal LVM. Rises sequentially in the order of the activation control signal S [3] to the activation control signal S [0]. Note that, as in the first embodiment, only the number of activation control signals S corresponding to the operation set value held in the register 21a is output.

  Next, FIG. 6 shows a timing chart showing the operation of the voltage generation circuit 2 according to the second exemplary embodiment. The operation of the voltage generation circuit 2 will be described with reference to FIG. Note that the timing chart shown in FIG. 6 corresponds to the timing chart shown in FIG. 3, and each timing corresponds in FIG. 6 and FIG.

  As shown in FIG. 6, when the output voltage exceeds the ideal voltage value VT at timing t1, the monitor signal LVM falls. Then, the sequential signal SQ [3] falls in response to the fall of the monitor signal LVM. Thereafter, the signals fall in order from the sequential signal SQ [2] to the sequential signal SQ [0]. The signal levels of the activation control signals S [3] to S [0] also change according to the sequential signals SQ [3] to SQ [0]. That is, in the voltage generation circuit 2, the charge pump circuit is inactivated in order as time passes.

  When the force voltage falls below the ideal voltage value VT at timing t4, the monitor signal LVM rises. Then, the sequential signal SQ [3] rises in response to the rise of the monitor signal LVM. Thereafter, the signals rise in order from the sequential signal SQ [2] to the sequential signal SQ [0]. In addition, the signal levels of the activation control signals S [2] to S [0] change according to the sequential signals SQ [2] to SQ [0]. Since the operation setting value is 3 at timing t4, the activation control signal S [3] maintains the low level. That is, in the voltage generation circuit 2, the charge pump circuit is sequentially activated in accordance with the passage of time. The number of charge pump circuits activated is determined by the operation set value. The operation after timing t4 is performed from timing t1 to t4 according to the operation set value. Therefore, description is abbreviate | omitted here.

  From the above description, in the voltage generation circuit 2, the sequential control circuit 23 sequentially performs the activation or deactivation timing of the charge pump circuit. Therefore, the fluctuation of the output voltage of the voltage generation circuit 2 becomes gentler than that in the first embodiment. Thereby, in the voltage generation circuit 2, the overshoot in which the output voltage exceeds the first voltage range can be reduced.

Embodiment 3
FIG. 7 shows a block diagram of the voltage generation circuit 3 according to the third embodiment. In the third embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof is omitted.

  As shown in FIG. 3, the voltage generation circuit 3 is obtained by replacing the voltage detection unit 30a in the voltage generation circuit 1 with a voltage detection unit 30b. The voltage detection unit 30b outputs a second detection signal (hereinafter referred to as a reset signal RST) in addition to the monitor signal LVM and the first detection signal DN output from the voltage detection unit 30a. Therefore, the voltage detection unit 30b includes a resistance voltage dividing unit 31b including one more resistor than the resistance voltage dividing unit 31a of the voltage detection unit 30a. Further, the voltage detection unit 30 b includes a comparator 34 in addition to the comparators 32 and 33.

  The resistance voltage divider 31b includes resistors R31 to R34. The resistors R31 to R34 are connected in series between the output terminal OUT and the ground terminal. Here, one end of the resistor R31 is connected to the output terminal OUT, and the other end of the resistor R34 is connected to the ground terminal. The third monitor voltage VC33 is output from the connection node between the resistor R31 and the resistor R32. The first monitor voltage VC31 is output from the connection node between the resistor R32 and the resistor R33. The second monitor voltage VC32 is output from the connection node between the resistor R33 and the resistor R34. Note that the first monitor voltage VC31 and the second monitor voltage VC32 are voltages corresponding to the first monitor voltage VC11 and the second monitor voltage VC12, respectively, and thus description thereof is omitted here. The third monitor voltage VC33 becomes the same voltage as the reference voltage Vref when the output voltage reaches the lower limit voltage value VL (for example, 4.4V) of the first voltage range. Therefore, the resistance values of the resistors R31 to R34 are set so as to satisfy this condition.

  The third monitor voltage VC33 is input to the negative input terminal of the comparator 34. The reference voltage Vref is input to the positive input terminal of the comparator 34. The comparator 34 compares the two input voltages and outputs a reset signal RST.

  Next, a timing chart showing the operation of the voltage generation circuit 3 is shown in FIG. The operation of the voltage generation circuit 3 will be described with reference to FIG. In the operation example shown in FIG. 8, the voltage generation circuit 3 operates with an operation set value of 2. More specifically, among the outputs of the register 21a, F13 and F12 are at a high level, and F11 and F10 are at a low level. Therefore, before the timing t20, the activation control signals S [1] and S [0] are at the high level, and the two charge pump circuits are activated.

  When the output voltage exceeds the ideal voltage value VT at timing t20, the monitor signal LVM falls, and the activation control signals S [1] and S [0] fall in response to this fall. Thereafter, the output voltage begins to drop. At timing t21, when the output voltage falls below the ideal voltage value VT, the monitor signal LVM rises, and the activation control signals S [1] and S [0] rise in response to this rise. Thereafter, the output voltage starts to rise.

  However, at timing t22, an increase in the load current drawn from the output terminal occurs, and when it becomes impossible to cover the load current only by the operation of the two charge pump circuits, the output voltage starts to drop. Therefore, the output voltage falls below the lower limit voltage value VL of the first voltage range at timing t23. When the voltage detection unit 30b detects that the output voltage has fallen below the lower limit voltage value VL, the reset signal RST rises. As a result, the reset signal RST is at a high level, so that all the D flip-flops in the register 21a are in a reset state, and all the outputs F13 to F10 of the register 21a are at a low level. Thereby, the operation set value is reset and switched from 2 to 4.

  Then, when the operation set value is switched, the activation control signals S [3] and S [2] that have been inactive in the previous period are switched to the active state. As a result, the number of activated charge pump circuits is switched from two to four. As the four charge pump circuits operate, the output voltage starts to increase.

  At time t24, when the output voltage exceeds the lower limit voltage value VL, the reset signal RST falls. Thereafter, when the output voltage exceeds the ideal voltage value VT at timing t25, the monitor signal LVM falls, and the activation control signals S [3] to S [0] fall in response to the fall. Then, the output voltage starts to drop. Thereafter, when the output voltage falls below the ideal voltage value VT at timing t26, the monitor signal LVM rises, and the activation control signals S [3] to S [0] rise in response to this rise. Then, the output voltage starts to rise. Thereafter, the voltage generation circuit 3 repeats the operation from timing t25 to t26 unless the output voltage exceeds the upper limit voltage value VH or the lower limit voltage value VL.

  From the above description, when the voltage generation circuit 3 falls below the lower limit voltage value VL, the voltage setting circuit 3 resets the operation setting value that has been reduced so far and increases the operation setting value. As a result, the voltage generation circuit 3 can increase the number of charge pump circuits to be activated in accordance with the increase in the load current even when the load current increases in a state where the operation set value is small. . As a result, the voltage generation circuit 3 can prevent the output voltage from decreasing. In particular, in a nonvolatile memory, when the output voltage of the voltage generation circuit 3 is low, a problem such as a write failure may occur. Therefore, it is important to keep the lower limit value of the output voltage at a predetermined voltage value.

Embodiment 4
FIG. 9 shows a block diagram of the voltage generation circuit 4 according to the fourth exemplary embodiment. As illustrated in FIG. 9, the voltage generation circuit 4 includes a plurality of booster circuits (for example, n charge pump circuits 10x), a charge pump control circuit 20c, and a voltage detection unit 30c.

  Each of the charge pump circuits included in the charge pump circuit 10x operates based on a power supply voltage (not shown) input from the outside, and outputs an output voltage obtained by boosting the power supply voltage. The outputs of the charge pump circuits included in the charge pump circuit 10x are each connected to one output terminal OUT. The activation state of the charge pump circuit 10x is controlled by the activation control signal S output from the charge pump control circuit 20c.

  The charge pump control circuit 20c is substantially the same as the charge pump control circuit 20b described in the third embodiment, but the method for updating the operation set value is different from the charge pump control circuit 20b. Details of the charge pump control circuit 20b will be described later.

  The voltage detection unit 30c outputs a third detection signal DNH in addition to the monitor signal LVM, the first detection signal DN, and the reset signal RST output from the voltage detection unit 30b described in the third embodiment. Therefore, the voltage detection unit 30c includes a resistance voltage dividing unit 31c including one more resistor than the resistance voltage dividing unit 31b of the voltage detection unit 30b. The voltage detection unit 30 c includes a comparator 35 in addition to the comparators 32 to 34.

  The resistance voltage divider 31c has resistors R41 to R45. The resistors R41 to R45 are connected in series between the output terminal OUT and the ground terminal. Here, one end of the resistor R41 is connected to the output terminal OUT, and the other end of the resistor R45 is connected to the ground terminal. The third monitor voltage VC44 is output from the connection node between the resistor R41 and the resistor R42. The first monitor voltage VC43 is output from the connection node between the resistor R42 and the resistor R43. The second monitor voltage VC42 is output from the connection node between the resistor R43 and the resistor R44. The fourth monitor voltage VC41 is output from the connection node between the resistor R44 and the resistor R45. The first monitor voltage VC43, the second monitor voltage VC42, and the third monitor voltage VC44 are voltages corresponding to the first monitor voltage VC11, the second monitor voltage VC12, and the third monitor voltage VC31, respectively. Therefore, the description is omitted here. The fourth monitor voltage VC41 is the reference voltage Vref when the output voltage reaches the upper limit voltage value VHH (for example, 5.6 V) of the second voltage range set as a voltage range larger than the first voltage range. Becomes the same voltage. Therefore, the resistance values of the resistors R41 to R45 are set so as to satisfy this condition.

  The fourth monitor voltage VC41 is input to the negative input terminal of the comparator 35. The reference voltage Vref is input to the positive input terminal of the comparator 35. The comparator 35 compares the two input voltages and outputs a third detection signal DNH.

  Next, details of the charge pump control circuit 20c will be described. A block diagram of the charge pump control circuit 20c is shown in FIG. As shown in FIG. 10, the charge pump control circuit 20c includes a register 21c, a gating circuit 22c, and a CKB control circuit 24. The register 21c in the present embodiment has n D flip-flops (210 to 21n-1 in the drawing). D flip-flops 210 to 21n-1 constitute a shift register as in the first embodiment. That is, the register 21c is obtained by increasing the number of D flip-flops of the register 21a. Therefore, a description of circuit connection is omitted here. Note that the number of D flip-flops constituting the shift register is set in accordance with the number of charge pump circuits.

  The gating circuit 22c is obtained by increasing the number of AND gates of the gating circuit 22a according to the number of charge pump circuits. Therefore, the detailed description of the gating circuit 22c is omitted here.

  The CKB control circuit 24 generates a signal CKB supplied to the CKB terminal of the D flip-flop constituting the register 21c based on the first detection signal DN and the third detection signal DNH. The CKB control circuit 24 in the present embodiment is a one-shot pulse circuit, for example. The CKB control circuit 24 in the present embodiment uses the one-shot pulse signal as the CKB signal to the D flip-flop in accordance with the falling edge of the first detection signal DN or the second detection signal DNH.

  Next, a timing chart showing the operation of the voltage generation circuit 4 is shown in FIG. The operation of the voltage generation circuit 4 will be described with reference to FIG. In the operation example shown in FIG. 11, the voltage generation circuit 4 operates with the operation set value as n. More specifically, the outputs F1n-1 to F10 of the register 21c are all in a low level state. Therefore, before the timing t30, the activation control signals S [n−1] to S [0] are at the high level, and the n charge pump circuits are activated.

  When the output voltage exceeds the ideal voltage value VT at timing t30, the monitor signal LVM falls, and the activation control signals S [n−1] to S [0] fall in response to the fall. Thereafter, the output voltage further rises and exceeds the upper limit voltage value VH of the first voltage range at timing t31. Therefore, the second monitor voltage VC42 exceeds the reference voltage Vref, and the first detection signal DN falls. Then, in response to the fall of the first detection signal DN, the CKB control circuit 24 sets the CKB signal to a low level for a predetermined period. Then, in synchronization with the fall of the CKB signal, the D flip-flop raises the output F1n-1. Accordingly, the operation set value is subtracted from n to n-1 at timing t31.

  Subsequently, the output voltage further rises, and the output voltage exceeds the upper limit voltage value VHH of the second voltage range at timing t32. Therefore, the fourth monitor voltage VC41 exceeds the reference voltage Vref, and the third detection signal DNH falls. In response to the fall of the third detection signal DNH, the CKB control circuit 24 sets the CKB signal to a low level for a predetermined period. Then, in synchronization with the fall of the CKB signal, the D flip-flop raises the output F1n-2. Therefore, the operation set value is subtracted from n-1 to n-2 at timing t32.

  Thereafter, the output voltage begins to drop. Then, at timing t33, the third detection signal DNH rises when the output voltage falls below the upper limit voltage value VHH of the second voltage range. Then, at the timing t34, the first detection signal DN rises when the output voltage falls below the upper limit voltage value VH of the first voltage range. Subsequently, when the output voltage falls below the ideal voltage value VT at timing t35, the monitor signal LVM rises, and the activation control signals S [n-3] to S [0] rise in response to this rise. On the other hand, the activation control signals S [n−1] and S [n−2] are maintained at the low level because the operation set value is n−2 before the timing t35, and the charge pump circuit To indicate the inactive state. Thereafter, the output voltage starts to rise.

  Subsequently, when the output voltage exceeds the ideal voltage value VT at timing t36, the monitor signal LVM falls, and the activation control signals S [n-3] to S [0] fall in response to the fall. Thereafter, the output voltage further increases and exceeds the upper limit voltage value VH of the first voltage range at timing t37. Therefore, the second monitor voltage VC42 exceeds the reference voltage Vref, and the first detection signal DN falls. Then, in response to the fall of the first detection signal DN, the CKB control circuit 24 sets the CKB signal to a low level for a predetermined period. The D flip-flop raises the output F1n-3 in synchronization with the fall of the CKB signal. Accordingly, the operation set value is subtracted from n−2 to n−3 at timing t37.

  Thereafter, the output voltage further increases, but the number of charge pump circuits activated during the period of timing t35 to t36 is two fewer than the number of charge pump circuits activated before timing t30. Therefore, an increase in the output voltage after timing t37 is suppressed, and the output voltage starts to decrease without exceeding the upper limit voltage value VHH of the second voltage range.

  Then, at the timing t38, the first detection signal DN rises when the output voltage falls below the upper limit voltage value VH of the first voltage range. Subsequently, when the output voltage falls below the ideal voltage value VT at timing t39, the monitor signal LVM rises, and the activation control signals S [n-4] to S [0] rise in response to this rise. On the other hand, the activation control signals S [n−1] to S [n−3] are maintained at the low level because the operation set value is n−3 before the timing t39, and the charge pump circuit To indicate the inactive state. Thereafter, the output voltage starts to rise.

  At timing t40, when the output voltage exceeds the ideal voltage value VT, the monitor signal LVM falls, and the activation control signals S [n-3] to S [0] fall in response to the fall. Then, the output voltage starts to drop. Thereafter, when the output voltage falls below the ideal voltage value VT at timing t41, the monitor signal LVM rises, and the activation control signals S [n-3] to S [0] rise in response to this rise. Then, the output voltage starts to rise. Thereafter, the voltage generation circuit 4 repeats the operations at timings t40 to t41 unless the output voltage exceeds the upper limit voltage value VH or the lower limit voltage value VL.

  From the above description, according to the voltage generation circuit 4 according to the fourth embodiment, the third detection signal DNH that monitors the output voltage with respect to the second voltage range having a voltage range that is larger than the first voltage range. Is provided. Then, the subtraction of the operation set value is instructed by the first detection signal DN and the third detection signal DNH. As a result, the voltage generation circuit 4 can detect a ripple that greatly exceeds the first voltage range at an early stage, and can reduce the operation set value more quickly. That is, in the voltage generation circuit 4, a large ripple can be reduced earlier than in the examples of the first to third embodiments. In particular, the large ripple accelerates the deterioration of the transistor that receives the output voltage output from the voltage generation circuit 4. Therefore, reducing the magnitude of the ripple at an early stage has a great effect for preventing the deterioration of the transistor.

Embodiment 5
FIG. 12 shows a block diagram of the voltage generation circuit 5 according to the fifth embodiment. As shown in FIG. 12, the voltage generation circuit 5 includes a charge pump control circuit 20d and a voltage detection unit 30d, which are modifications of the charge pump control circuit 20c and the voltage detection unit 30c of the voltage generation circuit 4 according to the fourth embodiment. Have.

  The charge pump control circuit 20d is substantially the same as the charge pump control circuit 20c described in the fourth embodiment, but the operation setting value updating method is different from the charge pump control circuit 20c. Details of the charge pump control circuit 20d will be described later.

  The voltage detection unit 30d outputs a fourth detection signal UP in addition to the monitor signal LVM, the first detection signal DN, and the reset signal RST output from the voltage detection unit 30b described in the third embodiment. Therefore, the voltage detection unit 30d includes a resistance voltage dividing unit 31d including one more resistor than the resistance voltage dividing unit 31b of the voltage detection unit 30b. Further, the voltage detection unit 30d includes a comparator 36 in addition to the comparators 32-34.

  The resistance voltage dividing unit 31d includes resistors R51 to R55. The resistors R51 to R55 are connected in series between the output terminal OUT and the ground terminal. Here, one end of the resistor R51 is connected to the output terminal OUT, and the other end of the resistor R55 is connected to the ground terminal. The third monitor voltage VC54 is output from the connection node between the resistor R51 and the resistor R52. The fifth monitor voltage VC53 is output from the connection node between the resistor R52 and the resistor R53. The first monitor voltage VC52 is output from the connection node between the resistor R43 and the resistor R44. The second monitor voltage VC51 is output from the connection node between the resistor R44 and the resistor R45. The first monitor voltage VC52, the second monitor voltage VC51, and the third monitor voltage VC54 are voltages corresponding to the first monitor voltage VC11, the second monitor voltage VC12, and the third monitor voltage VC33, respectively. Therefore, the description is omitted here. The fifth monitor voltage VC53 is the reference voltage Vref when the output voltage reaches the lower limit voltage value VLL (for example, 4.7V) of the second voltage range set as a voltage range smaller than the first voltage range. Becomes the same voltage. Therefore, the resistance values of the resistors R51 to R55 are set so as to satisfy this condition.

  The fifth monitor voltage VC53 is input to the negative input terminal of the comparator 36. The reference voltage Vref is input to the positive input terminal of the comparator 36. The comparator 36 compares the two input voltages and outputs a fourth detection signal UP.

  Next, details of the charge pump control circuit 20d will be described. A block diagram of the charge pump control circuit 20d is shown in FIG. As shown in FIG. 13, the charge pump control circuit 20d includes a register 21c, a gating circuit 22c, and a reset control circuit 25. Here, since the register 21c and the gating circuit 22c are the same as the charge pump control circuit 21c, description thereof is omitted.

  The reset control circuit 25 individually controls the reset signal of the D flip-flop. The number of ANDOR gates 250 to 25n-1 according to the number of D flip-flops is provided. And each of the ANDOR gates 250 to 25n-1 outputs a reset signal to the corresponding D flip-flop. ANDOR gates 250 to 25n-1 receive reset signal RST and fourth detection signal UP from voltage detection unit 30d. Further, the ANDOR gates 250 to 25n−1 refer to the output of the D flip-flop in which the input D is connected to the output Q of the corresponding D flip-flop (this output is referred to as Fx + 1). The ANDOR gates 250 to 25n−1 reset the D flip-flops provided correspondingly when the output Fx + 1 is at the low level and the fourth detection signal UP is at the high level. The ANDOR gates 250 to 25n−1 reset the D flip-flop regardless of the value of the output Fx + 1 of the D flip-flop when the reset signal RST becomes high level. The inverting input terminal of the AND gate of the ANDOR gate 250 provided corresponding to the D flip-flop 210 that is the final stage of the shift register is connected to the ground terminal GND.

  That is, the reset control circuit 25 sets the rearmost high level output in the shift register constituting the register 21c to the low level in response to the rise of the fourth detection signal UP. In other words, the reset control circuit 25 performs an operation of adding 1 to the operation set value held in the register 21c in response to the rise of the fourth detection signal UP.

  Next, a timing chart showing the operation of the voltage generation circuit 5 is shown in FIG. The operation of the voltage generation circuit 5 will be described with reference to FIG. In the operation example illustrated in FIG. 14, the voltage generation circuit 5 operates with an operation set value of n−3. More specifically, among the outputs of the register 21c, F1n-1 to F1n-3 are at a high level, and F1n-4 to F10 are at a low level. Therefore, at a time point before the timing t5, the activation control signals S [n−1] to S [n−3] are at the high level and the n−3 charge pump circuits are activated. It has become.

  When the output voltage exceeds the ideal voltage value VT at timing t50, the monitor signal LVM falls, and the activation control signals S [n-4] to S [0] fall in response to the fall. Thereafter, the output voltage begins to drop. At timing t51, when the output voltage falls below the ideal voltage value VT, the monitor signal LVM rises, and the activation control signals S [n-4] to S [0] rise in response to this rise. Thereafter, the output voltage starts to rise.

  However, at timing t52, an increase in the load current drawn from the output terminal occurs, and the output voltage begins to drop when the load current cannot be covered only by the operation of the n-3 charge pump circuits. Therefore, the output voltage falls below the lower limit voltage value VLL of the second voltage range at timing t53. When the voltage detection unit 30d detects that the output voltage has fallen below the lower limit voltage value VLL, the fourth detection signal UP rises. As a result, the fourth detection signal UP becomes high level, the output F1n-3 of the register 21c is reset, and the outputs F1n-3 to F10 of the register 21c all become low level. Further, the outputs F1n-1 to F1n-2 maintain a high level. Thereby, 1 is added to the operation set value from n-3 to n-2.

  Then, when the operation set value is switched, the activation control signal S [n-3] that has been inactive in the previous period is switched to the active state. As a result, the number of activated charge pump circuits increases from n−3 to n−2. Then, the n-2 charge pump circuits operate, so that the output voltage starts to rise.

  Then, at timing t54, when the output voltage exceeds the lower limit voltage value VLL, the fourth detection signal UP falls. Thereafter, when the output voltage exceeds the ideal voltage value VT at timing t55, the monitor signal LVM falls, and the activation control signals S [n-3] to S [0] fall in response to the fall. Then, the output voltage starts to drop. Thereafter, when the output voltage falls below the ideal voltage value VT at timing t56, the monitor signal LVM rises, and the activation control signals S [n-3] to S [0] rise in response to this rise. Then, the output voltage starts to rise. Thereafter, the voltage generation circuit 5 repeats the operations at timings t55 to t56 unless the output voltage exceeds the upper limit voltage value VH or the lower limit voltage value VLL.

  From the above description, the voltage generation circuit 5 according to the fifth exemplary embodiment can add 1 to the subtracted operation setting value instead of returning the operation setting value by reset. As a result, the voltage generation circuit 5 prevents the ripple from increasing upward when the load current increases. That is, when the subtracted operation setting value is increased by resetting, all the charge pump circuits operate after resetting, so that the charge pump circuit may have an excessive current supply capability with respect to the load current. In such a case, a large overshoot occurs in the output voltage, and there is a risk that the output voltage becomes excessively large. However, since the operation setting value can be gradually returned in the voltage generation circuit 5, it is possible to prevent the output voltage from becoming excessively large. Preventing such an excessive increase in the output voltage is effective in improving the reliability of the transistor to which the output voltage is applied.

Embodiment 6
FIG. 15 shows a block diagram of the voltage generation circuit 6 according to the sixth embodiment. In the sixth embodiment, the same components as those in the fifth embodiment are denoted by the same reference numerals as those in the fifth embodiment, and the description thereof is omitted.

  As shown in FIG. 15, the voltage generation circuit 6 is obtained by replacing the charge pump control circuit 20d in the voltage generation circuit 5 with a charge pump control circuit 20e. The charge pump control circuit 20e operates in response to the same control signals as the charge pump control circuit 20d (for example, the reset signal RST, the monitor signal LVM, the first detection signal DN, and the fourth detection signal UP). The value update method is different.

  A block diagram of the charge pump control circuit 20e is shown in FIG. As shown in FIG. 16, the charge pump control circuit 20e has a gating circuit 22c, a P register 26, and an N register 27. The gating circuit 22c is the same as the gating circuit 22c of the charge pump control circuit 20d. In the charge pump control circuit 20 e, the operation set value is held by the P register 26 and the N register 27. Hereinafter, the P register 26 and the N register 27 will be described.

  The P register 26 outputs a signal FP [n−1: 0] in response to the monitor signal LVM and the fourth detection signal UP. The signal FP [n−1: 0] is composed of n signals. This signal is input to one terminal of each of the AND gates 220 to 22n-1 of the gating circuit 22c. The P register 26 outputs a signal having the same logic as the monitor signal LVM. At this time, one of the signals FP [n−1: 0] is output as the monitor signal LVM in response to the rising edge of the fourth detection signal UP. Regardless of the logic level, the charge pump circuit is rendered inactive. The P register 26 increases the number of signals FP indicating the inactive state every time the rising edge of the fourth detection signal UP is input. The operation set value held in the P register 26 is referred to as the minimum number of activated circuits here.

  The N register 27 is the register 21a in which the number of D flip-flops is n. Further, the signal FN [n−1: 0] output in response to the first detection signal DN and the reset signal RST is the same as the number of outputs F of the register 21a is n.

  Next, FIG. 17 shows a timing chart showing the operation of the voltage generation circuit 6. In the operation example shown in FIG. 17, first, 0 is set as the minimum activation circuit number in the P register 26, and n is set as the operation set value in the N register 27. Therefore, before the timing t60, the activation control signals S [n−1] to S [0] are all at a high level instructing activation. When the output voltage exceeds the ideal voltage value VT at timing t60, the monitor signal LVM falls. At this time, since the minimum number of activation circuits held in the P register 26 is 0, the activation control signals S [n−1] to S [0] fall in response to the fall of the monitor signal LVM. . Thereafter, the output voltage begins to drop. Thereafter, when the output voltage falls below the ideal voltage value VT at timing t61, the monitor signal LVM rises. Then, the activation control signals S [n−1] to S [0] rise in response to the rise of the monitor signal LVM. However, when the load current is large and the output voltage drop is large, the output voltage falls below the lower limit voltage value VL at timing t63. Therefore, the fourth detection signal UP rises at timing t62. Then, in response to the rise of the fourth detection signal UP, the minimum number of activated circuits held in the P register 26 increases from 0 to 1.

  Thereafter, the output voltage starts to increase. Then, when the output voltage exceeds the lower limit voltage value VL at timing t63, the fourth detection signal UP falls. The output voltage continues to rise. At time t64, the output voltage exceeds the ideal voltage value VT. Therefore, the monitor signal LVM falls according to this output voltage. At this time, the minimum number of activated circuits held in the P register 26 is one. Therefore, there are n−1 activation control signals S [n−1] to [1] indicating an inactive state in response to the fall of the monitor signal LVM at the timing t64.

  Then, the output voltage starts to drop. At this time, the rate of drop of the output voltage is slower than the period before timing t62 because one charge pump circuit is operating. At time t65, the output voltage falls below the ideal voltage value VT, and the monitor signal LVM rises. Then, the activation control signals S [n−1] to [1] rise in response to the rise of the monitor signal LVM. At this time, the activation control signal S [0] maintains a state (for example, high level) instructing activation to the charge pump circuit.

  Then, the output voltage starts to rise. At this time, since the output voltage drop rate is slow, the output voltage starts to rise before the output voltage falls below the lower limit voltage value VL. At time t66, the output voltage exceeds the ideal voltage value VT, and the monitor signal LVM falls according to this output voltage. In response to the fall of the monitor signal LVM, the activation control signal S falls from [n−1] to [1]. Also at this timing t66, since the minimum number of activation circuits of the P register 26 is 1, the activation control signal S [0] maintains a high level. In the subsequent period, the operations at timings t64 to t65 are repeated.

  From the above description, the voltage generation circuit 6 can set the number of charge pump circuits that are activated regardless of the logic level of the monitor signal LVM by the minimum number of activation circuits. By operating the charge pump circuit in accordance with the minimum number of activated circuits, the output voltage drop rate can be moderated. As a result, the amount of voltage drop that occurs from when the output voltage falls below the ideal voltage value VT until the charge pump circuit is activated and the output voltage starts to increase can be reduced. The voltage generation circuit 6 is particularly effective when the load current is large. That is, when the load current is large, a voltage drop that occurs between the time when the output voltage falls below the ideal voltage value VT and the time when the output voltage starts to rise becomes large. However, by reducing the speed of this voltage drop, it is possible to reduce the amount of voltage drop of the output voltage that occurs from when the output voltage falls below the ideal voltage value VT until the charge pump circuit actually starts operating. That is, when the load current is large, the voltage generation circuit 6 can efficiently prevent the voltage drop of the output voltage. In addition, by applying such a voltage generation circuit 6 to a nonvolatile memory, a great effect can be obtained in preventing malfunction in the nonvolatile memory.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the method of updating the operation set value can be changed as appropriate according to the use of the system to which the voltage generation circuit is applied.

1 is a block diagram of a voltage generation circuit according to a first exemplary embodiment; 1 is a block diagram of a charge pump control circuit according to a first embodiment; 3 is a timing chart illustrating an operation of the voltage generation circuit according to the first exemplary embodiment; FIG. 3 is a block diagram of a voltage generation circuit according to a second embodiment. FIG. 3 is a block diagram of a charge pump control circuit according to a second embodiment. 6 is a timing chart illustrating an operation of the voltage generation circuit according to the second exemplary embodiment; FIG. 6 is a block diagram of a voltage generation circuit according to a third embodiment. 10 is a timing chart illustrating an operation of the voltage generation circuit according to the third exemplary embodiment; FIG. 6 is a block diagram of a voltage generation circuit according to a fourth embodiment. FIG. 9 is a block diagram of a charge pump control circuit according to a fourth embodiment. 10 is a timing chart illustrating an operation of the voltage generation circuit according to the fourth exemplary embodiment; FIG. 9 is a block diagram of a voltage generation circuit according to a fifth embodiment. FIG. 9 is a block diagram of a charge pump control circuit according to a fifth embodiment. 10 is a timing chart illustrating an operation of the voltage generation circuit according to the fifth exemplary embodiment; FIG. 10 is a block diagram of a voltage generation circuit according to a sixth embodiment. FIG. 10 is a block diagram of a charge pump control circuit according to a sixth embodiment. 12 is a timing chart illustrating an operation of the voltage generation circuit according to the sixth embodiment; It is a block diagram of the conventional charge pump circuit. It is a timing chart which shows operation | movement of the conventional charge pump circuit.

Explanation of symbols

1-6 Voltage generation circuits 10-13, 10x Charge pump circuits 20a-20e Charge pump control circuits 21a, 21c Registers 22a, 22c Gating circuit 23 Sequential control circuit 24 CKB control circuit 25 Reset control circuit 26 P register 27 N register 30a ˜30d Voltage detectors 31a to 31d Resistor voltage dividers 210 to 213, 210 to 21n−1 flip-flops 220 to 223, 220 to 22n−1 AND gates 32 to 36 Comparator 210-21n−1 D flip-flops 250-25n− 1 ANDOR gates DN, DNH, UP detection signal LVM monitor signal RST reset signal S activation control signal SQ sequential signal OUT output terminal VDD power supply terminal GND ground terminals R11 to R13, R31 to R34, R41 to R 5, R51~R55 resistance VC11, VC12, VC31~VC33 monitor voltage VC41~VC44, VC51~VC54 monitor voltage Vref reference voltage VH, VHH upper limit voltage value VL, VLL lower limit voltage value VT ideal voltage value

Claims (14)

A plurality of booster circuits that output an output voltage to the output terminal;
A voltage detection unit that monitors the output voltage, detects the output voltage exceeding a predetermined first voltage range, and outputs a detection signal;
A register for storing the number of boosting circuits to be activated, updating a value held in the register in accordance with the detection signal, and for the number of boosting circuits in accordance with the value held in the register A control circuit for giving an activation instruction;
A voltage generating circuit. The voltage detection unit outputs a first detection signal that gives an instruction to reduce a value held in the register when the output voltage exceeds an upper limit of the first voltage range;
The voltage generation circuit according to claim 1, wherein the control circuit subtracts a value held in the register in accordance with the first detection signal. The voltage detection unit outputs a second detection signal that gives an instruction to initialize a value held in the register when the output voltage falls below a lower limit of the first voltage range;
The voltage generation circuit according to claim 1, wherein the control circuit sets an initial value to a value held in the register in accordance with the first detection signal. The voltage detection unit outputs a third detection signal when the output voltage exceeds a second voltage range set as a voltage range larger than the first voltage range,
4. The voltage generation circuit according to claim 1, wherein the control circuit updates a value held in the register in accordance with the third detection signal. 5. The voltage detection unit outputs a fourth detection signal that gives an instruction to add a value held in the register when the output voltage falls below a lower limit of the first voltage range;
The voltage generation circuit according to claim 1, wherein the control circuit increases a value held in the register in accordance with the fourth detection signal. The voltage detector outputs a monitor signal indicating whether the output voltage is higher or lower than a preset target voltage;
The voltage generation circuit according to claim 1, wherein the control circuit includes a gating circuit that controls a period for activating a plurality of the booster circuits in accordance with the monitor signal.   The voltage generation circuit according to claim 6, wherein the gating circuit gives an activation instruction to a number of booster circuits specified by a value held in the register. The control circuit outputs a sequential signal designating different activation periods for the plurality of booster circuits according to the monitor signal,
The voltage generation circuit according to claim 7, wherein the gating circuit gives an activation instruction to a plurality of the booster circuits based on a value held in the register and the sequential signal. The control circuit includes:
A first register that holds the number of boosting circuits that are activated when the output voltage is raised;
A second register that holds the number of boosting circuits that are activated when the output voltage is lowered;
The voltage generation circuit according to claim 1.   The voltage generation circuit according to claim 1, wherein the booster circuit is a charge pump circuit. An operation control method in a voltage generation circuit having a plurality of booster circuits for outputting an output voltage to an output terminal,
An operation setting value indicating the number of boost circuits to be activated among the plurality of boost circuits is held,
Activate the number of booster circuits according to the operation set value,
An operation control method in a voltage generation circuit, wherein the operation set value is updated when the output voltage exceeds a predetermined voltage range.   The operation control method in the voltage generation circuit according to claim 11, wherein the operation set value is increased when the output voltage falls below a lower limit of the voltage range.   The operation control method in the voltage generation circuit according to claim 12, wherein when the output voltage falls below a lower limit of the voltage range, the operation setting value is returned to an initial value.   The operation control method in the voltage generation circuit according to claim 11, wherein the operation set value is decreased when the output voltage exceeds an upper limit of the voltage range.

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