CN120832001A

CN120832001A - semiconductor devices

Info

Publication number: CN120832001A
Application number: CN202510260077.0A
Authority: CN
Inventors: 山崎尊永
Original assignee: Sanken Electric Co Ltd
Current assignee: Sanken Electric Co Ltd
Priority date: 2024-04-17
Filing date: 2025-03-06
Publication date: 2025-10-24
Also published as: JP2025163434A

Abstract

The invention provides a semiconductor device capable of simplifying an external power supply circuit. A SoC (1) (semiconductor device) having a plurality of power supply channels (VDD, VCORE, VCC), the plurality of power supply channels (VDD, VCORE, VCC) respectively receiving power supply voltages (V1, V2, vn) from a plurality of external power supply ICs (20, ₁、20₂、20_n) (power supply circuits), wherein the SoC (1) (semiconductor device) has a self-power supply management circuit (3), and the self-power supply management circuit (3) outputs a plurality of control signals respectively controlling the plurality of power supply ICs (20, ₁、20₂、20_n). The plurality of control signals are a plurality of enable signals (EN 1, EN2, ENn) controlling the sequence and time intervals of power-up and power-down of the power supply voltages (V1, V2, vn) from the plurality of power ICs (20 ₁、20₂、20_n).

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Technical Field

Embodiments of the present disclosure relate to a semiconductor device.

Background

In recent years, soC (System on Chip) has been reduced in power supply voltage and increased in current due to miniaturization and higher performance of the process. In addition, with the complexity of the internal structure of the SoC, various power supply specifications are required (for example, refer to non-patent document 1).

Non-patent document 1 Ralsac electronics (Renesas Electronics)RAA271000(General-Purpose Power Management IC for the Renesas R-Car SoC series) data handbook https:// www.renesas.com/jp/ja/document/dst/raa271000-datasheetr = 1497496

In recent computing socs for AI processing and the like, the power supply is reduced in voltage and the current is increased due to miniaturization and high performance of the process. With the complexity of the internal structure of the SoC, the following functional specifications (1) to (4) are required as the functional specifications of the power supply.

(1) There are a variety of power supply channels (power supply channels of different voltages, different power supply channels even at the same voltage).

(2) When the SoC is powered on, there is a specification of a power-on sequence (timing) of a plurality of power channels.

(3) When the power of the SoC is turned off, a power-off sequence (timing) of the plurality of power channels is defined.

(4) A power channel with a prescribed rise time (ramp time) in the power channel.

As shown in fig. 5, these power supply specifications are all implemented by an external power supply circuit. Therefore, control as shown in fig. 6 needs to be performed in an external circuit for each SoC so as to conform to the functional specification of the power supply. In the example of fig. 5, VDD, VCORE, VCC is provided as a power supply channel of the SoC, and if the voltages are V1, V2, and V.

Power on sequence, in order of V2-Vn-V1, time interval is defined by tON2n and tONn1

Power supply cut-off sequence, cut-off in the order of V1-Vn-V2, time intervals defined by tOF n and tOFn2

The rise time (ramp time) of V1 is defined by tR1

The rise time (ramp time) of V2 is defined by tR2

If the above-described rule is not satisfied, the SoC may malfunction or be damaged in some cases. Therefore, in the power management circuit, as shown in fig. 6, it is necessary to generate enable signals (EN 1, EN2, &.& gt, ENn) of the respective power circuits and reference voltage signals (VREF 1, VREF 2) for controlling the rise time (ramp time) in accordance with the specifications of the SoC, respectively.

Disclosure of Invention

The present disclosure is to provide a semiconductor device capable of simplifying an external power supply circuit.

The semiconductor device of the present disclosure has a plurality of power supply channels that receive power supply from a plurality of external power supply circuits, respectively, wherein the semiconductor device has a self-power supply management circuit that outputs a plurality of control signals that control a plurality of the power supply circuits, respectively.

The semiconductor device of the present disclosure can control a plurality of external power supply circuits, and can simplify the external power supply circuits.

Drawings

Fig. 1 is a diagram showing a structure of an embodiment of a semiconductor device.

Fig. 2 is a waveform diagram showing a functional specification example of a power supply channel of the semiconductor device shown in fig. 1.

Fig. 3 is a diagram showing a configuration example of the self-power management circuit.

Fig. 4 is a waveform diagram of an enable signal and a reference voltage signal.

Fig. 5 is an example of a prior art SoC power management circuit.

Fig. 6 is an example of control waveforms of a prior art SoC power management circuit.

Description of the reference numerals

1: Soc;2: auxiliary power supply circuit; 3: self power supply management circuit; 20: power supply IC;31: built-in oscillator; 32: vin voltage detection circuit; 33: ₁、33₂: delay circuit; 34: _EN1、34_EN2、34_ENn、34_RESET: flip-flop; 35: delay counter; 36: _REF1、36_REF2: D/a converter; 37: _REF1、37_REF2: data selector; EN1, EN2, ENn: enable signal; VREF1, VREF2: reference voltage signal.

Detailed Description

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

The semiconductor device of the present embodiment is an SoC 1 configured by various functional devices. Referring to fig. 1, soC 1 has CPU 11, GPU 12, CACHE 13, and other peripheral devices 14 as devices for various functions. The SoC 1 has a plurality of power supply channels VDD, VCORE, VCC, and operates by receiving power supply voltages (V1, V2, vn) from an external power supply block for each power supply channel. In addition, the power supply channel of the SoC is not limited to VDD, VCORE, VCC shown here. In addition to this, there are typically a plurality of power channels.

The SoC 1 has an auxiliary power supply circuit 2 constituted by an LDO (Low Drop Out) regulator and a self-power supply management circuit 3. The auxiliary power supply circuit 2 is a circuit for generating a power supply for operation from the power supply management circuit 3 based on the basic input voltage VIN.

The power management circuit 3 receives the power supply from the auxiliary power circuit 2, and outputs the enable signal ENx and the reference voltage signal VREFx to an external power supply block. The enable signal ENx is a control signal that controls the power-up timing (the sequence and time interval of power-up) and the power-down timing (the sequence and time interval of power-down) of the plurality of power channels. The reference voltage signal VREFx is a ramp control signal for controlling the rise time (ramp time). Further, a reset signal RESETn to the inside of the SoC 1 is generated from the power management circuit 3.

The power supply block includes power supply ICs 20 ₁、20₂、20_n, and the power supply ICs 20 ₁、20₂、20_n generate power supply voltages (V1, V2, vn) for each of a plurality of power supply channels provided in the SoC 1. The power supply IC 20 ₁、20₂、20_n is not limited, and is constituted by a switching power supply, for example. The enable signal ENx is output to the power supply IC 20 ₁、20₂、20_n having a predetermined power supply channel with timing (power-up, power-down). The reference voltage signal VREFx is output to the power supply IC 20 ₁、20₂ having a prescribed power supply channel of a rise time (ramp time).

Fig. 2 is a functional specification example of power supply voltages V1, V2, and Vn of a power supply channel VDD, VCORE, VCC provided in the SoC 1, and defines a power-on timing, a power-off timing, and a ramp time.

The power-up timing is a sequence of the power supply voltage V2, the power supply voltage Vn, and the power supply voltage V1, and defines a time tON2n from the completion of the power-up of the power supply voltage V2 to the start of the power-up of the power supply voltage Vn and a time tONn1 from the start of the power-up of the power supply voltage Vn to the start of the power-up of the power supply voltage V1.

The power-off timing is a sequence of the power supply voltage V1, the power supply voltage Vn, and the power supply voltage V2, and defines a time tOF n from the start of power-off of the power supply voltage V1 to the start of power-off of the power supply voltage Vn and a time tOFn from the start of power-off of the power supply voltage Vn to the start of power-off of the power supply voltage V2.

Regarding the ramp time, a time tR1 from which the power supply voltage V1 starts to rise to reach a predetermined level and a time tR2 from which the power supply voltage V2 starts to rise to reach a predetermined level are specified.

The power-on timing and the power-off timing are controlled by outputting the enable signals EN1, EN2, ENn to all the power ICs 20 ₁、20₂、20_n receiving power supply from the power management circuit 3, respectively. The ramp time is controlled by the power management circuit 3 outputting the reference voltage signals VREF1 and VREF2 to a predetermined power supply IC having a ramp time from among the power supply ICs 20 ₁、20₂、20_n, respectively. That is, the SoC 1 itself, which receives power from the outside to the plurality of power supply channels, has the self-power management circuit 3 incorporated therein, and outputs a signal for controlling timing or rise time (ramp time) of the power supply IC that supplies power to each power supply channel.

Referring to fig. 3, the self-power management circuit 3 has a built-in oscillator 31, a VIN voltage detection circuit 32, and a delay circuit 33 ₁、33₂ with internal logic actions. The VIN voltage detection circuit 32 is constituted by a voltage comparator or the like, and monitors the input voltage VIN to perform start detection and shut-off detection.

The self-power management circuit 3 has a flip-flop 34 _EN1、34_EN2、34_ENn、34_RESET. The flip-flop 34 _EN1、34_EN2、34_ENn is provided at the output stage of the enable signals EN1, EN2, ENn, respectively, and enables the enable signals EN1, EN2, ENn by setting and disables by resetting. The flip-flop 34 _RESET is provided at the output stage of the reset signal RESETn, and sets the reset signal RESETn to a high level (negative logic inactive) by setting and to a low level (negative logic active) by resetting.

The self-power-management circuit 3 has a delay counter 35 _ON2n、35_ONn1、35_OF1n、35_OFn2、35_R1、35_R2. The delay counter 35 _ON2n、35_ONn1 counts the times tON2n, tON 1 defined by the power-on timing. The delay counter 35 _OF1n、35_OFn2 counts the times tOF n, tOFn2 specified by the power-off timing. Delay counter 35 _R1、35_R2 counts ramp times tR1, tR 2.

The self-power management circuit 3 has a D/a converter 36 _REF1、36_REF2 and a data selector 37 _REF1、37_REF2. The D/a converter 36 _REF1、36_REF2 converts the count value (digital input) of the delay counter 35 _R1、35_R2 into analog voltages, respectively, and outputs as reference voltage signals VREF1, VREF 2. The data selector 37 _REF1、37_REF2 is a circuit that switches the digital input to the D/a converter 36 _REF1、36_REF2 to either one of the delay counter 35 _R1、35_R2 and zero.

The operation of the self-power management circuit 3 will be described with reference to fig. 4.

When the VIN voltage detection circuit 32 detects that the turned-on VIN voltage reaches the preset start-up voltage at time t0, a start-up detection signal is output from the delay circuit 33 ₁ at time t 1. The enable detect signal sets flip-flop 34 _EN2, enables enable signal EN2, and starts counting of delay counter 35 _R2. The delay counter 35 _R2 is a counter that counts the ramp time tR2 of the reference voltage signal VREF 2. The count value of the delay counter 35 _R2 is set so that the reference voltage signal VREF2 analog-converted by the D/a converter 36 _REF2 reaches a predetermined voltage at a time t2 when the ramp time tR2 has elapsed.

When delay counter 35 _R2 overflows at time t2, counting by delay counter 35 _ON2n is started. The delay counter 35 _ON2n is a counter that counts a time tON2n defined by the power-on timing. Delay counter 35 _ON2n, when overflowed at time t3, sets flip-flop 34 _ENn, enables enable signal ENn, and starts counting of delay counter 35 _ONn1. The delay counter 35 _ONn1 is a counter that counts a time tONn1 defined by the power-on timing. When the delay counter 35 _ONn1 overflows at time t4, the count of the delay counter 35 _R1 starts. The delay counter 35 _R1 is a counter that counts the ramp time tR 1. The count value of the delay counter 35 _R1 is set so that the reference voltage signal VREF1 analog-converted by the D/a converter 36 _REF1 reaches a predetermined voltage at a time t5 when the ramp time tR2 has elapsed.

When delay counter 35 _R1 overflows at time t5, flip-flop 34 _RESET is set at time t6 delayed by delay circuit 332, and reset signal RESETn goes high (negative logic is disabled).

Thus, the enable signals EN1, EN2, ENn of the plurality of external power ICs 20 ₁、20₂、20_n are asserted in a predetermined order and at predetermined time intervals. Further, reference voltage signals VREF1, VREF2 to the external power supply IC 20 ₁、20₂ for controlling the rise time (ramp time) of the power supply voltages V1, V2 are generated by the delay counter 35 _R1、35_R2, the D/a converter 36 _REF1、36_REF2.

Next, when the VIN voltage detection circuit 32 detects that the turned-on VIN voltage is lower than the preset off voltage at time t10, an off detection signal is output from the delay circuit 33 ₁ at time t 11. The off detection signal resets the flip-flop 34 _EN1, disables the enable signal EN1, and is input to the data selector 37 _REF1. The data selector 37 _REF1 switches the digital input of the D/a converter 36 _REF1 to zero. Thus, the reference voltage signal VREF1 to the power supply IC 20 ₁ falls to zero potential at the timing of disabling the enable signal EN1 connected to the same power supply IC 20 ₁.

Further, the off detection signal resets the flip-flop 34 _RESETn, sets the reset signal RESETn to low (negative logic active), and starts counting by the delay counter 35 _OF1n. The delay counter 35 _OF1n is a counter that counts a time tOF n specified by the power-off timing. When the delay counter 35 _OF1n overflows at time t12, the flip-flop 34 _ENn is reset, the enable signal ENn is disabled, and the counting of the delay counter 35 _OFn2 is started.

The delay counter 35 _OFn2 is a counter that counts a time tOFn2 specified by the power-off timing. When the delay counter 35 _OFn2 overflows at time t13, the flip-flop 34 _EN2 is reset, the enable signal EN2 is disabled, and the enable signal EN2 is input to the data selector 37 _REF2. The data selector 37 _REF2 switches the digital input of the D/a converter 36 _REF2 to zero. Thus, the reference voltage signal VREF2 to the power supply IC 20 ₂ falls to zero potential at the timing of disabling the enable signal EN2 connected to the same power supply IC 20 ₂.

Thus, the enable signals EN1, EN2, ENn of the plurality of external power ICs 20 ₁、20₂、20_n are invalidated in a predetermined order and time interval. The reference voltage signals VREF1 and VREF2 drop to zero potential at the timing when the enable signals EN1 and EN2 connected to the same power supply IC 20 ₁、20₂ are deactivated.

Since the SoC 1 is built in the power management circuit 3, the state notification signal is output to the external power supply IC 20 ₁、20₂、20_n according to the operation state of the SoC 1, and thus the characteristics of the power supply can be changed. Although not particularly shown, the self-power management circuit 3 outputs a state notification signal, for example, while the SoC 1 is reduced in processing load and power consumption. Thereby, the power supply IC 20 ₁、20₂、20_n decreases the switching frequency or changes the transfer function of the feedback control, whereby the power supply capability can be reduced and the power consumption of the power supply IC 20 ₁、20₂、20_n itself can be reduced.

As described above, the present embodiment is a SoC 1 (semiconductor device) having a plurality of power supply channels VDD, VCORE, VCC, the plurality of power supply channels VDD, VCORE, VCC receiving supply of power supply voltages V1, V2, and Vn from a plurality of external power supply ICs 20 ₁、20₂、20_n (power supply circuits), respectively, wherein the SoC 1 has a self-power supply management circuit 3, and the self-power supply management circuit 3 outputs a plurality of control signals for controlling the plurality of power supply ICs 20 ₁、20₂、20_n, respectively.

According to this configuration, soC 1 (self-power management circuit 3) receiving supply of power supply voltages V1, V2, and Vn to power supply channels VDD, VCORE, VCC can control a plurality of external power supply circuits, and can simplify the external power supply circuits.

Further, according to the present embodiment, the plurality of control signals are a plurality of enable signals EN1, EN2, ENn for controlling the order and time intervals of power-up and power-down of the power supply voltages V1, V2, vn from the plurality of power supply ICs 20 ₁、20₂、20_n.

According to this configuration, since the SoC1 (the self-power management circuit 3) can control the timings of the power supply voltages V1, V2, and Vn, the external power supply circuit does not need to be provided with a timing control circuit for each different product, and simplification can be achieved.

Further, according to the present embodiment, the control signals are the reference voltage signals VREF1, VREF2 that control the ramp time at the time of power-up, and the reference voltage signals VREF1, VREF2 drop to the zero potential at the timing of disabling the enable signals EN1, EN2 input to the same power supply IC 20 ₁、20₂.

According to this configuration, since the SoC 1 (the self-power management circuit 3) can control the ramp times of the power supply voltages V1, V2, and Vn, the external power supply circuit does not need to prepare a circuit for ramp time control for each different product, and simplification can be achieved.

The reference voltage signals VREF1, VREF2 are not limited to control the rise (ramp) time of the power supply voltage. Even for SoC 1 that needs slope control at the time of power-off of the power supply voltage, the reference voltage signals VREF1 and VREF2 can be gradually lowered in potential without abruptly lowering to zero potential to obtain a desired specification.

The present invention is not limited to the above embodiments, and it is understood that the embodiments can be appropriately modified within the scope of the technical idea of the present invention. The number, position, shape, and the like of the structural members are not limited to the above embodiment, and may be those suitable for the practice of the present invention. In the drawings, the same components are denoted by the same reference numerals.

Claims

1. A semiconductor device having a plurality of power supply channels, wherein the plurality of power supply channels receive power supply from a plurality of external power supply circuits, wherein:

The semiconductor device includes a self-power supply management circuit that outputs a plurality of control signals for controlling the plurality of power supply circuits.

2. The semiconductor device according to claim 1, wherein

The plurality of control signals are a plurality of enable signals for controlling the order and time intervals of powering on and off the power supplies from the plurality of power circuits.

3. The semiconductor device according to claim 1, wherein

The multiple control signals are multiple reference voltage signals for controlling the slope when the power is powered on or powered off.