JP2010056512A - Solid state image sensor, methods of operating and manufacturing the same, and digital camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a solid state image sensor capable of reading data sufficiently adaptive (small variations and linear or nonlinear) to an amount of received light from a nonvolatile memory cell. <P>SOLUTION: The solid state image sensor includes: a photodetector which receives incident light and generates signal electric charges; a first transistor whose one end is connected to the photodetector and whose the other end is connected to a detection node; a second transistor whose one end is connected to the detection node; and a memory cell transistor having an electric charge storage layer, whose control gate or one end is connected to the detection node. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a solid-state imaging device, an operation method thereof, a manufacturing method thereof, and a digital camera.

2. Description of the Related Art Conventionally, MOS solid-state image sensors, CCD solid-state image sensors, CMOS solid-state image sensors, and the like are known as solid-state image sensors.

However, since these conventional solid-state imaging devices sequentially read out the matrix, the image flows when a moving subject is imaged, and it is difficult to realize a complete electronic shutter function.

In view of this, a solid-state imaging device in which pixels including a light receiving element and a nonvolatile semiconductor memory element are integrated has been proposed (see the following patent documents).

JP 2002-280537 A JP-A-8-288495 JP-A-2-26076 JP 63-109672 A

Each of the solid-state imaging devices described in the above patent documents has a photodiode directly connected to a nonvolatile memory cell transistor, and has a nonvolatile memory cell composed of an N-type MOS transistor. Some of them use a tunnel current for writing, etc., so data that sufficiently corresponds to the amount of light received (linear or nonlinear with little variation) cannot be read from the nonvolatile memory cell, and as a result, practical use It was difficult. In addition, when hot electron writing is used, there is a problem that it is difficult to realize a large-capacity solid-state imaging device.

In addition, various configurations proposed so far use a split gate type transistor, a local tunnel oxide film, and a special high voltage transistor as a nonvolatile semiconductor memory element, and a special manufacturing process is required. There was also a problem of doing.

Furthermore, the various configurations proposed so far use n-type floating gate MOS transistors as storage elements, so that the write characteristics are not sufficient, and the various configurations have low disturb resistance. There was a problem.

In addition, the various configurations proposed so far have made it difficult to configure pixels with a small number of wiring layers and small patterns.

In order to solve the above problems, in the present invention, a light receiving element that receives incident light to generate a signal charge, a first transistor having one end connected to the light receiving element and the other end connected to a detection node, and one end A solid-state imaging device comprising: a second transistor connected to a detection node; and a memory cell transistor having a charge storage layer having a control gate or one end connected to the detection node.

In order to solve the above problems, in the present invention, one end is connected to each of a plurality of light receiving elements that receive incident light and generate signal charges, and a corresponding plurality of light receiving elements, and the other end is commonly connected to a detection node. A plurality of first transistors, a second transistor having one end connected to the detection node, and a plurality of memory cell transistors each having a control gate or one end connected to the detection node and each having a charge storage layer. Provided is a solid-state imaging device.

In order to solve the above-described problems, the present invention further includes a light receiving element that receives incident light and generates a signal charge, a first transistor having one end connected to the light receiving element and the other end connected to the detection node, Operation of a solid-state imaging device comprising: a second transistor having one end connected to a detection node; and a memory cell transistor formed of a P-type MOS transistor having a control gate or a charge storage layer having one end connected to the detection node In the method, when the gate voltage of the memory cell transistor is Vg, the well voltage is Vsub, the voltage at one end is Vs, and the voltage at the other end is Vd, Vg and Vsub are set higher than Vs and Vd to accumulate charges. Provided is a method of operating a solid-state imaging device, characterized by performing injection into a layer.

In order to solve the above problems, the present invention further includes a solid-state imaging device having a plurality of pixels arranged in a matrix, wherein each of the plurality of pixels receives incident light and generates a signal charge. A first transistor having one end connected to the light receiving element and the other end connected to the detection node; a second transistor having one end connected to the detection node; and a control gate or one end connected to the detection node. In a method of operating a solid-state imaging device including a memory cell transistor having a charge storage layer, when writing data corresponding to a signal charge generated by a light receiving element to the memory cell transistor, one or more columns Provided is a method for operating a solid-state imaging device, wherein writing is performed sequentially for each row or row.

In order to solve the above problems, in the present invention, a plurality of pixels arranged in a matrix, a plurality of word lines, a first signal line and a second signal line arranged in each row, and each column In the solid-state imaging device including a plurality of bit lines and source lines arranged in each of the plurality of pixels, each of the plurality of pixels has a light receiving element that receives incident light and generates a signal charge, and a gate connected to the first signal line, A first transistor having one end connected to the light receiving element, the other end connected to the detection node, a gate connected to the second signal line, one end connected to the detection node, and the other end connected to the word line And a memory cell transistor having a charge storage layer having a control gate connected to a detection node, one end connected to a source line, and the other end connected to a bit line. Solid-state imaging device To provide. Note that the first signal line may be arranged in the column direction.

In order to solve the above problem, in the present invention, a plurality of pixels arranged in a matrix, a plurality of word lines, a first signal line, a second signal line, and a third signal arranged in each row In a solid-state imaging device including a signal line and a plurality of bit lines arranged in each column, each of the plurality of pixels includes a light receiving element that receives incident light and generates a signal charge, and a gate serving as the first signal line A first transistor having one end connected to the light-receiving element, the other end connected to the detection node, a gate connected to the second signal line, one end connected to the detection node, and the other end third; A memory cell transistor having a charge storage layer having a control gate connected to a word line, one end connected to a detection node, and the other end connected to a bit line. Solid imaging characterized by To provide a device. Note that the plurality of first signal lines, second signal lines, and third signal lines may be arranged in the column direction.

In order to solve the above problems, the present invention further includes a light receiving element that receives incident light to generate a signal charge, and a memory cell transistor having a charge storage layer that stores information corresponding to the signal charge. And calculating a difference between the read value of the memory cell transistor in the initial state and the read value of the memory cell transistor in the written state in accordance with the signal charge. An operation method of a solid-state imaging device is provided. Note that the memory cell transistor that has been written in accordance with the signal charge may be read and then erased to the initial state.

In order to solve the above problems, the present invention further includes a light receiving element that receives incident light to generate a signal charge, a first memory cell transistor having a charge storage layer that stores information corresponding to the signal charge, In a method of operating a solid-state imaging device, comprising: a memory cell transistor having two memory cell transistors; a value obtained by reading the second memory cell transistor in an initial state and a state in which writing is performed according to a signal charge The operation method of the solid-state imaging device is characterized in that the difference from the read value of the first memory cell transistor is calculated. Note that erasing is simultaneously performed on the first memory cell transistor and the second memory cell transistor, the second memory cell transistor is initialized, and then the first memory cell transistor is set in accordance with the signal charge. You may write.

In order to solve the above-described problem, in the present invention, an element isolation region that partitions the first region and the second region on the surface of the semiconductor substrate is further formed, and the first region is formed on a part of the second region and the element isolation region. The second gate electrode film is formed on the first region, the other part of the element isolation region, and the first gate electrode film, and the first region and the second region are respectively first. And patterning the first gate electrode film and the second gate electrode film so as to form a second transistor, and forming a diffusion layer connected to the first transistor in a part of the first region, A method for manufacturing a solid-state imaging device is provided.

In order to solve the above problems, in the present invention, an element isolation region that partitions the first region and the second region on the surface of the semiconductor substrate is further formed, and the first region, the second region, and the element isolation region are formed on the first region. The first gate electrode film is formed, the second gate electrode film is formed on the first gate electrode film, and the first and second transistors are formed in the first region and the second region, respectively. The solid-state imaging device is characterized in that the gate electrode film and the second gate electrode film are patterned to form a photodiode by forming a diffusion layer connected to the first transistor in a part of the first region. A manufacturing method is provided. Further, the first gate electrode film and the second gate electrode film on the first region may be electrically connected. Alternatively, the first gate electrode film and the second gate electrode film on the first region may be in contact with each other on the second region to be electrically connected.

In order to solve the above-described problem, in the present invention, an element isolation region that partitions the first region and the second region on the surface of the semiconductor substrate is further formed, and the first region is formed on a part of the second region and the element isolation region. A second gate electrode film is formed on the first region, another part of the element isolation region, and the first gate electrode film, and a first transistor is formed in the first region. The second gate electrode film is patterned to form a second transistor in the second region, and the second gate electrode film and the first gate electrode film are patterned to form the first gate electrode on the element isolation region. The solid-state imaging device is characterized in that the gate electrode film and the second gate electrode film are left and a diffusion layer connected to the first transistor is formed in a part of the first region to form a photodiode. Provide manufacturing.

In order to solve the above-described problems, the present invention further includes a semiconductor substrate, an element isolation region that partitions the first region and the second region on the surface of the semiconductor substrate, and a first gate insulation formed in the first region. A first MOS transistor having a film, a second MOS transistor formed in the second region and having a second gate insulating film, and a photodiode formed in the first region and connected to the first first MOS transistor The solid-state imaging device is characterized in that the first gate electrode film and the second gate electrode film have different film thicknesses.

In order to solve the above-described problems, the present invention further includes a semiconductor substrate, an element isolation region that partitions the first region and the second region on the surface of the semiconductor substrate, and a first gate insulation formed in the first region. A first MOS transistor having a film, a second MOS transistor formed in the second region and having a second gate insulating film, and a photodiode formed in the first region and connected to the first first MOS transistor The solid-state imaging device is characterized in that a charge storage layer is formed on the first gate electrode film.

A typical effect of the present invention is that it is possible to realize a solid-state imaging device capable of reading data from a non-volatile memory cell sufficiently corresponding to the amount of received light (linear or non-linear with little variation).

Hereinafter, the present invention will be described with reference to the drawings. When the expression “connection” is used in the text, it includes not only a direct connection but also an indirect connection through a transistor or the like, unless otherwise specified.

FIG. 1 shows a solid-state imaging device 100 of the present invention. In the solid-state imaging device 100, a plurality of word lines WL, TG lines (first control signal lines), and RG lines (second control signal lines) are arranged in the row direction. A plurality of bit lines BL and source lines SL are arranged in the column direction. The solid-state imaging device 100 has a plurality of pixels 1000... 100 m, 1010... 10 n0.

All of the plurality of pixels have the same internal configuration. The pixel 1000 includes a photodiode PD (light receiving element) that receives incident light and generates a signal charge, transistors 12 and 13, and a memory cell transistor 14 having a floating gate (which may be a charge storage layer, a nitride film, or the like). The transistor 12 has a gate connected to the TG line, one end connected to the photodiode PD, and the other end connected to the FD node. The gate of the transistor 13 is connected to the RG line, one end is connected to the FD node, and the other end is connected to the word line WL. The memory cell transistor 14 has a control gate connected to the FD node, one end connected to the bit line BL, and the other end connected to the source line SL. All the transistors are P-type, and as will be described later, writing to the memory cell transistor 14 is performed by the Back Bias Assisted Band To Band (B4) method.

With the above configuration, the photodiode PD (light receiving element) and the FD node are electrically separated by the transistor 12. The transistor 14 sets the potential of the FD node and supplies various potentials to the memory cell transistor 13. Since the bit line BL and the source line SL are independent for each column, resistance to various disturbances is increased.

In FIG. 1, the dotted lines surround the memory cell transistors 14 belonging to one column, but writing to the memory cell transistors is performed for each column. As a result, the write current required at the same time is reduced. Note that a plurality of columns may be grouped and writing may be performed for each group. In that case, the writing time is shortened. The same applies to the following description.

Further, since the source line SL is separated for each column, no disturb problem occurs.

FIG. 2 shows a solid-state imaging device 200 which is a modification of the present invention. Looking at the configuration of the four pixels, a plurality of photodiodes PD1, PD2, PD3, and PD4 that receive incident light and generate signal charges, and one ends thereof are connected to the corresponding photodiodes PD1, PD2, PD3, and PD4, A plurality of transistors 22, 23, 24 and 25 whose other ends are commonly connected to the FD node, a transistor 21 whose one end is connected to the word line WL and the other end is connected to the FD node, and a control gate which is an FD node And a plurality of memory cell transistors 26, 27, 28 and 29 each having a charge storage region.

With the above configuration, the transistor 21 is shared by the four photodiodes PD, and a pixel can be configured with a small area. As described above, writing is performed for each column. As a result, the write current required at the same time is reduced. Further, since the source line SL is separated for each column, no disturb problem occurs.

FIG. 3 shows an operation sequence. Take a solid-state image sensor composed of 10 Mb pixels as an example.

First, the 10 Mb memory cell transistors are erased all at once (step 31). FIG. 4 shows the voltage applied to each node during erasing. -10 V is applied to the control gate of the memory cell transistor 14 and 10 V is applied to the well region, and electrons in the floating gate are tunneled and emitted to the well region. When the tunnel oxide film is about 5 nm, it is possible to lower the voltage, while the Vpp transistor (high voltage transistor) needs to have an oxide film thickness of about 15 nm. Further, an erase gate may be provided on the side wall of the floating gate to reduce the voltage.

Subsequently, initial writing after batch erasure is performed (step 32). The initial writing method is performed by repeating writing in units of columns by the number of columns (or the number of groups). FIG. 5 shows the voltage applied to each node during writing. 5V applied to the word line WL is transmitted to the control gate of the memory cell transistor 14 by the transistor 13. 8V is applied to the well region. Then, by setting both the bit line BL and the source line SL to 0V, electrons are charged in the floating gate.

Subsequently, the initial writing state is read (step 33). Reading is performed in units of rows, details of which will be described later.

Subsequently, writing according to the amount of charge generated in the photodiode PD is performed (step 34). The writing method is performed by repeating writing in units of columns by the number of columns (or the number of groups). When the voltage applied to the control gate of the memory cell transistor is Vg, the voltage applied to the well is Vsub, the voltage applied to the source line SL is Vs, and the voltage applied to the bit line BL is Vd, then Vg and Vsub> Vs and Vd condition (Back Bias Assisted Band To Band (B4) method). As shown in FIG. 6, when charge is injected, a voltage (6.5 V to 8 V) depending on the amount of light is applied to the FD node, and the charge is held in the charge storage layer of the memory cell transistor 14 according to this voltage. . FIG. 7 is a chart showing the voltage applied to each node. First, the photodiode PD and the node FD are precharged (reset). Subsequently, the charge generated in the photodiode PD is sensed at the FD node, and TG becomes 8V, whereby the transistor 12 is turned off, and the voltage at that time is held at the FD node. Next, the program (Program) is performed by setting the bit line BL and the source line SL to 0V.

Finally, reading from the memory cell transistor is performed. Reading is performed in units of rows. As shown in FIG. 8, the source line SL is set to Vcc (power supply voltage, for example, 3 V), and the bit line BL is connected to a sense amplifier (current comparison type differential amplifier) (a sense voltage is applied to the bit line BL). Is equivalent to.) Then, the potential of the control gate of the memory cell transistor 14 is set to −2V. Here, when the current source Iref compared by the sense amplifier is changed, the amount of current flowing through the memory cell transistor 14 can be measured. In the present invention, a current output substantially proportional to the amount of light received by the photodiode PD can be obtained by using the transistors 12 and 13 and using the B4 method for writing. FIG. 9 illustrates IV characteristics of the memory cell transistor 14. Immediately after the initial writing (PGM) after erasing (ERS), the characteristic is shown by the graph on the left side of the figure. When a voltage of −2 V is applied to the control gate, the current amount shown by 91 in the figure is obtained. However, when writing is performed according to the amount of light received by the photodiode PD, the characteristics shown by the graph on the right side of the figure are obtained, and when a voltage of −2 V is applied to the control gate, the current quantity shown by 92 in the figure is obtained. This difference 93 is substantially proportional to the amount of light received by the photodiode PD.

A first embodiment of the present invention will be described with reference to FIGS.

FIG. 10 is a plan view of the first embodiment of the present invention. An N-type well n-well is formed on a P-type semiconductor substrate surface p-sub, and active regions 1131 and 1133 that become sources, drains, channels, photodiodes, and the like are partitioned as shown in FIG. . The active region 1131 includes a photodiode region 1132 where the photodiode PD is to be formed and a region extending from this region. Over these regions, polysilicon patterns 1104, 1105, and 1106 are formed via a gate insulating film. The polysilicon pattern 1105 has a two-layer structure, in which a pattern serving as a control gate is formed in the upper layer and an isolated pattern serving as a floating gate is formed in the lower layer, both of which are formed on a part of the active region 1133, and A floating gate and a control gate of the cell transistor 1103 are formed. A polysilicon pattern 1106 is formed in the vicinity of the end of the region extending from the active region 1131 and constitutes the gate of the transistor 1102. The polysilicon pattern 1104 is formed across the region extending from the active region 1131 and constitutes the gate of the transistor 1101. On these polysilicon patterns, the metal pattern 1107 (word line), 1108 (TG line), 1109 (active region 1131 and the control gate of the memory cell transistor 1103) made of a one-layer metal wiring are formed on the polysilicon pattern via an interlayer insulating film. Electrical connection) is formed. Further, metal patterns 1141 (bit lines BL) and 1142 (source lines SL) made of two-layer metal wirings are formed on these first-layer metal wirings.

The write operation is as shown in FIG. Focusing on the memory cell transistor 1103, the n-well voltage Vsub is 9V, the applied voltage Vs of the source line SL is Vcc (power supply voltage, 3V), the applied voltage Vd of the bit line BL is 0V, and the control gate (detection node). The voltage applied to the FD is approximately 6.5 to 8 V depending on the amount of received light. At the same time, all the column circuits can be realized with Vcc transistors (transistors that do not have a high breakdown voltage). The TG line becomes high level immediately before the write operation, and the transistor 1101 becomes non-conductive, so that the potential of the detection node FD (control gate) faithfully reproduces the amount of received light.

The read operation is as shown in FIG. Focusing on the memory cell transistor 1103, the n-well voltage Vsub is Vcc, the applied voltage Vs of the source line SL is Vcc, the bit line BL is sense (connected to one input terminal of a current comparison type differential amplifier), a control gate ( The voltage applied to the word line WL through the transistor 1102 in the conductive state appears.) Is −2V. As a result, a current corresponding to the amount of received light flows through the bit line.

The erase operation is as shown in FIG. Focusing on the memory cell transistor 1103, the n-well voltage Vsub is 10V, the applied voltage Vs of the source line SL is 10V, the applied voltage Vd of the bit line BL is also 10V, the control gate (the word line via the transistor 1102 in the conductive state). The voltage applied to the WL appears as -10). As a result, the charge accumulated in the floating gate is released by the tunnel current.

With the above configuration, the amount of received light can be faithfully reproduced as read data, and a small area pixel, a small metal wiring layer, and efficient writing can be realized.

A second embodiment of the present invention will be described with reference to FIGS.

FIG. 14 is a plan view of a second embodiment of the present invention. An N-type well n-well is formed on a P-type semiconductor substrate surface p-sub, and an active region 1401 serving as a source / drain / channel / photodiode or the like is partitioned in the element isolation region as shown in FIG. The active region 1401 includes a photodiode region 1402 in which the photodiode PD is to be formed, a region 1402 extending from this region, and a region 1403 extending in a branched manner. On these regions, polysilicon patterns 1405, 1406, and 1407 are formed via a gate insulating film. The polysilicon pattern 1406 is a two-layer structure pattern, in which an upper layer pattern is formed as a control gate, and a lower layer is formed as an isolated pattern serving as a floating gate. A floating gate and a control gate of the cell transistor 1502 are formed. A polysilicon pattern 1407 (RST line) is formed in the vicinity of the end portion of the region extending from the active region 1402 and constitutes the gate of the transistor 1503. The polysilicon pattern 1405 is formed across the region extending from the active region 1402 and constitutes the gate of the transistor 1501. On these polysilicon patterns, metal patterns 1405 (VP lines) 1409 (word lines WL) and 1410 (TG lines) made of one-layer metal wiring are formed via an interlayer insulating film. Further, a metal pattern 1411 (bit line BL) made of a two-layer metal wiring is formed on the first-layer metal wiring.

The write operation is as shown in FIG. First, the VP line is set to 0V, the RST is set to -2V, and the transistor 1503 is turned on. At the same time, the TG line is set to 0V and the transistor 1501 is turned on, and the output of the photodiode PD and the detection node FD are preset to 0V. Then, the program operation is started. Focusing on the memory cell transistor 1502 at the time of programming, the n-well voltage Vsub is 8V, the applied voltage Vs of the bit line BL is Vcc (power supply voltage, 3V), the applied voltage Vg of the control gate (word line WL) is 9V, The drain voltage Vd is about 0 to 3 V depending on the amount of received light. As a result, Vg> Vsub> Vs> Vd, Vsub> 0, and Vd = <Vcc can be realized, so that efficient B4 writing is possible. At the same time, all the column circuits can be realized with Vcc transistors (transistors that do not have a high breakdown voltage). The TG line becomes high level immediately before the write operation, and the transistor 1101 becomes non-conductive, so that the potential of the detection node FD (control gate) faithfully reproduces the amount of received light.

The read operation is as shown in FIG. Focusing on the memory cell transistor 1502, the n-well voltage Vsub is Vcc, the bit line BL is sense (connected to one input terminal of a current comparison type differential amplifier), the applied voltage to the word line WL is -2V, and the detection node FD. The potential Vd becomes Vcc. As a result, a current corresponding to the amount of received light flows through the bit line.

The erase operation is as shown in FIG. Focusing on the memory cell transistor 1502, the n-well voltage Vsub is 10 V, and the applied voltage of the word line is -10. As a result, the charge accumulated in the floating gate is released by the tunnel current. In the figure, Hiz means a high impedance state.

With the above configuration, the amount of received light can be faithfully reproduced as read data, and a small area pixel, a small metal wiring layer, and efficient writing can be realized.

A third embodiment of the present invention will be described with reference to FIGS.

FIG. 18 is a circuit configuration diagram of a solid-state imaging device according to the third embodiment of the present invention. FIG. 19 is an explanatory diagram illustrating the operation of the solid-state imaging device according to the third embodiment of the present invention.

As shown in FIG. 18, the solid-state image sensor according to the third embodiment of the present invention includes a photodiode PD, transistors 12, 13 and a nonvolatile memory element 14, and is similar to the solid-state image sensor 100 shown in FIG. A circuit configuration is adopted (however, a plate line PL that runs orthogonal to the bit line is formed instead of the source line SL that runs parallel to the bit line BL). The transistor 12 has a gate connected to the TG line, one end connected to the photodiode PD, and the other end connected to the FD node. The gate of the transistor 13 is connected to the RG line, one end is connected to the FD node, and the other end is connected to the word line WL. The nonvolatile memory element 14 has a control gate connected to the FD node, one end connected to the bit line BL, and the other end connected to the plate line PL. Although not shown, the peripheral region of the solid-state imaging device is provided with two buffer memories (referred to as latches arranged in a row), and can temporarily store read data to be described later. It is like that.

Next, write and read operations of the nonvolatile memory element in the solid-state imaging device according to the third embodiment will be described with reference to FIG. FIG. 19 shows the operations of the exposure step and the reading step of the nonvolatile memory element (NVM) in order from the left in the column of the table, and shows the voltage application conditions of each node in each operation.

In the exposure step, first, collective erasure of charges accumulated in the floating gate of the nonvolatile memory element 14 is performed. When -13V is applied to the word line WL and -14V is applied to the RG line, and the TG line, well region, plate line PL, and bit line BL are set to Vcc, the charge accumulated in the floating gate is released and erased. The

Subsequently, PD / NVM reset is performed on the photodiode PD and the nonvolatile memory element 14. When 7V is applied to the word line WL and the photodiode PD, 0V is applied to the RG line and TG line, 10V is applied to the well region, 0V is applied to the plate line PL, and 3V is applied to the bit line BL, the photodiode PD and the nonvolatile memory element 14 Is weakly written, and the initial charge is retained.

Subsequently, NVM writing is performed in which signal charges from the photodiodes by exposure are written in the nonvolatile memory element 14. When not applied to the word line WL, 10V applied to the RG line, 10V applied to the well region, 0V applied to the plate line PL, 3V applied to the bit line BL, and the applied voltage from the photodiode PD increased from 7V to 10V by exposure. Exposure data is written into the nonvolatile memory element 14.

Next, the operation of the reading step will be described. Following the NVM writing operation, reading 1 for reading exposure data is performed first. Here, the exposure data is read in a state including the initial charge. When -5V is applied to the word line WL, -6V is applied to the RG line, the TG line, well region, and plate line PL are set to Vcc, and the bit lines BL and / BL are set to 0V, the charge accumulated in the nonvolatile memory element 14 A signal charge corresponding to the signal flows through the bit line BL and is read out by a sense amplifier or the like (not shown) connected to the bit line BL. The read data is temporarily stored in a first buffer memory (not shown).

Subsequently, before erasing the exposure data, writing before erasure is performed. When 10V is applied to the word line WL, 0V to the RG line, 10V to the TG line, 10V to the well region, 0V to the plate line PL, and 3V to the bit line BL, weak writing is performed on the nonvolatile memory element 14, The nonvolatile memory element 14 is in a state where a substantially constant charge is accumulated, and variations in write characteristics (for example, threshold value) of the nonvolatile memory element 14 are reduced. This pre-erase writing may be selectively performed only on cells for which writing is insufficient.

Subsequently, the exposure data is erased. When -13V is applied to the word line WL and -14V is applied to the RG line, and the TG line, well region, plate line PL, and bit line BL are set to Vcc, the charge accumulated in the floating gate is released.

Subsequently, an NVM reset for storing the initial charge in the floating gate is performed. When 7V is applied to the word line WL, 0V is applied to the RG line, 10V is applied to the TG line, 10V is applied to the well region, 0V is applied to the plate line PL, and 3V is applied to the bit line BL, the nonvolatile memory element 14 is weakly written. The initial charge is stored.

Subsequently, reading 2 for reading the initial state is performed. When -5V is applied to the word line WL, -6V is applied to the RG line, and the TG line, well region, and plate line PL are set to Vcc, the signal charge in the initial state flows to the bit line BL and the sense connected to the bit line BL. It is read by an amplifier or the like (not shown). The read data is temporarily stored in a second buffer memory (not shown).

Finally, the difference between the exposure data stored in the buffer memory by reading 1 and reading 2 and the data corresponding to the current amount or voltage value corresponding to the signal charge in the initial state is detected. This detection may be performed by sequentially reading data from the first and second buffer memories, calculating a difference between them, and writing back to the first buffer memory, or a hardware that simultaneously calculates differences between a large number of data. You may detect a difference collectively using wear. Thereby, the difference between the state in which writing is performed in the nonvolatile memory element 14 corresponding to the signal intensity from the photodiode PD (light receiving element) and the initial state is detected.

Further, a nonvolatile memory element in the solid-state imaging device according to the third embodiment of the present invention will be described with reference to FIGS. FIG. 20 is an explanatory diagram showing the write characteristic distribution of the conventional nonvolatile memory element, and FIG. 21 is an explanatory diagram showing the write characteristic distribution of the nonvolatile memory element according to the third embodiment of the present invention.

In FIG. 20, the horizontal axis represents the characteristic value (for example, threshold value) of the nonvolatile memory element, and the vertical axis represents the number of nonvolatile memory elements having the characteristic. On the other hand, the characteristic distribution when writing is performed under the same conditions is shown. When a floating gate type nonvolatile memory element is used, the average value of the threshold shift amount due to writing is generally several volts, whereas the characteristic variation of 10M nonvolatile memory elements is about several volts. spread. In a state having such a characteristic variation, it is difficult to store the signal from the light receiving element in the nonvolatile memory element with a desired accuracy.

As shown in FIG. 21, in the nonvolatile memory element according to the third embodiment of the present invention, the weak write state is set as the initial state, and the difference between the write state for each nonvolatile memory element is obtained. It was confirmed that the variation can be reduced to about 1/10. That is, the signal can be stored with an accuracy of 10% or less with respect to the signal intensity by the operation of taking the difference.

With the above configuration, the nonvolatile memory element according to the third embodiment of the present invention forms an initial state by performing weak writing on the nonvolatile memory elements of all the pixels, and the signal charge after exposure. The write operation variation of the non-volatile memory element is performed in order to perform the operation of writing to the non-volatile memory element of each pixel in accordance with the operation and the operation of obtaining the difference between the state of the non-volatile memory element after exposure and the initial state. Can be reduced.

A fourth embodiment of the present invention will be described with reference to FIGS.

FIG. 22 is a circuit configuration diagram of a solid-state imaging device according to the fourth embodiment of the present invention. FIG. 23 is an explanatory diagram illustrating the operation of the solid-state imaging device according to the fourth embodiment of the present invention.

As shown in FIG. 22, the fourth embodiment of the present invention is a modification of the third embodiment, and the circuit configuration is the same as that of the third embodiment in that it includes two nonvolatile memory elements per pixel. Different. The solid-state imaging device according to the fourth embodiment of the present invention includes a photodiode PD, transistors 12, 13 and nonvolatile memory elements 14a, 14b. The transistor 12 has a gate connected to the TG line, one end connected to the photodiode PD, and the other end connected to the FD node. The gate of the transistor 13 is connected to the RG line, one end is connected to the FD node, and the other end is connected to the word line WL. The two nonvolatile memory elements are composed of two nonvolatile memory elements: an exposure data storage element 14a that performs an operation of writing in accordance with a signal charge after exposure, and an initial state storage element 14b that performs an operation of forming an initial state. Become. The exposure data storage element 14a has a control gate connected to the FD node, one end connected to the bit line BL, and the other end connected to the plate line PL. The initial state storage element 14b has a control gate connected to the FD node, one end connected to the bit line / BL, and the other end connected to the plate line / PL.

Next, write and read operations of the nonvolatile memory element in the solid-state imaging device according to the fourth embodiment will be described with reference to FIG. FIG. 23 shows the operations of the exposure step and the reading step of the nonvolatile memory element (NVM) in order from the left in the column of the table, and shows the voltage application conditions of each node in each operation.

First, during the exposure step, batch erasure is performed first. Since the batch erase is the same as the batch erase operation in the third embodiment, a detailed description is omitted.

Subsequently, PD / NVM reset is performed. When 7V is applied to the word line WL and the photodiode PD, Vcc is applied to the RG line, 0V is applied to the TG line, 10V is applied to the well region, 0V is applied to the plate lines PL and / PL, and 3V is applied to the bit lines BL and / BL. Weak writing is performed on the diode PD and the nonvolatile memory elements 14a and 14b, and the initial charge is stored.

Subsequently, NVM writing is performed. Without applying to the word line WL, 10V is applied to the RG line, 10V is applied to the well region, 0V is applied to the plate line PL, 3V is applied to the plate line / PL, and the bit lines BL and / BL. When the voltage increases from 7V to 10V, the exposure data is written only in the nonvolatile memory element 14a that stores the exposure data.

Next, reading is performed. When -5V is applied to the word line WL and -6V is applied to the RG line, the TG line, the well region, the plate lines PL and / PL are set to Vcc, and the bit lines BL and / BL are set to 0 V, they are stored in the nonvolatile memory element 14a. The signal charge of the exposed exposure data flows to the bit line BL, and the signal charge in the initial state stored in the nonvolatile memory element 14b flows to the bit line / BL. The exposure data and the initial signal charge are read out by a sense amplifier or the like (not shown) connected to the bit lines BL and / BL.

Here, the current (or sense amplifier output) that flows through the exposure data storage element 14a and the current (or sense amplifier output) that flows through the initial state storage element 14b are compared, and the difference between them is taken to obtain the photodiode PD (light receiving element). The data corresponding to the signal intensity from) is accurately read without variation. In this embodiment, by simultaneously reading from the elements 14a and 14b, the difference can be calculated without using a buffer memory or the like.

Subsequently, writing before erasure is performed. When 10V is applied to the word line WL, Vcc to the RG line, 10V to the TG line, 10V to the well region, 0V to the plate lines PL and / PL, and 3V to the bit lines BL and / BL, weak writing to the floating gate As a result, the variation in write characteristics (for example, threshold value) of the nonvolatile memory element 14 can be reduced before performing batch erase, which is the first operation when proceeding to the next exposure step. it can.

With the above configuration, the solid-state imaging device according to the fourth embodiment of the present invention can receive data corresponding to the amount of received light from the nonvolatile memory element with sufficient accuracy in the nonvolatile memory element, as in the third embodiment. A solid-state imaging device that can be read can be realized.

Further, the manufacturing process and the structure of the solid-state imaging device according to the fifth to eighth embodiments of the present invention will be described with reference to FIGS. The solid-state imaging devices according to the fifth to eighth embodiments of the present invention each include one or more nonvolatile memory elements, photodiodes, and MOS transistors in one pixel.

24A to 24G are schematic cross-sectional views showing the manufacturing process of the solid-state imaging device according to the fifth embodiment of the present invention, and show the manufacturing process up to the transistor process.

In the manufacturing process of the solid-state imaging device according to the fifth example, first, a thin SiO ₂ film is formed by thermally oxidizing Si crystal on the silicon substrate 10 shown in FIG. 24A (not shown). Next, a SiN film is formed by a CVD (Chemical Vapor Deposition) method. On top of that, a photoresist is applied, exposed and developed to form a pattern, and using this as a mask, etching is performed in the order of SiN / SiO ₂ / Si by a dry etching method to form a trench (shallow trench). When the SiO ₂ film is deposited by the CVD method to completely fill the trench, and the SiO ₂ film and the SiN film deposited on the surface of the silicon substrate 10 are removed by the CMP (Chemical Mechanical Polishing) method, element isolation is performed only in the trench. A separation structure (FIG. 24B) in which 11 is embedded is obtained.

The element isolation 11 used here is an STI (Shallow Trench Isolation) isolation film, but may be a LOCOS (Local Oxidation of Silicon) film formed by thermal oxidation, or other types of isolation oxide films. There may be.

Subsequently, an n-type well (p-well) or the like is appropriately formed on the silicon substrate in the region where the MOS transistor and the nonvolatile memory element are formed by annealing after ion implantation. (Not shown).

Subsequently, although not shown, a first gate insulating film 5a made of SiO ₂ is formed by thermal oxidation or the like, and PolySi is deposited on the first gate insulating film 5a by a CVD method. 1 gate electrode film 17a is formed. As shown in FIG. 24C, the first gate electrode film 17a and the first gate insulating film 5a are formed by photolithography and dry etching up to the element isolation 11 which is the boundary between the non-volatile memory element and the MOS transistor. It is set as the structure which laminated | stacked.

Subsequently, as shown in FIG. 24D, the second gate insulating film 5b made of SiO _{2 is formed} by using the CVD method, and the second gate electrode film 17b is formed on the second gate insulating film 5b by using PolySi. And WSi ₂ are deposited by the CVD method to form a film.

Subsequently, as shown in FIG. 24E, a photoresist 19 is applied on the second gate electrode film 17b to form gate patterns of MOS transistors and nonvolatile memory elements. As shown in FIG. The gate electrode film 17b and the second gate insulating film 5b are etched by a dry etching method. At this time, the second gate electrode film 17b made of PolySi is etched by using a halogen-based gas such as Cl ₂ or HBr as the plasma gas, and the second gate electrode film 17 made of SiO ₂ is used by using CF ₄ or the like as the plasma gas. The second gate insulating film 5b is etched.

Subsequently, the first gate electrode film 17a and the first gate insulating film 5a are etched by a dry etching method. At this time, the first gate electrode film 17a is etched by using a halogen-based gas such as Cl ₂ or HBr as the plasma gas. Further, at the same time as etching the first gate electrode film 17a, regions other than the photoresist 19 and the element isolation 11 not masked by the first gate insulating film 5a are etched on the surface of the silicon substrate 10. Further, by using CF ₄ or the like as the plasma gas, the first gate insulating film 5a made of SiO ₂ is etched. After the etching, the photoresist 19 is peeled off by oxygen plasma or the like.

Finally, as shown in FIG. 24G, ion implantation is performed to form the source 15 and drain 16 of the nonvolatile memory element 4 and the drain 16 of the MOS transistor 2. At this time, ion implantation is performed using B (boron) for a P-type MOS and P (phosphorus) or AS (arsenic) for a N-type MOS dopant. Further, as shown in FIG. 24G, the photodiode 1 is formed and connected to the source portion of the MOS transistor 2.

Through the above manufacturing process, the solid-state imaging device according to the fifth embodiment of the present invention is formed. However, as described above, the photodiode 1 and the drain 16 of the MOS transistor 2 are formed in a portion where the surface of the silicon substrate 10 is etched as shown in FIG. 24G.

Therefore, in order to improve the problem of etching the silicon substrate, a manufacturing process of the solid-state imaging device according to the sixth embodiment of the present invention will be described with reference to FIGS. 25A to 25F.

25A to 25F are schematic cross-sectional views showing the manufacturing process of the solid-state imaging device according to the sixth embodiment of the present invention.

In the manufacturing process of the solid-state imaging device according to the sixth embodiment, first, as shown in FIGS. 25A and 25B, the element isolation region 11 is formed on the silicon substrate 10. Subsequently, an n-type well (n-well) or a p-type well (p-well) is formed by annealing after ion implantation in the silicon substrate 10 in a region where a MOS transistor and a nonvolatile memory element are to be formed (FIG. Not shown). Since the above process is the same as the manufacturing process according to the fifth embodiment, detailed description thereof is omitted.

Subsequently, as shown in FIG. 25C, a first gate insulating film 5a made of SiO ₂ is formed by the CVD method, and PolySi is deposited on the first gate insulating film 5a by the CVD method. A gate electrode film 17a is formed. Further, as shown in FIG. 25D, a second gate insulating film 5b made of SiO ₂ is formed by the CVD method, and PolySi and WSi ₂ are deposited on the second gate insulating film 5b by the CVD method. Second gate electrode film 17b is formed.

Subsequently, as shown in FIG. 25E, the gate pattern of the MOS transistor and the nonvolatile memory element is formed with the photoresist 19, and the second gate electrode film 17b, the second gate insulating film 5b, and the first gate electrode film are formed. 17a and the first gate insulating film 5a are etched by a dry etching method. The photoresist 19 is peeled off by oxygen plasma or the like.

Subsequently, as shown in FIG. 25F, the first gate electrode 7a and the second gate electrode 7b of the MOS transistor 2 are replaced with a metal wiring layer or the like in a region different from this cross section, for example, somewhere on the element isolation insulating film. And electrically connect.

Finally, as shown in FIG. 25F, ion implantation is performed to form the source 15 and drain 16 of the nonvolatile memory element 4 and the drain 16 of the MOS transistor 2. Further, as shown in FIG. 25F, the photodiode 1 is formed and connected to the source portion of the MOS transistor 2.

Through the above steps, the manufacturing process of the solid-state imaging device according to the sixth embodiment of the present invention is such that a MOS type transistor is formed in a double gate structure, and two gates are electrically connected to each other to form a normal MOS. An element that operates in the same manner as a transistor can be realized, and a MOS transistor and a nonvolatile memory element can be formed in one pixel without unnecessary etching of the silicon substrate.

Next, a manufacturing process of the solid-state imaging device according to the seventh embodiment of the present invention will be described with reference to FIGS.

26A to 26F are schematic cross-sectional views showing the manufacturing process of the solid-state imaging device according to the seventh embodiment of the present invention.

As shown in FIGS. 26A to 26C, the manufacturing process of the solid-state imaging device according to the seventh embodiment is the same as the manufacturing process according to the sixth embodiment until the first gate electrode film 17a is formed. Therefore, detailed description is omitted.

As shown in FIG. 26D, a second gate insulating film 5b made of SiO ₂ is formed on the first gate electrode film 17a by using the CVD method, and the second gate insulating film is formed by photolithography and dry etching. The opening 18 in the film 5b is formed in a region narrower than the region that becomes the gate electrode of the MOS transistor. Further, PolySi and WSi ₂ are deposited on the second gate insulating film 5b by the CVD method, thereby forming the second gate electrode film 17b. As a result, the second gate electrode film 17 b is embedded in the opening 18, and the first gate electrode film 17 a and the second gate electrode film 17 b are electrically connected by the insulating film opening 18. It becomes a structure.

Subsequently, as shown in FIG. 26E, a photoresist 19 is applied to form a gate pattern of the MOS transistor and the nonvolatile memory element, and the second gate electrode film 17b, the second gate insulating film 5b, The gate electrode film 17a and the first gate insulating film 5a are etched by dry etching. Thereafter, the photoresist 19 is peeled off by oxygen plasma or the like.

Finally, as shown in FIG. 26F, ion implantation is performed to form the source 15 and drain 16 of the nonvolatile memory element 4 and the drain 16 of the MOS transistor 2. Further, as shown in FIG. 26F, the photodiode 1 is formed and connected to the source portion of the MOS transistor 2.

Through the above steps, the manufacturing process according to the seventh embodiment of the present invention is such that a MOS transistor is formed with a double gate structure, an insulating film between two gates is opened and electrically connected. An element that operates in the same manner as a normal MOS transistor is realized, and a MOS transistor and a nonvolatile memory element can be formed in one pixel without unnecessary etching of the silicon substrate.

Next, a manufacturing process of the solid-state imaging device according to the eighth embodiment of the present invention will be described with reference to FIGS.

27A to 27G are schematic cross-sectional views each showing a manufacturing process for a solid-state imaging device according to the eighth embodiment of the present invention.

As shown in FIGS. 27A to 27D, the manufacturing process of the solid-state imaging device according to the eighth embodiment is the same as the manufacturing process according to the fifth embodiment until the second gate electrode film 17b is formed. Therefore, detailed description is omitted.

As shown in FIG. 27E, a gate pattern of a MOS transistor is formed on the second gate electrode film 17b that is not stacked on the first gate electrode film 17a with the photoresist 19, and the first gate electrode film 17a is formed. A photoresist 19 is coated so as to cover the second gate electrode film 17b stacked on the upper surface of the element isolation 11 at the boundary between the MOS transistor and the non-volatile memory element. . The second gate electrode film 17b is etched by dry etching, and after the etching, the photoresist 19 is peeled off by oxygen plasma or the like.

Subsequently, as shown in FIG. 27F, the gate pattern of the nonvolatile memory element is formed on the second gate electrode film 17b stacked on the first gate electrode film 17a with the photoresist 19, and the MOS transistor A photoresist 19 is coated on the region where the semiconductor device is formed so as not to exceed the element isolation 11 at the boundary between the region where the MOS transistor and the nonvolatile memory element are formed. The second gate electrode film 17b, the second gate insulating film 5b, the first gate electrode film 17a, and the first gate insulating film 5a are etched by dry etching. Peel off with plasma.

Finally, as shown in FIG. 27G, ion implantation is performed to form the source 15 and drain 16 of the nonvolatile memory element 4 and the drain 16 of the MOS transistor 2. Further, as shown in FIG. 27G, the photodiode 1 is formed and connected to the source portion of the MOS transistor 2.

Through the above steps, the manufacturing process according to the eighth embodiment of the present invention provides a single / double gate coexistence structure region between the double gate structure formation region and the single gate structure formation region of the MOS transistor, Thus, a MOS transistor and a nonvolatile memory element can be formed in one pixel without unnecessarily etching the silicon substrate.

Further, the structure of the solid-state imaging device according to the ninth embodiment of the present invention will be described with reference to FIGS.

FIG. 28 is a schematic sectional view showing a first solid-state imaging device according to the ninth embodiment of the present invention. The first solid-state imaging device according to the ninth embodiment has a first MOS transistor 2 and a second MOS transistor 3, and the first gate insulation of the first MOS transistor 2 as shown in FIG. The film 5 a is thicker than the second gate insulating film 5 b of the second MOS transistor 3.

FIG. 29 is a schematic sectional view showing a second solid-state imaging device according to the ninth embodiment of the present invention. The second solid-state imaging device according to the ninth embodiment has a first MOS transistor 2 and a second MOS transistor 3, and the second MOS transistor 3 has a charge storage layer 6, as shown in FIG. As shown, the first gate insulating film 5 a of the first MOS transistor 2 is thicker than the second gate insulating film 5 b of the second MOS transistor 3.

FIG. 30 is a schematic cross-sectional view showing a third solid-state imaging device according to the ninth embodiment of the present invention. The third solid-state imaging device according to the ninth embodiment has a MOS transistor 2 and a nonvolatile memory element 4, and the first gate insulating film 5a of the MOS transistor 2 is a nonvolatile memory element as shown in FIG. 4 thicker than the second gate insulating film 5b.

As described above, in the solid-state imaging device according to the ninth embodiment of the present invention, a MOS type transistor handling a high voltage is applied with a structure having a thicker gate insulating film than a transistor handling a normal power supply voltage. Thus, a high voltage can be used when writing / erasing information to / from the nonvolatile memory element in each pixel.

31 to 39 show circuit configurations of a solid-state imaging device using the photodiode 1 and the MOS transistors 2 and 3 formed by the manufacturing methods of Examples 6 to 9, respectively. FIG. 31 shows a circuit configuration similar to that of the first embodiment of the present invention. The MOS transistors 12 and 13 correspond to the MOS transistor 2, and the memory cell 14 corresponds to the MOS transistor 3 or the nonvolatile memory element 4, respectively. FIG. 32 shows a circuit configuration similar to that of the third embodiment of the present invention. The MOS transistors 12 and 13 correspond to the MOS transistor 2, and the memory cell 14 corresponds to the MOS transistor 3 or the nonvolatile memory element 4, respectively. FIG. 33 shows a circuit configuration similar to that of the fourth embodiment of the present invention. The MOS transistors 12 and 13 correspond to the MOS transistor 2, and the memory cells 14a and 14b correspond to the MOS transistor 3 or the nonvolatile memory element 4, respectively. 34 to 36 are circuits in which the PN of the circuits of FIGS. 31 to 33 is inverted. 37 to 39 are examples in which each MOS transistor except the memory cell transistors in the circuits of FIGS. 31 to 33 is formed of an n-type MOS transistor.

FIG. 40 is a schematic block diagram showing the digital camera of this embodiment. The solid-state imaging device described in Examples 1 to 10 is used. In the figure, reference numeral 101 denotes the entire digital camera. Reference numeral 102 denotes a lens that forms a subject image, 103 denotes a diaphragm mechanism that adjusts the amount of incident light from the lens 102, 104 denotes a solid-state imaging device that converts an optical signal incident from the lens 102 through the diaphragm mechanism 103 into an electrical signal, and 105. Is a CDS / AGC circuit for sampling and gain-controlling the signal photoelectrically converted by the solid-state imaging device 104, and 106 is an analog / digital converter (hereinafter referred to as a digital signal) for converting an analog signal output from the CDS / AGC circuit 105 (Denoted as A / D converter), 111 is a camera signal processing circuit for performing predetermined processing on the signal A / D converted by the A / D converter 106, and 113 is a microcomputer for controlling the entire digital camera ( (Hereinafter referred to as CPU) 119 represents a digital signal output from the camera signal processing circuit 111 as C A recording device (hereinafter referred to as a memory) that temporarily stores data via U113, 110 compresses the raw image data output from the camera signal processing circuit 111 using a compression algorithm such as JPEG, or decompresses the compressed image An image compression / decompression circuit for generating an image for display; 112, an image display memory for holding a video signal output to the LCD liquid crystal display device 108; 107, a digital for converting the digital signal output to the image display memory into an analog signal An analog converter (hereinafter referred to as a D / A converter), 108 is an LCD liquid crystal display device that displays an analog video signal output from the D / A converter 107 to the user, and 120 is temporarily stored in the memory 119 A secondary recording device 118 such as a memory card or a disk for storing stored image data in the form of an image file; A card interface (hereinafter referred to as a card I / F) for writing and reading image data to and from the recording device 120, 121 (121-1 to 121-3) are other devices on the network, and 117 is a network interface. This is a communication interface (hereinafter referred to as communication I / F) for connecting to another device 121. Here, the other device 121 on the network is a device capable of transmitting image data held in the device to an external device. Specifically, a digital camera, a flatbed scanner, a personal computer, etc. Conceivable. Further, the communication I / F 117 does not have to be wired, and may use a wireless LAN device or the like. Further, various existing types of communication protocols with other devices 121 on the network can be considered. As a combination of the communication I / F 117 and the communication protocol, specifically, a PTP protocol in the case of a USB interface, SBP2 in the case of IEEE1394, a digital camera profile in the case of BlueTooth, or the like can be considered.

Reference numeral 116 denotes communication management means for managing communication with other devices 121 on the network. In a situation where a plurality of devices 121 are simultaneously connected to the digital camera 101, the 116 manages communication with each device 121. . Reference numeral 115 denotes image management means for managing the image data received from the plurality of apparatuses 121 by the communication management means 116 for each apparatus 121, and 114 controls the group of images managed by the image management means 115. It is an image display means for displaying automatically.

The present invention can be used for a digital camera or the like using a solid-state imaging device.

It is a circuit block diagram of the solid-state imaging device of this invention. It is a circuit block diagram concerning the modification of the solid-state imaging device of this invention. It is a sequence diagram showing operation | movement of the solid-state imaging device of this invention. It is operation | movement explanatory drawing at the time of erasure | elimination of the solid-state imaging device of this invention. It is operation | movement explanatory drawing at the time of the initial writing of the solid-state imaging device of this invention. It is operation | movement explanatory drawing at the time of writing of the solid-state imaging device of this invention. 6 is a voltage chart of a writing operation of the solid-state imaging device of the present invention. It is operation | movement explanatory drawing at the time of the reading of the solid-state imaging device of this invention. It is IV characteristic view of the memory cell transistor of the solid-state imaging device of this invention. It is a layout pattern of Example 1 of this invention. It is operation | movement explanatory drawing at the time of the writing of Example 1 of this invention. It is operation | movement explanatory drawing at the time of the reading of Example 1 of this invention. It is operation | movement explanatory drawing at the time of the erase | elimination of Example 1 of this invention. It is a layout pattern of Example 2 of this invention. It is operation | movement explanatory drawing at the time of the writing of Example 2 of this invention. It is operation | movement explanatory drawing at the time of the reading of Example 2 of this invention. It is operation | movement explanatory drawing at the time of the erase | elimination of Example 2 of this invention. It is a circuit block diagram of the solid-state image sensor which concerns on the 3rd Example of this invention. It is explanatory drawing showing operation | movement of the solid-state image sensor which concerns on the 3rd Example of this invention. It is explanatory drawing showing the write-in characteristic distribution of the conventional non-volatile memory element. It is explanatory drawing showing the write-in characteristic distribution of the non-volatile memory element based on 3rd Example of this invention. It is a circuit block diagram of the solid-state image sensor which concerns on the 4th Example of this invention. It is explanatory drawing showing operation | movement of the solid-state image sensor which concerns on the 4th Example of this invention. It is a schematic sectional drawing showing the 1st process in the manufacturing process of the solid-state image sensor which concerns on the 5th Example of this invention. It is a schematic sectional drawing showing the 2nd process in the manufacturing process of the solid-state image sensor which concerns on the 5th Example of this invention. It is a schematic sectional drawing showing the 3rd process in the manufacturing process of the solid-state image sensor which concerns on the 5th Example of this invention. It is a schematic sectional drawing showing the 4th process in the manufacturing process of the solid-state image sensor which concerns on the 5th Example of this invention. It is a schematic sectional drawing showing the 5th process in the manufacturing process of the solid-state image sensor which concerns on the 5th Example of this invention. It is a schematic sectional drawing showing the 6th process in the manufacturing process of the solid-state image sensor which concerns on the 5th Example of this invention. It is a schematic sectional drawing showing the 7th process in the manufacturing process of the solid-state image sensor which concerns on the 5th Example of this invention. It is a schematic sectional drawing showing the 1st process in the manufacturing process of the solid-state image sensor which concerns on the 6th Example of this invention. It is a schematic sectional drawing showing the 2nd process in the manufacturing process of the solid-state image sensor which concerns on the 6th Example of this invention. It is a schematic sectional drawing showing the 3rd process in the manufacturing process of the solid-state image sensor which concerns on the 6th Example of this invention. It is a schematic sectional drawing showing the 4th process in the manufacturing process of the solid-state image sensor which concerns on the 6th Example of this invention. It is a schematic sectional drawing showing the 5th process in the manufacturing process of the solid-state image sensor which concerns on the 6th Example of this invention. It is a schematic sectional drawing showing the 6th process in the manufacturing process of the solid-state image sensor which concerns on the 6th Example of this invention. It is a schematic sectional drawing showing the 1st process in the manufacturing process of the solid-state image sensor which concerns on the 7th Example of this invention. It is a schematic sectional drawing showing the 2nd process in the manufacturing process of the solid-state image sensor which concerns on the 7th Example of this invention. It is a schematic sectional drawing showing the 3rd process in the manufacturing process of the solid-state image sensor which concerns on the 7th Example of this invention. It is a schematic sectional drawing showing the 4th process in the manufacturing process of the solid-state image sensor which concerns on the 7th Example of this invention. It is a schematic sectional drawing showing the 5th process in the manufacturing process of the solid-state image sensor which concerns on the 7th Example of this invention. It is a schematic sectional drawing showing the 6th process in the manufacturing process of the solid-state image sensor which concerns on the 7th Example of this invention. It is a schematic sectional drawing showing the 1st process in the manufacturing process of the solid-state image sensor which concerns on the 8th Example of this invention. It is a schematic sectional drawing showing the 2nd process in the manufacturing process of the solid-state image sensor which concerns on the 8th Example of this invention. It is a schematic sectional drawing showing the 3rd process in the manufacturing process of the solid-state image sensor which concerns on the 8th Example of this invention. It is a schematic sectional drawing showing the 4th process in the manufacturing process of the solid-state image sensor which concerns on the 8th Example of this invention. It is a schematic sectional drawing showing the 5th process in the manufacturing process of the solid-state image sensor which concerns on the 8th Example of this invention. It is a schematic sectional drawing showing the 6th process in the manufacturing process of the solid-state image sensor which concerns on the 8th Example of this invention. It is a schematic sectional drawing showing the 7th process in the manufacturing process of the solid-state image sensor which concerns on the 8th Example of this invention. It is a schematic sectional drawing showing the 1st solid-state image sensor which concerns on the 9th Example of this invention. It is a schematic sectional drawing showing the 2nd solid-state image sensor which concerns on the 9th Example of this invention. It is a schematic sectional drawing showing the 3rd solid-state image sensor which concerns on the 9th Example of this invention. It is a modification (corresponding to the first embodiment) of the present invention. This is a modification of the present invention (corresponding to the third embodiment). It is a modification (corresponding to the fourth embodiment) of the present invention. This is a modification of the present invention (corresponding to the first embodiment, but PN inversion). This is a modification of the present invention (corresponding to the third embodiment, but PN inversion). This is a modification of the present invention (corresponding to the fourth embodiment, but PN inversion). This is a modification of the present invention (corresponding to the first embodiment, except that the memory transistor is P-type and the other MOS transistors are N-type). This is a modification of the present invention (corresponding to the third embodiment, except that the memory transistor is P-type and the other MOS transistors are N-type). This is a modification of the present invention (corresponding to the fourth embodiment, except that the memory transistor is P-type and the other MOS transistors are N-type). It is an example of the digital camera using the solid-state image sensor of this invention.

Explanation of symbols

100 Solid-state imaging device 101 Digital camera 1100, 1101... 10 nm Pixel 1 Photodiode 2 First MOS transistor 3 Second MOS transistor 4 Non-volatile memory element 5 Gate insulating film 5a First gate insulating film 5b Second gate insulating film 5c Third Gate insulating film 6 Charge storage layer 7 Gate electrode 7a First gate electrode 7b Second gate electrode 8 Floating gate 9 Single / double gate coexisting region 10 Silicon substrate 11 Element isolation 12, 13 P-type MOS transistors 12n, 13n N-type MOS Transistor 14 Memory cell transistor (nonvolatile memory element)
14a Exposure data storage element 14an Exposure data storage element (N-type)
14b Initial state memory element 14bn Initial state memory element (N-type)
15 drain 16 source 17a first gate electrode film 17b second gate electrode film 19 photoresist WL word line NW N-type well PW P-type well PD photodiode FD detection node BL bit line PL plate line SL source line TG first Control signal line RG Second control signal line

Claims (19)

A light receiving element that receives incident light and generates a signal charge;
A first transistor having one end connected to the light receiving element and the other end connected to a detection node;
A second transistor having one end connected to the detection node;
And a memory cell transistor having a charge storage layer having a control gate or one end connected to the detection node. A plurality of light receiving elements that receive incident light and generate signal charges;
A plurality of first transistors each having one end connected to the corresponding plurality of light receiving elements and the other end commonly connected to a detection node;
A second transistor having one end connected to the detection node;
A solid-state imaging device comprising: a plurality of memory cell transistors each having a charge storage layer having a control gate or one end connected to the detection node. A light receiving element that receives incident light and generates a signal charge, a first transistor having one end connected to the light receiving element and the other end connected to the detection node, and a second transistor having one end connected to the detection node And a memory cell transistor composed of a P-type MOS transistor having a charge storage layer having a control gate or one end connected to the detection node, and a method of operating a solid-state imaging device,
When the gate voltage of the memory cell transistor is Vg, the well voltage is Vsub, the voltage at one end is Vs, and the voltage at the other end is Vd, Vg and Vsub are set higher than Vs and Vd to the charge accumulation layer. A method for operating a solid-state imaging device, wherein the solid-state imaging device is injected. A solid-state imaging device having a plurality of pixels arranged in a matrix, wherein each of the plurality of pixels includes a light receiving element that receives incident light and generates a signal charge, one end connected to the light receiving element, and the other end A first transistor connected to the detection node, a second transistor having one end connected to the detection node, a memory cell transistor having a charge storage layer having a control gate or one end connected to the detection node, In the operation method of the solid-state imaging device comprising:
A method of operating a solid-state imaging device, wherein when data corresponding to a signal charge generated by the light receiving element is written to a memory cell transistor, the data is sequentially written for each of one or a plurality of columns or rows. A plurality of pixels arranged in a matrix, a plurality of first signal lines arranged across the plurality of pixels, a plurality of word lines and second signal lines arranged in each row, and arranged in each column In a solid-state imaging device comprising a plurality of bit lines and source lines,
Each of the plurality of pixels is
A light receiving element that receives incident light and generates a signal charge;
A first transistor having a gate connected to a first signal line, one end connected to the light receiving element, and the other end connected to a detection node;
A second transistor having a gate connected to a second signal line, one end connected to the detection node, and the other end connected to the word line;
A solid-state imaging device comprising: a memory cell transistor having a charge storage layer having a control gate connected to the detection node, one end connected to the source line, and the other end connected to the bit line. . A plurality of pixels arranged in a matrix, a plurality of first signal lines, a second signal line and a third signal line arranged over the plurality of pixels, and a plurality of word lines arranged in each row, In a solid-state imaging device composed of a plurality of bit lines arranged in each column,
Each of the plurality of pixels is
A light receiving element that receives incident light and generates a signal charge;
A first transistor having a gate connected to a first signal line, one end connected to the light receiving element, and the other end connected to a detection node;
A second transistor having a gate connected to the second signal line, one end connected to the detection node, and the other end connected to the third signal line;
A solid-state imaging device comprising: a memory cell transistor having a charge storage layer having a control gate connected to the word line, one end connected to the detection node, and the other end connected to the bit line. 2. The solid-state imaging device according to claim 1, further comprising an initial state storage memory cell transistor having a charge storage layer having a control gate or one end connected to the detection node. A light receiving element that receives incident light and generates a signal charge;
A solid-state imaging device operating method comprising: a memory cell transistor having a charge storage layer for storing information corresponding to the signal charge.
A method for operating a solid-state imaging device, comprising: calculating a difference between a read value of the memory cell transistor in an initial state and a read value of the memory cell transistor in a state in which writing is performed according to the signal charge. The operation method of the solid-state imaging device according to claim 8,
An operation method of a solid-state imaging device, wherein after reading the memory cell transistor in a state of being written according to the signal charge, the memory cell transistor is erased to be in the initial state. A light receiving element that receives incident light and generates a signal charge;
In a method for operating a solid-state imaging device, comprising: a first memory cell transistor having a charge storage layer that stores information corresponding to the signal charge; and a second memory cell transistor.
A difference between a value obtained by reading the second memory cell transistor in an initial state and a read value of the first memory cell transistor in a state of writing according to the signal charge is calculated. An operation method of the solid-state imaging device. The operation method of the solid-state imaging device according to claim 10,
Erasing the first memory cell transistor and the second memory cell transistor simultaneously, setting the second memory cell transistor to the initial state,
11. The operation method of the solid-state imaging device according to claim 10, wherein writing is performed on the first memory cell transistor in accordance with the signal charge. Forming an element isolation region that partitions the first region and the second region on the surface of the semiconductor substrate;
Forming a first gate electrode film on a part of the second region and the element isolation region;
Forming a second gate electrode film on the first region, another part of the element isolation region, and the first gate electrode film;
Patterning the first gate electrode film and the second gate electrode film so as to form first and second transistors in the first region and the second region, respectively;
A method for manufacturing a solid-state imaging device, wherein a photodiode is formed by forming a diffusion layer connected to the first transistor in a part of the first region. Forming an element isolation region that partitions the first region and the second region on the surface of the semiconductor substrate;
Forming a first gate electrode film on the first region, the second region, and the element isolation region;
Forming a second gate electrode film on the first gate electrode film;
Patterning the first gate electrode film and the second gate electrode film so as to form first and second transistors in the first region and the second region, respectively;
A method for manufacturing a solid-state imaging device, wherein a photodiode is formed by forming a diffusion layer connected to the first transistor in a part of the first region. 14. The method of manufacturing a solid-state imaging device according to claim 13, wherein the first gate electrode film and the second gate electrode film on the first region are electrically connected. Method. 15. The method of manufacturing a solid-state imaging device according to claim 14, wherein the first gate electrode film and the second gate electrode film on the first region are brought into contact with and electrically connected to the second region. A method for manufacturing a solid-state imaging device. Forming an element isolation region that partitions the first region and the second region on the surface of the semiconductor substrate;
Forming a first gate electrode film on a part of the second region and the element isolation region;
Forming a second gate electrode film on the first region, another part of the element isolation region, and the first gate electrode film;
Patterning the second gate electrode film to form a first transistor in the first region;
The second gate electrode film and the first gate electrode film are patterned so as to form a second transistor in the second region, and the first gate electrode film and the first gate electrode film are formed on the element isolation region. 2 gate electrode film,
A method for manufacturing a solid-state imaging device, wherein a photodiode is formed by forming a diffusion layer connected to the first transistor in a part of the first region. A semiconductor substrate;
An element isolation region that partitions the first region and the second region on the surface of the semiconductor substrate;
A first MOS transistor formed in the first region and having a first gate insulating film;
A second MOS transistor formed in the second region and having a second gate insulating film;
A photodiode formed in the first region and connected to the first first MOS transistor;
The solid-state imaging device, wherein the first gate electrode film and the second gate electrode film have different film thicknesses. A semiconductor substrate;
An element isolation region that partitions the first region and the second region on the surface of the semiconductor substrate;
A first MOS transistor formed in the first region and having a first gate insulating film;
A second MOS transistor formed in the second region and having a second gate insulating film;
A photodiode formed in the first region and connected to the first first MOS transistor;
A solid-state imaging device, wherein a charge storage layer is formed on the first gate electrode film. A digital camera using the solid-state imaging device according to any one of claims 1, 2, 5 to 7, 17, or 18.

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