JP2010278143A - Solid-state imaging device, imaging apparatus, and imaging method - Google Patents

Abstract

Provided is a solid-state imaging device capable of improving image quality by suppressing variations in threshold voltage of a nonvolatile memory transistor.
A solid-state imaging device 10 having a plurality of pixel units 100, wherein the pixel unit 100 includes a photoelectric conversion unit 3 and floating gates FG1 and FG2 capable of storing charges generated in the photoelectric conversion unit 3, respectively. The charge generated in the photoelectric conversion unit 3 after resetting the photoelectric conversion unit 3 is accumulated in the floating gates FG1 and FG2 and then generated in the photoelectric conversion unit 3 during the exposure period. The difference between the control unit 40 that stores the signal in the floating gate FG1, the first signal corresponding to the charge stored in the floating gate FG1 and the second signal corresponding to the charge stored in the floating gate FG2 is an imaging signal. And a readout circuit 20 that reads out as.
[Selection] Figure 5

Description

  The present invention relates to a solid-state imaging device, an imaging apparatus, and an imaging method.

  A solid-state imaging device has been proposed in which charges generated by photoelectric conversion are recorded by a nonvolatile MOS memory transistor having a charge accumulation region such as a floating gate, and a change in threshold voltage of the memory transistor due to the charges is read as an imaging signal (patent) References 1 and 2).

  In such a solid-state imaging device, when the thickness of the tunnel oxide film of the memory transistor varies depending on the manufacturing process, there are a memory transistor having a large increase in threshold voltage and a memory transistor having a small increase in threshold voltage. Such a variation in threshold voltage appears as uneven brightness of image data at the time of reading, and is preferably as small as possible.

  Patent Document 2 discloses a method for reducing the above-described variation in threshold voltage in a solid-state imaging device having a nonvolatile MOS memory transistor. In this method, first, dummy information is written into the memory transistors of all the pixels under a weak write condition. Next, the dummy information written in each pixel is read and stored in the memory. Next, the channel region of the memory transistor of the pixel is precharged with a voltage corresponding to the dummy information of the pixel stored in the memory. In this state, exposure is started.

JP 2002-280537 A JP 2001-85660 A

  In the method described in Patent Document 2, the driving steps until the start of exposure are complicated, and there is a concern that imaging and signal processing speeds are reduced. Further, since an external memory for storing dummy information is necessary, for example, when a global shutter that exposes all pixels simultaneously is realized, a large-capacity memory that can store dummy information for all pixels is provided. Necessary.

  The present invention has been made in view of the above circumstances, and is a compact solid-state imaging device capable of achieving high image quality without complicating driving, an imaging apparatus including the same, and the solid-state imaging device An object of the present invention is to provide an imaging method using the.

  The solid-state imaging device of the present invention is a solid-state imaging device having a plurality of pixel units, and the pixel unit includes a photoelectric conversion unit, a first charge storage unit capable of storing charges generated in the photoelectric conversion unit, and a first charge storage unit. A charge storage unit, and after resetting the photoelectric conversion unit, the charge generated in the photoelectric conversion unit is simultaneously stored in each of the first charge storage unit and the second charge storage unit, Writing means for accumulating charges generated in the photoelectric conversion unit during the exposure period in the first charge accumulation unit; a first signal corresponding to the charges accumulated in the first charge accumulation unit; Signal readout means for reading out a difference from the second signal corresponding to the charge accumulated in the second charge accumulation unit as an imaging signal;

  The imaging device of the present invention includes the solid-state imaging device.

  The imaging method of the present invention is an imaging method using a solid-state imaging device having a plurality of pixel units, and the pixel unit includes a photoelectric conversion unit and a first charge capable of accumulating charges generated in the photoelectric conversion unit. A storage unit and a second charge storage unit, and after resetting the photoelectric conversion unit, charge generated in the photoelectric conversion unit is simultaneously applied to each of the first charge storage unit and the second charge storage unit; A writing step for accumulating, and then accumulating charges generated in the photoelectric conversion unit during the exposure period in the first charge accumulating unit, and a first corresponding to the electric charge accumulated in the first charge accumulating unit A signal reading step of reading a difference between the signal and the second signal corresponding to the charge accumulated in the second charge accumulation unit as an imaging signal.

  According to the present invention, there are provided a small solid-state imaging device capable of achieving high image quality without complicating driving, an imaging apparatus including the same, and an imaging method using the solid-state imaging device. Can do.

1 is a schematic plan view showing a schematic configuration of a solid-state imaging device for explaining an embodiment of the present invention. 1 is an equivalent circuit diagram of a pixel portion of the solid-state imaging device shown in FIG. FIG. 2 is a schematic plan view showing a planar layout example of the pixel portion shown in FIG. A-A 'line cross-sectional schematic view of the pixel portion shown in FIG. B-B 'line cross-sectional schematic diagram of the pixel portion shown in FIG. Timing chart for explaining a method of driving the solid-state imaging device shown in FIG. The figure which showed the change of distribution of the threshold voltage of a non-volatile memory transistor during the imaging operation of the solid-state image sensor shown in FIG. 1 is an equivalent circuit diagram showing a first modification of the pixel portion of the solid-state imaging device shown in FIG. The equivalent circuit diagram which shows the 2nd modification of the pixel part of the solid-state image sensor shown in FIG. The figure which showed the example of a plane layout of the equivalent circuit diagram shown in FIG.

  Hereinafter, a solid-state imaging device for describing an embodiment of the present invention will be described with reference to the drawings. This solid-state imaging device is used by being mounted on an imaging unit built in an imaging device such as a digital camera or a digital video camera, a mobile phone, an electronic endoscope, or the like.

  FIG. 1 is a schematic plan view showing a schematic configuration of a solid-state imaging device for explaining an embodiment of the present invention. FIG. 1A is a diagram illustrating the entire solid-state imaging device, and FIG. 1B is a diagram illustrating a configuration example of a readout circuit of the solid-state imaging device in FIG. 1 includes a pixel unit 100, a readout circuit 20, an output circuit (a transistor 30, a signal line 70, a horizontal shift register 50, an output unit 60), a control unit 40, and an overall control unit 80. With.

  A plurality of the pixel portions 100 are provided, and are arranged in a two-dimensional shape (in this example, a square lattice shape) in the column direction of the semiconductor substrate K and the row direction orthogonal thereto.

  The readout circuit 20 is provided for each pixel unit column including the pixel units 100 arranged in the column direction, and is used for reading out an imaging signal from each pixel unit 100.

  The output circuit is a circuit for outputting an imaging signal for one pixel unit row read by the readout circuit 20.

  The control unit 40 controls each pixel unit 100.

  The overall control unit 80 performs overall control of the entire solid-state imaging device 10. The solid-state imaging device 10 operates by the overall control unit 80 controlling each unit under the control of the system control unit of the imaging apparatus on which the solid-state imaging device 10 is mounted.

  FIG. 2 is a diagram showing an equivalent circuit of the pixel portion in the solid-state imaging device shown in FIG. As shown in FIG. 2, the pixel unit 100 includes a photoelectric conversion unit 3, a nonvolatile memory transistor MT1, a nonvolatile memory transistor MT2, and a reset transistor RT.

  The photoelectric conversion unit 3 is formed in the semiconductor substrate K. The nonvolatile memory transistor MT1 has a MOS transistor structure including a floating gate FG1 which is a charge storage region formed above the semiconductor substrate K and a control gate CG1 which is a gate electrode. The nonvolatile memory transistor MT2 has a MOS transistor structure including a floating gate FG2 which is a charge storage region formed above the semiconductor substrate K and a control gate CG2 which is a gate electrode. The reset transistor RT is for resetting the electric charge of the photoelectric conversion unit 3. Each of the nonvolatile memory transistor MT1 and the nonvolatile memory transistor MT2 functions as a charge accumulation unit capable of accumulating charges generated in the photoelectric conversion unit 3.

  The outputs (drain regions D1, D2) of the nonvolatile memory transistor MT1 and the nonvolatile memory transistor MT2 are commonly connected to a column signal line 12 which is an output signal line provided for each pixel unit column. A readout circuit 20 is connected to the signal line 12. The source regions S of the nonvolatile memory transistors MT1 and MT2 are commonly connected to a source line SL provided for each pixel unit column.

  The reset transistor RT has a MOS structure including a reset drain RD, a photoelectric conversion unit 3 that functions as a source region, and a reset gate RG that is a gate electrode. A reset power supply line Vcc for supplying a reset voltage is connected to the reset drain RD.

  The control gate CG1 of the nonvolatile memory transistor MT1 is connected to a gate control line CGL1 provided for each line composed of pixel portions arranged in the row direction. The gate control line CGL1 of each line is connected to the control unit 40, and a voltage can be applied independently for each line.

  A gate control line CGL2 provided for each line is connected to the control gate CG2 of the nonvolatile memory transistor MT2. The gate control line CGL2 of each line is connected to the control unit 40 so that a voltage can be applied independently for each line.

  A reset control line RL provided for each line is connected to the reset gate RG of the reset transistor RT. The reset control line RL of each line is connected to the control unit 40 so that a voltage can be applied independently for each line. A configuration in which a reset pulse is applied from the control unit 40 via a reset control line RL, whereby the reset transistor RT is turned on, and the charge accumulated in the photoelectric conversion unit 3 is discharged to the drain RD of the reset transistor RT It has become.

  The read circuit 20 includes a first signal corresponding to the charge accumulated in the floating gate FG1 of the nonvolatile memory transistor MT1, and a second signal corresponding to the charge accumulated in the floating gate FG2 of the nonvolatile memory transistor MT2. Is a signal readout means for reading out the difference between them as an imaging signal.

  As shown in FIG. 1B, the read circuit 20 includes a read control unit 20a, a sense amplifier 20b, a precharge circuit 20c, a ramp-up circuit 20d, transistors 20e and 20f, and a count direction switching unit 20g. It is the composition provided with.

  The read control unit 20a controls on / off of the transistors 20e and 20f. The precharge circuit 20 c is a circuit for supplying a predetermined voltage to the column signal line 12 to precharge the column signal line 12. The sense amplifier 20b monitors the voltage of the column signal line 12, detects that this voltage has changed, and notifies the ramp-up circuit 20d accordingly. For example, it detects that the drain voltage precharged by the precharge circuit 20c has dropped, and inverts the sense amplifier output.

  The ramp-up circuit 20d includes an N-bit counter (for example, N = 8 to 12), and supplies a ramp waveform voltage that gradually increases or decreases to the control gates CG1 and CG2 of the pixel unit 100 via the control unit 40. At the same time, a count value (a combination of N 1, 0) corresponding to the value of the ramp waveform voltage is output.

  The count direction switching unit 20g performs control to set the count direction by the counter built in the ramp-up circuit 20d to either up-count or down-count.

  When the voltage of the control gate CG1 exceeds the threshold voltage of the nonvolatile memory transistor MT1 in a state where the column signal line 12 is precharged, the nonvolatile memory transistor MT1 becomes conductive, and at this time, the column signal line 12 of the precharged column signal line 12 is turned on. The potential drops. This is detected by the sense amplifier 20b and an inverted signal is output. The ramp-up circuit 20d holds (latches) a count value corresponding to the value of the ramp waveform voltage at the time when the inverted signal is received. Thereby, the threshold voltage of the nonvolatile memory transistor MT1 can be read as a signal as a digital value (combination of 1 and 0).

  When the voltage of the control gate CG2 exceeds the threshold voltage of the nonvolatile memory transistor MT2 in a state where the column signal line 12 is precharged, the nonvolatile memory transistor MT2 becomes conductive, and at this time, the column signal line 12 of the precharged column signal line 12 is turned on. The potential drops. This is detected by the sense amplifier 20b and an inverted signal is output. The ramp-up circuit 20d holds a count value corresponding to the value of the ramp waveform voltage when the inverted signal is received. Thereby, the threshold voltage of the nonvolatile memory transistor MT2 can be read as a signal as a digital value.

  In the readout circuit 20, the signal readout from the nonvolatile memory transistor MT1 and the signal readout from the nonvolatile memory transistor MT2 are continuously performed, and the count direction of the Nbit counter at the time of each signal readout is reversed. Thus, a signal obtained by taking the difference between the two signals can be read out as an imaging signal.

  When one horizontal selection transistor 30 is selected by the horizontal shift register 50, the counter value held in the ramp-up circuit 20d connected to the horizontal selection transistor 30 is output to the signal line 70, and this is output as an imaging signal. Output from the unit 60.

  Note that the method of reading the threshold voltages of the nonvolatile memory transistors MT1 and MT2 as a signal is not limited to the above. For example, the drain current of the nonvolatile memory transistor MT1 when a constant voltage is applied to the control gate CG1 and the drain region D1, and the nonvolatile memory transistor MT2 when a constant voltage is applied to the control gate CG2 and the drain region D2. The drain current may be read out as a signal.

  The control unit 40 controls the non-volatile memory transistors MT1 and MT2, and performs driving for injecting and accumulating charges generated in the photoelectric conversion unit 3 into the floating gates FG1 and FG2. In the nonvolatile memory transistor MT1 (MT2), when a write pulse is applied to the control gate CG1 (CG2), FN tunnel injection and direct tunnel injection in which charges are injected using a Fowler-Nordheim (FN) tunnel current. For example, charges generated in the photoelectric conversion unit 3 are injected into the floating gate FG1 (FG2) and accumulated.

  Further, the control unit 40 resets the electric charge generated and accumulated in the photoelectric conversion unit 3 of each pixel unit 100 to the outside to make the photoelectric conversion unit 3 in an empty state, and the floating gates FG1 and FG2 Charge erasure driving is also performed in which the accumulated charges are discharged to the semiconductor substrate and erased.

  FIG. 3 is a schematic plan view showing a planar layout example of the pixel portion of the solid-state imaging device shown in FIG. 4 is a schematic cross-sectional view taken along line A-A ′ of the pixel portion shown in FIG. 3. FIG. 5 is a schematic cross-sectional view taken along line B-B ′ of the pixel portion shown in FIG. 3.

  As shown in FIG. 4, the photoelectric conversion unit 3 is an N-type impurity region formed in the P-well layer 2 on the N-type silicon substrate 1, and a PN junction between the N-type impurity region and the P-well layer 2. Thus, the photoelectric conversion function is realized. The photoelectric conversion unit 3 is a so-called embedded photodiode in which a P-type impurity layer 5 is formed on the surface for complete depletion and dark current suppression. The N-type silicon substrate 1 and the P well layer 2 constitute the semiconductor substrate K.

  Adjacent pixel portions 100 are separated from each other by an element isolation layer 4 formed in the p well layer 2. As the element isolation method, a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, a method using high-concentration impurity ion implantation, and the like can be applied.

  The source region S of the nonvolatile memory transistor MT1 is an N-type impurity region that is provided adjacent to the photoelectric conversion unit 3 in the column direction. In addition, the drain region D1 of the nonvolatile memory transistor MT1 is an N-type impurity region that is provided adjacent to the source region S in the row direction. A channel region 6a, which is a P-type impurity region, is formed between the source region S and the drain region D1. The floating gate FG1 is provided above the semiconductor substrate between the source region S and the drain region D1 via the insulating film 7, and the control gate CG1 is provided above the floating gate FG1 via the insulating film 14. Yes. The channel region 6a is a region where carriers flow according to the voltage applied to the control gate CG1. Here, a P-type impurity is implanted into a region sandwiched between the source region S and the drain region D1 to form the channel region 6a. However, the channel region 6a may be left as it is.

  The drain region D2 of the nonvolatile memory transistor MT1 is an N-type impurity region that is provided adjacent to the source region S in the row direction. A channel region 6b which is a P-type impurity region is formed between the source region S and the drain region D2. The floating gate FG2 is provided above the semiconductor substrate between the source region S and the drain region D2 via the insulating film 7, and the control gate CG2 is provided above the floating gate FG2 via the insulating film 14. Yes. The channel region 6b is a region where carriers flow according to the voltage applied to the control gate CG2. Here, a P-type impurity is implanted into a region sandwiched between the source region S and the drain region D2 to form the channel region 6b. However, the p well layer 2 may be left as it is.

  For example, polysilicon can be used as the conductive material forming the control gates CG1 and CG2. A doped polysilicon that is highly doped with phosphorus (P), arsenic (As), and boron (B) may be used. Alternatively, silicide (Silicide) or salicide (Self-alingn Silicide) in which various metals such as titanium (Ti) and tungsten (W) are combined with silicon may be used. The same conductive material as that of the control gates CG1 and CG2 can be used as the conductive material constituting the floating gates FG1 and FG2.

  In the layout example of FIG. 3, the source region S and the drain regions D1, D2 are arranged side by side in the row direction, and the gap between them is elongated so that the floating gates FG1, FG2 and the control gates CG1, CG2 extend in the column direction. Is formed. The control gate CG1 extends below the gate control line CGL1, which is an aluminum wiring extending in the row direction. Here, the control gate CG1 is connected to the gate control line CGL1 by a contact portion 11 formed of aluminum or the like.

  The control gate CG2 extends below the gate control line CGL2, which is an aluminum wiring extending in the row direction. Here, the control gate CG2 is connected to the gate control line CGL2 by a contact portion 16 formed of aluminum or the like.

  Above the drain regions D1 and D2, a part of the column signal line 12 which is an aluminum wiring extending in the column direction extends, and this part and the drain region D1 are electrically connected by a contact portion 9 formed of aluminum or the like. A part of the drain region D2 and the drain region D2 are electrically connected by a contact portion 10a formed of aluminum or the like.

  A contact portion 8a made of aluminum or the like is formed on the source region S, and a wiring 8 is connected to the contact portion 8a. The wiring 8 passes under the reset power supply line Vcc, which is an aluminum wiring extending in the column direction, and extends below the source line SL. The wiring 8 and the source line SL are electrically connected by a contact portion 8b made of aluminum or the like. The source line SL is provided for each column including the pixel portions 100 arranged in the column direction, and is connected to a predetermined potential (for example, ground potential).

  The reset transistor RT includes a photoelectric conversion unit 3 that functions as a source region, a drain region RD that is an N-type impurity region that is provided adjacent to the photoelectric conversion unit 3 in the column direction, a photoelectric conversion unit 3 and a drain region RD. And a reset gate RG provided via an insulating film 7 above the semiconductor substrate.

  In the layout example of FIG. 3, the reset gate RG is arranged below the reset control line RL that is an aluminum wiring extending in the row direction. Here, the reset control line RL and the reset control line RL are formed by a contact portion RGa formed of aluminum or the like. It is connected.

  A part of the reset power supply line Vcc extends above the drain region RD, and this part and the drain region RD are electrically connected by a contact portion RDa formed of aluminum or the like. The reset power supply line Vcc is provided for each column including the pixel units 100 arranged in the column direction, and is connected to a predetermined power supply voltage.

  The arrangement of the reset transistor RT and the nonvolatile memory transistors MT1 and MT2 is not limited to that shown in FIG. 3, and may be appropriately arranged according to the space.

  The positional relationship between the various wirings is that the source line SL, the reset power supply line Vcc, and the column signal line 12 are formed in an upper layer than the gate control lines CGL1, CGL2, the reset control line RL, and the wiring 8. ing.

  The pixel unit 100 has a structure in which light does not enter a region other than a part of the photoelectric conversion unit 3 by a light shielding film W made of, for example, tungsten. As shown in FIGS. 4 and 5, an opening WH is formed above a part of the photoelectric conversion unit 3 above the semiconductor substrate (above the source line SL, the reset power supply line Vcc, and the column signal line 12). A light shielding film W is formed.

  In the solid-state imaging device 10, for the purpose of improving the efficiency of charge injection into the floating gates FG1 and FG2, as shown in FIGS. 4 and 5, the photoelectric conversion unit 3 is not only below the opening WH of the light shielding film W, The nonvolatile memory transistors MT1 and MT2 extend below the channel regions 6a and 6b.

  As shown in FIGS. 4 and 5, the photoelectric conversion unit 3 includes a main body 3a formed below the opening WH and an extending portion 3b extending from the main body 3a to below the channel region 6a (6b). In FIG. 4, a boundary line (broken line) is shown on the main body 3a and the extension 3b. However, this is for explanation, and such a boundary does not actually exist.

  The main body 3a is a portion formed below the opening WH in order to receive light. The extending portion 3b is a portion extending from the main body portion 3a to the bottom of the channel regions 6a and 6b of the nonvolatile memory transistors MT1 and MT2 inside the p well layer 2. The extension 3b is formed to extend in the column direction from the position facing the region between the source region S and the drain regions D1 and D2 of the main body 3a in plan view. That is, in the plan view, in the region where the nonvolatile memory transistors MT1 and MT2 and the reset transistor RT are formed, the photoelectric conversion unit 3 exists only under the channel regions 6a and 6b of the nonvolatile memory transistors MT1 and MT2. The photoelectric conversion unit 3 is formed. Note that the extending portion 3b may be formed so that the photoelectric conversion portion 3 exists not only under the channel regions 6a and 6b but also under the entire nonvolatile memory transistors MT1 and MT2.

  The channel region 6a (6b) is immediately below the control gate CG1 (CG2) and the floating gate FG1 (FG2). For this reason, by extending the photoelectric conversion unit 3 under the channel region 6a (6b) (preferably the entire range overlapping the channel region 6a (6b) in plan view), the charge of the photoelectric conversion unit 3 is reduced to FN. When injecting into the floating gate FG1 (FG2) by tunnel injection or direct tunnel injection, the voltage (CG voltage) applied to the control gate CG1 (CG2) causes the photoelectric conversion unit 3 to move to the floating gate FG1 (FG2) in a substantially vertical direction. An electric field can be applied. Thereby, the electric charge of the photoelectric conversion unit 3 is easily accelerated toward the control gate CG1 (CG2). As a result, tunneling can be caused with a low CG voltage.

  In the solid-state imaging device 10, since the photoelectric conversion unit 3 extends under the channel region 6a (6b) while securing the channel region 6a (6b), the photoelectric conversion unit 3 and the control gate CG1 (CG2). There is no restriction on the size of the overlapping portion, and the electric field direction can be made almost vertical. As a result, a tunnel current can be generated efficiently.

  The photoelectric conversion unit 3 can control the length in the direction parallel to the substrate surface by controlling the mask pattern during ion implantation, and can control the length in the direction perpendicular to the substrate surface by controlling ion implantation energy. it can. By doing in this way, it is possible to form the photoelectric conversion part 3 which consists of the main-body part 3a and the extension part 3b.

  Next, a method for driving the solid-state imaging device 10 configured as described above will be described.

  FIG. 6 is a timing chart for explaining a method of driving the solid-state imaging device shown in FIG. In FIG. 6, the voltage change supplied to each part in the pixel part 100 of an arbitrary line is shown with time.

  In the solid-state imaging device 10, when an imaging instruction is received, the control unit 40 supplies a reset pulse to the reset gates RG of the reset transistors RT of all the pixel units 100 using this as a start trigger. A voltage having a polarity opposite to that of the reset pulse is supplied to the control gates CG1 and CG2. Thereby, unnecessary charges accumulated in the photoelectric conversion unit 3 are discharged to the drain RD of the reset transistor RT, and charges accumulated in the floating gates FG1 and FG2 are also transferred to the drain RD via the photoelectric conversion unit 3. As a result, the floating gates FG1, FG2 become empty. When the application of the reset pulse is finished, the photoelectric conversion unit 3 is in a state where reset noise charges due to the reset operation are accumulated.

  When the application of the reset pulse is completed, the control unit 40 applies a write pulse (for example, a voltage of 7 V) to the control gates CG1 and CG2 of all the pixel units 100 at the same time, thereby reset noise accumulated in the photoelectric conversion unit 3. Charge is injected into floating gates FG1 and FG2.

  When the application of the write pulse to the control gates CG1 and CG2 of all the pixel units 100 is completed, the exposure period (charge accumulation period) is started in all the pixel units 100.

  Immediately before the end of the exposure period, the control unit 40 supplies a write voltage (for example, 7 V) to the control gates CG1 of all the pixel units 100, and charges generated in the photoelectric conversion unit 3 from the start of the exposure period to the present time are floating gates. Inject into FG1. Even during the application of the write voltage, light is incident on the photoelectric conversion unit 3, so that charges generated in the photoelectric conversion unit 3 in response to the light are also injected into the floating gate FG 1. The charge accumulated in the photoelectric conversion unit 3 moves from the main body 3a to the extension 3b, and is injected from the extension 3b into the floating gate FG1 through the channel region 6a.

  When the application of the write voltage to the control gate CG1 is finished, the exposure period is finished. Then, after the exposure period ends, the read control unit 20a turns on the transistor 20f to precharge the column signal line 12. Next, the read control unit 20a turns on the transistor 20e to conduct the column signal line 12 and the sense amplifier 20b. In this state, the ramp-up circuit 20d starts applying a ramp waveform voltage (Vth read voltage) to the control gate CG2 of each pixel unit 100 in the first line via the control unit 40.

  When the drain potential of the nonvolatile memory transistor MT2 of each pixel unit 100 on the first line drops after the ramp waveform voltage is applied, a count value corresponding to the value of the ramp waveform voltage at that time is held in each readout circuit 20. Is done. The N-bit counter of the readout circuit 20 counts down from the initial value, for example, with the count value “0” as an initial value under the control of the count direction switching unit 20g, and the non-volatile memory transistor of each pixel unit 100 in the first line The count value at the time when the drain potential of MT2 drops (hereinafter referred to as the first count value) is held.

  Next, the ramp-up circuit 20d stops applying the ramp waveform voltage to the control gate CG1 and turns off the transistor 20f. In this state, the read control unit 20a turns on the transistor 20f again to precharge the column signal line 12. In this state, the ramp-up circuit 20d starts applying a ramp waveform voltage (Vth readout voltage) to the control gate CG1 of each pixel unit 100 in the first line via the control unit 40.

  When the drain potential of the nonvolatile memory transistor MT1 of each pixel unit 100 in the first line drops after the ramp waveform voltage is applied, a count value corresponding to the value of the ramp waveform voltage at that time is held in each readout circuit 20. Is done. The N-bit counter of the reading circuit 20 counts up from the initial value using the previously held first count value as an initial value under the control of the count direction switching unit 20g, and the nonvolatile memory transistor in the first line The count value at the time when the drain potential of MT1 drops is held. The count value is output from the output amplifier 60 as an imaging signal.

  Since the first count value is negative, the up-count makes it possible to respond to the reset noise charge from a signal corresponding to the charge obtained by combining the reset noise charge and the charge generated in the photoelectric conversion unit 3 during the exposure period. Only a signal obtained by subtracting the obtained signal, that is, a signal corresponding to the charge generated in the photoelectric conversion unit 3 during the exposure period can be read out as an imaging signal. An example of a method for combining up-counting and down-counting is also disclosed in Japanese Patent Application Laid-Open No. 2007-60080.

  The same driving is performed for the pixel units 100 in the second and subsequent lines, and imaging signals are output from all lines. Thereafter, the control unit 40 applies a negative erase voltage to the control gates CG1 and CG2 of all the pixel units 100, and applies a positive voltage to the semiconductor substrate. As a result, the charges accumulated in the floating gates FG1 and FG2 are extracted by the semiconductor substrate and erased.

  FIG. 7 is a diagram showing changes in the threshold voltage distribution of the nonvolatile memory transistors MT1 and MT2 during the imaging operation. As shown in FIG. 7, the threshold voltage distribution is immediately after erasing the charges of the floating gates FG1 and FG2 and after injecting the reset noise charge after erasing the charge. The width becomes narrower. As described above, since the charge generated in the photoelectric conversion unit 3 during the exposure period can be injected into the floating gate FG1 in a state where the variation in the threshold voltage is suppressed, the nonvolatile memory transistor MT1 due to the charge generated during the exposure period. The variation in the threshold voltage change is small, and the unevenness of the image can be suppressed. The same amount of reset noise charge is injected into both the floating gate FG1 and the floating gate FG2, and photoelectric conversion is performed from a signal corresponding to the charge accumulated in the floating gate FG1 after the reset of the photoelectric conversion unit 3 is completed. Since the readout circuit 20 performs a process of subtracting a signal corresponding to the charge accumulated in the floating gate FG2 after the reset of the unit 3 is completed, an imaging signal from which reset noise has been removed can be obtained. As described above, according to the solid-state imaging device 10, it is possible to suppress image quality degradation caused by variations in threshold voltage and noise generated at the time of charge erasing in the floating gate or resetting the photodiode.

  In addition, according to the solid-state imaging device 10, it is only necessary to add a process of injecting a reset noise charge to the floating gate FG 1 and the floating gate FG 2 after resetting the charge of the photoelectric conversion unit 3, so that the driving step becomes complicated. In other words, the imaging and signal processing speed can be improved.

  Further, according to the solid-state imaging device 10, since the photoelectric conversion unit 3 exists under the channel region 6a of the nonvolatile memory transistor MT1 and the channel region 6b of the nonvolatile memory transistor MT2, it enters from the light shielding film opening WH. The charges generated in the photoelectric conversion unit 3 in response to the received light are efficiently injected from the overlapping portions of the photoelectric conversion unit 3 with the channel regions 6a and 6b into the floating gates FG1 and FG2 through the channel regions 6a and 6b. Therefore, the sensitivity can be improved.

  Note that the control unit 40 preferably switches the storage destination of the charges generated in the photoelectric conversion unit 3 during the exposure period alternately between the nonvolatile memory transistor MT1 and the nonvolatile memory transistor MT2 at regular intervals. . When the storage destination of the charge generated in the photoelectric conversion unit 3 during the exposure period is the nonvolatile memory transistor MT2, the signal from the nonvolatile memory transistor MT1 is read first by down-counting, and then the nonvolatile memory transistor What is necessary is just to read the signal from MT2 by up-counting and to output an imaging signal.

  In the above description, the signal is read from the floating gate FG2 in which only reset noise charges are accumulated. However, after the signal is read from the floating gate FG1, the signal from the floating gate FG2 is read. Reading may be performed. In addition, the count direction is down-counted when reading the signal from the floating gate FG2, and the count direction is up-counted when reading the signal from the floating gate FG1, but this may be reversed. In any case, the difference between the signal corresponding to the charge accumulated in the floating gate FG1 and the signal corresponding to the charge accumulated in the floating gate FG2 can be read as an imaging signal.

  In the solid-state imaging device 10, in order to effectively eliminate reset noise, the channel length and the channel width of the nonvolatile memory transistor MT1 are designed to be the same as the channel length and the channel width of the nonvolatile memory transistor MT2. It is preferable to keep it.

  In the above description, the MOS transistors having the floating gates FG1 and FG2 are taken as examples of the nonvolatile memory transistors MT1 and MT2. However, the nonvolatile memory transistors MT1 and MT2 can adopt a structure other than the MOS structure. . For example, there are a MNOS type transistor structure in which the floating gates FG1 and FG2 are nitride films and the control gates CG1 and CG2 are formed directly on the nitride film, and a MONOS type transistor structure in which the floating gates FG1 and FG2 are nitride films. May be. In either case, the nitride film functions as a charge storage region for storing charges.

  In the above description, it is assumed that the handling charge (charge taken out as a signal) is an electron, but the idea is the same even when the handling charge is a hole. In the case where the charge handled is a hole, the N-type region and the P-type region are exchanged in the drawing, and the polarity of the voltage applied to each part is reversed.

  Hereinafter, modifications of the solid-state imaging device 10 illustrated in FIG. 1 will be described.

(First modification)
FIG. 8 is an equivalent circuit diagram showing a first modification of the pixel portion of the solid-state imaging device shown in FIG. In FIG. 8, the same components as those in FIG. The difference between the solid-state imaging device shown in FIG. 8 and the solid-state imaging device shown in FIG. 2 is that two readout circuits 20 are provided for each column composed of pixel portions arranged in the column direction. In the solid-state imaging device shown in FIG. 8, separate column signal lines 12a and 12b are connected to the output (drain region D1) of the nonvolatile memory transistor MT1 and the output (drain region D2) of the nonvolatile memory transistor MT2, respectively. The readout circuit 20 is connected to each of the column signal lines 12a and 12b.

  The readout circuit 20 shown in FIG. 8 has a configuration in which the count direction switching unit 20g is deleted from the configuration shown in FIG. 1B, and the N-bit counter built in the ramp-up circuit 20d has, for example, an initial value. The count up corresponding to “0” is performed, and the count value corresponding to the value of the ramp waveform voltage when the potential of the column signal lines 12a and 12b changes is held.

  In the solid-state imaging device shown in FIG. 8, a difference circuit 21 is further provided for each column. The difference circuit 21 is connected to the two readout circuits 20 in the corresponding column, and calculates the difference between the two imaging signals read from the two readout circuits 20. The imaging signal obtained by the calculation is output from the output unit 60 via the selection transistor 30 and the signal line 70 under the control of the horizontal shift register 50.

  An imaging operation of the solid-state imaging device configured as described above will be described. The operation until the charge generated in the exposure period is accumulated in the floating gate FG1 is the same as that described with reference to FIG.

  After the completion of the charge injection to the floating gate FG1, the signal is read by the read circuit 20 connected to the column signal line 12a. First, the read control unit 20a turns on the transistor 20f to precharge the column signal line 12a. Next, the read control unit 20a turns on the transistor 20e to make the column signal line 12a and the sense amplifier 20b conductive. In this state, the ramp-up circuit 20d starts applying a ramp waveform voltage (Vth readout voltage) to the control gate CG1 of each pixel unit 100 in the first line via the control unit 40. A count value corresponding to the value of the ramp waveform voltage at the time when the drain potential of the nonvolatile memory transistor MT1 of each pixel unit 100 in the first line drops is held in each readout circuit 20.

  Next, signals are read out by the readout circuit 20 connected to the column signal line 12b. First, the read control unit 20a turns on the transistor 20f to precharge the column signal line 12b. Next, the read control unit 20a turns on the transistor 20e to make the column signal line 12b and the sense amplifier 20b conductive. In this state, the ramp-up circuit 20d starts applying a ramp waveform voltage (Vth read voltage) to the control gate CG2 of each pixel unit 100 in the first line via the control unit 40. A count value corresponding to the value of the ramp waveform voltage at the time when the drain potential of the nonvolatile memory transistor MT2 of each pixel unit 100 in the first line drops is held in each readout circuit 20.

  Next, the difference circuit 21 subtracts the count value held by the read circuit 20 connected to the column signal line 12b from the count value held by the read circuit 20 connected to the column signal line 12a. Output as a signal.

  The same driving is performed for the pixel units 100 in the second and subsequent lines, and imaging signals are output from all the lines. After the imaging signals are output from all the lines, the control unit 40 applies a negative erasing voltage to the control gates CG1 and CG2 of all the pixel units 100, and applies a positive voltage to the semiconductor substrate. As a result, the charges accumulated in the floating gates FG1 and FG2 are extracted by the semiconductor substrate and erased.

  As described above, even with the configuration shown in FIG. 8, image quality can be improved by suppressing variations in threshold voltage and noise generated during charge erasing or resetting the photodiode in the floating gate. The configuration illustrated in FIG. 2 is a configuration in which the read circuit 20 is shared by the nonvolatile memory transistor MT1 and the nonvolatile memory transistor MT2, and thus has an advantage that the circuit scale can be reduced as compared with the configuration illustrated in FIG.

(Second modification)
FIG. 9 is an equivalent circuit diagram showing a second modification of the pixel portion of the solid-state imaging device shown in FIG. In this modification, the nonvolatile memory transistor MT1 shown in FIG. 2 is replaced with a write transistor WT1 for writing charges into the floating gate FG1 and a threshold value of the nonvolatile memory transistor MT1 according to the charges accumulated in the floating gate FG1. The read transistor RT1 for detecting the voltage is composed of two transistors, and each has a configuration as described in Patent Document 1 in which the floating gate FG1 is shared. Similarly, the nonvolatile memory transistor MT2 includes a write transistor WT2 and a read transistor RT2, and has a structure in which the floating gate FG2 is shared by the transistors.

  In FIG. 9, the photoelectric conversion unit 3 and the source regions of the write transistors WT1 and WT2 are connected. Further, the drain regions of the read transistors RT1 and RT2 are commonly connected to the column signal line 12, and the read circuit 20 shown in FIG. 1B is connected to the column signal line 12. The gate electrode (write control gate) of the write transistor WT1 is indicated by WCG1, the gate electrode (write control gate) of the write transistor WT2 is indicated by WCG2, the gate electrode (read control gate) of the read transistor RT1 is indicated by RCG1, and the read transistor The gate electrode (read control gate) of RT2 is indicated by RCG2. A wiring wcg1 is connected to the write control gate WCG1, a wiring wcg2 is connected to the write control gate WCG2, a wiring rcg1 is connected to the read control gate RCG1, and a wiring rcg2 is connected to the read control gate RCG2. The wirings wcg1, wcg2, rcg1, and rcg2 are provided for each line of the pixel unit 100 arranged in the row direction, respectively, and a voltage can be applied by the control unit 40.

  FIG. 10 is a diagram showing a planar layout example of the equivalent circuit diagram shown in FIG. FIG. 10 illustrates two pixel units 100 adjacent in the row direction. In each line, a plurality of patterns of the two pixel portions 100 shown in FIG. 10 are arranged in the row direction. Since the two pixel portions shown in FIG. 10 are symmetrical with respect to the drain 32 of the reset transistor RT, only the left pixel portion 100 will be described below.

  The photoelectric conversion unit 3 is formed in the P well layer of the pixel unit 100, and the drain 34 of the readout transistor RT1, the source 33 shared by the readout transistors RT1 and RT2, and the readout are slightly spaced to the left of the photoelectric conversion unit 3. The drains 35 of the transistors RT2 are formed side by side in the column direction. Further, a drain 32 of the reset transistor RT is formed slightly adjacent to the right side of the photoelectric conversion unit 3.

  An insulating film (not shown) is formed on the P well layer, and a floating gate FG1 and a floating gate FG2 are formed thereon. The floating gate FG1 extends from the upper side of the photoelectric conversion unit 3 to the upper side between the drain 34 and the source 33 along the left side. The floating gate FG2 is formed to extend from the lower side of the photoelectric conversion unit 3 to the upper part between the drain 35 and the source 33 along the left side.

  An insulating film is provided on the floating gates FG1 and FG2, and write control gates WCG1 and WCG2, read control gates RCG1 and RCG2, and a reset gate RG are formed thereon.

  The write control gate WCG1 is formed so as to overlap the floating gate FG1. The read control gate RCG1 is formed so as to overlap with the floating gate FG1 above between the drain 34 and the source 33.

  The write control gate WCG2 is formed so as to overlap the floating gate FG2. The read control gate RCG2 is formed to overlap the upper floating gate FG2 between the drain 35 and the source 33.

  The reset gate RG is formed above the photoelectric conversion unit 3 and the drain 32. In the layout example of FIG. 10, the drain 32 of the reset transistor RT is shared by two adjacent pixel units 100, and the reset gate RG is connected to the photoelectric conversion unit 3 and the drain 32 of the adjacent pixel unit 100. It is also formed to extend above the gap.

  Global wiring (read control line rcg1, write control line wcg1, write control line wcg2, read) extending in the row direction via an insulating film above the write control gates WCG1, WCG2, read control gates RCG1, RCG2, and reset gate RG. A control line rcg2 and a reset line RL) are formed.

  The read control line rcg1 and the write control line wcg1 are formed on the upper side of the line of the pixel unit 100 so as to extend in the row direction. The write control line wcg2, the read control line rcg2, and the reset line RL are formed to extend in the row direction on the lower side of the line of the pixel portion 100.

  The read control gate RCG1 extends below the read control line rcg1, and is electrically connected to the read control line rcg1 through the contact via 38 here. The write control gate WCG1 extends below the write control line wcg1, and is electrically connected to the write control line wcg1 through the contact via 37 here.

  The read control gate RCG2 extends below the read control line rcg2, and is electrically connected to the read control line rcg2 through the contact via 39 here. The write control gate WCG2 extends below the write control line wcg2, and is electrically connected to the write control line wcg2 through the contact via 36 here.

  The reset gate RG extends below the reset line RL, and is electrically connected to the reset line RL through the contact via RGa.

  An insulating film is formed on the read control line rcg1, the write control line wcg1, the write control line wcg2, the read control line rcg2, and the reset line RL, and a global wiring extending in the column direction (column signal line 12, source) Line SL, reset drain line Vcc) are formed.

  The column signal line 12 and the source line SL are provided for each column of the pixel portion 100, and one reset drain line Vcc is provided for every two columns.

  The column signal line 12 extends to above the drain 34 and is electrically connected to the drain 34 through a contact via 34a. The column signal line 12 also extends above the drain 35 and is electrically connected to the drain 35 through a contact via 35a.

  The source line SL extends to above the source 33 and is electrically connected to the source 33 through a contact via 33a.

  The reset drain line Vcc is formed so as to pass above the drain 32, and is electrically connected to the drain 32 via the contact via 32a above the drain 32.

  In the layout example of FIG. 10, the drains of the write transistors WT1 and WT2 are omitted, and the write transistors WT1 and WT2 are each a two-terminal MOS transistor in which the source (also used as the drain) is connected to the photoelectric conversion unit 3. It is said. As the two-terminal device, there are a resistor, a coil, a capacitor, a diode and the like, but there is no active device such as switching or signal amplification.

  It is understood as common sense that a transistor, which is an active device for performing pixel selection, reset, signal recording, readout, and the like in a general solid-state imaging device, does not function with two terminals, and no one has tried.

  The structure of the solid-state imaging device in FIG. 10 has a structure in which the write transistor WT1 and the read transistor RT1 share the floating gate FG1, and therefore the write transistor WT1 is exclusively written (charge injection and recording to the floating gate FG1). Only single operation and charge transfer in only one direction are required, and at the time of signal reading, the signal can be read also on the adjacent reading transistor RT1 side by the shared FG structure, so that the writing transistor WT1 has a two-terminal structure. It turns out that there is no problem in operation even if it exists. The same applies to the write transistor WT2.

  In the solid-state imaging device shown in FIG. 10, since it is necessary to form a plurality of readout units in the pixel unit 100, the degree of freedom in design is reduced. Therefore, it is effective to simplify the configuration by providing the write transistors WT1 and WT2 with a two-terminal structure including a source connected to the photoelectric conversion unit 11 and a write control gate. In addition, in the example of FIG. 10, the sources of the readout transistor RT1 and the readout transistor RT2 are also shared, and the reset transistors RT of the two adjacent pixel units 100 are also shared. For this reason, it is possible to reduce the size and chip size of the pixel unit 100, and it is possible to realize a large number of pixels and miniaturization.

  The imaging operation of the solid-state imaging device shown in FIG. 9 is the same as that shown in FIG. Specifically, after resetting the photoelectric conversion unit 3, a write voltage is applied to the write control gates WCG1 and WCG2 to accumulate reset noise charges in the floating gates FG1 and FG2. Next, charges generated during the exposure period are accumulated in the floating gate FG1. When the charge accumulation is completed, the readout circuit 20 reads out the threshold voltage of the readout transistor RT2 as a signal, and then reads out the threshold voltage of the readout transistor RT1 as a signal, thereby outputting an imaging signal.

  As described above, even in the shared FG structure shown in FIG. 9, high-quality imaging can be performed by suppressing variations in threshold voltage and noise generated at the time of charge erasing or resetting the photodiode in the floating gate. Can do. In the configuration shown in FIG. 10 as well, the floating gate FG1 and channel region of the write transistor WT1 and the floating gate FG2 and channel region of the write transistor WT2 are shielded by the light shielding film, and the photoelectric conversion unit 3 is connected to the channel of the write transistor WT1. The charge injection efficiency can be improved by extending the region and the channel region of the write transistor WT2.

  As described above, the following items are disclosed in this specification.

  The disclosed solid-state imaging device is a solid-state imaging device having a plurality of pixel units, and the pixel unit includes a photoelectric conversion unit, a first charge storage unit capable of storing charges generated in the photoelectric conversion unit, and a first charge storage unit. A charge storage unit, and after resetting the photoelectric conversion unit, the charge generated in the photoelectric conversion unit is simultaneously stored in each of the first charge storage unit and the second charge storage unit, Writing means for accumulating charges generated in the photoelectric conversion unit during the exposure period in the first charge accumulation unit; a first signal corresponding to the charges accumulated in the first charge accumulation unit; Signal readout means for reading out a difference from the second signal corresponding to the charge accumulated in the second charge accumulation unit as an imaging signal;

  With this configuration, it is possible to obtain an imaging signal in which noise is suppressed, and to improve image quality.

  In the disclosed solid-state imaging device, the first charge accumulation unit is a first transistor including a first charge accumulation region formed above a semiconductor substrate on which the photoelectric conversion unit is formed, and the second transistor The charge storage portion is a second transistor including a second charge storage region formed above the semiconductor substrate on which the photoelectric conversion portion is formed, and the first charge storage region and the second charge storage region Each of the regions is a region where the electric charge is accumulated by the writing unit.

  With this configuration, after the photoelectric conversion unit is reset, the charge of the photoelectric conversion unit is stored in each of the first charge storage region and the second charge storage region. Can be narrowed. Since the difference between the first signal and the second signal is output as an imaging signal in a state where the normal distribution is narrowed in this way, variations in threshold voltage occur during charge erasure in the floating gate or when the photodiode is reset An imaging signal in which noise is suppressed can be obtained, and high image quality can be achieved.

  In the disclosed solid-state imaging device, each of the first charge accumulation region and the second charge accumulation region is a floating gate.

  With this configuration, noise can be further suppressed.

  The disclosed solid-state imaging device includes a light-shielding film provided above the semiconductor substrate and having an opening formed above a part of the photoelectric conversion unit, the first charge accumulation region of the first transistor, and The channel region, the second charge storage region and the channel region of the second transistor are covered with the light shielding film, and the photoelectric conversion unit is connected to the channel region of the first transistor and the second transistor. Extends below the channel region.

  With this configuration, since the photoelectric conversion unit exists under the channel regions of the first transistor and the second transistor, the charge generated in the photoelectric conversion unit according to the light entering from the light shielding film opening is converted into the photoelectric conversion unit. It is possible to efficiently inject into the charge accumulating portion through the channel region from the overlapping portion of the conversion portion with the channel region.

  In the disclosed solid-state imaging device, the channel length and channel width of the first transistor and the channel length and channel width of the second transistor are the same.

  With this configuration, higher image quality can be achieved.

  In the disclosed solid-state imaging device, the signal reading unit is configured by one circuit connected to an output signal line commonly connected to the first transistor and the second transistor.

  In the disclosed solid-state imaging device, the writing unit is configured to store the charge generated in the photoelectric conversion unit during the exposure period between the first charge storage unit and the second charge storage unit for a predetermined period. Switch alternately every time.

  With this configuration, the lifetime of the solid-state imaging device can be expected to be extended.

  The disclosed imaging device includes the solid-state imaging device.

  With this configuration, the circuit scale can be reduced.

  The disclosed imaging method is an imaging method using a solid-state imaging device having a plurality of pixel units, and the pixel unit includes a photoelectric conversion unit and a first charge capable of accumulating charges generated in the photoelectric conversion unit. A storage unit and a second charge storage unit, and after resetting the photoelectric conversion unit, charge generated in the photoelectric conversion unit is simultaneously applied to each of the first charge storage unit and the second charge storage unit; A writing step for accumulating, and then accumulating charges generated in the photoelectric conversion unit during the exposure period in the first charge accumulating unit, and a first corresponding to the electric charge accumulated in the first charge accumulating unit A signal readout step of reading out a difference between the signal and the second signal corresponding to the charge accumulated in the second charge accumulation unit as an imaging signal.

  In the disclosed imaging method, the first charge storage unit is a first transistor including a first charge storage region formed above a semiconductor substrate on which the photoelectric conversion unit is formed, and the second transistor The charge storage unit is a second transistor including a second charge storage region formed above the semiconductor substrate on which the photoelectric conversion unit is formed, and the first charge storage region and the second charge storage region Are regions where the charge is accumulated by the writing means.

  In the disclosed imaging method, each of the first charge accumulation region and the second charge accumulation region is a floating gate.

  According to the disclosed imaging method, in the writing step, a storage destination of charges generated in the photoelectric conversion unit during the exposure period is set at regular intervals between the first charge storage unit and the second charge storage unit. Switch alternately.

3 photoelectric conversion unit 10 solid-state imaging device 20 readout circuit 40 control unit 100 pixel unit RT reset transistor WT1, WT2 nonvolatile memory transistors FG1, FG2 floating gate

Claims (12)

A solid-state imaging device having a plurality of pixel portions,
The pixel unit includes a photoelectric conversion unit, a first charge storage unit capable of storing charges generated in the photoelectric conversion unit, and a second charge storage unit,
After resetting the photoelectric conversion unit, charges generated in the photoelectric conversion unit are simultaneously stored in each of the first charge storage unit and the second charge storage unit, and then in the photoelectric conversion unit during an exposure period. Writing means for accumulating the generated charges in the first charge accumulating unit;
Signal readout for reading out the difference between the first signal corresponding to the charge accumulated in the first charge accumulation unit and the second signal corresponding to the charge accumulated in the second charge accumulation unit as an imaging signal A solid-state imaging device. The solid-state imaging device according to claim 1,
The first charge storage unit is a first transistor including a first charge storage region formed above a semiconductor substrate on which the photoelectric conversion unit is formed;
The second charge storage unit is a second transistor including a second charge storage region formed above a semiconductor substrate on which the photoelectric conversion unit is formed;
A solid-state imaging device, wherein each of the first charge accumulation region and the second charge accumulation region is a region where the charge is accumulated by the writing unit. The solid-state imaging device according to claim 2,
A solid-state imaging device in which each of the first charge accumulation region and the second charge accumulation region is a floating gate. The solid-state imaging device according to claim 2 or 3,
A light-shielding film provided above the semiconductor substrate and having an opening formed above a portion of the photoelectric conversion unit;
The first charge storage region and channel region of the first transistor and the second charge storage region and channel region of the second transistor are covered by the light shielding film;
The solid-state imaging device in which the photoelectric conversion unit extends below a channel region of the first transistor and a channel region of the second transistor. The solid-state image sensor according to any one of claims 2 to 4,
A solid-state imaging device in which a channel length and a channel width of the first transistor are the same as a channel length and a channel width of the second transistor. The solid-state image sensor according to any one of claims 2 to 5,
A solid-state imaging device, wherein the signal reading unit is configured by one circuit connected to an output signal line commonly connected to the first transistor and the second transistor. It is a solid-state image sensing device according to any one of claims 1 to 6,
A solid-state imaging device in which the writing unit alternately switches the accumulation destination of the charge generated in the photoelectric conversion unit during the exposure period between the first charge accumulation unit and the second charge accumulation unit at regular intervals. .   An imaging device provided with the solid-state image sensor of any one of Claims 1-7. An imaging method using a solid-state imaging device having a plurality of pixel portions,
The pixel unit includes a photoelectric conversion unit, a first charge storage unit capable of storing charges generated in the photoelectric conversion unit, and a second charge storage unit,
After resetting the photoelectric conversion unit, charges generated in the photoelectric conversion unit are simultaneously stored in each of the first charge storage unit and the second charge storage unit, and then in the photoelectric conversion unit during an exposure period. A writing step of storing the generated charge in the first charge storage unit;
Signal readout for reading out the difference between the first signal corresponding to the charge accumulated in the first charge accumulation unit and the second signal corresponding to the charge accumulated in the second charge accumulation unit as an imaging signal An imaging method comprising the steps. The imaging method according to claim 9,
The first charge storage unit is a first transistor including a first charge storage region formed above a semiconductor substrate on which the photoelectric conversion unit is formed;
The second charge storage unit is a second transistor including a second charge storage region formed above a semiconductor substrate on which the photoelectric conversion unit is formed;
An imaging method in which each of the first charge storage region and the second charge storage region is a region in which the charge is stored by the writing unit. The imaging method according to claim 10, comprising:
An imaging method in which each of the first charge accumulation region and the second charge accumulation region is a floating gate. The imaging method according to any one of claims 9 to 11,
In the writing step, an imaging method of alternately switching a storage destination of charges generated in the photoelectric conversion unit during the exposure period between the first charge storage unit and the second charge storage unit every predetermined period.

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